A piecewise linear interpolation device, chip and chip system

Abstract

The present disclosure provides a piecewise linear interpolation device, a chip and a chip system, relates to the field of computers, and can improve the working frequency of the piecewise linear interpolation device. The piecewise linear interpolation device comprises a data-to-be-interpolated buffer unit, an interpolation node generation unit, an interval comparison unit and an interpolation calculation unit. The data-to-be-interpolated buffer unit is used for buffering independent variables to be interpolated. The interpolation node generation unit is used for generating a plurality of first independent variable nodes based on known independent variable nodes when the number of the known independent variable nodes is less than a preset number threshold. The interval comparison unit is used for determining a first interval and a second interval in which the independent variables to be interpolated are located, comparing the independent variables to be interpolated with each first independent variable node in the second interval, and determining an upper boundary node and a lower boundary node of the independent variables to be interpolated. The interpolation calculation unit is used for determining the function value corresponding to the interpolation function of the independent variables to be interpolated based on the upper boundary node and the lower boundary node.

Description

Technical Field

[0001] This disclosure relates to the field of computers, and more particularly to a piecewise linear interpolation device, a chip, and a chip system. Background Technology

[0002] In the fields of numerical computation and data fitting, piecewise linear interpolation is widely used due to its simplicity and small error. The basic operation of this method involves two steps: first, determining the known node intervals to which the independent variable to be interpolated belongs; and then calculating the estimated value using a linear formula.

[0003] In the implementation of piecewise linear interpolation in RTL (register transfer level) digital circuits based on ASIC (application-specific integrated circuit) or FPGA (field-programmable gate array), to determine the interval of the independent variable, multiple comparators and selectors need to be cascaded in series. The independent variable to be interpolated is compared with the known nodes of the independent variable one by one to determine the known node interval to which the independent variable to be interpolated belongs.

[0004] However, when there are many known nodes, the number of combinational logic levels that compare the interpolated independent variable with the known independent variable nodes one by one is also large, resulting in a low operating frequency of the piecewise linear interpolation device based on the piecewise linear interpolation method. Summary of the Invention

[0005] This disclosure provides a piecewise linear interpolation device, chip, and chip system that can improve the operating frequency of the piecewise linear interpolation device.

[0006] In a first aspect, embodiments of this disclosure provide a piecewise linear interpolation apparatus, which includes a data buffer unit to be interpolated, an interpolation node generation unit, an interval comparison unit, and an interpolation calculation unit.

[0007] The interpolation data caching unit caches the independent variables to be interpolated. The interpolation node generation unit caches the known independent variable nodes of the interpolation function and, when the number of known independent variable nodes is less than a preset threshold, generates multiple first independent variable nodes based on the known independent variable nodes. The number of first independent variable nodes is the preset threshold plus one. The interval comparison unit compares the independent variable to be interpolated with N first independent variable nodes to determine the first interval in which the independent variable to be interpolated resides. The N first independent variable nodes divide the multiple first independent variable nodes into N+1 intervals with the same number of first independent variable nodes. The interval comparison unit also compares the independent variable to be interpolated with M first independent variable nodes within the first interval to determine the second interval in which the independent variable to be interpolated resides. The M first independent variable nodes divide the first interval into M+1 intervals with the same number of first independent variable nodes. The interval comparison unit is also used to compare the independent variable to be interpolated with each of the first independent variable nodes within the second interval to determine the upper and lower boundary nodes of the independent variable to be interpolated. The upper and lower boundary nodes are the two first independent variable nodes that are closest to the independent variable to be interpolated among the multiple first independent variable nodes. The interpolation calculation unit is used to determine the function value of the independent variable to be interpolated in the interpolation function based on the upper and lower boundary nodes.

[0008] In this scheme, when the number of known independent variable nodes is less than a preset threshold, multiple first independent variable nodes can be generated. Compared to traditional implementation devices where the number of input known independent variable nodes cannot be changed, the piecewise linear interpolation device in this scheme can arbitrarily input a number of known independent variable nodes less than the preset threshold, improving the flexibility and practicality of the piecewise linear interpolation device. Furthermore, compared to traditional implementation devices that compare the interpolated independent variable with each known independent variable node one by one—which requires more comparisons and higher levels of serial combinational logic—this scheme achieves a more efficient interpolation by comparing the interpolated independent variable with each known independent variable node in a three-level comparison process. The first interval containing the independent variable to be interpolated is obtained by comparison. Then, the function value corresponding to the independent variable to be interpolated is calculated based on the upper and lower boundary nodes of the first interval. The number of serial combinational logic layers in the first level comparison is N, the number of serial combinational logic layers in the second level comparison is M, and the number of serial combinational logic layers in the third level comparison is the number of nodes of the first independent variable in the second interval. By hierarchical comparison, the number of serial combinational logic layers in each level comparison is significantly reduced, thereby increasing the operating frequency of the piecewise linear interpolation device. Furthermore, fewer serial combinational logic layers are more conducive to timing convergence, reducing the hardware implementation cost and resource overhead of the piecewise linear interpolation device.

[0009] In one possible implementation, the interval comparison unit includes a first-level cache update module, a second-level cache update module, and an interval index update module. The first-level cache update module determines N first-variable nodes from multiple first-variable nodes, compares the variable to be interpolated with the N first-variable nodes, and determines the first interval where the variable to be interpolated resides. The second-level cache update module determines M first-variable nodes from the first-variable nodes in the first interval, compares the variable to be interpolated with the M first-variable nodes, and obtains the second interval where the variable to be interpolated resides. The interval index update module compares the variable to be interpolated with each first-variable node in the second interval to determine the upper and lower boundary nodes of the variable to be interpolated.

[0010] In one possible implementation, the N first independent variable nodes include a first comparison node, a second comparison node, and a third comparison node. The first-level cache update module includes a first selector, a second selector, a third selector, a first comparator, a second comparator, a third comparator, and a first-level cache register group. The first input of the first comparator is the independent variable to be interpolated, the second input of the first comparator is the first comparison node, and the output of the first comparator is connected to the control terminal of the first selector. The first input of the first selector is the index range of the first node, the second input of the first selector is the index range of the second node, and the output of the first selector is connected to the first input of the second selector. The first input of the second comparator is the independent variable to be interpolated, the second input of the second comparator is the second comparison node, and the output of the second comparator is connected to the control terminal of the second selector. The second input of the second selector is the index range of the third node, and the output of the second selector is connected to the first input of the third selector. The first input of the third comparator is the independent variable to be interpolated, and the second input is the third comparison node. The output of the third comparator is connected to the control terminal of the third selector. The second input of the third selector is the fourth node index range, and the output of the third selector is connected to the input of the first-level buffer register. The output of the first-level buffer register outputs the first independent variable node corresponding to the first interval.

[0011] In one possible implementation, the piecewise linear interpolation device further includes a sub-interval comparison unit. This sub-interval comparison unit is used to generate multiple second independent variable nodes based on the lower and upper boundary nodes. It is also used to compare the independent variable to be interpolated with P second independent variable nodes to determine the first sub-interval where the independent variable to be interpolated resides. Furthermore, it is used to compare the independent variable to be interpolated with each second independent variable node within the first sub-interval to determine the upper and lower boundary sub-nodes of the independent variable to be interpolated. The upper and lower boundary sub-nodes are the two second independent variable nodes closest to the independent variable to be interpolated among the multiple second independent variable nodes. Finally, it is used to determine the lower boundary sub-node as an offset node. The interpolation calculation unit is used to determine the function value of the independent variable to be interpolated in the interpolation function based on the offset node, the upper boundary node, and the lower boundary node.

[0012] In one possible implementation, the sub-interval comparison unit includes a new node generation module, a cache update module, and an offset index update module. The new node generation module is used to generate multiple second independent variable nodes based on the lower boundary node and the upper boundary node, wherein the number of the multiple second independent variable nodes satisfies 2. n The cache update module is used to determine P second independent variable nodes from multiple second independent variable nodes, compare the independent variable to be interpolated with the P second independent variable nodes, and determine the first sub-interval where the independent variable to be interpolated is located. The offset index update module is used to compare the independent variable to be interpolated with each second independent variable node in the first sub-interval, determine the upper boundary child node and the lower boundary child node of the independent variable to be interpolated, and determine the lower boundary child node as the offset node.

[0013] In one possible implementation, the P second argument nodes include a first comparison sub-node, a second comparison sub-node, a third comparison sub-node, a fourth comparison sub-node, a fifth comparison sub-node, and a sixth comparison sub-node. The cache update module includes a first sub-comparator, a second sub-comparator, a third sub-comparator, a fourth sub-comparator, a fifth sub-comparator, a sixth sub-comparator, a first sub-selector, a second sub-selector, a third sub-selector, a first OR gate logic unit, a second OR gate logic unit, a third OR gate logic unit, and a data index cache register group.

[0014] The first input of the first sub-comparator is the independent variable to be interpolated, and the second input is the first sub-comparison node. The output of the first sub-comparator is connected to the first input of the first OR gate logic unit. The second input of the second sub-comparator is the independent variable to be interpolated, and the second input is the second sub-comparison node. The output of the second sub-comparator is connected to the second input of the first OR gate logic unit. The output of the first OR gate logic unit is connected to the control terminal of the first sub-selector. The first input of the first sub-selector is the index range of the first sub-node, and the second input of the second sub-selector is the index range of the second sub-node. The output of the first sub-selector is connected to the first input of the second sub-selector.

[0015] The first input of the third sub-comparator is the independent variable to be interpolated, and the second input is the third sub-comparison node. The output of the third sub-comparator is connected to the first input of the second OR gate logic unit. The first input of the fourth sub-comparator is the independent variable to be interpolated, and the second input is the fourth sub-comparison node. The output of the fourth sub-comparator is connected to the second input of the second OR gate logic unit. The output of the second OR gate logic unit is connected to the control terminal of the second sub-selector. The second input of the second sub-selector is the index range of the third sub-node, and the output of the second sub-selector is connected to the first input of the third sub-selector.

[0016] The first input of the fifth sub-comparator is the independent variable to be interpolated, and the second input is the fifth sub-comparison node. The output of the fifth sub-comparator is connected to the first input of the third OR gate logic unit. The first input of the sixth sub-comparator is the independent variable to be interpolated, and the second input is the sixth sub-comparison node. The output of the sixth sub-comparator is connected to the second input of the third OR gate logic unit. The output of the third OR gate logic unit is connected to the control terminal of the third sub-selector. The second input of the third sub-selector is the index range of the fourth sub-node, and the output of the third sub-selector is connected to the input of the data index buffer register group.

[0017] In one possible implementation, the cache update module also includes a first child node selector, a second child node selector, a third child node selector, and a data node cache register group.

[0018] The control terminal of the first child node selector is connected to the output terminal of the first OR gate logic unit. The first input terminal of the first child node selector is the first child node range, and the second input terminal of the first child node selector is the second child node range. The output terminal of the first child node selector is connected to the first input terminal of the second child node selector. The second input terminal of the second child node selector is the third child node range, and the output terminal of the second child node selector is connected to the first input terminal of the third child node selector. The second input terminal of the third child node selector is the fourth child node range, and the output terminal of the third child node selector is connected to the input terminal of the data node buffer register group.

[0019] In one possible implementation, the data buffer unit to be interpolated consists of multiple registers connected in series. The input of the first register is the independent variable to be interpolated, and the inputs of the other registers are connected to the output of the previous register.

[0020] In one possible implementation, the first independent variable node satisfies the following relationship: ; in, Indicates the first The first independent variable node is a data bit width of [number]. A non-negative integer of bits; This indicates the index corresponding to the first independent variable node; This represents the preset threshold number of nodes for the first independent variable. Indicates the first There are 1 known independent variable nodes, where the data width of the known independent variable node is 1. A non-negative integer of bits; This indicates the number of nodes with known independent variables; Indicates data bit width is The 0th bit.

[0021] Secondly, embodiments of this disclosure provide a chip that includes the piecewise linear interpolation device described in the first aspect.

[0022] Thirdly, embodiments of this disclosure provide a chip system that includes the piecewise linear interpolation device described in the first aspect.

[0023] It should be noted that any of the possible implementations of any of the above aspects can be combined, provided that the solutions do not contradict each other. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings.

[0025] Figure 1 This is a schematic diagram of the structure of a piecewise linear interpolation device provided in an embodiment of the present disclosure; Figure 2 This is a schematic diagram of the structure of an interval comparison unit provided in an embodiment of the present disclosure; Figure 3 A schematic diagram of another piecewise linear interpolation device provided in this embodiment of the present disclosure; Figure 4 This is a schematic diagram of the structure of a sub-interval comparison unit provided in an embodiment of the present disclosure; Figure 5 A schematic diagram of a circuit implementation of a first-level cache update module provided in an embodiment of this disclosure; Figure 6 A schematic diagram of a circuit implementation of a cache update module provided in an embodiment of this disclosure; Figure 7 This is a schematic flowchart illustrating an embodiment of the present disclosure for obtaining an interval index signal; Figure 8 This is a schematic diagram illustrating the calculation process of an offset index provided in an embodiment of this disclosure. Detailed Implementation

[0026] The technical solutions of this disclosure will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0027] It should be noted that, in this disclosure, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this disclosure should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0028] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

[0029] In the description of this disclosure, unless otherwise stated, " / " means "or," for example, A / B can mean A or B. "And / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. Furthermore, "at least one" means one or more, and "more than one" means two or more.

[0030] Piecewise linear interpolation is a commonly used interpolation method, frequently applied in numerical computation and data function fitting. It involves connecting adjacent interpolation nodes with straight lines, using these segmented lines to obtain estimates of the function at other points.

[0031] Specifically, piecewise linear interpolation refers to, for a given function... Assuming there is known Nodes , ,satisfy , Then, given an independent variable... ,when , At that time, one can obtain Interpolated estimates: Equation (1).

[0032] Especially for monotonic functions, piecewise linear interpolation is commonly used in various numerical computation systems that require interpolation fitting due to its simplicity and small error.

[0033] As can be seen from the above, conventional piecewise linear interpolation mainly consists of two steps: first, determining the independent variable to be interpolated. The known node interval to which the interpolation variable belongs is determined, and then the estimated value to be interpolated is calculated according to equation (1). It can be seen that, in order to determine the node interval to which the interpolation variable belongs, it is necessary to compare the interpolation variable with the given node interval multiple times. Size.

[0034] In the implementation of piecewise linear interpolation in RTL (register transfer level) digital circuits based on ASIC (application-specific integrated circuit) or FPGA (field-programmable gate array), to determine the interval of the independent variable, multiple comparators and selectors need to be cascaded in series. The independent variable to be interpolated is compared with the known nodes of the independent variable one by one to determine the known node interval to which the independent variable to be interpolated belongs.

[0035] However, when there are many known independent variable nodes, the number of combinational logic levels for comparing the independent variable to be interpolated with the known independent variable nodes one by one is large, which leads to a low operating frequency of the piecewise linear interpolation device based on the piecewise linear interpolation method.

[0036] Furthermore, due to the characteristics of hardware resources—that is, once the number of comparators and selectors, and their connections, are determined—the number of known nodes in traditional piecewise linear interpolation is usually difficult to adjust flexibly and must be a fixed number. Therefore, traditional piecewise linear interpolation methods have low flexibility in high-speed digital system applications.

[0037] To address the aforementioned problems, this disclosure provides a piecewise linear interpolation apparatus, comprising a data caching unit, an interpolation node generation unit, an interval comparison unit, and an interpolation calculation unit. The data caching unit caches the independent variable to be interpolated. The interpolation node generation unit caches known independent variable nodes of the interpolation function and, when the number of known independent variable nodes is less than a preset threshold, generates multiple first independent variable nodes based on the known independent variable nodes, the number of which is the preset threshold plus one. The interval comparison unit compares the independent variable to be interpolated with N first independent variable nodes to determine the first interval in which the independent variable to be interpolated resides. The N first independent variable nodes divide the multiple first independent variable nodes into N+1 intervals with the same number of first independent variable nodes. The interval comparison unit further compares the independent variable to be interpolated with M first independent variable nodes within the first interval to determine the second interval in which the independent variable to be interpolated resides. The M first independent variable nodes divide the first interval into M+1 intervals with the same number of first independent variable nodes. The interval comparison unit is also used to compare the independent variable to be interpolated with each of the first independent variable nodes within the second interval to determine the upper and lower boundary nodes of the independent variable to be interpolated. The upper and lower boundary nodes are the two first independent variable nodes that are closest to the independent variable to be interpolated among the multiple first independent variable nodes. The interpolation calculation unit is used to determine the function value of the independent variable to be interpolated in the interpolation function based on the upper and lower boundary nodes.

[0038] In this scheme, when the number of known independent variable nodes is less than a preset threshold, multiple first independent variable nodes can be generated. Compared to traditional implementation devices where the number of input known independent variable nodes cannot be changed, the piecewise linear interpolation device in this scheme can arbitrarily input a number of known independent variable nodes less than the preset threshold, improving the flexibility and practicality of the piecewise linear interpolation device. Furthermore, compared to traditional implementation devices that compare the interpolated independent variable with each known independent variable node one by one—which requires more comparisons and higher levels of serial combinational logic—this scheme achieves a more efficient interpolation by comparing the interpolated independent variable with each known independent variable node in a three-level comparison process. The first interval containing the independent variable to be interpolated is obtained by comparison. Then, the function value corresponding to the independent variable to be interpolated is calculated based on the upper and lower boundary nodes of the first interval. The number of serial combinational logic layers in the first level comparison is N, the number of serial combinational logic layers in the second level comparison is M, and the number of serial combinational logic layers in the third level comparison is the number of nodes of the first independent variable in the second interval. By hierarchical comparison, the number of serial combinational logic layers in each level comparison is significantly reduced, thereby increasing the operating frequency of the piecewise linear interpolation device. Furthermore, fewer serial combinational logic layers are more conducive to timing convergence, reducing the hardware implementation cost and resource overhead of the piecewise linear interpolation device.

[0039] For ease of explanation, it is assumed that the main input and output signals of the piecewise linear interpolation device in this embodiment include: 1. Input signal: the independent variable to be interpolated , for An unsigned non-negative integer with a bit width.

[0040] 2. Input signal: The number of known independent variable nodes of the interpolation function. , It is a positive integer.

[0041] 3. Input signal: The set of known independent variable nodes corresponding to the interpolation function. ,here This indicates a node with a known independent variable. yes An unsigned non-negative integer with a bit width that satisfies , for The corresponding known function value is also An unsigned non-negative integer with a bit width.

[0042] 4. Output signal: The piecewise linear interpolation device is based on the independent variable to be interpolated. The calculated piecewise linear interpolation results That is, the independent variable to be interpolated The function value corresponding to the interpolation function Also for An unsigned non-negative integer with a bit width.

[0043] In particular, if When, the piecewise linear interpolation result is specified as ;like When, the piecewise linear interpolation result is specified as .

[0044] Figure 1 This is a schematic diagram of a piecewise linear interpolation device provided in an embodiment of this disclosure. Figure 1 As shown, the piecewise linear interpolation device 100 includes a data buffer unit 101 to be interpolated, an interpolation node generation unit 102, an interval comparison unit 103, and an interpolation calculation unit 104.

[0045] The input to the input terminal of the data buffer unit 101 to be interpolated is the independent variable to be interpolated. The output of the data buffer unit 101 to be interpolated is connected to the input of the interval comparison unit 103; the input of the interpolation node generation unit 102 is the known independent variable node. and known independent variable nodes Number of The output of the interpolation node generation unit 102 is connected to the input of the interval comparison unit 103; the input of the interval comparison unit 103 can also be the independent variable to be interpolated. The output of the interval comparison unit 103 is connected to the input of the interpolation calculation unit 104; the input of the interpolation calculation unit 104 also includes known independent variable nodes. The corresponding known function value The output of the interpolation calculation unit 104 outputs the independent variable to be interpolated. function value .

[0046] The interpolation data caching unit 101 is used to cache the interpolation independent variables. .

[0047] In some embodiments, the data buffer unit 101 to be interpolated may be composed of multiple registers connected in series, and the input of the first register is the independent variable to be interpolated. The inputs of other registers are connected to the output of the previous register.

[0048] The number of registers can be configured based on the clock cycle delay in the piecewise linear interpolation device 100. For example, if there is a 4-clock-cycle delay in the piecewise linear interpolation device 100, the data buffer unit 101 to be interpolated can consist of 4 registers. The registers are connected in series, and the first register input is... The inputs to the second, third, and fourth registers come from the outputs of the registers in the previous stage. The outputs of these four registers can be denoted as follows: , , and The outputs of the four registers are relative to the original input independent variable signals. Delay by 1, 2, 3 and 4 clock cycles respectively.

[0049] Interpolation node generation unit 102 is used to cache the known independent variable nodes of the interpolation function. .

[0050] The interpolation node generation unit 102 is also used to generate nodes when the number of independent variable nodes is known. If the number is less than a preset threshold, multiple first independent variable nodes are generated based on known independent variable nodes.

[0051] The number of nodes in the first independent variable is a preset threshold number. +1. Preset quantity threshold It can be a multiple of the set value of 16. For example, the preset quantity threshold can be 32, 64, etc.

[0052] Based on a preset quantity threshold To illustrate, let's assume the independent variable nodes are known. quantity Less than 32, the data of the known nodes is Bit, interpolation node generation unit 102 can be based on Nodes with known independent variables This generates 33 first-variable nodes, which are as follows: , … , .

[0053] In some embodiments, the first independent variable node satisfies the following relationship: Equation (2).

[0054] in, Indicates the first The first independent variable node; This represents the index corresponding to the first independent variable node. The total number of first independent variable nodes is 33. Indicates the first One known independent variable node; This indicates the number of nodes with known independent variables.

[0055] Based on equation (2), it can be seen that the data bit width for each first independent variable node is... For the former The highest bit of the first independent variable node is 0, and the rest... Bit equals known independent variable node For the remainder The first independent variable node has a highest bit of 1 and all other bits of 0.

[0056] It should be noted that the interpolation node generation unit 102 is implemented based on combinational logic. Therefore, the timing of the generated first independent variable node is aligned with that of the known independent variable node, and there is no clock cycle delay.

[0057] The interval comparison unit 103 can be used to compare the independent variable to be interpolated with N first independent variable nodes to determine the first interval in which the independent variable to be interpolated is located.

[0058] Among them, N first independent variable nodes divide multiple first independent variable nodes into N+1 intervals with the same number of first independent variable nodes.

[0059] The N first independent variable nodes can be any N first independent variable nodes selected from the multiple first independent variable nodes generated by the interpolation node generation unit 102, or they can be first independent variable nodes selected at fixed positions from multiple first independent variable nodes, for a total of N. This embodiment does not impose specific limitations on this.

[0060] For example, N can be 3, 4, 6, 7, etc. For instance, when the number of first independent variable nodes is 33 and N is 3, the N first independent variable nodes can be respectively... , , For example, when the number of first independent variable nodes is 33 and N is 7, the N first independent variable nodes can be respectively... , , , , , , .

[0061] The interval comparison unit 103 can also be used to compare the independent variable to be interpolated with the M first independent variable nodes in the first interval to determine the second interval in which the independent variable to be interpolated is located.

[0062] Among them, M first independent variable nodes can divide the first interval into M+1 intervals with the same number of first independent variable nodes.

[0063] In some embodiments, the M first independent variable nodes can be any M nodes selected from the first independent variable nodes in the first interval, or they can be M nodes selected from fixed positions in the first independent variable nodes in the first interval.

[0064] In particular, in some embodiments, M and N are equal. For example, M and N can both be 3 or 4.

[0065] The interval comparison unit 103 is also used to compare the independent variable to be interpolated with each node of the first independent variable in the second interval to determine the upper boundary node and the lower boundary node of the independent variable to be interpolated.

[0066] Among them, the upper boundary node and the lower boundary node are the two first independent variable nodes that are closest to the independent variable to be interpolated among multiple first independent variable nodes, that is, there are no other first independent variable nodes between the upper boundary node and the lower boundary node.

[0067] In some embodiments, the interval comparison unit 103 includes a first-level cache update module, a second-level cache update module, and an interval index update module.

[0068] Figure 2 This is a schematic diagram of the structure of an interval comparison unit provided in an embodiment of this disclosure. Figure 2 As shown, the interval comparison unit 103 includes a first-level cache update module 1031, a second-level cache update module 1032, and an interval index update module 1033.

[0069] The first-level cache update module 1031 is used to determine N first-variable nodes from multiple first-variable nodes, compare the interpolated variable with the N first-variable nodes, and determine the first interval where the interpolated variable is located.

[0070] The second-level cache update module 1032 is used to determine M first independent variable nodes from the first independent variable nodes of the first interval, compare the independent variable to be interpolated with the M first independent variable nodes, and obtain the second interval where the independent variable to be interpolated is located.

[0071] The interval index update module 1033 compares the independent variable to be interpolated with each node of the first independent variable in the second interval to determine the upper and lower boundary nodes of the independent variable to be interpolated.

[0072] Figure 1 The interpolation calculation unit 104 shown is used to determine the independent variable to be interpolated based on the upper boundary node and the lower boundary node. The function value corresponding to the interpolation function.

[0073] In this embodiment, when the number of known independent variable nodes is less than a preset threshold, multiple first independent variable nodes can be generated. Compared to the traditional implementation device where the number of input known independent variable nodes cannot be changed, the piecewise linear interpolation device of this solution can arbitrarily input a number of known independent variable nodes less than the preset threshold, improving the flexibility and practicality of the piecewise linear interpolation device. Furthermore, compared to the traditional implementation device that compares the independent variable to be interpolated with each known independent variable node one by one—which requires more comparisons and higher levels of serial combinational logic—this solution compares the independent variable to be interpolated through three levels of comparisons. The first interval containing the independent variable to be interpolated is obtained by comparison. Then, the function value corresponding to the independent variable to be interpolated is calculated based on the upper and lower boundary nodes of the first interval. The number of serial combinational logic layers in the first level comparison is N, the number of serial combinational logic layers in the second level comparison is M, and the number of serial combinational logic layers in the third level comparison is the number of nodes of the first independent variable in the second interval. By hierarchical comparison, the number of serial combinational logic layers in each level comparison is significantly reduced, thereby increasing the operating frequency of the piecewise linear interpolation device. Furthermore, fewer serial combinational logic layers are more conducive to timing convergence, reducing the hardware implementation cost and resource overhead of the piecewise linear interpolation device.

[0074] In some embodiments, the piecewise linear interpolation apparatus further includes a sub-interval comparison unit. Figure 3 A schematic diagram of another piecewise linear interpolation device provided in an embodiment of this disclosure. (See attached diagram.) Figure 3 As shown, the piecewise linear interpolation device 100 includes a data buffer unit 101 to be interpolated, an interpolation node generation unit 102, an interval comparison unit 103, an interpolation calculation unit 104, and a sub-interval comparison unit 105.

[0075] The input to the input terminal of the data buffer unit 101 to be interpolated is the independent variable to be interpolated. The output of the data buffer unit 101 to be interpolated is connected to the input of the interval comparison unit 103 and the sub-interval comparison unit 105; the input of the interpolation node generation unit 102 is the known independent variable node. and known independent variable nodes Number of The output of the interpolation node generation unit 102 is connected to the input of the interval comparison unit 103 and the sub-interval comparison unit 105; the input of the interval comparison unit 103 can also be the independent variable to be interpolated. The output of interval comparison unit 103 is connected to the input of sub-interval comparison unit 105; the output of sub-interval comparison unit 105 is connected to the input of interpolation calculation unit 104; the input of interpolation calculation unit 104 also includes known independent variable nodes. The corresponding known function value The output of the interpolation calculation unit 104 outputs the independent variable to be interpolated. function value .

[0076] The sub-interval comparison unit 105 can be used to generate multiple second independent variable nodes based on the lower boundary node and the upper boundary node.

[0077] The number of multiple second independent variable nodes satisfies , It is a positive integer greater than 1.

[0078] For example, the number of second independent variable nodes can be 16, 64, etc.

[0079] In some embodiments, when the number of second independent variable nodes is 16, the calculation rule for the second independent variable nodes is as follows: Equation (3).

[0080] in, Indicates the first The second independent variable node, This indicates the node index corresponding to the second independent variable node; Indicates the lower boundary node; This represents the upper boundary node.

[0081] Using the first independent variable node as Taking a non-negative integer as an example, the second independent variable node is also... A non-negative integer of bits, and satisfying Furthermore, for each new input interpolated independent variable, there is a corresponding new set of second independent variable nodes. Specifically, if there exists... In the case of the second independent variable node, the results are all equal.

[0082] In some embodiments, the second independent variable node can be a register output, which can avoid excessively long paths in combinational logic and is beneficial for timing convergence.

[0083] The sub-interval comparison unit 105 can also be used to compare the independent variable to be interpolated with P second independent variable nodes to determine the first sub-interval in which the independent variable to be interpolated is located.

[0084] In some embodiments, the P second independent variable nodes can be P nodes arbitrarily selected from a plurality of second independent variable nodes, or P nodes can be selected from fixed positions among a plurality of second independent variable nodes.

[0085] Let's take an example where the number of secondary independent variable nodes is 16. If P is 6, then the P secondary independent variable nodes can be... , , , , , .

[0086] The sub-interval comparison unit 105 can also be used to compare the independent variable to be interpolated with each second independent variable node in the first sub-interval to determine the upper boundary sub-node and lower boundary sub-node of the independent variable to be interpolated.

[0087] Among them, the upper boundary child node and the lower boundary child node are the two second independent variable nodes that are closest to the independent variable to be interpolated among multiple second variable nodes.

[0088] The sub-interval comparison unit 105 can also be used to determine the lower boundary child node as the offset node.

[0089] The specific comparison process assumes that the first subinterval includes four second independent variable nodes, and the four second independent variable nodes are as follows: , , and Let's take an example to illustrate. In the independent variable to be interpolated... or In the case of offset node ; in the independent variable to be interpolated or In the case of offset node ; in the independent variable to be interpolated or In the case of offset node ; in the independent variable to be interpolated In the case of offset node .

[0090] In some embodiments, the sub-interval comparison unit 105 may also determine the node closest to the independent variable to be interpolated from the upper boundary sub-node and the lower boundary sub-node, and use that node as the offset node.

[0091] In one feasible implementation, the sub-interval comparison unit 105 can compare the independent variable to be interpolated with the median of the upper boundary child node and the lower boundary child node. If the independent variable to be interpolated is less than the median, the lower boundary child node is determined as the offset node of the independent variable to be interpolated. If there is an independent variable to be interpolated that is greater than or equal to the median, the upper boundary child node is determined as the offset node of the independent variable to be interpolated.

[0092] Specifically, this can be achieved using an adder, a shifter, and a comparator. The adder accumulates the sum of the upper and lower boundary child nodes; then, the shifter shifts the interpolated independent variable one position to the left, effectively multiplying it by 2; finally, the sum of the upper and lower boundary child nodes is compared with twice the interpolated independent variable to determine the offset node of the interpolated independent variable.

[0093] In another feasible implementation, the sub-interval comparison unit 105 can compare the difference between the independent variable to be interpolated and the upper boundary child node and the difference between the lower boundary child node and the independent variable to be interpolated. If the difference between the independent variable to be interpolated and the upper boundary child node is greater than or equal to the difference between the lower boundary child node and the independent variable to be interpolated, then the lower boundary child node is determined as the offset node of the node to be interpolated; if the difference between the independent variable to be interpolated and the upper boundary child node is less than the difference between the lower boundary child node and the independent variable to be interpolated, then the upper boundary child node is determined as the offset node of the node to be interpolated.

[0094] Specifically, this can be achieved using two subtractors and one comparator. The two subtractors calculate the difference between the independent variable to be interpolated and the upper boundary child node, and the difference between the lower boundary child node and the independent variable to be interpolated, respectively. Finally, the comparator compares the outputs of the two subtractors, that is, it compares the difference between the independent variable to be interpolated and the upper boundary child node, and the difference between the lower boundary child node and the independent variable to be interpolated.

[0095] In some embodiments, the sub-interval comparison unit includes a new node generation module, a cache update module, and an offset index update module.

[0096] Figure 4 This is a schematic diagram of the structure of a sub-interval comparison unit provided in an embodiment of this disclosure. Figure 4 As shown, the sub-interval comparison unit 105 includes a new node generation module 1051, a cache update module 1052, and an offset index update module 1053, which are used to implement the functions of the sub-interval comparison unit 105.

[0097] The new node generation module 1051 is used to generate multiple second independent variable nodes based on the lower boundary node and the upper boundary node.

[0098] The cache update module 1052 is used to determine P second independent variable nodes from multiple second independent variable nodes, compare the independent variable to be interpolated with the P second independent variable nodes, and determine the first sub-interval where the independent variable to be interpolated is located.

[0099] The offset index update module 1053 is used to compare the independent variable to be interpolated with each second independent variable node in the first sub-interval, determine the upper boundary child node and the lower boundary child node of the independent variable to be interpolated, and also to determine the lower boundary child node as the offset node.

[0100] Based on the offset nodes output by the sub-interval comparison unit 105, the interpolation calculation unit 104 can also be used to determine the function value of the independent variable to be interpolated in the interpolation function based on the offset nodes, the upper boundary nodes, and the lower boundary nodes.

[0101] In some embodiments, the interpolation formula for the function value of the independent variable to be interpolated in the interpolation function can be expressed as: Equation (4).

[0102] in, This represents the function value of the independent variable to be interpolated in the interpolation function; This represents the index corresponding to the lower boundary node. This represents the function value corresponding to the lower boundary node of the independent variable to be interpolated; This indicates the index corresponding to the offset node; This represents the index corresponding to the upper boundary node. This represents the function value corresponding to the upper boundary node of the independent variable to be interpolated.

[0103] The division by 16 in the above equation (4) can be obtained by shifting the multiplication result to the right by 4 bits, thereby avoiding the division operation and reducing the resource consumption and computational delay of the linear interpolation device.

[0104] Figure 5 This is a schematic diagram of a circuit implementation of a level-one cache update module provided in an embodiment of this disclosure. Figure 5 As shown, the first-level cache update module includes a first comparator 501, a second comparator 502, a third comparator 503, a first selector 504, a second selector 505, a third selector 506, and a first-level cache register set 507. The N first argument nodes include first comparison nodes. Second comparison node and the third comparison node .

[0105] like Figure 5 As shown, the input to the first input terminal x1 of the first comparator 501 is... The input to the second input terminal x2 of the first comparator 501 is The output of the first comparator 501 is connected to the control terminal of the first selector 504.

[0106] Specifically, the first comparator 501 is used for comparison. and The value of the first comparison is calculated and the first comparison result is output, which is either 1 or 0. If the result is 1, then the first comparison result is 1; otherwise, the first comparison result is 0.

[0107] like Figure 5 As shown, the control terminal of the first selector 504 is connected to the output terminal of the first comparator 501, and the input of the first input terminal 0 of the first selector 504 is the first node index range. The input to the second input terminal 1 of the first selector 504 is the second node index range. The output of the first selector 504 is connected to the first input 0 of the second selector 505.

[0108] Specifically, the first selector 504 is used to determine the first target node index range based on the first comparison result output by the first comparator 501. If the first comparison result is 1, then the first target node index range is... If the first comparison result is 0, then the index range of the first target node is... .

[0109] like Figure 5 As shown, the input to the first input terminal x1 of the second comparator 502 is... The input to the second input terminal x2 of the second comparator 502 is The output of the second comparator 502 is connected to the control terminal of the second selector 505.

[0110] Specifically, the second comparator 502 is used for comparison. and The value of the first comparison is calculated, and the second comparison result is output, which is either 1 or 0. If If the result is 1, then the second comparison result is 1; otherwise, the second comparison result is 0.

[0111] like Figure 5 As shown, the control terminal of the second selector 505 is connected to the output terminal of the second comparator 502. The input of the first input terminal 0 of the second selector 505 is the first target node index range, and the input of the second input terminal 1 of the second selector 505 is the third node index range. The output of the second selector 505 is connected to the third selector 506, and the first input of the third selector 506 is 0.

[0112] Specifically, the second selector 505 is used to determine the second target node index range based on the second comparison result output by the second comparator 502. If the second comparison result is 1, then the second target node index range is... If the second comparison result is 0, then the index range of the second target node is the index range of the first target node.

[0113] like Figure 5 As shown, the input to the first input terminal x1 of the third comparator 503 is... The input to the second input terminal x2 of the third comparator 503 is The output of the third comparator 503 is connected to the control terminal of the third selector 506.

[0114] Specifically, the third comparator 503 is used for comparison. and The value of the first comparison is calculated, and the result of the third comparison is output, which is either 1 or 0. If the result is 1, then the result of the third comparison is 1; otherwise, the result of the third comparison is 0.

[0115] like Figure 5 As shown, the control terminal of the third selector 506 is connected to the output terminal of the third comparator 503. The input of the first input terminal 0 of the third selector 506 is the second target node index range, and the input of the second input terminal 1 of the third selector 506 is the fourth node index range. The output of the third selector 506 is connected to the input of the first-level register group.

[0116] Specifically, the third selector 506 is used to determine the third target node index range based on the third comparison result output by the third comparator 503. If the third comparison result is 1, then the third target node index range is... If the third comparison result is 0, then the index range of the third target node is the index range of the second target node.

[0117] like Figure 5 As shown, the input of the first-level register group 507 is connected to the output of the third selector 506, and the output of the first-level register group 507 outputs the first independent variable node corresponding to the first interval.

[0118] The first-level register group 507 is used to convert the results of combinational logic calculations of selectors and comparators into synchronous, stable and low-timing-pressure timing signals. It can solve the timing convergence problem of long paths and provide a reliable synchronous interface for subsequent circuits.

[0119] In some embodiments, the first selector 504, the second selector 505, and the third selector 506 may be composed of nine two-to-one selectors.

[0120] In some embodiments, the first-level cache register group 507 may consist of nine 6-bit registers, used to cache the data index after the first comparison by the interval comparison unit and output the corresponding... The output of the third selector 506 serves as the input to the first-level register set 507, and the output of the first-level register set 507 is... The update results. For example... Figure 5 As shown, update each The serial combinational logic cascade has 3 layers, relative to the input independent variable signal. There is a calculation delay of 1 clock cycle.

[0121] The circuit structure of the L2 cache update module is similar to that of the L1 cache update module. Its internal L2 cache register set consists of three 6-bit registers, and the output of the L2 cache register set... Relative to the input signal of the independent variable to be interpolated There is a computation delay of 2 clock cycles. Similar to the L1 cache update module, each... The number of cascaded serial combinational logic layers is also 3.

[0122] Figure 6 This is a schematic diagram of a circuit implementation of a cache update module provided in an embodiment of this disclosure. Figure 6 As shown, the cache update module includes a first sub-comparator 601, a second sub-comparator 602, a third sub-comparator 603, a fourth sub-comparator 604, a fifth sub-comparator 605, a sixth sub-comparator 606, a first sub-selector 607, a second sub-selector 608, a third sub-selector 609, a first OR gate logic unit 610, a second OR gate logic unit 611, a third OR gate logic unit 612, and a data index cache register group 613. The number of multiple second argument nodes is 16, and P second argument nodes include first comparison sub-nodes. Second comparison child node Third comparison child node Fourth comparison child node Fifth comparison child node Compare with the sixth child node An example is provided for illustration.

[0123] In some embodiments, the cache update module further includes a first child node selector 614, a second child node selector 615, a third child node selector 616, and a data node cache register group 617.

[0124] like Figure 6 As shown, the input to the first input terminal x1 of the first sub-comparator 601 is the independent variable to be interpolated. The input of the second input terminal x2 of the first sub-comparator 601 is the first sub-comparison node. The output of the first sub-comparator 601 is connected to the first input of the first OR gate logic unit 610.

[0125] The first sub-comparator 601 is used for comparison. and The value of the first sub-comparison is calculated and the result of the first sub-comparison is output. The result of the first sub-comparison is either 1 or 0. Specifically, if If the first subcomparison result is 1, then the first subcomparison result is 0; otherwise, the first subcomparison result is 0.

[0126] like Figure 6 As shown, the input to the first input terminal x1 of the second sub-comparator 602 is the independent variable to be interpolated. The input of the second input terminal x2 of the second sub-comparator 602 is the second sub-comparison node. The output of the second sub-comparator 602 is connected to the second input of the first OR gate logic unit 610.

[0127] The second sub-comparator 602 is used for comparison. and Check if they are equal, and output the result of the second sub-comparison. The result of the first sub-comparison is 1 or 0. Specifically, if If the first subcomparison result is 1, then the first subcomparison result is 0; otherwise, the first subcomparison result is 0.

[0128] like Figure 6 As shown, the input of the first OR gate logic unit 610 is connected to the output of the first sub-comparator 601 and the second sub-comparator 602, and the output of the first OR gate logic unit 610 is connected to the control terminal of the first sub-selector 607.

[0129] The first OR gate logic unit 610 is used to determine the control signal of the first sub-selector 607 based on the output of the first sub-comparison result and the second sub-comparison result. Specifically, if there is a first sub-comparison result of 1 and a second sub-comparison result of 0, or a first sub-comparison result of 0 and a second sub-comparison result of 1, or a first sub-comparison result of 1 and a second sub-comparison result of 1, then the output of the first OR gate logic unit 610 is 1; if there is a first sub-comparison result of 0 and a second sub-comparison result of 0, then the output of the first OR gate logic unit 610 is 0.

[0130] like Figure 6 As shown, the input to the first input terminal 0 of the first sub-selector 607 is the index range of the first child node. The input to the second input terminal 1 of the second sub-selector 608 is the index range of the second sub-node. The output of the first sub-selector 607 is connected to the first input 0 of the second sub-selector 608.

[0131] The first sub-selector 607 is used to determine the first target sub-node index range based on the output of the first OR gate logic unit 610. Specifically, if the output of the first OR gate logic unit 610 is 0, then the first target sub-node index range is... If the output of the first OR gate logic unit 610 is 1, then the index range of the first target child node is... .

[0132] like Figure 6As shown, the input to the first input terminal x1 of the third sub-comparator 603 is the independent variable to be interpolated. The input of the second input terminal x2 of the third sub-comparator 603 is the third sub-comparison node. The output of the third sub-comparator 603 is connected to the first input of the second OR gate logic unit 611.

[0133] The third sub-comparator 603 is used for comparison. and The value of the third sub-comparison is calculated, and the result of the third sub-comparison is output, which is either 1 or 0. Specifically, if If the result is 1, then the result of the third subcomparison is 1; otherwise, the result of the third subcomparison is 0.

[0134] like Figure 6 As shown, the input to the first input terminal x1 of the fourth sub-comparator 604 is the independent variable to be interpolated. The input of the second input terminal x2 of the fourth sub-comparator 604 is the fourth sub-comparison node. The output of the fourth sub-comparator 604 is connected to the second input of the second OR gate logic unit 611.

[0135] The fourth sub-comparator 604 is used for comparison. and Check if they are equal, and output the result of the fourth sub-comparison, which is 1 or 0. Specifically, if If the result is 1, then the result of the fourth subcomparison is 1; otherwise, the result of the fourth subcomparison is 0.

[0136] like Figure 6 As shown, the input of the second OR gate logic unit 611 is connected to the output of the third sub-comparator 603 and the fourth sub-comparator 604, and the output of the second OR gate logic unit 611 is connected to the control terminal of the second sub-selector 608.

[0137] The second OR gate logic unit 611 is used to determine the control signal of the second sub-selector 608 based on the outputs of the third sub-comparison result and the fourth sub-comparison result. Specifically, if there is a third sub-comparison result of 1 and a fourth sub-comparison result of 0, or a first sub-comparison result of 0 and a fourth sub-comparison result of 1, or a third sub-comparison result of 1 and a fourth sub-comparison result of 1, then the output of the second OR gate logic unit 611 is 1; if there is a third sub-comparison result of 0 and a fourth sub-comparison result of 0, then the output of the second OR gate logic unit 611 is 0.

[0138] like Figure 6As shown, the input of the first input terminal 0 of the second sub-selector 608 is the first target child node index range output by the first sub-selector, the input of the second input terminal 1 of the second sub-selector 608 is the third child node index range, and the output terminal of the second sub-selector 608 is connected to the first input terminal of the third sub-selector 609.

[0139] The second sub-selector 608 is used to determine the second target sub-node index range based on the output of the second OR gate logic unit 611. Specifically, if the output of the second OR gate logic unit 611 is 0, the second target sub-node index range is the first target sub-node index range; if the output of the second OR gate logic unit 611 is 1, the second target sub-node index range is... .

[0140] like Figure 6 As shown, the input to the first input terminal x1 of the fifth sub-comparator 605 is the independent variable to be interpolated. The input of the second input terminal x2 of the fifth sub-comparator 605 is the fifth sub-comparison node. The output of the fifth sub-comparator 605 is connected to the first input of the third OR gate logic unit 612.

[0141] The fifth sub-comparator 605 is used for comparison. and The size of the value is calculated, and the result of the fifth sub-comparison is output, which is either 1 or 0. Specifically, if If the result is 1, then the result of the fifth subcomparison is 1; otherwise, the result of the fifth subcomparison is 0.

[0142] like Figure 6 As shown, the input to the first input terminal x1 of the sixth sub-comparator 606 is the independent variable to be interpolated. The input of the second input terminal x2 of the sixth sub-comparator 606 is the sixth sub-comparison node. The output of the sixth sub-comparator 606 is connected to the second input of the third OR gate logic unit 612.

[0143] The sixth sub-comparator 606 is used for comparison and Check if they are equal, and output the result of the sixth sub-comparison, which is 1 or 0. Specifically, if If the result is 1, then the result of the sixth subcomparison is 1; otherwise, the result of the sixth subcomparison is 0.

[0144] like Figure 6 As shown, the input of the third OR gate logic unit 612 is connected to the output of the fifth sub-comparator 605 and the sixth sub-comparator 606, and the output of the third OR gate logic unit 612 is connected to the control terminal of the third sub-selector 609.

[0145] The third OR gate logic unit 612 determines the control signal of the third sub-selector 609 based on the outputs of the fifth sub-comparison result and the sixth sub-comparison result. Specifically, if there is a fifth sub-comparison result of 1 and a sixth sub-comparison result of 0, or a fifth sub-comparison result of 0 and a sixth sub-comparison result of 1, or a fifth sub-comparison result of 1 and a sixth sub-comparison result of 1, then the output of the third OR gate logic unit 612 is 1; if there is a fifth sub-comparison result of 0 and a sixth sub-comparison result of 0, then the output of the third OR gate logic unit 612 is 0.

[0146] like Figure 6 As shown, the input to the first input terminal 0 of the third sub-selector 609 is the second target child node index range of the output of the second sub-selector 608, and the input to the second input terminal 1 of the third sub-selector 609 is the fourth child node index range. The output of the third sub-selector 609 is connected to the input of the data index cache register group 613.

[0147] The third sub-selector 609 is used to determine the third target sub-node index range based on the output of the third OR gate logic unit 612. Specifically, if the output of the third OR gate logic unit 612 is 0, the third target sub-node index range is the second target sub-node index range; if the output of the third OR gate logic unit 612 is 1, the third target sub-node index range is... .

[0148] like Figure 6 As shown, the input of the data index cache register group 613 is connected to the output of the third sub-selector 609, and the output of the data index cache register group 613 is the index of the second independent variable node corresponding to the first sub-interval.

[0149] like Figure 6 The control terminal of the first child node selector 614 is connected to the output terminal of the first OR gate logic unit 610, and the input of the first input terminal 0 of the first child node selector 614 is the first child node interval. The input to the second input terminal 1 of the first child node selector 614 is the second child node range. The output of the first child node selector 614 is connected to the first input 0 of the second child node selector 615.

[0150] The first child node selector 614 is used to determine the first target child node interval based on the output of the first OR gate logic unit 610. Specifically, if the output of the first OR gate logic unit 610 is 0, then the first target child node interval is... If the output of the first OR gate logic unit 610 is 1, then the first target child node interval is... .

[0151] like Figure 6 As shown, the control terminal of the second child node selector 615 is connected to the output terminal of the second OR gate logic unit 611, the input terminal of the first input terminal 0 of the second child node selector 615 is connected to the output terminal of the first child node selector 614, and the input of the second input terminal of the second child node selector 615 is the third child node interval. The output of the second child node selector 615 is connected to the first input 0 of the third child node selector 616.

[0152] The second child node selector 615 is used to determine the second target child node interval based on the output of the second OR gate logic unit 611. Specifically, if the output of the second OR gate logic unit 611 is 0, the second target child node interval is the first target child node interval; if the output of the second OR gate logic unit 611 is 1, the second target child node interval is... .

[0153] like Figure 6 As shown, the control terminal of the third child node selector 616 is connected to the output terminal of the third OR gate logic unit 612, the first input terminal 0 of the third child node selector 616 is connected to the output terminal of the second child node selector 615, and the input of the second input terminal 1 of the third child node selector 616 is the fourth child node interval. The output of the third child node selector 616 is connected to the input of the data node buffer register group 617.

[0154] The third child node selector 616 is used to determine the third target child node interval based on the output of the third OR gate logic unit 612. Specifically, if the output of the third OR gate logic unit 612 is 0, then the third target child node interval is the second target child node interval; if the output of the third OR gate logic unit 612 is 1, then the third target child node interval is... .

[0155] like Figure 6 As shown, the input of the data node cache register group 617 is connected to the output of the third child node selector 616, and the output of the data node cache register group 617 outputs the value of the second independent variable node in the first sub-interval where the independent variable to be interpolated is located.

[0156] In some embodiments, each of the first sub-selector 607, the second sub-selector 608, the third sub-selector 609, the first sub-node selector 614, the second sub-node selector 615, and the third sub-node selector 616 consists of four 2-to-1 selectors.

[0157] In some embodiments, the data index cache register group 613 consists of four 4-bit registers, and the output of the register group is... The updated results.

[0158] In some embodiments, the data node cache register group 617 consists of four... The data node buffer register set 617 is composed of bits and outputs. The updated results.

[0159] like Figure 6 As shown, the output of the cache update module is different from the input interpolation variable. There is a computation delay of one clock cycle, compared to the initial input of the independent variable to be interpolated into the piecewise linear interpolation device. There is a calculation delay of 4 clock cycles. Update each group. and The serial combinational logic cascade has three levels.

[0160] It is understandable that the offset node of the interpolation independent variable obtained in the sub-interval comparison unit... Compared to the initial input to the piecewise linear interpolation device, the independent variable to be interpolated... This results in a computation delay of 4 clock cycles. Therefore, to align the timing, the offset index update module in the sub-interval comparison unit will also perform adjustments. and Performing a two-level cache results in a delay of 2 clock cycles. and The sub-interval comparison unit will , and The input interpolation calculation unit can directly calculate based on... , and Perform interpolation calculations.

[0161] The following embodiments provide a complete process for calculating the function value of the independent variable to be interpolated in the interpolation function based on the piecewise linear interpolation device provided in the embodiments of this disclosure.

[0162] For ease of description, the data bit width in the disclosed embodiment is... Bit, the input interpolation variable for a given clock cycle. The number of known independent variable nodes in the corresponding interpolation function is That is, the independent variable to be interpolated It is accompanied by 28 known independent variable node groups. Let's take an example to illustrate.

[0163] Among them, the independent variable to be interpolated Known independent variable and known function values All An unsigned non-negative integer of bits, and Without loss of generality, the interpolation independent variable is received in a certain clock cycle. The actual node range is That is, the independent variable to be interpolated satisfy: Let's take an example to illustrate.

[0164] S1. The independent variable to be interpolated The data to be interpolated is input into the piecewise linear interpolation device and buffered in four levels to store the number of known independent variable nodes of the interpolation function. and known independent variable nodes The input is fed into the interpolation node generation unit of the piecewise linear interpolation device, and the function values ​​corresponding to the known independent variable nodes of the interpolation function are input into the interpolation calculation unit.

[0165] Among them, the data buffer unit to be interpolated consists of 4 It consists of a series of registers connected in sequence, with the first register input being... The inputs to the second, third, and fourth registers come from the outputs of the registers in the previous stage. The outputs of the four registers can be denoted as follows: , , and The outputs of the four registers are relative to the original input interpolation variables. Delay by 1, 2, 3 and 4 clock cycles respectively.

[0166] S2, the interpolation node generation unit is based on the input. Nodes with known independent variables Generate 33 first-variable nodes, as follows: .

[0167] Wherein, the data bit width of each first independent variable node is Bit. When hour, highest bit =0, the rest Bit equals known independent variable node ;when , highest bit =1, the rest The bit is 0.

[0168] For example, if the number of independent variable nodes is known Then the value of the first independent variable node is: Equation (5).

[0169] in, , representing the index corresponding to the first independent variable node. For the first 28 first independent variable nodes, the 11th bit (i.e., the highest bit) is updated to 0, and bits [11-1:0] are updated to the known independent variables. For the last 5 nodes of the first independent variable, the highest bit is updated to 1, and the remaining bits are updated to 0. Since... for For a bit signal, the result of the last 5 first independent variable nodes is 2048 in decimal.

[0170] According to the generation rules, the x-nodes output by the interpolation node generation unit satisfy the following relationship: According to the generation rules, Definitely satisfy .

[0171] S3. In the first-level cache update module of the interval comparison unit, the interpolation data cache unit inputs the interpolation independent variable and the first comparison node in the first independent variable node input by the interpolation node generation unit. Second comparison node Third comparison node The data is compared, and the L1 cache register set of the interval comparison unit is updated according to the comparison result. The L1 cache register set is denoted as... That is, the first interval.

[0172] because Therefore, there are a total of 4 comparison results, specifically: when hour, ;when hour, ;when hour, ;when hour, .

[0173] Since the actual node interval of the independent variable to be interpolated is The output of the first register set is: That is, the node index of the first independent variable node within the first interval includes .

[0174] Table 1 shows the output results of the L1 register bank of the interval comparison unit. The specific value to be taken.

[0175] Table 1

[0176] S4. In the interval comparison unit, the output of the first-level cache register set is input to the second-level cache update module, and the update is performed based on the output of the first-level cache register set. , and This allows us to obtain the new first independent variable node at the corresponding index. Specifically, it includes: , , .

[0177] Cache the results of the input interpolation variables. With the new first independent variable node The data are compared in size. Based on the comparison results, the L2 register of the interval comparison unit is updated, and the output of the L2 register is denoted as... That is, the second interval.

[0178] Similar to step S3 above, the second-level cache update module of the interval comparison unit also has four possible comparison results, namely: when hour, Otherwise, when hour, Otherwise, when hour, Otherwise, when hour, .

[0179] Since the actual node interval of the independent variable to be interpolated is The output of the L2 register set is .

[0180] Table 2 shows the output results of the L2 register bank of the interval comparison unit. The specific value to be taken.

[0181] Table 2

[0182] S5. In the interval comparison unit, the output of the secondary buffer register group is sent to the interval index update module. According to This yields the comparison value of the new first independent variable node at the corresponding index. ,Right now Cache the results of the input interpolation variables. Comparison value with the new first independent variable node The data are compared in size, and the independent variable to be interpolated is obtained based on the comparison results. The index signal of the lower boundary node of the interval. and the index signal of the upper boundary node , and All are 5-bit signals, recorded The index of the interval contained in the first independent variable node.

[0183] Figure 7 This is a schematic flowchart illustrating an embodiment of the present disclosure for obtaining an interval index signal. Depending on different comparison conditions, and Depend on The value is assigned.

[0184] like Figure 7 As shown, the specific calculation rules are as follows: First, determine If so, then , Output and .

[0185] If not, then determine .

[0186] If so, that is At this time, it is satisfied Then judge Is the highest bit 0? If so, that is... If the highest bit is 0, then , Output and If not, that is If the highest bit is 1, then , Output and .

[0187] If not, that is That is, at this time, it is satisfied. Then judge Is the highest bit 0? If so, that is... If the highest bit is 0, then , Output and If not, that is If the highest bit is 1, then , Output and .

[0188] According to the calculation rules, the interpolation independent variable can be calculated using three layers of serial combinational logic. The index signal of the lower boundary node of the interval. and the index signal of the upper boundary node .

[0189] in, , , ,because and The highest bit is 0, therefore... , The result was in line with expectations.

[0190] Furthermore, according to the calculation rules of the interval comparison unit, and It has the following relationship: when At that time, , ;when At that time, , .when hour, or ,and .when At that time, if ,express Exactly equal to a certain node And when ,express .

[0191] Among them, the interval comparison unit calculates a new set of and The signal requires two clock cycles, that is, for each independent variable to be interpolated. It takes two clock cycles to get the result.

[0192] It should be noted that the interval comparison unit can operate in a pipelined manner, meaning that the interval comparison unit can calculate the input interpolation variable in each clock cycle and output a set of results in each clock cycle, adapting to the new interpolation variable received in each clock cycle. .

[0193] S6. The new node generation module in the sub-interval comparison unit, based on... and The calculation outputs 16 new nodes for the second independent variable. The second independent variable node is calculated using equation (3) in the above embodiment, and will not be repeated here.

[0194] in, Relative to the input independent variable signal There is a computation delay of 3 clock cycles. New node for A non-negative integer of bits satisfies And each new input interpolation variable Each corresponds to a new set of node signals .

[0195] In particular, when At that time, each second independent variable node The results are all equal, that is .

[0196] S7. The cache update module in the sub-interval comparison unit updates the cached result of the input interpolation independent variable. With the new second independent variable node The data is compared, and based on the comparison results, the first-level buffer of the sub-interval comparison unit is updated and output.

[0197] The first-level cache of the sub-interval comparison unit is divided into a data node cache register group and a data index cache register group. The data node cache register group consists of four... The register is composed of bits, and the output of the register group is The data index buffer consists of four 4-bit registers, and the register set output is... That is, the first subinterval.

[0198] Based on the cached results of the independent variable to be interpolated With the new second independent variable node The comparison results have four possible outcomes, specifically: when or hour, , Otherwise, when or hour, , Otherwise, when or hour, , ;otherwise, , .

[0199] S8. In the offset index update module of the sub-interval comparison unit, Data node cache output in the first-level cache Perform a second comparison, and obtain the offset node based on the comparison results. Offset node It is a 4-bit signal with values ​​ranging from 0 to 15.

[0200] Figure 8 This is a schematic diagram illustrating the calculation process of an offset index provided in an embodiment of this disclosure. For example... Figure 8 As shown, this disclosure provides information regarding offset nodes. The calculation process.

[0201] Specifically: Judgment or If so, that is or hour, Output .

[0202] If not, then determine or If so, that is or hour, Output If not, then judge or .

[0203] If so, that is or hour, Output ;if not, Output .

[0204] Based on the comparison rules described above, this can be achieved using three layers of serial combinational logic. The calculation. Relative to the input independent variable signal There is a calculation delay of 4 clock cycles.

[0205] To align timings, it is necessary to... and After passing through two levels of register buffers, a delay of 2 clock cycles is obtained. and Offset node , and All data are sent to the interpolation calculation unit to calculate the interpolation result of the independent variable to be interpolated.

[0206] S9. In the interpolation calculation unit, based on the offset nodes... The interpolation formula is used to calculate the result. interpolation function value , for An unsigned number of bits is used as the final output.

[0207] Among them, the interpolation function value The calculation formula can be expressed as equation (4).

[0208] The division by 16 in the formula here can be obtained by right-shifting the multiplication result by 4 bits, thus avoiding the division operation. The interpolation formula used in this scheme is essentially... Take the existing formula (1) This avoids the complex division operation in equation (1).

[0209] Specifically, when hour, equal ;when hour, equal ;when Equal to a node with a known independent variable hour, It will also be equal to the corresponding known node function value. ;when At that time, the linear interpolation calculation method in this invention is equivalent to... and All are divided into 16 smaller intervals, according to In the interval Location index ,Sure In the interval The location is then used to calculate the interpolated function value. .

[0210] This disclosure provides a chip that may include a piecewise linear interpolation device.

[0211] This disclosure provides a chip system that may include a piecewise linear interpolation device.

[0212] In the several embodiments provided in this disclosure, it should be understood that the disclosed apparatus can also be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0213] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0214] In addition, the functional units in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0215] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions within the technical scope disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A piecewise linear interpolation device, characterized in that, The linear interpolation device includes a data buffer unit to be interpolated, an interpolation node generation unit, an interval comparison unit, and an interpolation calculation unit. The interpolation data caching unit is used to cache the interpolation independent variables; The interpolation node generation unit is used to cache the known independent variable nodes of the interpolation function; when the number of known independent variable nodes is less than a preset number threshold, it generates multiple first independent variable nodes based on the known independent variable nodes, and the number of the first independent variable nodes is the preset number threshold + 1. The interval comparison unit is used to compare the independent variable to be interpolated with N first independent variable nodes to determine the first interval in which the independent variable to be interpolated is located; wherein, the N first independent variable nodes divide the plurality of first independent variable nodes into N+1 intervals with the same number of first independent variable nodes; The interval comparison unit is further configured to compare the independent variable to be interpolated with the M first independent variable nodes in the first interval to determine the second interval in which the independent variable to be interpolated is located; wherein the M first independent variable nodes divide the first interval into M+1 intervals with the same number of first independent variable nodes; The interval comparison unit is further configured to compare the independent variable to be interpolated with each of the first independent variable nodes in the second interval to determine the upper boundary node and the lower boundary node of the independent variable to be interpolated; the upper boundary node and the lower boundary node are the two first independent variable nodes that are closest to the independent variable to be interpolated among the plurality of first independent variable nodes; The interpolation calculation unit is used to determine the function value of the independent variable to be interpolated in the interpolation function based on the upper boundary node and the lower boundary node.

2. The piecewise linear interpolation device according to claim 1, characterized in that, The interval comparison unit includes a first-level cache update module, a second-level cache update module, and an interval index update module; The first-level cache update module is used to determine N first independent variable nodes from the plurality of first independent variable nodes, compare the independent variable to be interpolated with the N first independent variable nodes, and determine the first interval where the independent variable to be interpolated is located; The second-level cache update module is used to determine M first independent variable nodes from the first independent variable nodes in the first interval, compare the independent variable to be interpolated with the M first independent variable nodes, and determine the second interval where the independent variable to be interpolated is located. The interval index update module is used to compare the independent variable to be interpolated with each first independent variable node in the second interval to determine the upper boundary node and lower boundary node of the independent variable to be interpolated.

3. The piecewise linear interpolation device according to claim 2, characterized in that, The N first independent variable nodes include a first comparison node, a second comparison node, and a third comparison node; The first-level cache update module includes a first selector, a second selector, a third selector, a first comparator, a second comparator, a third comparator, and a first-level cache register group; The input to the first input terminal of the first comparator is the independent variable to be interpolated, and the input to the second input terminal of the first comparator is the first comparison node; the output terminal of the first comparator is connected to the control terminal of the first selector. The input of the first input terminal of the first selector is the first node index range, and the input of the second input terminal of the first selector is the second node index range; The output of the first selector is connected to the first input of the second selector; The input to the first input terminal of the second comparator is the independent variable to be interpolated, and the input to the second input terminal of the second comparator is the second comparison node; the output terminal of the second comparator is connected to the control terminal of the second selector. The input to the second input terminal of the second selector is the index range of the third node; The output of the second selector is connected to the first input of the third selector; The input to the first input terminal of the third comparator is the independent variable to be interpolated, and the input to the second input terminal of the third comparator is the third comparison node; the output terminal of the third comparator is connected to the control terminal of the third selector. The input to the second input terminal of the third selector is the index range of the fourth node; The output of the third selector is connected to the input of the first-level buffer register group; The output of the first-level cache register group outputs the first independent variable node corresponding to the first interval.

4. The piecewise linear interpolation device according to claim 1, characterized in that, The piecewise linear interpolation device further includes a sub-interval comparison unit; The sub-interval comparison unit is used to generate multiple second independent variable nodes based on the lower boundary node and the upper boundary node; The sub-interval comparison unit is also used to compare the independent variable to be interpolated with P second independent variable nodes to determine the first sub-interval where the independent variable to be interpolated is located; The sub-interval comparison unit is further configured to compare the independent variable to be interpolated with each second independent variable node in the first sub-interval, and determine the upper boundary sub-node and the lower boundary sub-node of the independent variable to be interpolated, wherein the upper boundary sub-node and the lower boundary sub-node are the two second independent variable nodes that are closest to the independent variable to be interpolated among the plurality of second independent variable nodes; The sub-interval comparison unit is also used to determine the lower boundary sub-node as an offset node; The interpolation calculation unit is further configured to determine the function value of the independent variable to be interpolated in the interpolation function based on the offset node, the upper boundary node, and the lower boundary node.

5. The piecewise linear interpolation device according to claim 4, characterized in that, The sub-interval comparison unit includes a new node generation module, a cache update module, and an offset index update module; The new node generation module is used to generate multiple second independent variable nodes based on the lower boundary node and the upper boundary node, wherein the number of the multiple second independent variable nodes satisfies the following... ; The cache update module is used to determine P second independent variable nodes from the plurality of second independent variable nodes, compare the independent variable to be interpolated with the P second independent variable nodes, and determine the first sub-interval where the independent variable to be interpolated is located. The offset index update module is used to compare the independent variable to be interpolated with each second independent variable node in the first sub-interval to determine the upper boundary child node and the lower boundary child node of the independent variable to be interpolated, and is also used to determine the lower boundary child node as the offset node.

6. The piecewise linear interpolation device according to claim 5, characterized in that, The P second independent variable nodes include a first comparison sub-node, a second comparison sub-node, a third comparison sub-node, a fourth comparison sub-node, a fifth comparison sub-node, and a sixth comparison sub-node; The cache update module includes a first sub-comparator, a second sub-comparator, a third sub-comparator, a fourth sub-comparator, a fifth sub-comparator, a sixth sub-comparator, a first sub-selector, a second sub-selector, a third sub-selector, a first OR gate logic unit, a second OR gate logic unit, a third OR gate logic unit, and a data index cache register group; The input to the first input terminal of the first sub-comparator is the independent variable to be interpolated, and the input to the second input terminal of the first sub-comparator is the first sub-comparison node; the output terminal of the first sub-comparator is connected to the first input terminal of the first OR gate logic unit. The input to the first input terminal of the second sub-comparator is the independent variable to be interpolated, and the input to the second input terminal of the second sub-comparator is the second sub-comparison node; the output terminal of the second sub-comparator is connected to the second input terminal of the first OR gate logic unit. The output of the first OR gate logic unit is connected to the control terminal of the first sub-selector; The first input terminal of the first sub-selector is the first child node index range, and the second input terminal of the second sub-selector is the second child node index range; the output terminal of the first sub-selector is connected to the first input terminal of the second sub-selector. The input to the first input of the third sub-comparator is the independent variable to be interpolated, and the input to the second input of the third sub-comparator is the third sub-comparison node; the output of the third sub-comparator is connected to the first input of the second OR gate logic unit. The input to the first input terminal of the fourth sub-comparator is the independent variable to be interpolated, and the input to the second input terminal of the fourth sub-comparator is the fourth sub-comparison node; the output terminal of the fourth sub-comparator is connected to the second input terminal of the second OR gate logic unit. The output of the second OR gate logic unit is connected to the control terminal of the second sub-selector; The input to the second input terminal of the second sub-selector is the index range of the third child node; the output terminal of the second sub-selector is connected to the first input terminal of the third sub-selector. The input to the first input terminal of the fifth sub-comparator is the independent variable to be interpolated, and the input to the second input terminal of the fifth sub-comparator is the fifth sub-comparison node; the output terminal of the fifth sub-comparator is connected to the first input terminal of the third OR gate logic unit. The input to the first input of the sixth sub-comparator is the independent variable to be interpolated, and the input to the second input of the sixth sub-comparator is the sixth sub-comparison node; the output of the sixth sub-comparator is connected to the second input of the third OR gate logic unit. The output of the third OR gate logic unit is connected to the control terminal of the third sub-selector; The input of the second input terminal of the third sub-selector is the index range of the fourth sub-node; the output terminal of the third sub-selector is connected to the input terminal of the data index cache register group.

7. The piecewise linear interpolation device according to claim 6, characterized in that, The cache update module also includes a first child node selector, a second child node selector, a third child node selector, and a data node cache register group; The control terminal of the first child node selector is connected to the output terminal of the first OR gate logic unit; the input of the first input terminal of the first child node selector is the first child node interval, and the input of the second input terminal of the first child node selector is the second child node interval; the output terminal of the first child node selector is connected to the first input terminal of the second child node selector. The input to the second input terminal of the second child node selector is the third child node range; the output terminal of the second child node selector is connected to the first input terminal of the third child node selector. The input of the second input terminal of the third child node selector is the fourth child node interval; the output terminal of the third child node selector is connected to the input terminal of the data node buffer register group.

8. The piecewise linear interpolation device according to claim 1, characterized in that, The interpolation data buffer unit consists of multiple registers connected in series. The input of the first register is the interpolation independent variable, and the inputs of the other registers are connected to the output of the previous register.

9. The piecewise linear interpolation device according to claim 1, characterized in that, The first independent variable node satisfies the following relationship: ； in, Indicates the first The first independent variable node is a data bit width of [number]. A non-negative integer of bits; This indicates the index corresponding to the first independent variable node; This represents the preset threshold number of nodes for the first independent variable. Indicates the first There are 1 known independent variable node, where the known independent variable node has a data bit width of 1. A non-negative integer of bits; This indicates the number of known independent variable nodes; Indicates data bit width is The 0th bit.

10. A chip, characterized in that, The chip includes the piecewise linear interpolation device according to any one of claims 1 to 9.

11. A chip system, characterized in that, The chip system includes the piecewise linear interpolation device according to any one of claims 1 to 9.

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