Reference model construction and debugging method, integrated circuit verification method, electronic device, and computer program product

Abstract

The application relates to a reference model construction and debugging method, an integrated circuit verification method, an electronic device and a computer program product, wherein the reference model construction method comprises the following steps: defining trigger transactions, function input transactions and state visible resources of a reference model; dividing internal processing stages of the reference model, wherein the internal processing stages comprise a pre-stage, a function calculation stage and a timing submission stage, and constructing stage functions required by the function calculation stage; configuring the trigger transactions to correspond to trigger events generated by a verification platform and capable of exciting a to-be-tested design, and configuring the function input transactions to be input contents affecting the function behavior of the to-be-tested design, so as to obtain the reference model consistent with the function behavior of the to-be-tested design. The technical scheme of the application overcomes the problems of modeling complexity and difficulty in reuse caused by the construction of the reference model depending on the process code.

Description

Technical Field

[0001] This application relates to the field of integrated circuit functional verification technology, specifically to a reference model construction and debugging method, an integrated circuit verification method, electronic equipment, and computer program products. Background Technology

[0002] In the field of integrated circuit functional verification, reference models are used to deduce the expected behavior of the design under test (DUT) based on input stimuli and compare the expected output with the actual output of the DUT to determine the functional correctness of the DUT. In other words, the reference model is a key component of the verification platform, and its modeling accuracy and maintainability directly affect verification efficiency and quality. Currently, reference models based on system hardware description languages ​​or general verification methodologies generally use procedural code to directly describe the behavior of combinational and sequential logic. Specifically, for the combinational logic part of the system under test, the reference model typically calculates the output immediately upon the arrival of the input transaction; for the sequential logic part of the system under test, the reference model relies on always-procedural blocks, event-triggered mechanisms, or processing logic bound to specific clock signals to perform internal state evolutions such as register updates, FIFO queue pointer changes, and state machine state transitions when a specific clock edge arrives. Furthermore, for DUTs containing multiple clock domains, existing reference models typically establish independent timing processing logic for each clock domain and maintain various system architecture resources such as registers, memories, FIFO queues, queues, and intermediate state variables within the model. Such reference model construction methods, which rely on procedural code, suffer from the following problems: First, because procedural code is inherently bound to specific clock edges and event triggering points, when the design under test contains multiple asynchronous or synchronous clock domains, similar edge-sensitive logic must be repeatedly written for each clock domain, and cross-clock domain signal transmission and synchronization must be manually handled. This means that cross-clock domain behavior cannot be described in a declarative or modular manner, leading to complex model implementation and a high susceptibility to timing errors. Second, procedural coding encourages the distribution of state resources such as registers, FIFO queues, and queues as ordinary variables across different procedural blocks of the model. The lack of a unified state container or access interface makes state snapshots, restoration, initialization, and hierarchical composition of the model extremely difficult, severely reducing the model's maintainability and reusability. In summary, existing reference model construction methods, due to their reliance on procedural code, result in the mixing of multi-time-domain timing behavior descriptions with internal state maintenance, leading to difficulties in reference model modeling and reuse.

[0003] Therefore, providing a method that can overcome the modeling complexity and difficulty in reusing existing reference models that rely on procedural code construction is a technical problem that needs to be solved. Summary of the Invention

[0004] The technical problem solved by this application is to provide a reference model construction and debugging method, an integrated circuit verification method, an electronic device and a computer program product. This application reconstructs the processing flow of the reference model into a transaction-driven architecture, which fundamentally removes the hard binding of the existing procedural code construction method to specific clock edges and event triggering points. At the same time, it realizes centralized management and controlled updates of state resources, thereby solving the problems of modeling difficulties and model reuse caused by the complexity of multi-clock domain timing behavior description and the difficulty of maintaining state resources.

[0005] According to a first aspect of the embodiments of this application, a reference model construction method is provided, comprising: Define the triggering transaction, function input transaction, and state-visible resources of the reference model; the state-visible resources include sequential logic state resources, combinational logic state resources, and a next state buffer, wherein the next state buffer is used to store the next state candidate values ​​of the sequential logic state resources to be submitted; The reference model is divided into internal processing stages, which include a pre-processing stage, a function computation stage, and a timing submission stage, and the stage functions required for the function computation stage are constructed. The pre-stage refreshes the combined logic state resources based on the function-triggered transaction, a snapshot of the temporal logic state resources, and preset configuration rules for the combined logic state resources, and calculates the next state buffer. The function calculation stage includes multiple sub-stages, and in each sub-stage, a stage function is used to calculate the temporary update item or expected output transaction of the temporal logic state resources of that sub-stage based on the function input transaction, the snapshot of the temporal logic state resources, and the output of the pre-stage. After the temporal commit stage performs conflict detection on the temporary update item, it writes the conflict-detected temporary update item into the temporal logic state resources, completing the update of the state visible resources of the reference model. The triggering transaction is configured to correspond to a triggering event generated by the verification platform that can stimulate the design under test, and the functional input transaction is configured to be the input content that affects the functional behavior of the design under test, so as to obtain a reference model that is consistent with the functional behavior of the design under test.

[0006] Compared with existing technologies, this application reconstructs the internal processing flow of the reference model into a three-stage transaction-driven architecture. Signals that can trigger the reference model process are defined as triggering transactions according to their categories, and the internal state visible resources of the reference model are divided into combinational logic state resources and temporal logic state resources according to their properties. This fundamentally removes the hard binding of existing procedural coding methods to specific clock edges and event triggering points, while realizing centralized management and controlled updates of state resources. This solves the problems of complex description of multi-clock domain temporal behavior and difficulty in maintaining state resources. Specifically, this application configures triggering transactions as triggering events generated by the verification platform that can incentivize the design under test, abstracting different triggering events into a unified transaction. This makes the phase transformation of the reference model no longer directly dependent on specific clock edges or events, but rather driven by a transaction to advance a sequential action of the reference model. There is no need to write separate, distributed procedural processing code for each clock domain, decoupling the temporal modeling of the reference model from the underlying procedural triggering logic. This significantly reduces the modeling difficulty of multi-clock domain behavior and improves the reusability of the constructed model. In addition, unlike procedural code that distributes state resources as ordinary variables in different process blocks of the model, this application divides the state-visible resources in the reference model into combinational logic state resources and temporal logic state resources according to their properties, and processes different types of state-visible resources in different processing stages. This takes into account both combinational logic processing and temporal logic advancement, and can be used for behavioral modeling of complex modules in multiple clock domains, as well as supporting continuous tracking of architecture-level states, reducing the modeling difficulty of the reference model and improving its reusability.

[0007] In one embodiment, the triggering transaction includes at least one of a clock transaction and a control triggering transaction, and carries a trigger source identifier, a stage identifier, a barrier identifier, and stage function scheduling information required for the transformation of the reference model processing stage; wherein, the clock transaction includes clock edge and periodic advancement information, and the clock transaction carries a clock domain identifier, which is a type of trigger source identifier; The control triggering transaction includes hardware triggering information that affects the functional behavior of the design under test. The hardware triggering information includes at least one of reset information, enable information, pause information, refresh information, authorization information, and configuration change information. The control triggering transaction carries a control triggering identifier, which is used to indicate the identifier of the hardware triggering information corresponding to the control triggering transaction. The control triggering identifier is one of the triggering source identifiers.

[0008] In the above embodiments, the triggering transaction defined in this application carries a trigger source identifier, a stage identifier, a barrier identifier, and stage function scheduling information, which can provide clear and direct indications for the transition of processing stages within the reference model. Furthermore, the barrier identifier carried in the triggering transaction declaratively describes the cross-clock domain synchronization relationship, eliminating the need to embed the timing logic of the triggering event into the model in a procedural manner during the reference model construction phase. Thus, timing synchronization constraints and model functional logic are decoupled, effectively eliminating the modeling complexity and maintenance burden caused by procedural timing processing, thereby significantly reducing the modeling difficulty of the reference model.

[0009] In one implementation, when the triggering transaction includes a clock transaction, the reference model transforms the clock transaction into a global phase-driven transaction. The global phase-driven transaction triggers the reference model to perform a reference model calculation in the order of pre-phase, function computation phase, and timing commit phase.

[0010] In one implementation, when the triggering transaction includes a control triggering transaction, the reference model transforms the control triggering transaction into a local phase-driven transaction, and the local phase-driven transaction triggers the reference model to execute the corresponding processing phase; and when the processing phase is a time-commit phase, the triggering condition further includes: the phase function within the same barrier has generated a phase temporary update item to be time-committed.

[0011] In one implementation, the reference model performs the following operations during the function computation phase: Based on the trigger source identifier, stage identifier, barrier identifier, and stage function scheduling information carried by the triggering transaction, the barriers, sub-stage sequences, sub-stage processing order, and stage functions to be called in each sub-stage that the current reference model needs to process are determined; the trigger source identifier is at least one of clock domain identifier and control trigger identifier; In the current barrier, each sub-stage in the sub-stage sequence is processed according to the sub-stage processing order; and in each sub-stage, each stage function that needs to be scheduled reads the pre-stage refreshed combinational logic state resources, and combines the current functional input transaction and the snapshot of the timing logic state resources to output a stage temporary update item or an expected output transaction; the stage temporary update item is used to represent the change information of the timing logic state resources that need to be written in the timing commit stage, including at least one of virtual memory content changes, register image changes, command queue pointer changes, counter changes, and state machine state changes; the expected output transaction is the result output after the reference model simulates the functional behavior of the design under test, and this result is used to compare with the actual output of the design under test.

[0012] In one implementation, the sequential logic state resources include: register image, virtual memory content, register array, queue, queue pointer, state machine state, counter, and result buffer.

[0013] In one implementation, the combinational logic state resources include: combinational output, arbitration result, authorization, combinational read data, ready derived value, valid derived value, and output buffer.

[0014] In one implementation, the pre-stage further calculates an expected output, which characterizes the result output after the reference model simulates the functional behavior of the design under test in the pre-stage, and is stored in the combinational logic state resource.

[0015] According to a second aspect of the embodiments of this application, a reference model debugging method is provided, the debugging method being used to debug a reference model constructed by the above-described construction method, including: Select multiple debug trigger transactions from the debug trigger transaction set and select multiple debug function input transactions from the debug function input transaction set. Input the debug trigger transactions and debug function input transactions into the reference model. The reference model monitors changes in visible state resources. When any visible state resource changes, the change is encapsulated as a state change transaction. The state change transaction includes at least one of the following: the category of the visible state resource, its identifier, its value before the change, its value after the change, the stage identifier of the change, the trigger source identifier of the change, and the sequence identifier. The sequence identifier is used to record the output order of the state change transactions generated by the reference model within the same period or the same barrier. The state change transactions are unpacked and reconstructed according to predefined rules and transformed into monitoring interface signals; The internal state evolution process of the reference model is observed based on the monitoring interface signal, and the reference model is debugged based on the observation results.

[0016] Unlike existing technologies, this application encapsulates the changes in internal visible state resources caused by each triggering of the reference model into state change transactions. This gives the internal state evolution process of the model a unified and structured expression, facilitating the formation of a stable debugging observation surface. This improves the intuitiveness of the reference model debugging process and the efficiency of problem localization. In addition, this application unpacks and reconstructs state change transactions into visual monitoring interface information according to preset rules. This eliminates the need for the reference model body to be directly coupled to specific display signals, log interfaces, or waveform interfaces, thus separating the reference model kernel from the observation logic. Through this technique, this application can perform targeted debugging based on visual monitoring interface signals when facing different verification platforms, different designs under test, or different debugging views, improving the reusability and expansion of the reference model in multiple scenarios.

[0017] According to a third aspect of the embodiments of this application, an integrated circuit verification method is provided, comprising: For the design under test in the integrated circuit to be verified, obtain its corresponding trigger transactions and functional input transactions; The reference model is used to trigger the transaction and drive the internal processing stage to output the expected output transaction based on the functional input transaction; the reference model is constructed using the above-described reference model construction method. Obtain the actual output of the same design under test under the same triggering event; The expected output transaction and the actual output are used to verify the design under test in the integrated circuit.

[0018] According to a fourth aspect of the embodiments of this application, an electronic device is provided, including a memory and a processor, wherein the memory is used to store a computer program executable by the processor; and the processor is used to execute the computer program in the memory to implement the method described above.

[0019] According to a fifth aspect of the embodiments of this application, a computer program product is provided, including a computer program that, when executed by a processor, implements the above-described method. Attached Figure Description

[0020] Figure 1 This is a flowchart illustrating a reference model construction method according to an exemplary embodiment; Figure 2 This is a flowchart illustrating a reference model debugging method according to an exemplary embodiment; Figure 3 This is a flowchart illustrating an integrated circuit verification method according to an exemplary embodiment; Figure 4 This is a block diagram illustrating an electronic device according to an exemplary embodiment. Detailed Implementation

[0021] Unless otherwise defined, the technical or scientific terms used in this specification and claims shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. Specific embodiments of this application will be described below in conjunction with the accompanying drawings. It should be noted that, in order to provide a concise description, this specification cannot exhaustively describe all features of the actual embodiments. Without departing from the spirit and scope of this application, those skilled in the art can modify and substitute the embodiments of this application, and the resulting embodiments are also within the protection scope of this application.

[0022] The construction of existing reference models relies on procedural code. This modeling approach uses procedural timing code to describe behavioral evolution across different clock domains, resulting in strong coupling between the reference model implementation and underlying timing events. This is particularly problematic in multi-clock domain scenarios, requiring the maintenance of multiple trigger paths and update sequences. Furthermore, procedural coding encourages the distribution of state resources such as registers, FIFO queues, and queues as ordinary variables across different procedural blocks of the model, lacking a unified state container or access interface. This makes state snapshots, restorations, initialization, and hierarchical composition of the model exceptionally difficult. Therefore, the problems arising from using procedural coding for reference model construction result in high development complexity and poor code reusability.

[0023] To address the aforementioned technical problems, this application proposes a reference model construction and debugging method, an integrated circuit verification method, an electronic device, and a computer program product, which can overcome the problems of modeling complexity and difficulty in reuse caused by existing methods that rely on procedural code to construct reference models.

[0024] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0025] One embodiment of this application provides a method for constructing a reference model. This method can be applied to electronic devices such as processors and display chips. Please refer to [link to relevant documentation]. Figure 1 The reference model construction method may include the following steps 101 to 103: Step 101: Define the triggering transaction, function input transaction, and state visibility resources for the reference model.

[0026] Triggering transactions correspond to triggering events generated by the verification platform that can incentivize the design under test. They are used to drive the processing phase of the reference model. Triggering transactions must carry the trigger source identifier, phase identifier, barrier identifier, and phase function scheduling information required for the transformation of the reference model's processing phase.

[0027] Functional input transactions are input content that affects the functional behavior of the design under test, including at least one of data, commands, addresses, read / write attributes, configuration writes, and handshake information.

[0028] In one embodiment, the triggering transaction includes a clock transaction, which includes clock edges and periodic advance information. The clock transaction carries a clock domain identifier, which is one type of trigger source identifier. In this embodiment, the default reference model is clock-driven. That is, when the triggering transaction includes a clock transaction, the scheduler within the reference model converts the clock transaction into a global phase-driven transaction according to mapping rules. This global phase-driven transaction triggers the reference model to perform a reference model computation in the order of the pre-phase, function computation phase, and timing commit phase.

[0029] In another embodiment, the triggering transaction includes a control triggering transaction, which includes hardware trigger class information that affects the functional behavior of the design under test. The hardware trigger class information includes at least one of reset information, enable information, pause information, refresh information, authorization information, and configuration change information. The control triggering transaction carries a control trigger identifier, which is used to indicate the identifier of the hardware trigger class information corresponding to the control triggering transaction. The control trigger identifier is a type of trigger source identifier. In this embodiment, the scheduler within the reference model converts the received control triggering transaction into a local stage-driven transaction, which triggers the reference model to execute the corresponding processing stage. When the processing stage is a timing commit stage, the triggering condition further includes: the stage function within the same barrier has already generated a stage temporary update item to be time-committed.

[0030] In another embodiment, the triggering transaction includes a clock transaction and a control triggering transaction. In this case, the reference model is triggered by a clock transaction to complete a processing flow. When a control triggering transaction is received, the process phase or sub-phase corresponding to the control triggering transaction is executed.

[0031] It should be noted that when the triggering transaction includes the control triggering transaction, it is generally in the simulation and debugging stage of the reference model, the single-step observation stage, or the stage where partial replay is required.

[0032] In this embodiment, the state-visible resources include sequential logic state resources, combinational logic state resources, and a next state buffer. The next state buffer is used to store the next state candidate values ​​of the sequential logic state resources to be submitted.

[0033] In one embodiment, the sequential logic state resources include: register image, virtual memory content, register array, queue, queue pointer, state machine state, counter, and result buffer.

[0034] In one embodiment, the combinational logic state resources include: combinational output, arbitration result, authorization, combinational read data, ready derived value, valid derived value, and output buffer.

[0035] Step 102: Divide the internal processing stages of the reference model. The internal processing stages include the pre-stage, the function computation stage, and the timing submission stage, and construct the stage functions required for the function computation stage.

[0036] To facilitate understanding, the three processing stages within the reference model will now be explained in detail: 1) Pre-stage.

[0037] This stage is used to refresh the combinational logic state resources immediately before the function computation stage. The immediate refresh means that the combinational logic state resources take effect immediately during this process and are immediately visible to functions in subsequent stages. They do not need to wait for timing commits and are not subject to conflict detection.

[0038] Specifically, when the reference model is in the pre-stage, the reference model collects snapshots of the current input function triggering transactions, the sequential logic state resources, and the preset configuration rules of the combinational logic state resources. Based on the above data, the combinational logic state resources are refreshed, and the next state buffer is calculated to provide candidate state resources or transitional state resources for subsequent stage functions to read.

[0039] It is important to emphasize that when the triggering transaction includes a clock transaction, and the clock transaction only triggers the advancement of the reference model processing phase without carrying functional fields, then the clock transaction does not participate in the pre-phase; however, when the clock transaction carries barrier information, then the clock transaction also serves as the pre-phase input and participates in the update of combinational logic state resources.

[0040] Furthermore, in this pre-stage, the reference model also calculates the expected output, which is used to characterize the result of the reference model simulating the functional behavior of the design under test in the pre-stage. The expected output is stored in the output cache or combinational output in the combinational logic state resources. Whether the expected output is used as the final output of the reference model needs to be determined by the function calculation stage.

[0041] 2) Function calculation stage.

[0042] This phase includes multiple sub-phases: phase 0 to phase N. In each sub-phase, the phase function is used to calculate the temporary update item or expected output transaction of the temporal logic state resource of the sub-phase based on the functional input transaction, the snapshot of the temporal logic state resource, and the output of the pre-phase.

[0043] In one embodiment, the reference model performs the following operations during the function computation phase: Step 1021: Based on the trigger source identifier, stage identifier, barrier identifier, and stage function scheduling information carried by the triggering transaction, determine the barriers, sub-stage sequences, sub-stage processing order, and stage functions to be called for each sub-stage that the current reference model needs to process.

[0044] In this step, the trigger source identifier is at least one of a clock domain identifier and a control trigger identifier.

[0045] Step 1022: In the current barrier, each sub-stage in the sub-stage sequence is processed according to the sub-stage processing order. Specifically, in each sub-stage, each stage function that needs to be scheduled reads the pre-stage refreshed combinational logic state resources, and combines the current functional input transaction and the snapshot of the timing logic state resources to output the stage temporary update item or the expected output transaction.

[0046] It should be noted that the temporary update item in the stage is used to represent the change information of the timing logic state resources that need to be written in the timing commit stage, including at least one of the following: virtual memory content change, register image change, command queue pointer change, counter change, and state machine state change; the expected output transaction is the result output after the reference model simulates the functional behavior of the design under test, and this result is used to compare with the actual output of the design under test.

[0047] It should be emphasized that the processing order of the above sub-stages is determined according to the data dependencies or modeling order requirements between multiple sub-stages. They can be executed in parallel, sequentially, or in a specific order. In addition, if there is no valid input or no need to update a stage at the current moment, a no-operation can be performed on the corresponding sub-stage or no stage temporary update item can be generated.

[0048] 3) After performing conflict detection on the temporary update items during the timing submission phase, the temporary update items that have passed the conflict detection are written into the timing logic state resources, thus completing the update of the state visible resources of the reference model.

[0049] In one embodiment, when the triggering transaction includes a clock transaction, the timing commit phase is triggered after the pre-phase and function computation phases have been executed sequentially in the reference model.

[0050] In another embodiment, when the triggering transaction includes a control triggering transaction, the timing commit phase is triggered when the reference model receives the triggering control transaction and the function computation phase has generated timing logic state resources that can be used for timing commit.

[0051] Step 103: Configure the triggering transaction to correspond to the triggering event generated by the verification platform and that can stimulate the design under test, and configure the functional input transaction to the input content that affects the functional behavior of the design under test, so as to obtain a reference model that is consistent with the functional behavior of the design under test.

[0052] Through the above configuration, the triggering transactions and functional input transactions of the reference model are associated with the triggering events of the design under test and the input content that affects its functional behavior. This ensures that the final reference model can simulate the expected output transactions of the functional behavior of the design under test based on the corresponding control input transactions, driven by the corresponding triggering transactions.

[0053] To demonstrate the feasibility of the method provided in this application, an embodiment is also provided, in which the reference model constructed by the above-described construction method is used to verify the design under test in a practical general verification methodology verification environment, specifically including: Step 1: The reference model enters the pre-stage. In the pre-stage, the combinational logic state resources are refreshed based on the functional input transactions, snapshots of the temporal logic state resources, and the preset configuration rules of the combinational logic state resources, and the next state buffer is calculated.

[0054] Step 11: In this embodiment, the input function is a command queue. The reference model reads snapshots of each command queue and timing logic state resource in the pre-stage, and executes the command arbitration function according to the priority, validity or readiness conditions of each channel and the preset arbitration configuration rules.

[0055] Step 12: Instruct the arbitration function to calculate the combinational logic state resources for this round, so that they can be used uniformly in subsequent sub-stages.

[0056] This stage does not directly modify the sequential logic state resources, but only refreshes the combinational logic state resources and prepares the next state buffer.

[0057] Step 2: The reference model enters the function computation stage, which includes multiple sub-stages. Each sub-stage uses the corresponding stage function to calculate the temporary update item of the temporal logic state resource based on the functional input transaction, the snapshot of the temporal logic state resource, and the next state buffer of the pre-stage output.

[0058] In this step, each sub-stage no longer re-executes arbitration, but instead reads the authorization commands from the combinational logic state resources that have been refreshed in the pre-stage, determines the corresponding command queue item to be popped, and accesses the virtual memory maintained inside the reference model to perform calculations for read, write, count update, flag update or other resource updates, generating temporary update items for the virtual memory and related resources.

[0059] It should also be noted that, depending on the application scenario of the reference model, this step will also calculate the expected output. This expected output can be used to locate the timing and combinatorial behavior deviations between the design under test and the reference model. When the arbitration logic output of the design under test is inconsistent with the pre-stage arbitration result of the reference model, the source of the deviation can be observed through combinatorial logic state resources such as authorization validity, authorization channel, and authorization command. When the timing of enqueueing, dequeueing, or popping from the command queue is off by one beat, the problem can be located through the temporary update items of the sub-stage. When the virtual memory access order is incorrect or the response transaction timing is inconsistent, the specific problem can also be found by comparing the temporary update items of each stage with the visible state after submission.

[0060] Step 3: The reference model enters the timing submission stage, where conflict detection is performed on the temporary update items generated above. The temporary update items that pass the conflict detection are then formally written into the corresponding timing logic state resources. Another embodiment of this application provides a reference model debugging method. Please refer to... Figure 2 The reference model debugging method is used to debug the reference model constructed by the above-mentioned reference model construction method, and may include the following steps 201 to 204: Step 201: Select multiple debug trigger transactions from the debug trigger transaction set and multiple debug function input transactions from the debug function input transaction set, and input the debug trigger transactions and debug function input transactions into the reference model.

[0061] Step 202: Monitor changes in the state-visible resources of the reference model. When any state-visible resource changes, encapsulate the change in the state-visible resource as a state change transaction. The state change transaction includes at least one of the following: the category of the state-visible resource, its identifier, the value before the change, the value after the change, the stage identifier of the change, the trigger source identifier of the change, and the sequence identifier. The sequence identifier is used to record the output order of the state change transactions generated by the reference model within the same period or the same barrier.

[0062] Step 203: Unpack and reconstruct the state change transaction according to predefined rules, and convert it into a monitoring interface signal.

[0063] Step 204: Observe the internal state evolution process of the reference model based on the monitoring interface signal, and debug the reference model based on the observation results.

[0064] Specifically, this step is implemented using one or more dedicated reference monitoring interfaces. By driving the monitoring interface signals to the reference monitoring interface, real-time observation, waveform presentation, and debugging analysis of the internal state evolution process of the reference model can be achieved.

[0065] As can be seen, this application unpacks and visualizes state change transactions through an external monitoring module, so that the reference model body does not need to be directly coupled to specific display signals, log interfaces or waveform interfaces, thereby achieving the separation of the model kernel and the observation logic, which is beneficial for reuse and expansion between different verification platforms, different designs under test or different debugging views.

[0066] One embodiment of this application also provides a reference model construction and debugging system, which includes a transaction encapsulation layer, a reference model core processing layer and a debugging layer, wherein the debugging layer does not work when the reference model is constructed.

[0067] When this system is used for reference model construction, the transaction encapsulation layer and the reference model core processing layer perform the following steps: Step A1: Define the triggering transaction, function input transaction, and state visibility resources for the reference model.

[0068] In this step, the triggering transaction, function input transaction, and state visibility resources are defined similarly to those defined in step 101, and will not be repeated here.

[0069] Step A2 involves dividing the internal processing stages of the reference model, which include a pre-processing stage, a function computation stage, and a timing submission stage. The stage functions required for the function computation stage are then constructed to obtain the initial reference model framework, which is then stored in the core processing layer of the reference model.

[0070] Furthermore, the processing steps and conversion conditions of each internal processing stage are similar to those in step 102, so they will not be repeated here.

[0071] Step A3: In the transaction encapsulation layer, the triggering transaction is configured to correspond to the triggering event generated by the verification platform and can stimulate the design under test, and the functional input transaction is configured to the input content that affects the functional behavior of the design under test, so as to obtain a reference model that is consistent with the functional behavior of the design under test. Based on this reference model, the initial reference model framework is updated in the reference model core processing layer.

[0072] When this system is used for reference model debugging, each layer in the system performs the following steps: Step B1: Select multiple debug trigger transactions from the debug trigger transaction set stored in the transaction encapsulation layer, and select multiple debug function input transactions from the debug function input transaction set. Input the debug trigger transactions and debug function input transactions into the core processing layer of the reference model.

[0073] Step B2: The debugging layer monitors changes in the state-visible resources of the reference model in the reference model processing layer. When any state-visible resource changes, the change in the state-visible resource is encapsulated as a state change transaction.

[0074] State change transactions include at least one of the following: category of state-visible resource, identifier, value before change, value after change, stage identifier of change, trigger source identifier of change, and sequence identifier; the sequence identifier is used to record the output order of state change transactions generated by the reference model within the same cycle or the same barrier. In step B3, the debugging layer unpacks and reconstructs the state change transactions according to predefined rules, transforming them into monitoring interface signals; it observes the internal state evolution process of the reference model based on the monitoring interface signals, and debugs the reference model based on the observation results.

[0075] In summary, the technical solution provided in this application has the following advantages: 1) This solution abstracts the inputs and triggering events of the reference model into transaction-level objects and divides the internal behavior of the reference model into multiple stages, decoupling the behavioral modeling of the reference model from fragmented procedural triggering code. Compared to writing independent processing logic for each clock domain or interface, this application can form a clear scheduling relationship between processing stages, and clarifies that the pre-stage refreshes the combinational logic state resources, the function calculation stage calculates the changes in the sequential logic state resources, and the sequential logic state resources are submitted in the timing submission stage. This phased processing mechanism allows changes related to combinational logic and sequential logic in the design under test to be expressed according to different effective stages, and maintains traceability through unified submission rules. This reduces the development and maintenance complexity of multi-trigger source and multi-time domain reference models and improves the reusability of the constructed reference model.

[0076] 2) This application unifies the updates of memory-based resources such as registers, memory contents, queue pointers, queues, and state machines involved in the modeling process into structured sequential logical state resources. As a result, the reference model can clearly record the source stage, triggering transaction, value before update, value after update, and commit order of each change in sequential logical state resources, avoiding the problem of unclear state evolution caused by relying solely on temporary variables, logs, or local waveform observations.

[0077] 3) This application proposes a reference model debugging method in response to the provided reference model construction method. The method debugs the constructed reference model that has transaction-level driving characteristics and can perform combinational logic and sequential logic processing in stages. By expanding the changes inside the reference model to the monitoring interface, the debugging visibility is improved. Since the reference model only subscribes to normalized state change transactions and does not intrude into the internal implementation of each stage function, this process is conducive to reuse in different designs under test, different verification platforms and different debugging views.

[0078] Another embodiment of this application provides an integrated circuit verification method, which verifies the reference model constructed by the above-described reference model construction method, and the process is as follows: Figure 3 As shown, it includes: Step 301: For the design under test in the integrated circuit to be verified, obtain its corresponding trigger transaction and functional input transaction.

[0079] The triggering transactions and control input transactions mentioned in this step are the same as those mentioned in step 101, so they will not be repeated here.

[0080] Step 302: Utilize the trigger transaction-driven reference model to execute the internal processing phase of the functional input transaction and output the expected output transaction.

[0081] In this step, the process of the reference model performing the internal processing stage is similar to that in step 102, so it will not be described again.

[0082] Step 303: Obtain the actual output of the same design under test under the same triggering event.

[0083] Step 304: Verify the design under test in the integrated circuit based on the expected output transaction and the actual output. Embodiments of this application also propose an electronic device including a processor and a memory; the memory is used to store a computer program executable by the processor; the processor is used to execute the computer program in the memory to implement the reference model construction method or reference model debugging method of any of the above embodiments.

[0084] Embodiments of this application also propose a computer program product, including a computer program that, when executed by a processor, implements the reference model construction method and reference model debugging method of any of the above embodiments.

[0085] Regarding the system in the above embodiments, the specific manner in which the processor performs the operation has been described in detail in the embodiments related to the method, and will not be elaborated here.

[0086] Embodiments of this application also provide an electronic device 600, such as... Figure 4 As shown, the electronic device 600 includes a memory 601 and a processor 602. The memory 601 is used to store computer programs executable by the processor 602; the processor 602 is used to execute the computer programs in the memory 601 to implement the reference model construction method or reference model debugging method provided in any of the above embodiments.

[0087] The electronic device 600 also includes a communication interface 603. The processor 602, memory 601, and communication interface 603 are connected via a communication bus and communicate with each other.

[0088] Processor 602 may be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits used to control the execution of programs in the above scheme.

[0089] Communication interface 603 is used to communicate with other devices or communication networks, such as Ethernet, Radio Access Network (RAN), Wireless Local Area Networks (WLAN), etc.

[0090] The memory 601 may be a read-only memory (ROM) or other type of static storage device capable of storing static information and instructions, random access memory (RAM) or other type of dynamic storage device capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto. The memory may exist independently and be connected to the processor via a bus. The memory may also be integrated with the processor.

[0091] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "multiple" refers to two or more unless otherwise expressly defined.

[0092] The above description of the embodiments is intended to enable those skilled in the art to understand and apply this application. It will be apparent to those skilled in the art that various modifications can be easily made to these embodiments, and the general principles described herein can be applied to other embodiments without creative effort. Therefore, this application is not limited to the embodiments described herein, and any improvements and modifications made by those skilled in the art based on the disclosure of this application without departing from the scope and spirit of this application are within the scope of this application.

Claims

1. A method for constructing a reference model, characterized in that, include: Define the triggering transactions, functional input transactions, and state visibility resources of the reference model; The triggering transaction is used to drive the processing phase of the reference model; The state-visible resources include sequential logic state resources, combinational logic state resources, and a next state buffer. The next state buffer is used to store the next state candidate values ​​of the sequential logic state resources to be submitted. The reference model is divided into internal processing stages, including a pre-processing stage, a function computation stage, and a timing submission stage. The stage functions required for the function computation stage are constructed. The pre-processing stage refreshes the combined logic state resources based on function-triggered transactions, snapshots of timing logic state resources, and preset configuration rules for combined logic state resources, and calculates the next state buffer. The function computation stage includes multiple sub-stages, and in each sub-stage, the stage function calculates the temporary update item or expected output transaction of the timing logic state resources for that sub-stage based on the function input transaction, the snapshot of the timing logic state resources, and the output of the pre-processing stage. The timing submission stage performs conflict detection on the temporary update item and writes the conflict-detected temporary update item into the timing logic state resources, completing the update of the state-visible resources of the reference model. The triggering transaction is configured as a triggering event generated by the verification platform that can stimulate the design under test, and the functional input transaction is configured as input content that affects the functional behavior of the design under test, so as to obtain a reference model that is consistent with the functional behavior of the design under test.

2. The reference model construction method as described in claim 1, characterized in that, The triggering transaction includes at least one of clock transaction and control triggering transaction, and carries the trigger source identifier, stage identifier, barrier identifier and stage function scheduling information required for the transformation of the reference model processing stage; The clock transaction includes clock edge and period advancement information, and the clock transaction carries a clock domain identifier, which is one type of trigger source identifier; The control triggering transaction includes hardware triggering information that affects the functional behavior of the design under test. The hardware triggering information includes at least one of reset information, enable information, pause information, refresh information, authorization information, and configuration change information. The control triggering transaction carries a control triggering identifier, which is used to indicate the identifier of the hardware triggering information corresponding to the control triggering transaction. The control triggering identifier is one of the triggering source identifiers.

3. The reference model construction method as described in claim 2, characterized in that, When the triggering transaction includes a clock transaction, the reference model transforms the clock transaction into a global phase-driven transaction. The global phase-driven transaction triggers the reference model to perform a reference model calculation in the order of pre-phase, function computation phase, and timing commit phase.

4. The reference model construction method as described in claim 2, characterized in that, When the triggering transaction includes a control triggering transaction, the reference model transforms the control triggering transaction into a local phase-driven transaction, and the local phase-driven transaction triggers the reference model to execute the corresponding processing phase. Furthermore, when the processing stage is the timing submission stage, the triggering condition also includes: the stage function within the same barrier has generated a stage temporary update item to be submitted for timing.

5. The reference model construction method as described in claim 2, characterized in that, The reference model performs the following operations during the function computation phase: Based on the trigger source identifier, stage identifier, barrier identifier, and stage function scheduling information carried by the triggering transaction, the barriers, sub-stage sequences, sub-stage processing order, and stage functions to be called in each sub-stage that the current reference model needs to process are determined; the trigger source identifier is at least one of clock domain identifier and control trigger identifier; In the current barrier, each sub-stage in the sub-stage sequence is processed according to the sub-stage processing order; and in each sub-stage, each stage function that needs to be scheduled reads the pre-stage refreshed combinational logic state resources, and combines the current functional input transaction and the snapshot of the timing logic state resources to output a stage temporary update item or an expected output transaction; the stage temporary update item is used to represent the change information of the timing logic state resources that need to be written in the timing commit stage, including at least one of virtual memory content changes, register image changes, command queue pointer changes, counter changes, and state machine state changes; the expected output transaction is the result output after the reference model simulates the functional behavior of the design under test, and this result is used to compare with the actual output of the design under test.

6. The reference model construction method as described in claim 1, characterized in that, The sequential logic state resources include: register image, virtual memory content, register array, queue, queue pointer, state machine state, counter, and result buffer.

7. The reference model construction method as described in claim 1, characterized in that, The combined logic state resources include: combined output, arbitration result, authorization, combined read data, ready derived value, valid derived value, and output buffer.

8. The reference model construction method as described in claim 1, characterized in that, The pre-stage also calculates the expected output, which is used to characterize the result output after the reference model simulates the functional behavior of the design under test in the pre-stage, and is stored in the combinational logic state resource.

9. A reference model debugging method, characterized in that, The debugging method is used to debug a reference model constructed by any one of claims 1 to 8, including: Select multiple debug trigger transactions from the debug trigger transaction set and select multiple debug function input transactions from the debug function input transaction set. Input the debug trigger transactions and debug function input transactions into the reference model. The reference model monitors changes in visible state resources. When any visible state resource changes, the change is encapsulated as a state change transaction. The state change transaction includes at least one of the following: the category of the visible state resource, its identifier, its value before the change, its value after the change, the stage identifier of the change, the trigger source identifier of the change, and the sequence identifier. The sequence identifier is used to record the output order of the state change transactions generated by the reference model within the same period or the same barrier. The state change transactions are unpacked and reconstructed according to predefined rules and transformed into monitoring interface signals; The internal state evolution process of the reference model is observed based on the monitoring interface signal, and the reference model is debugged based on the observation results.

10. An integrated circuit verification method, characterized in that, include: For the design under test in the integrated circuit to be verified, obtain its corresponding trigger transactions and functional input transactions; The triggering transaction-driven reference model is used to process the functional input transaction and output the expected output transaction. The reference model is constructed using the reference model construction method described in any one of claims 1 to 8; Obtain the actual output of the same design under test under the same triggering event; The expected output transaction and the actual output are used to verify the design under test in the integrated circuit.

11. An electronic device, characterized in that, The system includes a memory and a processor, wherein the memory stores a computer program executable by the processor; and the processor executes the computer program in the memory to implement the reference model construction method as described in any one of claims 1 to 8, the reference model debugging method as described in claim 9, or the integrated circuit verification method as described in claim 10.

12. A computer program product, comprising a computer program, characterized in that, When executed by a processor, the computer program implements the reference model construction method as described in any one of claims 1 to 8, the reference model debugging method as described in claim 9, or the integrated circuit verification method as described in claim 10.

Images