Clock detection method, system, electronic device, storage medium and computer program product

Abstract

This application relates to a clock detection method, system, electronic device, storage medium, and computer program product, comprising: acquiring the measured value of the clock cycle for the current period; ignoring the corresponding measured value and disabling assertions during the reset validity period; storing the measured value in a queue during the baseline calibration period or normal period, and disabling assertions during the baseline calibration period; calculating the moving baseline mean and moving standard deviation during the normal period; calculating the absolute error between the measured value and the expected value, and making frequency compliance assertions based on the absolute error; calculating the dynamic statistical envelope based on the moving baseline mean, moving standard deviation, and sensitivity coefficient, and making transient disturbance and glitch assertions based on the measured value and the dynamic statistical envelope; and determining whether the clock violates regulations for cycles in the normal period based on the results of the above two types of assertions. The technical solution of this application can achieve accurate detection in scenarios of dynamic frequency changes, single-cycle glitch scenarios, and slow frequency drift scenarios.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to a clock detection method, system, electronic device, storage medium, and computer program product. Background Technology

[0002] In digital integrated circuit front-end simulation verification, clock signals and reset signals need to be checked to ensure the correctness of circuit timing functions. Existing clock signal checking methods mainly fall into two categories: First, waveform post-processing, which involves reading waveform database files using a scripting language after simulation, calculating the time difference between adjacent clock transitions, and determining if the clock period is within specifications. This method is offline and cannot detect clock anomalies in real time during simulation. Second, SystemVerilog assertions based on fixed thresholds. This method typically triggers at each clock rising edge, checking whether the next rising edge occurs after a preset delay. Compared to waveform post-processing, it overcomes the limitation of real-time monitoring. However, this approach still has several technical drawbacks: Firstly, the anomaly detection threshold is fixed and not adaptive, unable to adapt to dynamically changing clock signals. For common verification scenarios such as dynamic frequency conversion clocks and spread spectrum clocks, the static threshold cannot dynamically adjust with real-time clock parameters. Users must manually modify the threshold, recompile the verification environment, or develop multiple sets of differentiated assertion codes to adapt to different operating conditions. On the one hand, fixed threshold assertions increase verification costs and reduce the reusability of the verification environment. On the other hand, fixed threshold assertions have insufficient detection accuracy and suffer from both false alarms and missed detections. For slow frequency drift scenarios, the deviation between adjacent clock cycles is small, and fixed thresholds cannot identify subtle timing changes, making it difficult to achieve early warning of faults. For single-cycle clock glitches with extremely short durations, the assertion also cannot effectively detect them, resulting in false alarms. In addition, after the reset is released, the phase-locked loop has not yet completed locking and the clock has inherent jitter. Traditional assertions will immediately start clock detection after the reset is lifted, which cannot distinguish between normal jitter in the stable phase of the phase-locked loop and real clock faults, thus generating a large number of false alarms.

[0003] Therefore, existing technologies lack a clock detection scheme that can simultaneously accommodate the non-steady-state clock characteristics during the initial stage of PLL locking, the periodic modulation characteristics of spread spectrum clock, and the transient abnormal characteristics of single-cycle glitches or gradual drift in a single verification environment, without requiring manual switching of fixed thresholds or recompiling of the verification environment. Summary of the Invention

[0004] The technical problem solved by this application is to provide a clock detection method, system, electronic device, storage medium and computer program product, which calculates the mean of the sliding baseline and the sliding standard deviation based on the sliding time window, thereby constructing a dynamic statistical envelope. In a single verification environment, it is compatible with the non-steady clock characteristics in the early stage of phase-locked loop locking, the periodic modulation characteristics of the spread spectrum clock, and the transient abnormal characteristics of single-cycle glitches, avoiding the problems of needing to manually switch fixed thresholds and needing to recompile the verification environment.

[0005] According to a first aspect of the embodiments of this application, a clock detection method is provided, comprising: Obtain the measured value of the clock cycle of the current period of the clock signal to be detected; If the current cycle state is within the reset validity period, ignore the measured value of the clock cycle corresponding to that cycle and disable assertions; When the current cycle is in the baseline calibration period or normal period, the measured value of the clock cycle corresponding to the cycle is stored in the sliding window data queue, and assertions are disabled when it is in the baseline calibration period; the baseline calibration period is N consecutive cycles after reset release, and N is a positive integer greater than or equal to the depth of the sliding window data queue; When the current cycle is in a normal period, after storing the measured value of the clock cycle of the current cycle into the sliding window data queue, the sliding baseline mean and sliding standard deviation are calculated based on all the data in the sliding window data queue. Assertions are enabled for cycles in the normal period. The absolute error between the measured and expected clock cycle values ​​is calculated, and frequency compliance assertions are performed based on the absolute error. A dynamic statistical envelope is calculated based on the sliding baseline mean, sliding standard deviation, and preset sensitivity coefficients. Transient disturbance and glitches assertions are performed based on the measured clock cycle values ​​and the dynamic statistical envelope. The dynamic statistical envelope includes an upper limit dynamic statistical envelope and a lower limit dynamic statistical envelope. For cycles in the normal period, the clock violation is determined based on the results of the frequency compliance assertion and the results of the transient disturbance and glitches assertion.

[0006] The method provided in this application generates a dynamic threshold by statistically analyzing the mean and standard deviation of the clock cycle using a sliding window. It optimizes the assertion logic using the reset valid signal and the baseline calibration period, abandoning the traditional fixed threshold and fixed assertion scheme. This method is compatible with the non-steady-state clock characteristics in the initial stage of PLL locking, the periodic modulation characteristics of spread spectrum clocks, and the transient abnormal characteristics of single-cycle glitches, thus improving clock detection accuracy and the reusability of the detection method. On one hand, this application employs different processing methods for different clock states. During the reset validity period, clock detection assertions are disabled, and abnormal sampling values ​​with excessively large cycles caused by clock gating are eliminated, avoiding detection interference caused by such invalid gating signals. After reset release, the unstable phase of the PLL is included in the baseline calibration period. During this phase, assertions are disabled, but clock cycle sampling values ​​are retained and participate in the dynamic statistical envelope calculation, adaptively adapting to the initial characteristics of clock oscillation, effectively solving the false alarm problem caused by clock instability at the moment of reset. On the other hand, this application utilizes a sliding window statistical method to calculate the sliding standard deviation and the sliding baseline mean based on the obtained measured clock cycle value. The sliding standard deviation is used to quantify the normal jitter range of the clock, and the dynamic statistical envelope is used to define the envelope boundary of the normal clock behavior. This ensures that some random, normal jitter with an amplitude on the same order of magnitude as the sliding standard deviation is within the envelope, such as jitter caused by the periodic modulation characteristics of the spread spectrum clock, thus avoiding misjudgment of this type of jitter. As for glitches or gradual drift, both exhibit systematic deviations with amplitudes significantly greater than normal jitter, and do not fall within the dynamic statistical envelope, thus they can be assertively detected. For slow frequency drift, the sliding baseline mean has the ability to follow and track, but there is an upper limit to the tracking rate. When the drift continues to develop in the same direction and exceeds the tracking ability of the mean, the clock cycle will continue to break through the dynamic statistical envelope, thereby achieving early prediction of frequency drift. It is important to emphasize that this application employs a dual-dimensional independent detection architecture: the first-dimensional frequency compliance assertion is based on a preset expected period, while the second-dimensional transient disturbance and glitch assertion is based on a dynamic statistical envelope obtained through real-time statistics using a sliding window. These two assertions are independent of each other, decoupling the detection configuration from the actual clock operating conditions. In summary, this application can simultaneously accommodate the non-steady-state clock characteristics during the initial phase-locked loop locking phase, the periodic modulation characteristics of the spread spectrum clock, and the transient anomalies of single-cycle glitches or gradual drift in a single verification environment, achieving accurate and reliable clock detection.

[0007] In one embodiment, the method for obtaining the measured clock cycle value is as follows: The time stamps of the effective edges of the current cycle and the effective edges of the previous cycle of the clock signal to be detected are collected; the difference between the time stamps of the current cycle and the previous cycle is calculated, and this difference is the measured clock cycle value of the current cycle; wherein the type of the effective edge is either a rising edge or a falling edge, and the type of the effective edge is the same in each calculation. In one embodiment, the mean of the sliding baseline is the mean of all measured clock cycle values ​​in the sliding window data queue. In this embodiment, because the sliding window data queue always stores the most recent multiple cycle measured values, when the spread spectrum clock modulation changes slowly, this mean will smoothly follow the central trend of the modulation curve, thereby reflecting the legitimate cycle changes caused by the spread spectrum clock as an adaptive offset of the mean of the sliding baseline, rather than a frequency error under a fixed threshold, to ensure that frequency drift of the cycle can also be detected.

[0008] In one embodiment, the sliding standard deviation is calculated as follows: ; in, Indicates the sliding standard deviation; This indicates the number of data items in the sliding window data queue. Measured value per clock cycle ; Indicates the depth of the sliding window data queue; This represents the moving baseline mean.

[0009] In one embodiment, the frequency compliance assertion based on the absolute error includes: calculating the ratio of the absolute error to the expected value; if the ratio is greater than the configuration tolerance, the assertion is determined to be a violation; otherwise, the assertion is determined to be normal.

[0010] In one embodiment, the method for calculating the upper limit dynamic statistical envelope is as follows: ; in, This indicates the upper limit of the dynamically calculated envelope; Indicates the moving baseline mean; Indicates the sliding standard deviation; The sensitivity coefficient is an integer value that satisfies the following rules: it is inversely proportional to the false alarm rate and directly proportional to the false negative rate.

[0011] In one embodiment, the method for calculating the lower limit dynamic statistical envelope is as follows: ; in, This represents the lower limit of the dynamic statistical envelope; Indicates the moving baseline mean; Indicates the sliding standard deviation; The sensitivity coefficient is an integer value that satisfies the following rules: it is inversely proportional to the false alarm rate and directly proportional to the false negative rate.

[0012] In one embodiment, the transient disturbance and glitches assertion is as follows: when the measured value of the clock cycle is greater than the upper limit dynamic statistical envelope or less than the lower limit dynamic statistical envelope, an assertion violation is determined; when the measured value of the clock cycle is less than or equal to the upper limit dynamic statistical envelope and the measured value of the clock cycle is greater than or equal to the lower limit dynamic statistical envelope, an assertion is determined to be normal.

[0013] In one embodiment, determining whether a clock violation occurs based on the results of the frequency compliance assertion and the results of the transient disturbance and glitches assertion includes: If the results of the frequency compliance assertion and the transient disturbance and glitches assertion are both normal, the clock is determined to be not in violation. If the frequency compliance assertion results in an assertion violation, but the transient disturbance and glitch assertion results in a normal assertion, the frequency test is deemed to have failed, and a clock violation is determined. If the frequency compliance assertion result is normal, but the transient disturbance and glitch assertion result is invalid, the glitch test is deemed to have failed and a clock violation is determined. If both the frequency compliance assertion and the transient disturbance and glitch assertion result in an assertion violation, and both the frequency test failure and the glitch test failure are triggered simultaneously, a clock violation is determined.

[0014] According to a second aspect of the embodiments of this application, a clock detection system is provided, the system comprising: Edge timestamp capture unit, used to obtain the measured value of the clock cycle for the current period; The dynamic gating and self-calibration unit is used to ignore the measured clock cycle value corresponding to the current cycle and disable assertions when the current cycle state is the reset validity period; when the current cycle state is the baseline calibration period or the normal period, it stores the measured clock cycle value corresponding to the current cycle into the sliding window data queue and disables assertions during the baseline calibration period; the baseline calibration period is N consecutive cycles after the reset release, and N is a positive integer greater than or equal to the depth of the sliding window data queue; The statistical feature calculation unit is used to calculate the sliding baseline mean and sliding standard deviation based on all data in the sliding window data queue after storing the measured value of the clock cycle of the current cycle into the sliding window data queue when the current cycle state is normal. The dynamic assertion checking unit is used to enable assertions for cycles in the normal period, calculate the absolute error between the measured and expected values ​​of the clock cycle, and perform frequency compliance assertions based on the absolute error; calculate the dynamic statistical envelope based on the sliding baseline mean, sliding standard deviation, and preset sensitivity coefficient, and perform transient disturbance and glitch assertions based on the measured clock cycle and the dynamic statistical envelope; for cycles in the normal period, determine whether the clock is in violation based on the results of the frequency compliance assertions and the results of the transient disturbance and glitch assertions; the dynamic statistical envelope includes an upper limit dynamic statistical envelope and a lower limit dynamic statistical envelope.

[0015] According to a third aspect of the embodiments of this application, an electronic device is provided, including a memory and a processor, wherein the memory is used to store a computer program executable by the processor; and the processor is used to execute the computer program in the memory to implement the clock detection method described above.

[0016] According to a fourth aspect of the embodiments of this application, a computer-readable storage medium is provided, on which a computer program is stored, wherein when the executable computer program in the storage medium is executed by a processor, the clock detection method described above can be implemented.

[0017] According to a fifth aspect of the embodiments of this application, a computer program product is provided, including a computer program or computer instructions, which, when executed by a processor, implement the clock detection method described above. Attached Figure Description

[0018] Figure 1 This is a flowchart illustrating a clock detection method according to an exemplary embodiment; Figure 2 This is a schematic diagram illustrating the storage of measured clock cycle values ​​into a queue according to an exemplary embodiment; Figure 3 This is a structural diagram of a clock detection system according to another exemplary embodiment; Figure 4 This is a schematic diagram of the timing waveforms of a clock detection system in operation according to an exemplary embodiment; Figure 5 This is a schematic diagram of the structure of a clock detection electronic device according to another exemplary embodiment. Detailed Implementation

[0019] Unless otherwise defined, the technical or scientific terms used in this specification and claims shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. Specific embodiments of this application will be described below in conjunction with the accompanying drawings. It should be noted that, in order to provide a concise description, this specification cannot exhaustively describe all features of the actual embodiments. Without departing from the spirit and scope of this application, those skilled in the art can modify and substitute the embodiments of this application, and the resulting embodiments are also within the protection scope of this application.

[0020] As mentioned above, existing clock signal detection methods suffer from the following problems due to fixed judgment thresholds and fixed assertions: 1) The period of a spread spectrum clock varies periodically around its center value, and fixed judgment thresholds easily misjudge legitimate modulation as a frequency error; 2) During dynamic frequency conversion, fixed thresholds require recompiling and verifying the environment or writing multiple sets of assertion code, resulting in low assertion reusability; 3) For single-cycle glitches and gradual frequency drift, the former is usually undetectable by fixed assertions because its duration is much shorter than the normal period; the latter, due to the small difference between adjacent periods during slow frequency drift, is difficult for fixed assertions to detect early, resulting in low detection accuracy; 4) Fixed assertions are usually masked during the reset period and resumed immediately after the reset is released. At this time, the phase-locked loop output is not yet stable, and the clock period fluctuates significantly, leading to false alarms from fixed assertions.

[0021] To address the aforementioned technical problems, this application proposes a clock detection method, apparatus, electronic device, and storage medium. By introducing a baseline calibration period and dynamic statistical envelope to address the four problems mentioned above, accurate clock detection can be achieved and the reusability of assertions can be improved.

[0022] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0023] One embodiment of this application provides a clock detection method. This clock detection method can be applied to clock detection systems and electronic devices. Please refer to... Figure 1 The clock detection method may include the following steps 101 to 107: Step 101: Obtain the measured value of the clock cycle of the current period of the clock signal to be detected.

[0024] In some embodiments, the method for obtaining the measured clock cycle value is as follows: acquiring the effective edge time markers of the current cycle and the effective edge time markers of the previous cycle of the clock signal to be detected, and calculating the difference between the time markers of the current cycle and the previous cycle. This difference is the measured clock cycle value of the current cycle. In one embodiment, the type of effective edge is a rising edge; in another embodiment, the type of effective edge is a falling edge.

[0025] Step 102: If the current cycle state is in the reset validity period, ignore the measured value of the clock cycle corresponding to this cycle and disable the assertion.

[0026] Specifically, a very large measured value of the clock cycle is generated during the reset period, but this value is an invalid signal and will affect the detection accuracy. In order to avoid the detection of the clock signal by this signal, this application does not record the measured value of the clock cycle corresponding to this state, and assertions are disabled during this state.

[0027] Step 103: If the current cycle is in a normal state, store the measured value of the clock cycle corresponding to the cycle into the sliding window data queue.

[0028] Step 104: When the current period is the baseline calibration period, store the measured clock cycle value corresponding to the period into the sliding window data queue and disable assertions. The measured clock cycle value stored in the sliding window data queue during the baseline calibration period is used as the filling data of the sliding window data queue and participates in the subsequent calculation of the sliding baseline mean and sliding standard deviation.

[0029] It should be noted that the baseline calibration period is N consecutive cycles after the reset release, and N is a positive integer greater than or equal to the depth of the sliding window data queue. Therefore, step 102 must be executed before step 104.

[0030] Through this step, this application is able to tolerate the initial instability of the clock signal after reset release, such as the periodic fluctuations in the early stage of phase-locked loop oscillation.

[0031] Steps 103 and 104 are selected to be executed based on the current cycle state: during the baseline calibration period, step 104 is executed after the reset release, and step 103 is executed after N consecutive cycles are completed and the normal period begins. The two steps will not be executed simultaneously.

[0032] In some embodiments, the following requirements apply: 1) The value of N satisfies the following: it covers the initial unstable phase of the clock under test after reset release, such as the clock fluctuation phase during the phase-locked loop (PLL) lock time. The reasons are as follows: First, setting the value of N to be greater than or equal to the depth of the sliding window data queue ensures that the sliding window data queue is filled with valid data by the end of the calibration period. Second, setting the value of N to cover the initial unstable phase after PLL reset release adapts to the differentiated lock time caused by different PLL parameters, while supporting flexible parameter configuration and compatibility with various high- and low-frequency clock test scenarios. For example, if the depth of the sliding window data queue in this embodiment is no more than 16, then the value of N can be set to 16. In a typical high-speed digital verification environment, such as when the frequency of the clock under test is tens of MHz or higher, this value can simultaneously meet the initial filling requirements of the sliding window and provide basic stability waiting. This limitation ensures that the sliding time data queue can cover relatively complete periodic data during the clock oscillation period, thereby ensuring that false alarms caused by reset instability are avoided.

[0033] 2) Each newly generated clock cycle measured value is pushed to the head of the queue, and the oldest data at the tail of the queue is used to maintain a constant depth of M in the sliding window data queue. The value of M determines the statistical sample size of the sliding window and can be customized according to the actual clock jitter characteristics and response speed requirements. It should be noted that the value of M should be able to balance statistical significance and response speed. When M is too small, such as M less than or equal to 8, it will lead to unstable standard deviation calculation and excessive influence from single point anomalies; while when M is too large, such as M greater than 32, it will lead to slow response to frequency changes. After engineering practice, the value of M is generally set to 16. This value can provide a sufficient statistical sample size to calculate a stable sliding standard deviation, while maintaining a reasonable response speed to frequency changes. To illustrate how this application stores measured clock cycle values, we assume a sliding window data queue with a depth of M=4. The four measured clock cycle values ​​stored sequentially are [10.2], [9.8], [9.9], and [10.5], and the storage process is as follows: Figure 2 As shown.

[0034] Step 105: When the current cycle is in a normal period, after storing the measured value of the clock cycle of the current cycle into the sliding window data queue, calculate the sliding baseline mean and sliding standard deviation based on all the data in the sliding window data queue.

[0035] In some embodiments, the sliding baseline mean is the mean of all clock cycle measurements in the sliding window data queue, and its expression is: ; in, This indicates the number of data items in the sliding window data queue. Measured value per clock cycle ; Indicates the depth of the sliding window data queue; This represents the moving baseline mean.

[0036] By calculating the sliding baseline mean, the spread spectrum clock modulation curve is adaptively tracked to capture its subtle changes. Specifically, in the spread spectrum clock scenario, the clock period exhibits periodic triangular wave modulation over time, with the period changing sequentially as follows: 10ns, 10.05ns, 10ns, 9.95ns, and 10ns. The sliding window data queue always stores the most recent M measured values, and the sliding baseline mean is the arithmetic mean of these M values. When the spread spectrum clock modulation changes slowly, the sliding baseline mean smoothly follows the central trend of the modulation curve, thus reflecting the legitimate period changes caused by the spread spectrum clock as an adaptive offset of the sliding baseline mean. This allows the dynamic statistical envelope to be dynamically adjusted around the modulation curve, rather than being a frequency error under a fixed threshold.

[0037] In some embodiments, the sliding standard deviation is calculated as follows: ; in, Indicates the sliding standard deviation; This indicates the number of data items in the sliding window data queue. Measured value per clock cycle ; Indicates the depth of the sliding window data queue; This represents the moving baseline mean.

[0038] The sliding standard deviation calculated above quantifies the normal jitter range of the clock, while the dynamic statistical envelope defines the boundaries of normal clock behavior. Normal jitter, such as small periodic variations caused by power supply noise, temperature drift, and legitimate modulation due to the periodic modulation characteristics of spread spectrum clocks, is random and its amplitude is usually on the same order of magnitude as the sliding standard deviation, thus falling within the envelope. In contrast, glitches or asymptotic drift exhibit systematic deviations with amplitudes significantly greater than normal jitter, thus exceeding the envelope and being detected.

[0039] Step 106: For cycles in the normal period, assertions are enabled, the absolute error between the measured and expected values ​​of the clock cycle is calculated, and frequency compliance assertions are performed based on the absolute error; the dynamic statistical envelope is calculated based on the sliding baseline mean, sliding standard deviation, and preset sensitivity coefficients, and transient disturbance and glitches assertions are performed based on the measured clock cycle and the dynamic statistical envelope. The dynamic statistical envelope includes an upper limit dynamic statistical envelope and a lower limit dynamic statistical envelope.

[0040] In some embodiments, the ratio of absolute error to expected value is calculated. If this ratio is greater than the configuration tolerance, an assertion violation is determined. Conversely, if the statement does not meet the criteria, the assertion is considered normal. Indicates the preset value of the tolerance; This represents the expected value for the period.

[0041] The expression for calculating the absolute error is as follows: ; in, Indicates absolute error. Indicates the expected period.

[0042] Frequency compliance assertions can detect significant frequency deviations caused by clock configuration errors, severe phase-locked loop (PLL) lockouts, and clock source switching failures.

[0043] In some embodiments, the upper limit dynamic statistical envelope is calculated as follows: ; in, This indicates the upper limit of the dynamically calculated envelope; Indicates the moving baseline mean; Indicates the sliding standard deviation; This represents the sensitivity coefficient, which is an integer value.

[0044] in, The value of satisfies the principle of standard deviation multiples in statistics, and is inversely proportional to the false alarm rate and directly proportional to the false negative rate, that is... The smaller the value, the narrower the dynamic statistical envelope, and the more sensitive it is to anomalies, but the false alarm rate increases. A larger value results in a wider dynamic statistical envelope and a lower false alarm rate, but may miss minor anomalies, such as when... The dynamic statistical envelope covers approximately 95% of normal jitter, exhibiting high detection sensitivity and making it suitable for scenarios sensitive to glitches, but it is prone to false alarms; when Corresponding to statistics The principle is that for data with an approximately Gaussian distribution, the dynamic statistical envelope covers about 99.7% of normal jitter, effectively balancing the false alarm rate and the false negative rate; when The dynamic statistical envelope covers approximately 99.994% of normal jitter, but its detection sensitivity is low, limiting its application to extremely noisy environments. Therefore, The standard setting is 3.

[0045] In one embodiment, the lower limit dynamic statistical envelope is calculated as follows: ; in, This represents the lower limit of the dynamic statistical envelope; Indicates the moving baseline mean; Indicates the sliding standard deviation; This represents the sensitivity coefficient, which is an integer value and must meet the same requirements as described above.

[0046] In one embodiment, transient disturbances and glitches are asserted as follows: when the measured value of the clock cycle is greater than the upper limit dynamic statistical envelope or less than the lower limit dynamic statistical envelope, an assertion violation is determined; when the measured value of the clock cycle is less than or equal to the upper limit dynamic statistical envelope and greater than or equal to the lower limit dynamic statistical envelope, an assertion is determined to be normal.

[0047] By calculating the dynamic statistical envelope, the method provided in this application can tolerate conventional clock jitter that conforms to a Gaussian distribution, i.e., clock jitter that falls within the dynamic statistical envelope; it can also detect subtle anomalies such as clock glitches or abnormal overshoots of spread spectrum clocks and single-cycle narrow pulses.

[0048] Step 107: For cycles in the normal period, determine whether the clock is in violation based on the results of frequency compliance assertion and transient disturbance and glitch assertion.

[0049] In some embodiments, the method for determining the clock based on the assertion result is as follows: If both the frequency compliance assertion and the transient disturbance and glitch assertion results are normal, the clock is deemed not to be in violation. If the frequency compliance assertion results in an assertion violation, while the transient disturbance and glitch assertion results in normal assertions, the frequency test is deemed a failure and a clock violation is determined. If the frequency compliance assertion result is normal, but the transient disturbance and glitch assertion result is invalid, the glitch test is deemed to have failed and the clock is deemed to have violated the rules. If both the frequency compliance assertion and the transient disturbance and glitch assertion result in an assertion violation, and both the frequency test failure and the glitch test failure are triggered simultaneously, a clock violation is determined.

[0050] It should also be noted that after step 107 is executed, a detection report will be generated. This detection report includes abnormal cycle values, error percentages, and window statistical parameters. The fault cycle can be directly located through this detection report without having to backtrack to the waveform database afterward, thus achieving a closed loop for the entire detection process.

[0051] In summary, the technical solution provided in this application has the following advantages: 1) This application generates a dynamic detection threshold based on the mean and standard deviation of the clock cycle using a sliding window statistical method. Combined with a reset shielding and baseline calibration mechanism, it replaces the traditional fixed threshold and fixed assertion detection scheme, making it suitable for various complex operating conditions such as dynamic frequency conversion clocks, spread spectrum clocks, and unstable PLL power-on. Furthermore, it designs differentiated detection logic for different clock operating states: during the reset validity period, clock detection assertions are directly disabled, and invalid sample values ​​with excessively large cycles caused by clock gating are eliminated, thus removing interference from invalid gating signals on the detection results; a separate baseline calibration period is set during the unstable transition period of the PLL after reset release. Assertions are disabled during this stage to avoid false alarms, while all clock cycle sample values ​​are retained for dynamic statistical envelope calculation, adaptively matching the unstable characteristics of the clock during the initial power-on oscillation. This fundamentally solves the problem of false alarms caused by clock fluctuations at the moment of reset, significantly improving clock detection accuracy and the versatility and reusability of the solution.

[0052] 2) The dynamic envelope is calculated based on the sliding baseline mean and sliding standard deviation, enabling effective detection of transient clock glitches and asymptotic drift. Using historical statistical behavior as a benchmark, rather than a fixed threshold, it can adapt to slow changes in clock frequency, such as spread spectrum clock modulation and dynamic voltage-frequency modulation, while maintaining sensitivity to sudden anomalies (such as glitches). Asymptotic drift can be detected through the hysteresis tracking characteristic of the sliding baseline mean; that is, when the drift rate exceeds the update rate of the sliding window, the period value of the new input will systematically deviate from the sliding baseline mean, thus exceeding the defined boundary of the dynamic statistical envelope. It should be noted that for extremely slow drifts, i.e., drift rates lower than the sliding window tracking rate, dynamic statistical envelope detection may not trigger, but the first-dimensional frequency compliance assertion, based on a fixed expected period, will still eventually trigger as drift accumulates. Therefore, the dual-dimensional assertion architecture provided in this application is complementary, jointly covering the full range of anomalies from transient glitches to extremely slow drifts.

[0053] 3) This application adopts a dual-dimensional independent detection architecture to decouple the detection configuration from the actual clock operating conditions: the first dimension is frequency compliance assertion, mainly used to verify whether the clock parameters meet the design specifications; the second dimension is transient disturbance and glitch assertion, which generates a dynamic detection envelope entirely based on statistical parameters calculated in real time through a sliding window, without relying on any preset fixed frequency parameters. In scenarios with dynamic voltage and frequency adjustment, clock frequency division switching, and spread spectrum clocks, the second-dimensional statistical detection can automatically follow the actual clock operation and adaptively adjust the detection benchmark, without the need for manual modification of the detection threshold and detection parameters, significantly reducing the configuration cost of adapting the solution to different clock scenarios and improving the versatility of the solution.

[0054] 4) This application provides a closed-loop clock detection method, which sequentially performs real-time acquisition of clock cycle data, online calculation of statistical parameters, and automatic fault determination via assertions. When necessary, a detection report is generated after an assertion violation, allowing engineers to pinpoint the fault location. This closed-loop detection mode eliminates the need for post-detection waveform database backtracking, significantly shortening clock fault location time and improving simulation verification efficiency.

[0055] Another exemplary embodiment of this application provides a clock detection system. In this embodiment, the clock detection system includes the following units, the data flow interaction between the units, and the system structure as follows: Figure 3 As shown.

[0056] The input data for this detection system are clock signals and reset signals, and its configurable parameters are configured, including the sliding window data queue depth N, the desired clock period, the preset value of the frequency error tolerance, and the sensitivity coefficient.

[0057] 1) Edge timestamp capture unit.

[0058] This unit is used to obtain the measured value of the clock cycle for the current cycle. The process is similar to step 101 and will not be described in detail.

[0059] When the clock detection system is running, this unit performs the following operations on each rising edge of the clock signal: If the reset signal is low, i.e. the cycle state is the reset validity period, then the validity time mark of the previous cycle is cleared to 0.0.

[0060] Otherwise, the current simulation time is assigned to the effective edge time flag of the current period of the variable.

[0061] If the effective edge time stamp of the previous cycle is not equal to 0.0, then the value of the effective edge time stamp of the current cycle is calculated by subtracting the value of the effective edge time stamp of the previous cycle from the value of the effective edge time stamp of the current cycle, and this is taken as the measured value of the current clock cycle.

[0062] Finally, the value of the valid edge time stamp of the current period is assigned to the value of the valid edge time stamp of the previous period to update the last recorded time.

[0063] 2) Dynamic gating and self-calibration unit.

[0064] This unit is used to ignore the measured clock cycle value corresponding to the current cycle and disable assertions when the current cycle state is in the reset validity period; when the current cycle state is in the baseline calibration period or normal period, it stores the measured clock cycle value corresponding to the current cycle into the sliding window data queue and disables assertions when the current cycle state is in the baseline calibration period.

[0065] The above two processes are performed in the first and second sub-units, respectively, and an additional state machine linked to the reset signal is introduced. The baseline calibration period end signal generated by this state machine enables the reset statistical feature unit to receive the measured value of the clock cycle. When the first sub-unit is running, i.e., when the cycle state is in the reset validity period, it sends a data rejection signal to the statistical feature calculation unit and an assertion disable signal to the dynamic assertion check unit. When the second sub-unit is running, i.e., when the cycle state is in the baseline calibration period or the normal period, it sends a data receive signal to the statistical feature calculation unit. Only when the cycle state is in the baseline calibration period will the second sub-unit also send an assertion disable signal to the dynamic assertion check unit.

[0066] The aforementioned baseline calibration period refers to N consecutive cycles after reset and release, and the value of N is the same as the requirement for N in steps 103 and 104, and is a positive integer.

[0067] When the clock detection system is running, this unit performs the following operations on each rising edge of the clock signal: If the reset signal is low, the counter is cleared, the baseline calibration period end signal of the state machine is set to zero, and the periodic data queue is cleared. If the reset is ineffective and the baseline calibration period end signal is still 0, the counter count is incremented by one, and when the counter value is equal to the number of cycles N of the baseline calibration period, the baseline calibration period end signal is set to 1. It should be noted that in this application, the counter starts counting from 0 after the reset is released.

[0068] 3) Statistical characteristic calculation unit.

[0069] This unit is used to calculate the sliding baseline mean and sliding standard deviation based on all data in the sliding window data queue after storing the measured value of the clock cycle of the current cycle into the sliding window data queue when the current cycle state is normal.

[0070] In detail, the statistical feature calculation unit includes a third subunit and a fourth subunit. The third subunit is used to receive the measured value of the clock cycle and store it in the sliding window data queue. The fourth subunit is used to calculate the sliding baseline mean and sliding standard deviation based on all data in the sliding window data queue when the cycle state is in the normal period. The calculation process is shown in step 105, which will not be elaborated here.

[0071] When the clock detection system is running, if the reset signal is high and the measured clock period is greater than 0.0 at the rising edge of each clock signal, this unit performs the following operations: The measured value of the current clock cycle is inserted into the head of the sliding window data queue. This process is similar to the data storage process in steps 103 and 104, and will not be described in detail here.

[0072] If the size of the queue exceeds the set depth, discard one data item at the tail of the queue to ensure that the sliding window length does not exceed the preset sliding window data queue depth.

[0073] The function to calculate the average is called, taking the current queue contents as input, and calculates the arithmetic mean of the periodic values ​​within the window, assigning it to the moving baseline mean. The function to calculate the standard deviation is called, taking the current queue contents and the calculated mean as input, and calculates the moving standard deviation of the periodic values ​​within the window, assigning it to the moving standard deviation.

[0074] 4) Dynamic assertion checking unit This unit is used to enable assertions for cycles in the normal period, calculate the absolute error between the measured and expected values ​​of the clock cycle, and perform frequency compliance assertions based on the absolute error; calculate the dynamic statistical envelope based on the sliding baseline mean, sliding standard deviation, and preset sensitivity coefficients, and perform transient disturbance and glitches assertions based on the measured clock cycle and the dynamic statistical envelope; for cycles in the normal period, determine whether the clock is in violation based on the results of the frequency compliance assertions and the results of the transient disturbance and glitches assertions; and the dynamic statistical envelope includes an upper limit dynamic statistical envelope and a lower limit dynamic statistical envelope.

[0075] The above functions are implemented through a first comparator, a second comparator, and a fifth subunit. The first comparator is used to perform frequency compliance assertion, the second comparator is used to perform transient disturbance and glitch assertion, and the fifth subunit is used to determine whether the clock is in violation.

[0076] Taking a phase-locked loop clock with a frequency of approximately 1 GHz and a clock period of approximately 1.00 ns as an example, a clock detection process is set to include 34 clock cycles from T0 to T33. When the clock detection system is running in this scenario, the acquired timing diagram is as follows. Figure 4 As shown. It can be seen in the appendix Figure 4 During the baseline calibration period (T0~T16), after the reset validity period ends, the clock cycle is released at T0, and the clock cycle is allowed to return to its normal state. During this period, clock cycle instability and large fluctuations occur. The dynamic assertion check unit is disabled, but the measured clock cycle values ​​collected under this clock state are still stored in the sliding window data queue. After the baseline calibration period ends, the clock cycle enters T17~T24. At T17, the baseline calibration period end signal is set to 1, and the dynamic assertion check unit is enabled. If the measured clock cycle value collected during T17~T24 is approximately 1 ns, then the ratio of the absolute error to the expected value is 0%, which is less than the preset configuration tolerance of 5%. Therefore, T17~T24 is considered the normal period, and the clock test results show no clock violation. When a single-cycle glitch is detected in the T25 cycle, such as... Figure 4 As shown, in and There is a narrow pulse of 0.25ns between two adjacent rising edges of the clock. At this time, the measured clock period jumps from 1.00ns to 0.25ns. The calculated absolute error is 75% higher than the expected value, which is greater than the configuration tolerance of 5%. At this moment, both the glitch test and the frequency test fail simultaneously, and the clock test result is a clock violation. When entering T26~T29, from Figure 4 As can be seen, the measured clock cycle returns to 1ns, which is the normal period, and the corresponding clock detection result is no clock violation. When the PLL clock enters T30~T33, a frequency offset caused by PLL lockout is detected, and the clock cycle experiences systematic jitter with an average value of 1.05ns. At this time, the ratio of the calculated absolute error to the expected value is greater than the configuration tolerance, triggering a frequency test failure. In addition, in this cycle, the sliding baseline average adaptively converges to 1.05ns, deviating from the expected cycle by 0.05ns. This offset cycle is within the dynamic statistical envelope range, and transient disturbances and glitches are asserted to be normal, so the clock detection result is a clock violation.

[0077] It should be noted that the 1GHz frequency mentioned above is only an example, and the present invention is applicable to clock detection at various frequencies.

[0078] The method embodiments and system embodiments of this application can complement each other.

[0079] In some embodiments, when performing step 105 or calling the fourth subunit to calculate the sliding baseline average, this application may also use the exponentially weighted moving average method to calculate the average. This method assigns higher weight to recent periods and is suitable for scenarios that require smoothing historical data or emphasizing recent trends.

[0080] In some embodiments, if the above system is executed in a simulation environment, the effective edge time marker of the current or previous cycle is calculated based on the absolute time of the simulation when calculating the measured clock cycle value; if the above system is executed in a hardware environment, the following improvements can be made to adapt it to the hardware execution environment, including: 1) using a high-frequency reference clock, such as a reference clock with a frequency of 1 GHz or higher, to count and measure the clock cycle under test; 2) changing the storage format of the measured clock cycle value from sliding window data queue storage to register array, and embedding a divider and square root in the fourth sub-unit; 3) mapping the obtained measured clock cycle value, sliding baseline mean, sliding standard deviation, and the ratio of absolute error to the expected period to an AXI-Lite slave device or an APB slave device.

[0081] In some embodiments, the detection system provided in this application can be integrated into a general verification methodology environment in the following ways: 1) Embedding the system at the top level of the test platform, the general verification methodology component reads violation flags and statistical parameters through a virtual interface; once a violation is detected, it calls a reporting macro or broadcasts it through a transaction-level modeling port. 2) Introducing the macro definition file required by the general verification methodology into the clock detection system to ensure that a verification error is directly reported when the assertion condition is violated. 3) Incorporating the final output detection report of the clock detection system into the reporting system of the general verification methodology, supporting linkage with the simulation termination strategy.

[0082] Furthermore, to demonstrate the feasibility and reusability of the method and its corresponding system provided in this application, verification was conducted in the following three scenarios: 1) Double Data Rate Memory Controller Multi-Frequency Verification Mode.

[0083] In this scenario, the application is verified using fourth-generation double data rate synchronous dynamic random access memory or fifth-generation double data rate synchronous dynamic random access memory in a system-on-a-chip.

[0084] In this scenario, the clock frequency changes as the integrated double data rate memory controller switches between different power consumption modes, such as from the highest rate to a low power rate.

[0085] Therefore, if a fixed threshold assertion is used in this scenario, assertion code needs to be written separately for each frequency configuration. Furthermore, the intermediate frequency during mode switching is unpredictable, making it difficult for fixed assertions to effectively cover the frequency. In particular, when the physical layer interface of the double data rate memory controller involves timing conversion between multiple asynchronous clock domains, fixed threshold assertions cannot adaptively handle the phase relationship between clock domains.

[0086] When using the method provided in this application, the clock detection system described above is integrated into the controller verification environment of the double data rate memory controller. It is instantiated as an independent clock monitoring module in the clock domain of the double data rate memory controller's memory physical layer interface. Specifically, the expected period value is configured based on the default operating frequency of the double data rate memory controller; a sliding window data queue is set to automatically track the actual period changes of the clock domain of the double data rate memory controller's memory physical layer interface without the need for separate configuration for different frequency modes. The process is similar to steps 101 to 107 and will not be described in detail here.

[0087] 2) Spread-frequency clock verification mode during high-speed peripheral interconnect bus interface testing.

[0088] High-speed peripheral interconnect bus standards require support for spread spectrum clock modulation to reduce electromagnetic interference. Spread spectrum clocks periodically modulate the clock frequency around the center frequency, typically with a spread spectrum of 0.5% and a modulation frequency of about 30-33kHz, causing the clock period to change dynamically over time.

[0089] In this process, the clock cycle variation caused by the spread spectrum clock is a legitimate design, but the fixed threshold assertion will misjudge this legitimate variation as a frequency error. Therefore, during verification, it is necessary to turn off the clock cycle assertion or relax the threshold to the point of losing its detection significance, which makes it impossible to detect real clock faults.

[0090] When using the method provided in this application, the clock detection system described above is instantiated in the verification environment of the high-speed peripheral interconnect bus interface. Specifically, the sensitivity coefficient in step 106 is configured to 3 to accommodate normal periodic fluctuations caused by spread spectrum clock modulation. Through the transient disturbance and glitch assertion detection provided in this application, it is ensured that fluctuations caused by spread spectrum clock modulation can be removed from the anomaly judgment, thereby ensuring detection accuracy.

[0091] 3) Multi-clock domain on-chip system integration verification mode.

[0092] In this scenario, the verification of a system-on-a-chip integrating multiple independent clock domains, such as processor cores, memory controllers, and high-speed peripheral interfaces, operates at different clock frequencies. For this type of scenario, existing technologies require selecting fixed judgment thresholds for each object and writing corresponding assertions for different objects, which cannot adapt to frequency switching.

[0093] When using the method and corresponding system provided in this application, the above clock detection system is instantiated, and each maintains independent sliding window statistics. That is, the depth of the sliding window data queue is selected according to the characteristics of different clock domains. When a clock domain undergoes dynamic frequency switching, the average value of the sliding baseline of that domain automatically converges to the new frequency value, and other domains are not affected. Moreover, the introduced baseline calibration period mechanism tolerates the clock instability in the initial stage of reset and release of each clock domain. Finally, the violation information of each domain is summarized through the reporting system of the verification methodology to achieve global clock health monitoring.

[0094] In summary, the method and system provided in this application do not require different fixed judgment thresholds based on the environment type when facing different verification environments, nor do they require rewriting the assertions. They only need to adaptively adjust the configuration parameters, including the sliding window data queue depth N, the expected clock period, the preset value of the frequency error tolerance, and the sensitivity coefficient, according to the performance of the verification environment.

[0095] Embodiments of this application also provide an electronic device 600, such as... Figure 5As shown, the electronic device 600 includes a memory 601 and a processor 602. The memory 601 is used to store computer programs executable by the processor 602; the processor 602 is used to execute the computer programs in the memory 601 to implement the clock detection method provided in any of the above embodiments.

[0096] The electronic device 600 also includes a communication interface 603. The processor 602, memory 601, and communication interface 603 are connected via a communication bus and communicate with each other.

[0097] Processor 602 may be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits used to control the execution of programs in the above scheme.

[0098] Communication interface 603 is used to communicate with other devices or communication networks, such as Ethernet, Radio Access Network (RAN), Wireless Local Area Networks (WLAN), etc.

[0099] The memory 601 may be a read-only memory (ROM) or other type of static storage device capable of storing static information and instructions, random access memory (RAM) or other type of dynamic storage device capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto. The memory may exist independently and be connected to the processor via a bus. The memory may also be integrated with the processor.

[0100] Embodiments of this application also propose a computer-readable storage medium that, when an executable computer program in the storage medium is executed by a processor, can implement the clock detection method of any of the above embodiments.

[0101] Embodiments of this application also propose a computer program product, including a computer program or computer instructions that, when executed by a processor, implement the clock detection method of any of the above embodiments.

[0102] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "multiple" refers to two or more unless otherwise expressly defined.

[0103] The above description of the embodiments is intended to enable those skilled in the art to understand and apply this application. It will be apparent to those skilled in the art that various modifications can be easily made to these embodiments, and the general principles described herein can be applied to other embodiments without creative effort. Therefore, this application is not limited to the embodiments described herein, and any improvements and modifications made by those skilled in the art based on the disclosure of this application without departing from the scope and spirit of this application are within the scope of this application.

Claims

1. A clock detection method, characterized in that, include: Obtain the measured value of the clock cycle of the current period of the clock signal to be detected; If the current cycle state is within the reset validity period, ignore the measured value of the clock cycle corresponding to that cycle and disable assertions; When the current cycle is in the baseline calibration period or normal period, the measured value of the clock cycle corresponding to the cycle is stored in the sliding window data queue, and assertions are disabled when it is in the baseline calibration period; the baseline calibration period is N consecutive cycles after reset release, and N is a positive integer greater than or equal to the depth of the sliding window data queue; When the current cycle is in a normal period, after storing the measured value of the clock cycle of the current cycle into the sliding window data queue, the sliding baseline mean and sliding standard deviation are calculated based on all the data in the sliding window data queue. For cycles in the normal period, assertions are enabled, the absolute error between the measured and expected clock cycles is calculated, and frequency compliance assertions are performed based on the absolute error. The dynamic statistical envelope is calculated based on the mean of the sliding baseline, the sliding standard deviation, and the preset sensitivity coefficient, and transient disturbance and glitches assertions are performed based on the measured clock cycles and the dynamic statistical envelope. The dynamic statistical envelope includes an upper limit dynamic statistical envelope and a lower limit dynamic statistical envelope; For cycles in the normal period, the clock violation is determined based on the results of the frequency compliance assertion and the results of the transient disturbance and glitches assertion.

2. The clock detection method as described in claim 1, characterized in that, The method for obtaining the measured value of the clock cycle is as follows: collect the time stamp of the effective edge of the current cycle and the time stamp of the effective edge of the previous cycle of the clock signal to be detected, calculate the difference between the time stamps of the current cycle and the previous cycle, and the difference is the measured value of the clock cycle of the current cycle; wherein the type of the effective edge is either rising edge or falling edge, and the type of the effective edge is the same in each calculation.

3. The clock detection method as described in claim 1, characterized in that, The mean of the sliding baseline is the mean of all measured clock cycles in the sliding window data queue.

4. The clock detection method as described in claim 1, characterized in that, The method for calculating the sliding standard deviation is as follows: ； in, Indicates the sliding standard deviation; This indicates the number of data items in the sliding window data queue. Measured value per clock cycle ; Indicates the depth of the sliding window data queue; This represents the moving baseline mean.

5. The clock detection method as described in claim 1, characterized in that, The frequency compliance assertion based on the absolute error includes: calculating the ratio of the absolute error to the expected value; if the ratio is greater than the configuration tolerance, the assertion is determined to be a violation; otherwise, the assertion is determined to be normal.

6. The clock detection method as described in claim 1, characterized in that, The calculation method for the upper limit dynamic statistical envelope is as follows: ； in, This indicates the upper limit of the dynamically calculated envelope; Indicates the moving baseline mean; Indicates the sliding standard deviation; The sensitivity coefficient is an integer value that satisfies the following rules: it is inversely proportional to the false alarm rate and directly proportional to the false negative rate.

7. The clock detection method as described in claim 1, characterized in that, The method for calculating the lower limit dynamic statistical envelope is as follows: ； in, This represents the lower limit of the dynamic statistical envelope; Indicates the moving baseline mean; Indicates the sliding standard deviation; The sensitivity coefficient is an integer value that satisfies the following rules: it is inversely proportional to the false alarm rate and directly proportional to the false negative rate.

8. The clock detection method as described in claim 1, characterized in that, The transient disturbance and glitches assertion is defined as follows: when the measured value of the clock cycle is greater than the upper limit dynamic statistical envelope or less than the lower limit dynamic statistical envelope, an assertion violation is determined. When the measured value of the clock cycle is less than or equal to the upper limit dynamic statistical envelope, and the measured value of the clock cycle is greater than or equal to the lower limit dynamic statistical envelope, the assertion is determined to be normal.

9. The clock detection method as described in claim 1, characterized in that, The determination of whether a clock violation occurs is based on the results of the frequency compliance assertion and the results of the transient disturbance and glitches assertion, including: If the results of the frequency compliance assertion and the transient disturbance and glitches assertion are both normal, the clock is determined to be not in violation. If the frequency compliance assertion results in an assertion violation, but the transient disturbance and glitch assertion results in a normal assertion, the frequency test is deemed to have failed, and a clock violation is determined. If the frequency compliance assertion result is normal, but the transient disturbance and glitch assertion result is invalid, the glitch test is deemed to have failed and a clock violation is determined. If both the frequency compliance assertion and the transient disturbance and glitch assertion result in an assertion violation, and both the frequency test failure and the glitch test failure are triggered simultaneously, a clock violation is determined.

10. A clock detection system, characterized in that, The system includes: Edge timestamp capture unit, used to obtain the measured value of the clock cycle for the current period; The dynamic gating and self-calibration unit is used to ignore the measured clock cycle value corresponding to the current cycle and disable assertions when the current cycle state is the reset validity period; when the current cycle state is the baseline calibration period or the normal period, it stores the measured clock cycle value corresponding to the current cycle into the sliding window data queue and disables assertions during the baseline calibration period; the baseline calibration period is N consecutive cycles after the reset release, and N is a positive integer greater than or equal to the depth of the sliding window data queue; The statistical feature calculation unit is used to calculate the sliding baseline mean and sliding standard deviation based on all data in the sliding window data queue after storing the measured value of the clock cycle of the current cycle into the sliding window data queue when the current cycle state is normal. The dynamic assertion checking unit is used to enable assertions for cycles in the normal period, calculate the absolute error between the measured and expected values ​​of the clock cycle, and perform frequency compliance assertions based on the absolute error; calculate the dynamic statistical envelope based on the sliding baseline mean, sliding standard deviation, and preset sensitivity coefficient, and perform transient disturbance and glitch assertions based on the measured clock cycle and the dynamic statistical envelope; for cycles in the normal period, determine whether the clock is in violation based on the results of the frequency compliance assertions and the results of the transient disturbance and glitch assertions; the dynamic statistical envelope includes an upper limit dynamic statistical envelope and a lower limit dynamic statistical envelope.

11. An electronic device, characterized in that, The method includes a memory and a processor, wherein the memory is used to store a computer program executable by the processor; and the processor is used to execute the computer program in the memory to implement the method as described in any one of claims 1 to 9.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the executable computer program in the storage medium is executed by a processor, it can implement the method as described in any one of claims 1 to 9.

13. A computer program product, comprising a computer program or computer instructions, characterized in that, When the computer program or computer instructions are executed by the processor, they implement the method as described in any one of claims 1 to 9.

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