Chip constant port formal verification method, device and equipment and storage medium

Abstract

The application discloses a chip constant port formal verification method, device and equipment and a storage medium, relates to the chip verification technical field, and comprises the following steps: obtaining a design file and a timing model file of a to-be-verified submodule, wherein the design file comprises a logic design file and a physical implementation file, and the timing model file is marked with a constant attribute of a constant port; extracting the port marked with the constant attribute and the corresponding constant value from the timing model file; using a formal verification tool, based on the extracted port and the constant value, performing first equivalence verification on the logic function of the corresponding port in the logic design file and the constant value, and performing second equivalence verification on the logic function of the corresponding port in the physical implementation file and the constant value, to obtain a special verification result; and determining a special signature conclusion of the constant port of the submodule according to the special verification result. The application can solve the problems of non-standard constant port verification and attribute transmission loss in hierarchical design.

Description

Technical Field

[0001] This application relates to the field of chip verification technology, specifically to a method, apparatus, device, and storage medium for verifying chip constant port forms. Background Technology

[0002] With the rapid development of semiconductor technology, the scale of digital integrated circuits continues to expand, and chip design generally adopts a hierarchical process. In this process, large chips are broken down into multiple sub-modules for separate design and implementation, and then integrated layer by layer to the top layer. During this process, after the sub-modules have completed their physical implementation, timing models (such as ETM (Extracted Timing Model), DB (Design Database), and LIB (Liberty Library File) files) need to be extracted using static timing analysis tools for use by the top-level integration. These timing models serve as a key medium connecting the lower-level sub-modules and the upper-level integration, carrying important data such as the timing information and port attributes of the sub-modules. The port attributes include information such as the logical function and constant states of the ports.

[0003] Existing chip design verification processes typically focus on the functional and timing verification within submodules. For example, formal verification tools are used to check the overall logical equivalence between the submodule's RTL (Register Transfer Level) code and the implementation netlist to verify basic functional consistency; simultaneously, static timing analysis tools are used to ensure that the submodule meets timing constraints. The top-level integration stage directly reads in the timing model delivered by the submodule for synthesis, placement and routing, and timing analysis.

[0004] However, in the current hierarchical design process, the handling of constant ports in timing models still has the following shortcomings: First, there is a lack of a dedicated verification mechanism for constant ports in the timing model of submodules. Existing formal verification mainly focuses on the overall logical equivalence of RTL and netlist, without covering the consistency check of constant port attributes among the "submodule timing model, RTL design and implementation netlist". This makes it impossible to guarantee that the constant ports marked in the timing model are completely consistent with the original design and physical implementation.

[0005] Secondly, constant port attributes are prone to distortion during hierarchical transmission. Due to the lack of systematic checking and verification methods, constant attributes in the timing model delivered by submodules may be incorrectly passed to the top level. If the top-level synthesis tool optimizes based on incorrect constant attributes, it may lead to the propagation of erroneous constant optimizations, resulting in serious problems such as functional failure, timing degradation, performance deterioration, and reduced testability.

[0006] Finally, the existing process lacks a standardized and automated constant port verification mechanism. Faced with the complex requirements of large-scale SOC hierarchical design, relying on manual checks or non-standardized scripts makes it difficult to guarantee verification coverage and efficiency, and thus difficult to support high-quality design delivery requirements. Summary of the Invention

[0007] This application provides a method, apparatus, device, and storage medium for formal verification of chip constant ports, which can solve the problems of non-standard verification of constant ports and easy distortion of attribute transmission in hierarchical design.

[0008] In a first aspect, embodiments of this application provide a method for formal verification of chip constant ports, the method comprising: Obtain the design file and timing model file of the submodule to be verified. The design file includes a logic design file and a physical implementation file. The timing model file has constant attributes marked with constant ports. Extract the ports marked with the constant attributes and their corresponding constant values ​​from the time series model file; Using formal verification tools, based on the extracted ports and constant values, the logical functions of the corresponding ports in the logical design file are subjected to a first equivalence verification with the constant values, and the logical functions of the corresponding ports in the physical implementation file are subjected to a second equivalence verification with the constant values, thereby obtaining specific verification results; Based on the specific verification results, the specific approval conclusion for the constant ports of the submodule is determined.

[0009] In conjunction with the first aspect, in one implementation, the timing model file is a LIB library file, the constant attribute is a function attribute marked in the LIB library file, and the constant value is the value of the function attribute: 0 or 1.

[0010] In conjunction with the first aspect, in one implementation, extracting the ports marked with the constant attributes and their corresponding constant values ​​from the timing model file includes: Scan the LIB library files to obtain all ports that have the function attribute; The ports are categorized according to the value of the function attribute, generating a first port list with a constant value of 0 and a second port list with a constant value of 1.

[0011] In conjunction with the first aspect, in one implementation, the logic design file is a register transfer level RTL code file, and the physical implementation file is a netlist file after physical implementation.

[0012] In conjunction with the first aspect, in one implementation, the first equivalence verification of the logical function of the corresponding port in the logical design file with the constant value includes: In the formal verification tool, the RTL code file is set as the reference design end, and the constant value is set as the implementation design end to verify whether the logical functions of the two are equivalent.

[0013] In conjunction with the first aspect, in one implementation, the second equivalence verification of the logical function of the corresponding port in the physical implementation file and the constant value includes: In the formal verification tool, the constant value is set as the reference design end, and the netlist file is set as the implementation design end to verify whether the logical functions of the two are equivalent.

[0014] In conjunction with the first aspect, in one implementation, determining the special approval conclusion of the constant port of the submodule based on the special verification result includes: If the verification results of all constant ports in the special verification results are all passed, then the special approval conclusion is determined to be passed; If any constant port in the special verification results fails, then the special approval conclusion is determined to be a failure.

[0015] Secondly, embodiments of this application provide a chip constant port formal verification device, the chip constant port formal verification device comprising: The acquisition module is used to acquire the design file and timing model file of the submodule to be verified. The design file includes a logical design file and a physical implementation file. The timing model file has constant attributes marked with constant ports. An extraction module is used to extract ports marked with the constant attributes and their corresponding constant values ​​from the time series model file; The verification module is used to use formal verification tools to perform a first equivalence verification between the logical function of the corresponding port in the logical design file and the constant value based on the extracted port and constant value, and to perform a second equivalence verification between the logical function of the corresponding port in the physical implementation file and the constant value, so as to obtain specific verification results. The approval module is used to determine the special approval conclusion of the constant port of the submodule based on the special verification result.

[0016] Thirdly, embodiments of this application provide a chip constant port formal verification device, the chip constant port formal verification device including a processor, a memory, and a chip constant port formal verification program stored in the memory and executable by the processor, wherein when the chip constant port formal verification program is executed by the processor, it implements the steps of the chip constant port formal verification method as described above.

[0017] Fourthly, embodiments of this application provide a computer-readable storage medium storing a chip constant port formal verification program, wherein when the chip constant port formal verification program is executed by a processor, it implements the steps of the chip constant port formal verification method as described above.

[0018] The beneficial effects of the technical solutions provided in this application include: This application obtains the design file and timing model file of the submodule to be verified. The design file includes a logic design file and a physical implementation file. The timing model file has constant attributes marked with constant ports. The application extracts the ports marked with the constant attributes and their corresponding constant values ​​from the timing model file. Using a formal verification tool, based on the extracted ports and constant values, the application performs a first equivalence verification between the logical functions of the corresponding ports in the logic design file and the constant values, and performs a second equivalence verification between the logical functions of the corresponding ports in the physical implementation file and the constant values, to obtain a specific verification result. Based on the specific verification result, the application determines the specific approval conclusion for the constant ports of the submodule.

[0019] This application extracts ports marked with constant attributes and constant values ​​from timing model files, and uses formal verification tools to perform bidirectional equivalence verification on logic design files and physical implementation files, thereby achieving consistency checks of constant ports among logic design, physical implementation, and timing models. Based on the specific verification results, a specific approval conclusion is determined, providing a clear quality gate for submodules to enter upper-layer integration, effectively avoiding distortion of constant port attributes during transmission, and ensuring the accuracy of chip design data and integration reliability. Attached Figure Description

[0020] Figure 1 This is a flowchart illustrating an embodiment of the chip constant port formal verification method of this application; Figure 2 This is a flowchart of the ETM, RTL, and netlist constant port verification process for this application. Figure 3 This is a schematic diagram of the functional modules of an embodiment of the chip constant port formal verification device of this application; Figure 4This is a schematic diagram of the hardware structure of the chip constant port formal verification device involved in the embodiments of this application. Detailed Implementation

[0021] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0022] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0023] In a first aspect, embodiments of this application provide a method for verifying the form of chip constant ports.

[0024] In one embodiment, reference is made to Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the chip constant port formal verification method of this application. Figure 1 As shown, the chip constant port formal verification method includes: S1. Obtain the design file and timing model file of the submodule to be verified. The design file includes a logic design file and a physical implementation file. The timing model file is marked with constant attributes of constant ports. It's important to note that in large-scale chip design, the chip is typically broken down into multiple sub-modules, designed separately, and then assembled. After the sub-module design is completed, a simplified model (ETM) is generated for use by the top-level design. The ETM is primarily used for module-level timing abstraction in hierarchical design, enabling rapid integration and simulation by the top-level STA (Static Timing Analysis). It can also be used as a black-box model of the underlying modules for formal verification.

[0025] ETM is a crucial medium connecting lower-level submodules with upper-level integration, used to transmit timing, port attributes, and other information about submodules. In this model, some ports are fixed, i.e., constant ports, always either 0 or 1. Current technologies lack specific checks to ensure the consistency of these constant ports during model transmission, which can easily lead to errors in the top-level design.

[0026] To address this, this application proposes a verification method: specialized software is used to extract the information of these fixed ports, and then the original design code (RTL) and the actual circuit netlist are compared to confirm whether they are truly fixed as 0 or 1. Only after passing this verification is the model allowed to proceed to the next design stage.

[0027] In this embodiment, the timing model file is a LIB library file, and the constant attributes are the function attributes marked in the LIB library file. The logic design file is a register-transfer level RTL code file, and the physical implementation file is a netlist file after physical implementation.

[0028] S2. Extract the ports marked with the constant attributes and their corresponding constant values ​​from the timing model file; In step S2, the constant value is either 0 or 1, representing the value of the function attribute. Specifically, step S2 includes: S21. Scan the LIB library file to obtain all ports with the function attribute; S22. Classify the ports according to the value of the function attribute, and generate a first port list with a constant value of 0 and a second port list with a constant value of 1.

[0029] S3. Using formal verification tools, based on the extracted ports and constant values, perform a first equivalence verification between the logical functions of the corresponding ports in the logical design file and the constant values, and perform a second equivalence verification between the logical functions of the corresponding ports in the physical implementation file and the constant values ​​to obtain specific verification results. Specifically, the first equivalence verification of the logical function of the corresponding port in the logical design file with the constant value includes: In the formal verification tool, the RTL code file is set as the reference design end, and the constant value is set as the implementation design end to verify whether the logical functions of the two are equivalent.

[0030] The step of performing a second equivalence verification between the logical function of the corresponding port in the physical implementation file and the constant value includes: In the formal verification tool, the constant value is set as the reference design end, and the netlist file is set as the implementation design end to verify whether the logical functions of the two are equivalent.

[0031] In this embodiment, the formal verification tool is Formality, a tool for checking the logical formal equivalence of digital integrated circuits (ASIC / SoC).

[0032] It is worth noting that the specific verification result refers to the set of verification status data generated by the first equivalence verification and the second equivalence verification. Specifically, for each port in the constant port list, the specific verification result records the port's status (pass or fail) in the first equivalence verification and its status (pass or fail) in the second equivalence verification.

[0033] S4. Based on the specific verification results, determine the specific approval conclusion for the constant ports of the submodule.

[0034] Specifically, in step S4, if the verification results of all constant ports in the special verification results are all passed, then the special approval conclusion is determined to be passed; if the verification result of any constant port in the special verification results is failed, then the special approval conclusion is determined to be failed.

[0035] The following is combined with Figure 2 Further explanation of this application: Step 1: Submodules complete RTL design, logic synthesis, and physical implementation (PR). Step 1 primarily involves completing the standard front-end and back-end design process for the submodule (SUB). The goal is to generate the foundational design required for subsequent verification, serving as the physical basis for all verification work.

[0036] The process includes: RTL design (writing register-transfer level code); logic synthesis (converting RTL into a gate-level netlist); and physical implementation (completing placement and routing to generate the final physical netlist).

[0037] Step 2: Perform formal verification (RTL and netlist equivalence) and STA timing analysis on the SUB module; Step 2 mainly involves performing sub-module level verification according to industry standards to ensure that the module's own functions and timing are correct.

[0038] Among them, formal verification: compare whether the RTL and netlist are logically equivalent; static timing analysis: check whether the netlist meets the timing constraints.

[0039] Step 3: PT outputs the DB timing model (ETM) and LIB library file. The LIB file marks constant ports with the function:0 / 1. This function is built into PT. That is, if a port is a constant value of 0 or 1, the output LIB library file will mark the port with the function:0 / 1 attribute. Step 3 mainly involves using a static timing analysis tool (Prime Time, PT) to generate a timing model for top-level use, and leveraging the tool's capabilities to automatically identify constant ports. PT can generate LIB and DB files.

[0040] Step 4: Extract all ports with the function0 / 1 attribute from the LIB into a single file; Step 4 mainly involves parsing the constant port information from the LIB file and formatting it into a list that the verification tool can recognize. Specifically: 1. Full extraction: Scan the LIB file and capture all ports with the function:0 / 1 attribute.

[0041] 2. Categorization: Run the Python script to divide the extracted ports into two lists: a list of ports with a constant value of 0 and a list of ports with a constant value of 1.

[0042] Step 5: Use Formality to perform constant port-specific equivalence verification on the following two sets of objects; Step 5 primarily utilizes the formal verification tool Formality to perform equivalence comparisons between the extracted constant ports and the design source files. The aim is to verify whether the port retains its constant attribute in the netlist after physical implementation; the objects are constant ports in both the RTL and the netlist. Specifically: a) The constant ports in RTL (from the extraction results in step 4) are verified with 0 / 1 respectively, where RTL is the ref end and the constant is the impl end; b) Verify the constant ports in the netlist (from the extraction results in step 4) with 0 / 1 respectively, where the constant is the ref end and the netlist is the impl end; Step 6: Perform formal equivalence checks on all constant ports and save the results of failed checks for easy debugging. Step 6 mainly involves collecting verification results, logging failed cases, providing traceability, and facilitating investigation.

[0043] Step 7: After all constant ports have passed verification, complete the dedicated Signoff for constant ports before using this ETM to enter upper-layer integration.

[0044] Step 7 mainly involves making a final decision based on the verification results, deciding whether to allow the model to enter the top-level integration, to prevent models with erroneous constant attributes from polluting the top-level design.

[0045] Based on the above steps, this application establishes a systematic verification and signoff method for ETM, RTL, and netlist constant ports based on formal verification. This method solves the problems of non-standard ETM constant port signoff and distorted attribute transmission in hierarchical design, ensuring that the logic values ​​and attributes of submodule constant ports are stable and consistent throughout the entire process of ETM extraction, top-level integration, and optimization propagation. It avoids risks such as top-level functional abnormalities, timing collapses, and chip failures caused by constant port errors, and forms a standard process for formal verification of constant ports suitable for large-scale SOC hierarchical processes.

[0046] In summary, this application obtains the design file and timing model file of the submodule to be verified. The design file includes a logic design file and a physical implementation file. The timing model file contains constant attributes marked with constant ports. The application extracts the ports marked with the constant attributes and their corresponding constant values ​​from the timing model file. Using a formal verification tool, based on the extracted ports and constant values, the application performs a first equivalence verification between the logical functions of the corresponding ports in the logic design file and the constant values, and performs a second equivalence verification between the logical functions of the corresponding ports in the physical implementation file and the constant values, thereby obtaining a specific verification result. Based on the specific verification result, the application determines the specific approval conclusion for the constant ports of the submodule.

[0047] This application extracts ports marked with constant attributes and constant values ​​from timing model files, and uses formal verification tools to perform bidirectional equivalence verification on logic design files and physical implementation files, thereby achieving consistency checks of constant ports among logic design, physical implementation, and timing models. Based on the specific verification results, a specific approval conclusion is determined, providing a clear quality gate for submodules to enter upper-layer integration, effectively avoiding distortion of constant port attributes during transmission, and ensuring the accuracy of chip design data and integration reliability.

[0048] Secondly, embodiments of this application also provide a chip constant port form verification device.

[0049] In one embodiment, reference is made to Figure 3 , Figure 3 This is a functional module diagram of an embodiment of the chip constant port formal verification device of this application. Figure 3 As shown, the chip constant port formal verification device includes: The acquisition module is used to acquire the design file and timing model file of the submodule to be verified. The design file includes a logical design file and a physical implementation file. The timing model file has constant attributes marked with constant ports. An extraction module is used to extract ports marked with the constant attributes and their corresponding constant values ​​from the time series model file; The verification module is used to use formal verification tools to perform a first equivalence verification between the logical function of the corresponding port in the logical design file and the constant value based on the extracted port and constant value, and to perform a second equivalence verification between the logical function of the corresponding port in the physical implementation file and the constant value, so as to obtain specific verification results. The approval module is used to determine the special approval conclusion of the constant port of the submodule based on the special verification result.

[0050] Furthermore, in one embodiment, the timing model file is a LIB library file, the constant attribute is a function attribute marked in the LIB library file, and the constant value is the value of the function attribute: 0 or 1.

[0051] Further, in one embodiment, the extraction module extracts the ports marked with the constant attributes and their corresponding constant values ​​from the time-series model file, including: Scan the LIB library files to obtain all ports that have the function attribute; The ports are categorized according to the value of the function attribute, generating a first port list with a constant value of 0 and a second port list with a constant value of 1.

[0052] Furthermore, in one embodiment, the logic design file is a register transfer level RTL code file, and the physical implementation file is a netlist file after physical implementation.

[0053] Further, in one embodiment, the verification module performs a first equivalence verification between the logical function of the corresponding port in the logical design file and the constant value, including: In the formal verification tool, the RTL code file is set as the reference design end, and the constant value is set as the implementation design end to verify whether the logical functions of the two are equivalent.

[0054] Further, in one embodiment, the verification module performs a second equivalence verification between the logical function of the corresponding port in the physical implementation file and the constant value, including: In the formal verification tool, the constant value is set as the reference design end, and the netlist file is set as the implementation design end to verify whether the logical functions of the two are equivalent.

[0055] Further, in one embodiment, the approval module determines the special approval conclusion of the constant port of the submodule based on the special verification result, including: If the verification results of all constant ports in the special verification results are all passed, then the special approval conclusion is determined to be passed; If any constant port in the special verification results fails, then the special approval conclusion is determined to be a failure.

[0056] The functions of each module in the aforementioned chip constant port formal verification device correspond to the steps in the aforementioned chip constant port formal verification method embodiment, and their functions and implementation processes will not be described in detail here.

[0057] Thirdly, embodiments of this application provide a chip constant port format verification device, which can be a personal computer (PC), laptop computer, server, or other device with data processing capabilities.

[0058] Reference Figure 4 , Figure 4 This is a schematic diagram of the hardware structure of the chip constant port formal verification device involved in the embodiments of this application. In the embodiments of this application, the chip constant port formal verification device may include a processor, a memory, a communication interface, and a communication bus.

[0059] The communication bus can be of any type and is used to interconnect the processor, memory, and communication interface.

[0060] The communication interface includes input / output (I / O) interfaces, physical interfaces, and logical interfaces used for interconnecting devices within the chip constant port formal verification device, as well as interfaces used for interconnecting the chip constant port formal verification device with other devices (such as other computing devices or user equipment). Physical interfaces can be Ethernet interfaces, fiber optic interfaces, ATM interfaces, etc.; user equipment can be displays, keyboards, etc.

[0061] Memory can be various types of storage media, such as random access memory (RAM), read-only memory (ROM), non-volatile RAM (NVRAM), flash memory, optical storage, hard disk, programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), etc.

[0062] The processor can be a general-purpose processor, which can call the chip constant port formal verification program stored in memory and execute the chip constant port formal verification method provided in the embodiments of this application. For example, the general-purpose processor can be a central processing unit (CPU). The method executed when the chip constant port formal verification program is called can be referred to the various embodiments of the chip constant port formal verification method of this application, and will not be repeated here.

[0063] Those skilled in the art will understand that Figure 4The hardware structure shown does not constitute a limitation of this application and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0064] Fourthly, embodiments of this application also provide a computer-readable storage medium.

[0065] The present application stores a chip constant port formal verification program on a computer-readable storage medium, wherein when the chip constant port formal verification program is executed by a processor, it implements the steps of the chip constant port formal verification method as described above.

[0066] The method implemented when the chip constant port formal verification program is executed can be referred to in various embodiments of the chip constant port formal verification method of this application, and will not be repeated here.

[0067] It should be noted that the sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0068] The terms "comprising" and "having," and any variations thereof, in the specification, claims, and accompanying drawings of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus. The terms "first," "second," and "third," etc., are used to distinguish different objects, etc., and do not indicate a sequence, nor do they limit "first," "second," and "third" to different types.

[0069] In the description of the embodiments of this application, terms such as "exemplary," "for example," or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplary," "for example," or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary," "for example," or "for instance" is intended to present the relevant concepts in a concrete manner.

[0070] In the description of the embodiments of this application, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The "and / or" in the text is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of this application, "multiple" means two or more.

[0071] In some processes described in the embodiments of this application, multiple operations or steps are included in a specific order. However, it should be understood that these operations or steps may not be executed in the order they appear in the embodiments of this application, or they may be executed in parallel. The sequence number of the operation is only used to distinguish different operations, and the sequence number itself does not represent any execution order. In addition, these processes may include more or fewer operations, and these operations or steps may be executed sequentially or in parallel, and these operations or steps may be combined.

[0072] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a terminal device to execute the methods described in the various embodiments of this application.

[0073] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method for verifying the form of constant ports on a chip, characterized in that, The chip constant port formal verification method includes: Obtain the design file and timing model file of the submodule to be verified. The design file includes a logical design file and a physical implementation file. The timing model file has constant attributes marked with constant ports. Extract the ports marked with the constant attributes and their corresponding constant values ​​from the time series model file; Using formal verification tools, based on the extracted ports and constant values, the logical functions of the corresponding ports in the logical design file are subjected to a first equivalence verification with the constant values, and the logical functions of the corresponding ports in the physical implementation file are subjected to a second equivalence verification with the constant values, thereby obtaining specific verification results; Based on the specific verification results, determine the specific approval conclusion for the constant ports of the submodule; The logic design file is a register transfer level RTL code file, and the physical implementation file is a netlist file after physical implementation. The first equivalence verification of the logical function of the corresponding port in the logical design file with the constant value includes: In the formal verification tool, the RTL code file is set as the reference design end, and the constant value is set as the implementation design end to verify whether the logical functions of the two are equivalent. The step of performing a second equivalence verification between the logical function of the corresponding port in the physical implementation file and the constant value includes: In the formal verification tool, the constant value is set as the reference design end, and the netlist file is set as the implementation design end to verify whether the logical functions of the two are equivalent.

2. The chip constant port formal verification method as described in claim 1, characterized in that: The timing model file is a LIB library file, and the constant attribute is the function attribute marked in the LIB library file. The constant value is either 0 or 1.

3. The chip constant port formal verification method as described in claim 2, characterized in that: Extracting the ports marked with the constant attributes and their corresponding constant values ​​from the time series model file includes: Scan the LIB library files to obtain all ports that have the function attribute; The ports are categorized according to the value of the function attribute, generating a first port list with a constant value of 0 and a second port list with a constant value of 1.

4. The chip constant port formal verification method as described in claim 1, characterized in that, The step of determining the special approval conclusion for the constant port of the submodule based on the special verification result includes: If the verification results of all constant ports in the special verification results are all passed, then the special approval conclusion is determined to be passed; If any constant port in the special verification results fails, then the special approval conclusion is determined to be a failure.

5. A chip constant port form verification device, characterized in that, The chip constant port format verification device includes: The acquisition module is used to acquire the design file and timing model file of the submodule to be verified. The design file includes a logical design file and a physical implementation file. The timing model file has constant attributes marked with constant ports. An extraction module is used to extract ports marked with the constant attributes and their corresponding constant values ​​from the time series model file; The verification module is used to use formal verification tools to perform a first equivalence verification between the logical function of the corresponding port in the logical design file and the constant value based on the extracted port and constant value, and to perform a second equivalence verification between the logical function of the corresponding port in the physical implementation file and the constant value, so as to obtain specific verification results. The approval module is used to determine the approval conclusion of the constant port of the submodule based on the specific verification result. The logic design file is a register transfer level RTL code file, and the physical implementation file is a netlist file after physical implementation. The verification module performs a first equivalence verification between the logical function of the corresponding port in the logical design file and the constant value, including: In the formal verification tool, the RTL code file is set as the reference design end, and the constant value is set as the implementation design end to verify whether the logical functions of the two are equivalent. The verification module performs a second equivalence verification between the logical functions of the corresponding ports in the physical implementation file and the constant values, including: In the formal verification tool, the constant value is set as the reference design end, and the netlist file is set as the implementation design end to verify whether the logical functions of the two are equivalent.

6. A chip constant port form verification device, characterized in that, The chip constant port formal verification device includes a processor, a memory, and a chip constant port formal verification program stored in the memory and executable by the processor, wherein when the chip constant port formal verification program is executed by the processor, it implements the steps of the chip constant port formal verification method as described in any one of claims 1 to 4.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a chip constant port formal verification program, wherein when the chip constant port formal verification program is executed by a processor, it implements the steps of the chip constant port formal verification method as described in any one of claims 1 to 4.

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