Data sampling clock phase alignment system applied to ultra-high speed high-precision DAC

Abstract

The application provides a data sampling clock phase alignment system applied to a super-high-speed high-precision DAC, comprising: a clock receiving module, which divides an external input high-speed clock into a first clock signal and a second clock signal; an encoding module, which samples data by using the first clock signal; a phase shifter module, which adjusts the phase of the second clock signal and outputs a phase-shifted clock signal; a parallel-to-serial module, which samples input data according to the phase-shifted clock signal and outputs serial data; a phase detection module, which detects the phase relationship between the first clock signal and the serial data and outputs a phase detection result; and a digital control system, which adjusts the control code of the phase shifter module according to the phase detection result, so that the phase of the serial data and the first clock signal are automatically aligned. The application can effectively compensate for the timing mismatch caused by process deviation and temperature drift, and significantly improve the dynamic performance of the DAC, such as the spur-free dynamic range.

Description

Technical Field

[0001] This application belongs to the field of integrated circuit design technology, specifically relating to a data sampling clock phase alignment system for an ultra-high-speed, high-precision DAC. Background Technology

[0002] In cutting-edge systems such as quantum computing, ultra-high-speed data conversion, phased array radar, and next-generation wireless communications, ultra-high-speed digital-to-analog converters (DACs) with sampling rates of several GSPS or even tens of GSPS are facing severe challenges due to process scaling and signal integrity degradation. At advanced process nodes (such as 28nm / 16nm), the buffer in the global clock distribution network generates an inherent phase deviation of tens of picoseconds due to random mismatch between transistor threshold voltage and channel length. This deviation will be further amplified under temperature and voltage fluctuations, leading to timing mismatch between conversion units and causing high-frequency harmonic distortion of the output signal. At the same time, the difference in transmission delay between the data path and the clock path will directly degrade the setup / hold time margin, forming timing glitches and inter-symbol interference when multiple sub-DACs are interleaved. In addition, clock jitter (TJ) and power modulation effects introduced by synchronous switching noise through the power / ground network not only increase the floor noise but also further compress the available timing window, severely limiting the spurious-free dynamic range (SFDR) and signal-to-noise ratio (SNR) of the system.

[0003] To address the aforementioned issues, clock phase alignment circuits are widely used as a key timing convergence technique. This circuit is typically integrated between the data driver and the clock distribution path, employing a phase detector-based closed-loop control structure. It compares the relative positions of the clock edges of each channel with the data center in real time and uses adjustable delay lines or phase interpolators to perform channel-by-channel digital calibration of the offset. This dynamically compensates for static phase errors caused by process variations, interconnect RC parameter changes, and temperature drift, converging timing uncertainties to the sub-picosecond level. This ensures strictly synchronized conversion of all digital-to-analog converter units in the interleaved architecture, improving the spurious-free dynamic range of the output spectrum and reducing clock edge timing uncertainty.

[0004] However, existing clock phase alignment circuits still have certain limitations in interconnects used in ultra-high-speed, high-precision digital-to-analog converter applications. A single delay line or phase interpolator structure struggles to simultaneously achieve sufficient phase adjustment range and fine phase adjustment step size over a wide clock frequency range, making accurate alignment of clock edges with the data center difficult at different operating frequencies. Insufficient quantization accuracy of phase detection results limits the accurate determination of the optimal sampling point by the digital control loop. Furthermore, relying solely on automatic closed-loop calibration without flexible manual control methods can affect the reliability and applicability of the system locking the optimal phase under complex electromagnetic environments or abnormal operating conditions, thus restricting the full improvement of dynamic performance such as the spurious-free dynamic range of the digital-to-analog converter. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this application provides a data sampling clock phase alignment system for an ultra-high-speed, high-precision DAC. The technical problem to be solved by this application is achieved through the following technical solution: A data sampling clock phase alignment system for an ultra-high-speed, high-precision DAC includes: The clock receiving module is used to receive an external high-speed clock input and divide it into a first clock signal and a second clock signal. The encoding module is used to sample data using the first clock signal; A phase shifter module is used to adjust the phase of the second clock signal and output a phase-shifted clock signal; The parallel-to-serial converter module is used to sample its own input data according to the phase-shifting clock signal in order to output serial data at the optimal phase. A phase detection module is used to detect the phase relationship between the first clock signal and the serial data, and output the phase detection result; A digital control system is used to adjust the control code of the phase shifter module according to the phase detection result, thereby changing the phase of the phase-shifting clock signal so that the serial data is automatically aligned with the phase of the first clock signal.

[0006] Beneficial effects: 1. This application adopts a composite phase-shifting structure combining a delay chain and a phase interpolator. The clock phase is initially aligned by coarsely adjusting the delay chain, and then the clock phase is finely adjusted within the adjustment range of a single-stage delay unit by the phase interpolator, so as to achieve picosecond-level controllable clock adjustment, taking into account both sufficient phase adjustment range and fine phase adjustment step size.

[0007] 2. This application uses a two-stage phase shifter to broaden the phase adjustment range, thereby adapting to a wider range of clock frequencies and ensuring that the clock edges can be accurately aligned with the data center at different clock frequencies, thus improving the applicability and flexibility of the system.

[0008] 3. This application uses a 3-bit analog-to-digital converter to quantize the output of the phase detector, thereby improving the accuracy of digital control and ensuring that the clock alignment accuracy reaches the sub-picosecond level. At the same time, the digital control system can change the quantization level of the analog-to-digital converter to achieve quantization of any level of decision level, thereby enhancing the flexibility of phase detection.

[0009] 4. This application uses digital circuits to control the phase shifter and phase detection circuit, processes the detection results and feeds back the output control signal for automatic adjustment, thereby achieving automatic phase alignment between the high-speed sampling clock and high-speed data; at the same time, it supports manual phase adjustment through the SPI interface, which improves the reliability and applicability of the circuit in complex environments.

[0010] 5. In the process of adjusting the phase of the phase shifter module, this application keeps the first clock signal provided to the encoding module un-phase-shifted, ensuring that the clock performance of the sampling module is not affected by the phase adjustment, thereby ensuring the output performance of the entire DAC.

[0011] 6. This application uses a clock phase adjustment circuit to ensure that the clock edge is aligned with the data center when the encoding module samples, effectively compensating for timing mismatch caused by process deviations, changes in interconnect parameters and temperature drift, eliminating periodic spurious emissions caused by timing mismatch, and significantly improving the dynamic performance of the DAC, such as spurious-free dynamic range and signal-to-noise ratio.

[0012] The present application will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0013] Figure 1 This application provides a schematic diagram of the overall architecture of a data sampling clock phase alignment system for an ultra-high-speed, high-precision DAC. Figure 2 This is a schematic diagram of the phase shifter module provided in this application; Figure 3 A schematic diagram of the circuit structure of the phase interpolator provided in this application; Figure 4 A schematic diagram of the architecture of the phase detection module provided in this application; Figure 5 This is a schematic diagram of the input and output signal waveforms of the mixer provided in this application; Figure 6 A schematic diagram illustrating the workflow of the digital control system provided in this application performing automatic phase alignment. Detailed Implementation

[0014] The present application will be described in further detail below with reference to specific embodiments, but the implementation of the present application is not limited thereto.

[0015] like Figure 1 As shown, this application provides a data sampling clock phase alignment system for an ultra-high-speed, high-precision DAC, comprising: The clock receiving module is used to receive an external high-speed clock input and divide it into a first clock signal and a second clock signal. The encoding module is used to sample data using the first clock signal; A phase shifter module is used to adjust the phase of the second clock signal and output a phase-shifted clock signal; The parallel-to-serial converter module is used to sample its own input data according to the phase-shifting clock signal in order to output serial data at the optimal phase. A phase detection module is used to detect the phase relationship between the first clock signal and the serial data, and output the phase detection result; A digital control system is used to adjust the control code of the phase shifter module according to the phase detection result, thereby changing the phase of the phase-shifting clock signal so that the serial data is automatically aligned with the phase of the first clock signal.

[0016] refer to Figure 1 As shown, the clock phase alignment system of this invention mainly consists of a phase detector, a phase shifter, and a digital control system. The phase detection module detects the phase relationship between the data and the sampling clock, and outputs a 3-bit phase detection result to the digital control system after ADC quantization. The phase shifter adjusts the data sampling clock in the P2S, thereby changing the phase of the data output to the encoding module. The digital control system determines the phase relationship between the current clock and the data based on the output result of the phase detection module, and thereby controls the operation of the phase shifter.

[0017] exist Figure 1 In the circuit, clock receiving module 5 receives an external high-speed clock input, which is then split into two paths by module 8. One path is directly provided to encoding module 6 for sampling without any processing. The other path passes through phase shifter module 1 to generate the clock required by parallel-to-serial converter module 7. The final stage of parallel-to-serial converter module uses this clock for sampling and output, so the output data edge of parallel-to-serial converter module is the same as this clock. Phase detection module 3 outputs a 3-bit phase detection result based on the phase relationship between the input clock of encoding module 6 and the output data of parallel-to-serial converter module 7, and sends it to digital control system 2. Digital control system 2 determines the phase relationship between the current input clock of encoding module 6 and the output data of parallel-to-serial converter module 7 based on the phase detection result, and adjusts the control code of phase shifter module 1 accordingly to change the clock phase of parallel-to-serial converter module 7, thereby adjusting the data phase. At the same time, digital control system also allows external SPI manual adjustment of the clock phase.

[0018] In this invention, the clock edge of the encoding module is aligned with the data center during sampling by a clock phase adjustment circuit. Since the clock of the encoding module is not processed during the phase adjustment process, the clock performance of the sampling module is good, thereby ensuring the performance improvement of the entire DAC.

[0019] In one specific embodiment of this application, such as Figure 2 As shown, the phase shifter module is a composite structure combining a delay chain and a phase interpolator, comprising: The N-level delay chain is connected in series to receive the second clock signal and perform progressive delay. The first-level delay chain outputs the first delayed clock, the second-level delay chain outputs the second delayed clock, and so on until the Nth-level delay chain outputs the Nth delayed clock. An N-stage phase interpolator is provided, wherein the first input of the first-stage phase interpolator is connected to the first delayed clock output of the first-stage delay chain, and the second input is connected to the second clock signal; the first input of the i-th stage phase interpolator is connected to the i-th delayed clock output of the i-th stage delay chain, and the second input is connected to the output clock of the (i-1)-th stage phase interpolator, where i is an integer greater than 1 and less than or equal to N; The phase shifter module achieves coarse adjustment of the clock phase by controlling the number of conductions in the delay chain, and achieves fine adjustment of the clock phase by controlling the interpolation weight of the phase interpolator within the adjustment range of a single delay chain.

[0020] The phase shifter proposed in this invention is a composite structure combining a delay chain and a phase interpolator. For example... Figure 2 As shown, the input clock passes through The delay chain performs a delay, and the output of each delay chain is fed into the current stage's phase interpolator along with the output of the previous stage's phase interpolator for interpolation. A relatively large phase range can be adjusted by directly controlling the number of delay chains, while the phase interpolator can be fine-tuned within the delay chain adjustment range. The phase adjustment of the first-level delay chain is set to... The delay phase of the first-stage phase interpolator is That The total phase adjustment range obtained by the multi-stage delay chain is The first-stage phase interpolator adjusts the phase range to be... .

[0021] In one specific embodiment of this application, reference is made to Figure 3 As shown, each stage of the phase interpolator includes: The first differential clock input is used to receive the first set of differential clock signals, namely CLK_P1 and CLK_N1; The second differential clock input is used to receive the second set of differential clock signals, namely CLK_P2 and CLK_N2. The first bias PMOS transistor P1 and the second bias PMOS transistor P2 are used to provide bias current to the current source. The sources of the first bias PMOS transistor P1 and the second bias PMOS transistor P2 are both connected to the power supply VDD, the gates of the first bias PMOS transistor P1 and the second bias PMOS transistor P2 are both connected to the bias voltage BIAS, and the drains are respectively connected to the first output node and the second output node. The first output node outputs the first differential output signal CLK_OUTP, and the second output node outputs the second differential output signal CLK_OUTN. The third PMOS transistor P3 and the fourth PMOS transistor P4 are cross-coupled between the first output node and the second output node to form positive feedback to accelerate the output switching. The first and second sets of complementary current sinks are connected between ground and the output node. Each set consists of two input transistors and two switches. The four switches are controlled by an N-bit switch control signal to control the conduction of the two sets of current sinks in a complementary manner, thereby adjusting the weighting ratio of the two sets of differential clock signals so that the average phase of the output clock is the quantized adjustable value of the phase difference between the two sets of input clocks.

[0022] In one specific embodiment of this application, the first set of complementary current sinks consists of a first differential input transistor M1, a second differential input transistor M2, a first switch K1, and a second switch K2. The gate of the first differential input transistor M1 is connected to CLK_P1, its drain is connected to the first terminal of the first switch K1, and the second terminal of the first switch K1 is connected to the first output node. Similarly, the gate of the second differential input transistor M2 is connected to CLK_N1, its drain is connected to the first terminal of the second switch K2, and the second terminal of the second switch K2 is connected to the second output node. The second set of complementary current sinks consists of a third differential input transistor M3, a fourth differential input transistor M4, a third switch K3, and a fourth switch K4. The gate of the third differential input transistor M3 is connected to CLK_P2, its drain is connected to the first terminal of the third switch K3, and the second terminal of the third switch K3 is connected to the first output node. The gate of the fourth differential input transistor M4 is connected to CLK_N2, its drain is connected to the first terminal of the fourth switch K4, and the second terminal of the fourth switch K4 is connected to the second output node. The sources of the first differential input transistor M1, the second differential input transistor M2, the third differential input transistor M3, and the fourth differential input transistor M4 are grounded.

[0023] In one specific embodiment of this application, the phase shifter module employs a two-stage phase shifter to broaden the phase adjustment range. The coarse adjustment of the delay chain is coordinated with the fine adjustment of the phase interpolator, so that the total phase adjustment range of the phase shifter module covers multiple clock cycles to adapt to different clock frequency ranges, ensuring that the rising edge of the first clock signal can be aligned with the data center of the serial data at different clock frequencies.

[0024] The circuit structure of the phase interpolator is as follows: Figure 3As shown, the two sets of differential clocks entering the interpolator are CLK_P1, CLK_N1 and CLK_P2, CLK_N2, respectively. The two PMOS transistors at the top act as current sources to provide bias current, while the other two PMOS transistors form positive feedback to accelerate the output transition. Each of the bottom terminals consists of a set of complementary current sinks. CLK_P1, CLK_N1 and CLK_P2, CLK_N2 are controlled by N-bit switch control signals S_P and S_N, respectively. S_P and S_N are controlled by thermometers to ensure the stability of the output DC point. Assume the phase difference between the input differential clocks is... Thus, the average phase of the output clock adjustment is .

[0025] In one specific embodiment of this application, reference is made to Figure 4 As shown, the phase detection module includes: The first flip-flop D1 and the second flip-flop D2 have the serial data connected to their input terminals and the first clock signal connected to their clock terminals. Their output terminals output the first data signal DATA1_N and the second data signal DATA2_N, respectively. The first mixer MX1 ​​and the second mixer MX2 have their first input terminals connected to DATA1_N and DATA2_N respectively. The second input terminal of the first mixer MX1 ​​is connected to DATA2_N, and the second input terminal of the second mixer MX2 is connected to the first clock signal CLK_P. The first mixer MX1 ​​outputs a reference level COMP_REF, and the second mixer MX2 outputs a decision level COMP_DETE. An analog-to-digital converter (ADC) is used to compare the reference level COMP_REF with the decision level COMP_DETE to obtain a multi-bit comparison result, and quantize the multi-bit comparison result into a digital code, which is then input to the digital control system. Specifically, the ADC is a 3-bit ADC, used to quantize the comparison result of the decision level COMP_DETE and the reference level COMP_REF into a 3-bit digital code for output. The digital control system can change the quantization level of the 3-bit ADC to achieve quantization of the decision level COMP_DETE at any value.

[0026] The phase detection module adopts the following structure: Figure 4 As shown, the reference level COMP_REF is obtained through a set of quadrature data mixing, and the decision level COMP_DETE is obtained through data and clock mixing. Then, a 3-bit ADC is used to quantize COMP_DETE into a 3-bit comparison result COMP_OUT<2:0>, which is then sent to the digital control system for processing. In the ADC, the magnitudes of the three quantization levels can be changed through the digital control system to achieve arbitrary quantization of the decision level COMP_DETE.

[0027] In one specific embodiment of this application, the first mixer MX1 ​​obtains the reference level by charging the energy storage element when the first clock signal CLK_P is low, and discharging the energy storage element when the first clock signal CLK_P is high, thereby forming the reference level COMP_REF. The second mixer MX2 obtains the decision level by charging the energy storage element only when the first clock signal CLK_P is high, the first data signal DATA1_N is low, and the second data signal DATA2_N is low; at other times, the energy storage element discharges to form the decision level COMP_DETE. This ensures that when the rising edge of the first clock signal CLK_P is aligned with the rising edge of the second data signal DATA2_N, the decision level COMP_DETE is equal to the reference level COMP_REF, thereby ensuring that the rising edge of the first clock signal CLK_P is aligned with the data center of the first data signal DATA1_N.

[0028] The input and output signals of the mixer are as follows Figure 5 As shown, the COMP_DETE output is charged only when CLK_P, DATA1_N, and DATA2_N are both low; otherwise, it is discharged by the RC circuit. The COMP_REF output, on the other hand, charges the RC circuit when CLK_P is low and discharges when CLK_P is high. Therefore, the decision level COMP_DETE and the reference level COMP_REF are approximately equal only when the rising edges of clock CLK_P and DATA2_N are aligned. Since DATA2_N is orthogonal to DATA1_N, it ensures that the rising edge of clock CLK_P is aligned with the data center of DATA1_N, maintaining the optimal sampling point.

[0029] In one specific embodiment of this application, the digital control system is used to adjust the control code of the phase shifter module according to the phase detection result, thereby changing the phase of the phase-shifting clock signal so that the serial data is automatically aligned with the phase of the first clock signal. After the phase detection module stabilizes, the phase detection result output by the phase detection module is sampled. The coarse adjustment phases of the phase shifter module are traversed, and the corresponding quantization results are obtained and compared under each coarse adjustment phase. The coarse adjustment control codeword corresponding to the maximum quantization result is recorded as the optimal coarse adjustment phase. After completing the coarse adjustment traversal, the phase shifter module is adjusted to the optimal coarse adjustment phase, and the fine adjustment phase is traversed within a preset control code range near the optimal coarse adjustment phase. The fine adjustment is achieved by phase interpolation between two delay chains. After completing the fine-tuning traversal, the control code corresponding to the optimal fine-tuning phase is recorded, the phase of the phase shifter module is switched to the optimal fine-tuning phase, and the lock signal is pulled high so that the serial data is automatically aligned with the phase of the first clock signal.

[0030] The digital control system described in this application is also connected to an external SPI interface. The digital control system is able to respond to external control commands input through the external SPI interface and manually adjust the clock phase of the phase shifter module.

[0031] The digital control circuit controls the phase shifter and phase detection module. Based on the output of the phase detection module, it determines the phase difference between the current clock and data, iterates through the data to find the optimal sampling point, and locks it. The overall workflow is as follows: Figure 6 As shown, firstly, after the RC filter circuit of the phase detection module stabilizes, the 3-bit ADC quantization output COMP_OUT<2:0> of the phase detection module is sampled. The ADC quantization level is adjusted from small to large using the ADC algorithm, and the comparison results are stored sequentially in the quantization result register. This result serves as the quantization result of the current phase. Then, the coarse-adjustment phase of the phase shifter is traversed, and the above ADC quantization process is completed after each phase adjustment to obtain the quantization result of each phase. After each quantization, the size of the quantization result register is compared. The largest quantization result is taken as the current optimal phase, and its corresponding phase shifter control codeword is recorded. When a better quantization result is found, the optimal quantization result and the phase shifter control codeword are updated. After completing the coarse-adjustment phase traversal, the phase is adjusted to the optimal coarse-adjustment phase and then fine-tuned. Fine-tuning is achieved by phase interpolation between two delay chains. To ensure locking at the optimal sampling point, fine-tuning is performed within three control codes near the coarse-adjustment locked phase. After completing the fine-tuning traversal, record the optimal phase and the corresponding control codeword, switch the phase to the optimal phase, and pull the lock signal high, indicating that the clock phase has been aligned to the optimal sampling point.

[0032] This application provides a data sampling clock phase alignment system for an ultra-high-speed, high-precision DAC, comprising: a clock receiving module that divides an externally input high-speed clock into a first clock signal and a second clock signal; an encoding module that uses the first clock signal for data sampling; a phase shifter module that adjusts the phase of the second clock signal and outputs a phase-shifted clock signal; a serial-to-serial converter module that samples the input data based on the phase-shifted clock signal and outputs serial data; a phase detection module that detects the phase relationship between the first clock signal and the serial data and outputs the phase detection result; and a digital control system that adjusts the control code of the phase shifter module according to the phase detection result to automatically align the phase of the serial data with that of the first clock signal. The phase shifter module adopts a composite structure combining a delay chain and a phase interpolator, which widens the phase adjustment range by coarse adjustment of the delay chain and fine adjustment of the phase interpolator, adapting to a wide clock frequency range. The phase detection module generates a reference level and a decision level through a mixer, which are quantized by an analog-to-digital converter and sent to the digital control system for optimal sampling point search and locking. The digital control system supports both automatic phase alignment and external SPI manual adjustment modes, and maintains that the sampling clock of the encoding module is not phase-shifted during the alignment process. This invention can effectively compensate for timing mismatch caused by process deviations and temperature drift, and significantly improve the dynamic performance of the DAC, such as the spurious-free dynamic range.

[0033] It is worth noting that the terms "first" and "second" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0034] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. A data sampling clock phase alignment system for an ultra-high-speed, high-precision DAC, characterized in that, include: The clock receiving module is used to receive an external high-speed clock input and divide it into a first clock signal and a second clock signal. The encoding module is used to sample data using the first clock signal; A phase shifter module is used to adjust the phase of the second clock signal and output a phase-shifted clock signal; The parallel-to-serial converter module is used to sample its own input data according to the phase-shifting clock signal in order to output serial data at the optimal phase. A phase detection module is used to detect the phase relationship between the first clock signal and the serial data, and output the phase detection result; A digital control system is used to adjust the control code of the phase shifter module according to the phase detection result, thereby changing the phase of the phase-shifting clock signal so that the serial data is automatically aligned with the phase of the first clock signal.

2. The data sampling clock phase alignment system for an ultra-high-speed, high-precision DAC according to claim 1, characterized in that, The phase shifter module is a composite structure combining a delay chain and a phase interpolator, including: The N-level delay chain is connected in series to receive the second clock signal and perform progressive delay. The first-level delay chain outputs the first delayed clock, the second-level delay chain outputs the second delayed clock, and so on until the Nth-level delay chain outputs the Nth delayed clock. An N-stage phase interpolator is provided, wherein the first input of the first-stage phase interpolator is connected to the first delayed clock output of the first-stage delay chain, and the second input is connected to the second clock signal; the first input of the i-th stage phase interpolator is connected to the i-th delayed clock output of the i-th stage delay chain, and the second input is connected to the output clock of the (i-1)-th stage phase interpolator, where i is an integer greater than 1 and less than or equal to N; The phase shifter module achieves coarse adjustment of the clock phase by controlling the number of conductions in the delay chain, and achieves fine adjustment of the clock phase by controlling the interpolation weight of the phase interpolator within the adjustment range of a single delay chain.

3. The data sampling clock phase alignment system for an ultra-high-speed, high-precision DAC according to claim 2, characterized in that, Each stage of the phase interpolator includes: The first differential clock input is used to receive the first set of differential clock signals, namely CLK_P1 and CLK_N1; The second differential clock input is used to receive the second set of differential clock signals, namely CLK_P2 and CLK_N2. The first bias PMOS transistor (P1) and the second bias PMOS transistor (P2) are used to provide bias current to the current source. The sources of the first bias PMOS transistor (P1) and the second bias PMOS transistor (P2) are both connected to the power supply (VDD), the gates of both are connected to the bias voltage (BIAS), and the drains are connected to the first output node and the second output node, respectively. The first output node outputs a first differential output signal (CLK_OUTP), and the second output node outputs a second differential output signal (CLK_OUTN). The third PMOS transistor (P3) and the fourth PMOS transistor (P4) are cross-coupled between the first output node and the second output node to form positive feedback to accelerate the output switching. The first and second sets of complementary current sinks are connected between ground and the output node. Each set consists of two input transistors and two switches. The four switches are controlled by an N-bit switch control signal to control the conduction of the two sets of current sinks in a complementary manner, thereby adjusting the weighting ratio of the two sets of differential clock signals so that the average phase of the output clock is the quantized adjustable value of the phase difference between the two sets of input clocks.

4. The data sampling clock phase alignment system for an ultra-high-speed, high-precision DAC according to claim 3, characterized in that, The first set of complementary current sinks consists of a first differential input transistor (M1), a second differential input transistor (M2), a first switch (K1), and a second switch (K2). The gate of the first differential input transistor (M1) is connected to CLK_P1, the drain is connected to the first terminal of the first switch (K1), and the second terminal of the first switch (K1) is connected to the first output node. The gate of the second differential input transistor (M2) is connected to CLK_N1, the drain is connected to the first terminal of the second switch (K2), and the second terminal of the second switch (K2) is connected to the second output node. The second set of complementary current sinks consists of a third differential input transistor (M3), a fourth differential input transistor (M4), a third switch (K3), and a fourth switch (K4). The gate of the third differential input transistor (M3) is connected to CLK_P2, and its drain is connected to the first terminal of the third switch (K3). The second terminal of the third switch (K3) is connected to the first output node. The gate of the fourth differential input transistor (M4) is connected to CLK_N2, and its drain is connected to the first terminal of the fourth switch (K4). The second terminal of the fourth switch (K4) is connected to the second output node. The sources of the first differential input transistor (M1), the second differential input transistor (M2), the third differential input transistor (M3), and the fourth differential input transistor (M4) are grounded.

5. The data sampling clock phase alignment system according to claim 2, characterized in that, The phase shifter module employs a two-stage phase shifter to broaden the phase adjustment range. The coarse adjustment of the delay chain and the fine adjustment of the phase interpolator work together to ensure that the total phase adjustment range of the phase shifter module covers multiple clock cycles, adapting to different clock frequency ranges and ensuring that the rising edge of the first clock signal can be aligned with the data center of the serial data at different clock frequencies.

6. The data sampling clock phase alignment system for an ultra-high-speed, high-precision DAC according to claim 1, characterized in that, The phase detection module includes: The first flip-flop (D1) and the second flip-flop (D2) are connected to the serial data at their input terminals and to the first clock signal at their clock terminals. Their output terminals output the first data signal (DATA1_N) and the second data signal (DATA2_N), respectively. The first mixer (MX1) and the second mixer (MX2) have their first input terminals connected to DATA1_N and DATA2_N, respectively. The second input terminal of the first mixer (MX1) is connected to DATA2_N, and the second input terminal of the second mixer (MX2) is connected to the first clock signal (CLK_P). The first mixer (MX1) outputs a reference level (COMP_REF), and the second mixer (MX2) outputs a decision level (COMP_DETE). An analog-to-digital converter is used to compare the reference level (COMP_REF) with the decision level (COMP_DETE) to obtain a multi-bit comparison result, and quantize the multi-bit comparison result into a digital code, which is then input to the digital control system.

7. The data sampling clock phase alignment system for an ultra-high-speed, high-precision DAC according to claim 6, characterized in that, The first mixer (MX1) obtains the reference level by charging the energy storage element when the first clock signal (CLK_P) is low and discharging the energy storage element when the first clock signal (CLK_P) is high, thereby forming the reference level (COMP_REF). The second mixer (MX2) obtains the decision level by charging the energy storage element only when the first clock signal (CLK_P) is high, the first data signal (DATA1_N) is low, and the second data signal (DATA2_N) is low; at other times, the energy storage element discharges to form the decision level (COMP_DETE). This ensures that when the rising edge of the first clock signal (CLK_P) is aligned with the rising edge of the second data signal (DATA2_N), the decision level (COMP_DETE) is equal to the reference level (COMP_REF), thereby ensuring that the rising edge of the first clock signal (CLK_P) is aligned with the data center of the first data signal (DATA1_N).

8. The data sampling clock phase alignment system according to claim 6, characterized in that, The analog-to-digital converter is a 3-bit analog-to-digital converter used to quantize the comparison result between the decision level (COMP_DETE) and the reference level (COMP_REF) into a 3-bit digital code output; The digital control system can change the quantization level of the 3-bit analog-to-digital converter to achieve quantization of the decision level (COMP_DETE) at any value.

9. The data sampling clock phase alignment system according to claim 1, characterized in that, The digital control system, used to adjust the control code of the phase shifter module according to the phase detection result, thereby changing the phase of the phase-shifting clock signal, so that the serial data is automatically aligned with the phase of the first clock signal, is configured as follows: After the phase detection module stabilizes, the phase detection result output by the phase detection module is sampled. The coarse adjustment phases of the phase shifter module are traversed, and the corresponding quantization results are obtained and compared under each coarse adjustment phase. The coarse adjustment control codeword corresponding to the maximum quantization result is recorded as the optimal coarse adjustment phase. After completing the coarse adjustment traversal, the phase shifter module is adjusted to the optimal coarse adjustment phase, and the fine adjustment phase is traversed within a preset control code range near the optimal coarse adjustment phase. The fine adjustment is achieved by phase interpolation between two delay chains. After completing the fine-tuning traversal, the control code corresponding to the optimal fine-tuning phase is recorded, the phase of the phase shifter module is switched to the optimal fine-tuning phase, and the lock signal is pulled high so that the serial data is automatically aligned with the phase of the first clock signal.

10. The data sampling clock phase alignment system according to claim 1, characterized in that, The digital control system is also connected to an external SPI interface, which allows the digital control system to respond to external control commands input through the external SPI interface and manually adjust the clock phase of the phase shifter module.

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