Method, device and storage medium for generating a resistive network model

Abstract

A method and device for generating a resistance network model and a storage medium are disclosed. The method comprises the following steps: reading a circuit design file, parsing attribute information of a plurality of target ports, and constructing an initial improved node analysis matrix corresponding to the plurality of target ports; creating a virtual reference node, introducing a port excitation variable and a constraint relationship between the target port and the virtual reference node, and determining a target improved node analysis matrix; performing port excitation on the plurality of target ports, and determining a target improved node analysis equation set; solving to determine the response current variable of the plurality of target ports under port excitation; based on the response current variable, constructing a port admittance matrix for representing the electrical relationship between the plurality of target ports; generating a conductance network between the plurality of target ports and a resistance network between the plurality of target ports based on the port admittance matrix; and generating a circuit simulation netlist file based on the resistance network. The present application has the technical effect of improving the generation efficiency of the resistance network model.

Description

Technical Field

[0001] This disclosure relates to the field of electronic design automation technology, and in particular to a method, apparatus and storage medium for generating a resistor network model. Background Technology

[0002] In high-speed electronic circuit systems, power distribution networks are used to transmit electrical energy from power modules to processors, memory, interface chips, and other functional modules. The conductive structures in circuit boards and integrated circuit packages, such as traces, copper traces, vias, pads, and package interconnects, are not ideal conductors and generate parasitic resistance along the power transmission path. When load current flows through these paths, a DC voltage drop occurs, causing the actual supply voltage at the load end to deviate from the design value, thus affecting the operational stability of devices and the reliability of the system. Therefore, accurately generating a resistance network model between multiple device pins or critical connection points is crucial for evaluating power paths, locating local resistance anomalies, and verifying the reliability of the power distribution network during the design, verification, and debugging of circuit boards and integrated circuit packages. Summary of the Invention

[0003] In view of this, embodiments of this application provide a method, apparatus and storage medium for generating a resistor network model, in order to improve the generation efficiency of the resistor network model. Firstly, a method for generating a resistor network model is provided, comprising: reading a circuit design file and parsing the attribute information of multiple target ports, the attribute information including: component information, physical location information, network information, and corresponding node number information of the target ports; constructing an initial improved node analysis matrix corresponding to the multiple target ports based on the attribute information of the multiple target ports; creating virtual reference nodes in the initial improved node analysis matrix and introducing port excitation variables and constraint relationships between the target ports and the virtual reference nodes to determine the target improved node analysis matrix; performing port excitation on the multiple target ports according to a preset excitation sequence to determine the target improved node analysis equation set corresponding to each port excitation; solving each target improved node analysis equation set to determine the response current variables of the multiple target ports under port excitation; constructing a port admittance matrix to characterize the electrical relationship between the multiple target ports based on the response current variables of the multiple target ports under different port excitations; generating a conduction network between the multiple target ports based on the port admittance matrix and generating a resistance network between the multiple target ports based on the conduction network; and generating a circuit simulation netlist file based on the resistance network.

[0004] The above method for generating resistor network models can parse the attribute information of multiple target ports from the circuit design file and construct an initial improved node analysis matrix based on the node data and network data related to the multiple target ports. Subsequently, a target improved node analysis matrix is ​​formed through virtual reference nodes, port excitation variables, and constraint relationships, and port excitation and equation solving are performed sequentially for multiple target ports. A port admittance matrix is ​​constructed based on the response current variables under different port excitations, and then the port admittance matrix is ​​converted into a conductance network and a resistance network, finally outputting a circuit simulation netlist file. This improves the automation level of generating resistor network models between multiple target ports, reduces the workload of manually organizing the resistance connection relationships between ports, and increases the efficiency of resistor network model generation.

[0005] Optionally, a virtual reference node is created in the initial improved node analysis matrix, and port excitation variables and constraint relationships between the target port and the virtual reference node are introduced to determine the target improved node analysis matrix. This includes: determining the port relationship between the target port and the virtual reference node for each target port; adding matrix rows and columns of port excitation variables corresponding to the port relationship to the initial improved node analysis matrix; and configuring constraint coefficients to characterize the port relationship in the matrix rows and columns to obtain the target improved node analysis matrix.

[0006] Optionally, based on a preset excitation sequence, multiple target ports are excited respectively, and the target improvement node analysis equation set corresponding to each port excitation is determined, including: according to the preset excitation sequence, one of the multiple target ports is determined as the current excitation port; the current excitation port is set to the excitation state, and the other target ports among the multiple target ports except the current excitation port are set to the non-excitation state; based on the excitation state of the current excitation port, the non-excitation state of the other target ports, and the target improvement node analysis matrix, the target improvement node analysis equation set corresponding to the current excitation port is determined.

[0007] Optionally, the improved node analysis equations for each target are solved to determine the response current variables corresponding to multiple target ports under port excitation, including: solving the improved node analysis equations for the current excitation port to obtain the solution vector of the improved node analysis equations; extracting the response current variables corresponding to multiple target ports from the solution vector; wherein the response current variables are used to represent the response current of the target port when port excitation is applied to the current excitation port.

[0008] Optionally, during the process of stimulating multiple target ports according to a preset stimulation sequence, the target improvement node analysis matrix remains unchanged, and the stimulation terms in the target improvement node analysis equation set are adjusted based on the target port currently being stimulated.

[0009] Optionally, a conductance network between multiple target ports is generated based on the port admittance matrix, and a resistance network between multiple target ports is generated based on the conductance network, including: determining the mutual conductance between multiple target ports based on the off-diagonal elements in the port admittance matrix and generating the conductance network; performing an inverse transformation on the mutual conductance in the conductance network to obtain the equivalent resistance between multiple target ports; and generating a resistance network based on the equivalent resistance between multiple target ports.

[0010] Optionally, a circuit simulation netlist file is generated based on the resistor network, including: generating multiple resistor connection relationships based on multiple equivalent resistors; and generating a circuit simulation netlist file based on multiple resistor connection relationships, model connection point information, coordinate unit information, network information, and resistance value information corresponding to the resistor network.

[0011] Optionally, after reading the circuit design file and parsing the attribute information of multiple target ports, the method further includes: grouping the multiple target ports based on the network information to which they belong, to obtain at least one target port group; and constructing an initial improved node analysis matrix corresponding to each target port group.

[0012] Secondly, a device for generating a resistor network model is provided, comprising: a parsing unit for reading a circuit design file and parsing to obtain attribute information of multiple target ports, the attribute information including: component information, physical location information, network information, and corresponding node number information of the target ports; a matrix construction unit for constructing an initial improved node analysis matrix corresponding to the multiple target ports based on the attribute information of the multiple target ports; a port processing unit for creating virtual reference nodes in the initial improved node analysis matrix and introducing port excitation variables and constraint relationships between the target ports and the virtual reference nodes to determine the target improved node analysis matrix; and an excitation processing unit for using... The system performs port excitation on multiple target ports according to a preset excitation sequence, and determines the target improved node analysis equation set corresponding to each port excitation; a solution unit is used to solve the target improved node analysis equation set to determine the response current variables of multiple target ports under port excitation; a network generation unit is used to construct a port admittance matrix to characterize the electrical relationship between multiple target ports based on the response current variables of multiple target ports under different port excitations, generate a conductance network between multiple target ports based on the port admittance matrix, and generate a resistance network between multiple target ports based on the conductance network; a file generation unit is used to generate a circuit simulation netlist file based on the resistance network.

[0013] Thirdly, a computer-readable storage medium is provided, in which a computer program is stored, which, when executed by a processor, implements the method for generating the resistor network model as provided in the first aspect. Attached Figure Description

[0014] The accompanying drawings used in the description of the embodiments of this disclosure are briefly introduced below: Figure 1 A flowchart illustrating a method for generating a resistor network model provided in some embodiments of this application is shown. Figure 2 A flowchart illustrating a method for determining a target improved node analysis matrix provided in some embodiments of this application is shown. Figure 3 The diagram illustrates a matrix diagram of adding port excitation variables and constraint relationships according to some embodiments of this application; Figure 4 A schematic diagram of the structure of a resistor network model generation device provided in some embodiments of this application is shown. Detailed Implementation

[0015] To more clearly illustrate the technical solutions in the embodiments of this disclosure, examples of implementation methods of this disclosure will be described below with reference to the accompanying drawings. The accompanying drawings described below are merely some embodiments of this disclosure. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without creative effort. Adjustments and improvements made without departing from the concept of this disclosure are all within the protection scope of this disclosure.

[0016] To keep the drawings simple, each figure only schematically shows the parts relevant to the embodiment, and they do not represent the actual structure of the product. In addition, for the sake of clarity and ease of understanding, some figures only schematically show parts of components with the same structure or function, and there may actually be more or fewer components with the same structure or function.

[0017] In this disclosure, unless otherwise expressly specified and limited, ordinal numbers, such as “first”, “second”, etc., are used only to distinguish and describe related objects, and should not be construed as indicating or implying the relative importance or order between related objects; furthermore, they do not represent the quantity of related objects. “Multiple” includes two or more, and other quantifiers are similar. “ / ” is used to describe the relationship between related objects, indicating an “or” relationship between them. “And / or” is used to describe the relationship between related objects, including any combination relationship between them, such as “a and / or b” including: “a alone”, “b alone”, or “a and b”. “One or more” or “at least one” of multiple objects refers to any object or any combination of multiple objects, such as “one or more of a1, a2, a3” or “at least one of a1, a2, a3” including: “a1 alone”, “a2 alone”, “a3 alone”, “a1 and a2”, “a1 and a3”, “a2 and a3”, or “a1, a2 and a3”.

[0018] In high-speed electronic circuit systems, power distribution networks are used to transmit electrical energy output from power modules to processors, memory, interface chips, and other functional modules. With increasing system integration, operating frequency, and load current requirements, the parasitic resistance in the power distribution network has a more significant impact on system reliability. Conductive structures such as traces, pads, and package interconnects in circuit boards and integrated circuit packages are not ideal conductors in actual operation, and they create resistance along the power transmission path. When load current flows through these conductive structures, a DC voltage drop is generated, causing a difference between the actual supply voltage received at the load and the output voltage of the power module. If the DC voltage drop is too large, the load voltage may be lower than the voltage required for normal device operation, leading to device malfunctions, logic errors, or decreased system stability. Therefore, accurately modeling the resistance relationships between multiple target ports in the power network during the design, verification, and debugging of circuit boards and integrated circuit packages can provide a basis for power path evaluation, local resistance anomaly location, and power distribution network reliability verification.

[0019] In related technologies, parasitic resistance information can be extracted from circuit design files using electronic design automation (EDA) software to generate resistance models for circuit simulation. However, when multiple target ports are involved in modeling, solving for different combinations of target ports separately or generating resistance results individually leads to a significant increase in the number of solutions and post-processing workload as the number of target ports increases. Furthermore, the resistance extraction results output by some existing tools are not suitable for directly forming a complete resistance network among multiple target ports, nor are they easily integrated with standard circuit simulation workflows. Therefore, there is an urgent need for a method that can automatically parse target port information from circuit design files and generate resistance network models based on a unified matrix solving framework.

[0020] Therefore, embodiments of this application provide a method, apparatus, and storage medium for generating a resistor network model. This method can construct an improved node analysis matrix based on target port information in a circuit design file, and automatically generate a resistor network between multiple target ports and corresponding circuit simulation netlist files through port excitation, response current extraction, and network transformation. This allows the electrical relationships between ports in a circuit design file to be converted into a resistor network model usable for circuit simulation, thereby improving the automation and processing efficiency of multi-port resistor network model generation. Embodiments of this application will be described below with reference to the accompanying drawings.

[0021] Figure 1 The diagram illustrates a flowchart of a method for generating a resistor network model according to some embodiments of this application. The method includes at least the following steps: S110: Reads the circuit design file and parses the attribute information of multiple target ports. The attribute information includes: the component information, physical location information, network information, and corresponding node number information of the target port. S120: Based on the attribute information of multiple target ports, construct an initial improved node analysis matrix corresponding to the multiple target ports; S130: Create a virtual reference node in the initial improved node analysis matrix, and introduce the port excitation variables and constraint relationships between the target port and the virtual reference node to determine the target improved node analysis matrix; S140: Based on a preset excitation sequence, perform port excitation on multiple target ports respectively, and determine the target improved node analysis equation set corresponding to each port excitation; S150: Solve the set of analytical equations for each target improved node to determine the response current variables of multiple target ports under port excitation; S160: Based on the response current variables of multiple target ports under different port excitations, construct a port admittance matrix to characterize the electrical relationship between multiple target ports; S170: Generate a conductance network between multiple target ports based on the port admittance matrix, and generate a resistance network between multiple target ports based on the conductance network; S180: A netlist file for circuit simulation generated based on a resistor network.

[0022] In the above embodiments, the circuit design file can be a circuit board design file or an integrated circuit package design file, which may include parameter information such as components, pins, network names, layout coordinates, and data representing electrical connection relationships. In this application, the target port can be understood as an electrical port object that needs to participate in the generation of the resistor network model. It is determined by the device pins in the circuit design file, or by the connection points used to connect to external models or simulation models. Therefore, this application does not limit the target port to an independent physical device, but can also represent an object that needs to be excited by the port, have its response current extracted, and participate in the construction of admittance relationships during subsequent matrix solving and network transformation. The component information included in the attribute information of the target port can be used to determine the device or connection object to which the target port belongs, the physical location information can be used to determine the position of the target port in the circuit design file, the network information can be used to determine the electrical network in which the target port is located, and the node number information can be used to determine the node number corresponding to the target port in the circuit layout. Based on the above attribute information, the target port, which originally exists in the form of a layout, pin, or connection point, can be converted into a node object that can participate in the improved node analysis solution.

[0023] After obtaining the attribute information of multiple target ports, an initial improved node analysis matrix can be constructed based on the node and network data related to the target ports in the circuit design file. This matrix describes the electrical relationships between nodes in the network containing the target ports. During the construction process, the network range for modeling can be determined based on the network information of the target ports, and the nodes corresponding to the target ports within that network range can be determined based on the node numbers of the target ports. Subsequently, the electrical connections between the relevant nodes are organized into a matrix form, enabling the network containing the multiple target ports to participate in subsequent numerical solutions through the initial improved node analysis matrix.

[0024] After the initial improved node analysis matrix is ​​formed, virtual reference nodes can be created within it. These virtual reference nodes provide port excitation references for multiple target ports. For each target port, corresponding port excitation variables and constraints can be introduced into the initial improved node analysis matrix based on the target port and the virtual reference nodes. The port excitation variables characterize the port current response of the target port during the port excitation solution process, and the constraints characterize the excitation constraints between the node corresponding to the target port and the virtual reference nodes. Through this process, the node corresponding to the target port, the virtual reference nodes, and the port excitation variables can be incorporated into the same improved node analysis matrix, thus obtaining the target improved node analysis matrix.

[0025] In the target improvement node analysis matrix, multiple target ports can be excited according to a preset excitation sequence. Each port excitation corresponds to one target port, and the target improvement node analysis matrix forms a corresponding set of target improvement node analysis equations under that port excitation. Thus, multiple target ports can each correspond to multiple sets of target improvement node analysis equations. Further, after solving each set of target improvement node analysis equations, the response current variables corresponding to multiple target ports under port excitation can be determined, and these response current variables are used as the port response data under the current port excitation condition. Subsequently, the preset excitation sequence is continued to select the next target port for port excitation, and the processes of equation determination, equation solving, and response current variable extraction are repeated until all target ports have completed port excitation processing, obtaining multiple sets of port response data. Each set of port response data corresponds to a target port to which port excitation has been applied and includes the response current variables of multiple target ports under that port excitation condition. The system can arrange multiple sets of port response data according to the port excitation order and target port order to obtain a port admittance matrix that characterizes the electrical relationship between multiple target ports. The matrix elements in the port admittance matrix can be determined by the response current variables extracted under the corresponding port excitation conditions, so that the response relationship between different target ports can be uniformly expressed in matrix form.

[0026] After obtaining the port admittance matrix, a conductance network between multiple target ports can be generated based on the admittance relationships represented by each matrix element. Then, a resistance network is generated based on this conductance network, converting the conductance connections between the multiple target ports into corresponding equivalent resistance connections. Through this conversion, the system can transform the port admittance relationships obtained from matrix solving into a resistance network model suitable for circuit simulation. Finally, based on the multiple target ports in the resistance network, the connections between them, and the corresponding equivalent resistance values, a circuit simulation netlist file is generated for subsequent circuit simulation analysis, ensuring that the resistance network model between the multiple target ports can be integrated with the circuit simulation process.

[0027] This application can parse the attribute information of multiple target ports from circuit design files and construct an initial improved node analysis matrix based on the node data and network data related to the multiple target ports. Subsequently, a target improved node analysis matrix is ​​formed through virtual reference nodes, port excitation variables, and constraint relationships, and port excitation and equation solving are performed sequentially for multiple target ports. A port admittance matrix is ​​constructed based on the response current variables under different port excitations, and then the port admittance matrix is ​​converted into a conductance network and a resistance network, finally outputting a circuit simulation netlist file. This improves the automation level of generating resistance network models between multiple target ports, reduces the workload of manually organizing the resistance connection relationships between ports, and improves the efficiency of resistance network model generation.

[0028] Figure 2 The diagram illustrates a flowchart of a method for determining a target improved node analysis matrix according to some embodiments of this application. Step S130 creates a virtual reference node in the initial improved node analysis matrix and introduces port excitation variables and constraint relationships between the target port and the virtual reference node to determine the target improved node analysis matrix. The method further includes the following steps: S210: For each target port, determine the port relationship between the target port and the virtual reference node; S220: Add matrix rows and columns to the initial improved node analysis matrix to represent the port excitation variables corresponding to the port relationships; S230: Configure constraint coefficients in the matrix rows and columns to characterize the port relationships, thus obtaining the target improved node analysis matrix.

[0029] Figure 3 This diagram illustrates a matrix representation of adding port excitation variables and constraint relationships, as provided in some embodiments of this application. See also... Figure 3 n gnd Represents a virtual reference node, n p1 and n p2 Vn represents the node corresponding to the target port. p1 Vn p2 and Vn gnd Representing node n respectively p1 Node n p2 and virtual reference node n gnd The corresponding node voltage, I n+1 and I n+2 E represents the introduced port excitation variable. Sp1 and E Sp2 This represents the port excitation value corresponding to the target port.

[0030] For each target port, the node corresponding to that target port and the virtual reference node can be used as the two ends of the port excitation relationship, thereby determining the port relationship between the target port and the virtual reference node. See also Figure 3 For target port p1, this port relationship is formed at node n. p1 With virtual reference node n gnd Between; for target port p2, this port relationship is formed at node n p2 With virtual reference node n gnd between.

[0031] After determining the port relationships, you can add matrix rows and columns of the port excitation variables corresponding to those relationships to the initial improved node analysis matrix. See also Figure 3 For the target port p1, we can add a port excitation variable I.n+1 The corresponding matrix rows and columns; for the target port p2, the port excitation variable I can be added. n+2 The corresponding matrix rows and columns. Therefore, the port activation variables can be used as solution variables in the target improvement node analysis matrix to participate in the subsequent solution of the system of equations.

[0032] When configuring constraint coefficients in matrix rows and columns, the coefficients can be configured based on the port relationship between the node corresponding to the target port and the virtual reference node. See also Figure 3 In relation to the port excitation variable I n+1 In the corresponding matrix column, node n p1 The corresponding position configuration coefficient is 1, and the virtual reference node is n. gnd The corresponding position configuration coefficient is -1; in relation to the port excitation variable I n+2 In the corresponding matrix column, node n p2 The corresponding position configuration coefficient is 1, and the virtual reference node is n. gnd The corresponding position configuration coefficient is -1. Accordingly, in the newly added matrix row, constraint coefficients representing the excitation relationship between the node corresponding to the target port and the virtual reference node can be configured. See also Figure 3 In the newly added matrix row corresponding to target port p1, node n p1 The corresponding position configuration coefficient is 1, and the virtual reference node is n. gnd The corresponding position is configured with a coefficient of -1, and this matrix row corresponds to the port excitation value ESp1; in the newly added matrix row corresponding to the target port p2, node n p2 The corresponding position configuration coefficient is 1, and the virtual reference node is n. gnd The corresponding position is configured with a coefficient of -1, and the matrix row is made to correspond to the port excitation value ESp2.

[0033] Through the above processing, for each target port corresponding to a port excitation relationship added, the corresponding port excitation variables can be introduced into the initial improved node analysis matrix, and the corresponding matrix rows and columns can be added. Simultaneously, constraint coefficients can be configured in the matrix rows and columns to allow the port excitation relationship between the target port node and the virtual reference node to participate in the solution of subsequent equations. For multiple target ports, it can be done according to... Figure 3 The corresponding port excitation variables and constraint relationships are introduced in the manner shown to obtain the target improvement node analysis matrix.

[0034] In some embodiments of this application, multiple target ports are excited according to a preset excitation order, and the target improvement node analysis equation set corresponding to each port excitation is determined. This includes: determining one of the multiple target ports as the current excitation port according to the preset excitation order; setting the current excitation port to an excited state, and setting the other target ports among the multiple target ports except the current excitation port to an unexcited state; and determining the target improvement node analysis equation set corresponding to the current excitation port based on the excitation state of the current excitation port, the unexcited states of the other target ports, and the target improvement node analysis matrix.

[0035] A preset excitation order can be used to define the sequential order in which multiple target ports are excited, for example, based on the port numbers, port arrangement order, sorting results in the network, or a system-preset traversal order. In a single port excitation process, only one target port can be used as the current excitation port, while the remaining target ports are not used as input objects for the current port excitation. Thus, the response current variables corresponding to multiple target ports can be obtained when different target ports are used as excitation ports. With the target improvement node analysis matrix already determined, multiple target ports already have corresponding port excitation variables and constraint relationships within the matrix. Therefore, during port excitation, based on this matrix and the excitation state of the current excitation port and the non-excitation states of the remaining target ports, a set of target improvement node analysis equations corresponding to the current excitation port can be formed. This set of equations can include the target improvement node analysis matrix and excitation terms corresponding to the port excitation states. For the current excitation port, a port excitation value can be set in the corresponding excitation term; for the remaining target ports, the corresponding excitation term can be set to a non-excitation value. For example, the port excitation value can be a unit excitation value, and the non-excitation value can be zero. The analysis equations for the target improvement node corresponding to the current excitation port can be represented by the following formula 1: AX k =B k Formula 1 Where A represents the target improvement node analysis matrix, X k B represents the solution variable corresponding to the k-th port excitation. k Let B represent the excitation term corresponding to the k-th port excitation. The target improvement node analysis equations corresponding to different port excitations can have the same target improvement node analysis matrix A, but different excitation terms B. k By adjusting incentive term B kThis can represent the solution conditions when different target ports are in different excitation states. Through the above processing, multiple target improved node analysis equations can be sequentially formed based on a unified target improved node analysis matrix, each corresponding to a different target port as the current excitation port. Subsequently, by solving each target improved node analysis equation, the response current variables of multiple target ports under different port excitations can be obtained, and these can be further used to construct the port admittance matrix.

[0036] In some embodiments of this application, solving the target improved node analysis equation set and determining the response current variables corresponding to multiple target ports under port excitation includes: solving the target improved node analysis equation set corresponding to the current excitation port to obtain the solution vector of the target improved node analysis equation set; extracting the response current variables corresponding to multiple target ports from the solution vector; wherein, the response current variables are used to represent the response current corresponding to the target port when the current excitation port is subjected to port excitation.

[0037] In the above embodiments, each port excitation corresponds to solving a system of equations. The solution vector obtained can include node voltage results and port current results. The node voltage results represent the voltage state of each node under the current port excitation, and the port current results represent the current response of each target port under the current port excitation. Therefore, after solving the target improved node analysis equations corresponding to the current excitation port, the port current results corresponding to multiple target ports can be extracted from the solution vector, and these extracted port current results can be used as the response current variables corresponding to multiple target ports. For example, the multiple target ports include target port P1, target port P2, and target port P3. When target port P1 is subjected to port excitation, the target improved node analysis equations corresponding to target port P1 can be solved, and the response current variables corresponding to target ports P1, P2, and P3 can be extracted from the solution vector. At this time, the three extracted response current variables are used to represent the current responses of target ports P1, P2, and P3 respectively when target port P1 is subjected to port excitation. When target port P2 or target port P3 is subjected to port excitation, the response current variables corresponding to multiple target ports can be extracted from the corresponding solution vector in the same way.

[0038] In some embodiments of this application, during the process of stimulating multiple target ports according to a preset stimulation order, the target improvement node analysis matrix remains unchanged, and the stimulation terms in the target improvement node analysis equation set are adjusted based on the target port currently being stimulated.

[0039] During the sequential excitation of multiple target ports, the node relationships, virtual reference nodes, and port constraint relationships corresponding to the multiple target ports can remain unchanged. Therefore, it is not necessary to reconstruct the target improved node analysis matrix for each port excitation. When forming the target improved node analysis equation set corresponding to the current excitation port, the target improved node analysis matrix can be retained, and the corresponding excitation terms can be adjusted according to the currently excited target port. The excitation terms corresponding to the currently excited target port can be set as port excitation values, and the excitation terms corresponding to other target ports can be set as non-excitation values. For example, the port excitation value can be a preset voltage excitation value, and the non-excitation value can be zero. Thus, when different target ports are excited sequentially, the matrix part of the target improved node analysis equation set can remain consistent, and the changing part can be concentrated on the excitation terms.

[0040] In some embodiments of this application, a conductance network between multiple target ports is generated based on a port admittance matrix, and a resistance network between multiple target ports is generated based on the conductance network. This includes: determining the mutual conductance between multiple target ports based on the off-diagonal elements in the port admittance matrix and generating the conductance network; performing an inverse transformation on the mutual conductance in the conductance network to obtain the equivalent resistance between multiple target ports; and generating a resistance network based on the equivalent resistance between multiple target ports.

[0041] The elements in the port admittance matrix reflect the response current generated by one target port when a port excitation is applied to another target port. For example, the element Gij represents the response current of the i-th port when a unit excitation is applied to the j-th port. For an N-pin system, the off-diagonal element Gij of the converted conductance network matrix represents the mutual conductance between pin i and pin j, while the diagonal elements represent the self-conductance of pin i to ground and the sum of all mutual conductances. To convert the port admittance matrix into a connection network more suitable for circuit simulation, the mutual conductance between multiple target ports can be determined based on the off-diagonal elements of the port admittance matrix, and a conductance network can be generated accordingly. Taking three target ports as an example, the port admittance matrix can include matrix elements such as G11, G12, G13, G21, G22, G23, G31, G32, and G33. After conversion, the conductance network matrix is ​​obtained. The off-diagonal elements in the conductance network matrix represent the mutual conductance between target ports, while the diagonal elements represent the combination of mutual conductance and conductance to ground associated with the corresponding target port. The conversion relationship from the port admittance matrix to the conductance network matrix can be found in Formula 2 below: Formula 2 Where G11 to G33 represent the matrix elements in the port admittance matrix; 12. 13. twenty one, twenty three, 31. 32 indicates the mutual conductance between target ports; `gnd` represents the conductance to ground corresponding to the target port. The off-diagonal elements of the conductance network matrix are represented by the inverse of the mutual conductance. The diagonal elements of the conductance network matrix include the mutual conductance and the conductance to ground associated with the corresponding target port. Specifically, the off-diagonal elements in the conductance network matrix represent the conductance connection relationship between two different target ports. For example, the element in the first row and second column corresponds to the mutual conductance between target port P1 and target port P2. 12. The element in the first row and third column corresponds to the mutual conductance between target port P1 and target port P3. 13. A larger conductance value indicates a stronger equivalent conductance between the two target ports, resulting in a smaller equivalent resistance after subsequent conversion. The diagonal elements in the conductance network matrix represent the sum of the mutual conductance between the target port and other target ports, as well as the conductance of the target port to ground. For example, the diagonal element corresponding to target port P1 can be represented by the mutual conductance between target port P1 and target port P2. 12. Mutual conductance between target port P1 and target port P3 13 and the ground conductance corresponding to the target port P1 gnd is jointly determined. Therefore, the conductance network matrix can simultaneously express the mutual conductance relationship between each target port and the total conductance relationship of each target port's external connections in matrix form.

[0042] After obtaining the conductance network, the reciprocal conversion of the mutual conductances in the network can be performed to obtain the equivalent resistance between multiple target ports. The conversion relationship between mutual conductance and equivalent resistance can be found in the following formula 3: Formula 3 Here, Rij represents the equivalent resistance between the i-th and j-th target ports. Based on Equation 3, the mutual conductance in the conductance network can be converted into the equivalent resistance between the target ports. After obtaining the equivalent resistance between multiple target ports, a resistance network [Rij] can be generated based on the multiple target ports and multiple equivalent resistances. This matrix describes the equivalent DC resistance between any two pins. For any two target ports with mutual conductance, a corresponding equivalent resistance connection can be formed in the resistance network. Thus, the response relationship in the port admittance matrix can be successively converted into a conductance network and a resistance network, allowing the matrix solution results to participate in subsequent circuit simulations in the form of a resistance network model.

[0043] In some embodiments of this application, generating a circuit simulation netlist file based on a resistor network includes: generating multiple resistor connection relationships based on multiple equivalent resistors; and generating a circuit simulation netlist file based on the multiple resistor connection relationships, model connection point information, coordinate unit information, network information, and resistance value information corresponding to the resistor network.

[0044] When generating multiple resistance connections based on multiple equivalent resistances, the target ports corresponding to both ends of the equivalent resistance can be used as connection nodes, and the resistance value of the equivalent resistance can be used as the resistance value between the connection nodes. Thus, the resistance relationships expressed in matrix or network form in the resistance network can be converted into identifiable resistance element connection relationships in the circuit simulation netlist file.

[0045] When generating a circuit simulation netlist file, the connection point names in the netlist file can be determined based on the model connection point information. Model connection point information indicates the connection location of the target port in the circuit simulation model, ensuring that the target port in the resistor network corresponds to the port or node in the subsequent simulation model. Coordinate unit information records the coordinate units of the target port or model connection point in the circuit design file, allowing the circuit simulation netlist file to retain auxiliary information related to the layout location. Belonging network information identifies the electrical network corresponding to the target port, ensuring that the resistor connection relationships correspond to the network information in the original circuit design file. Resistance value information represents the equivalent resistance value corresponding to each resistor connection relationship. For example, the circuit simulation netlist file can use a SPICE-compatible netlist format, generating a resistor element record for each resistor connection relationship. This resistor element record can include the resistor element name, first connection node, second connection node, and resistance value. For example, a resistor element record can be represented in the form of "Resistor Element Name R1 First Connection Node Port1 Second Connection Node Port2 Resistance Value Ω". Using the above method, the equivalent resistance between multiple target ports can be converted into multiple resistive element records and written into the circuit simulation netlist file. The converted circuit simulation netlist file allows the resistance network model between multiple target ports to be used by subsequent circuit simulation tools. This enables automated conversion from circuit design files to resistance network models and then to circuit simulation netlist files, improving the ease of use of resistance network models in subsequent simulation analysis.

[0046] In some embodiments of this application, after reading the circuit design file and parsing the attribute information of multiple target ports, the method further includes: grouping the multiple target ports based on the network information to which the multiple target ports belong, to obtain at least one target port group; and constructing an initial improved node analysis matrix corresponding to each target port group.

[0047] Since different target ports may belong to different electrical networks, directly including all target ports in the same resistor network model generation process could lead to mixed port relationships across different networks, affecting the accuracy of subsequent port excitation, admittance matrix construction, and resistor network transformation. Therefore, multiple target ports can be grouped according to their network information, ensuring that target ports belonging to the same electrical network are grouped into the same target port group. For example, multiple target ports could include target port P1, target port P2, target port P3, and target port P4. If target ports P1 and P2 belong to the first network, and target ports P3 and P4 belong to the second network, then target ports P1 and P2 can be grouped into the first target port group, and target ports P3 and P4 into the second target port group. Thus, different target port groups can correspond to different network modeling ranges.

[0048] After obtaining at least one target port group, an initial improved node analysis matrix can be constructed for each target port group. For any target port group, based on the attribute information of each target port in the target port group, the network range corresponding to the target port group, the nodes corresponding to the target ports, and the electrical connection relationships between related nodes can be determined. The above electrical connection relationships are then organized into a matrix form to obtain the initial improved node analysis matrix corresponding to the target port group.

[0049] Figure 4A schematic diagram of a resistor network model generation device provided in some embodiments of this application is shown. The generation device 400 includes: a parsing unit 410, used to read circuit design files and parse attribute information of multiple target ports, including: component information, physical location information, network information, and corresponding node number information of the target ports; a matrix construction unit 420, used to construct an initial improved node analysis matrix corresponding to the multiple target ports based on the attribute information of the multiple target ports; a port processing unit 430, used to create virtual reference nodes in the initial improved node analysis matrix and introduce port excitation variables and constraint relationships between the target ports and the virtual reference nodes to determine the target improved node analysis matrix; and an excitation processing unit 440, used to... The excitation sequence applies port excitation to multiple target ports respectively, and determines the target improved node analysis equation set corresponding to each port excitation; the solution unit 450 is used to solve the target improved node analysis equation set to determine the response current variables of multiple target ports under port excitation; the network generation unit 460 is used to construct a port admittance matrix to characterize the electrical relationship between multiple target ports based on the response current variables of multiple target ports under different port excitations, generate a conductance network between multiple target ports based on the port admittance matrix, and generate a resistance network between multiple target ports based on the conductance network; the file generation unit 470 is used to generate a circuit simulation netlist file based on the resistance network.

[0050] The specific implementation method and beneficial effects of the device for generating the resistor network model can be found in the above-described generation method, and will not be repeated here.

[0051] Based on the same technical concept, this application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the method for generating the resistor network model as provided in the above embodiments.

[0052] In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not described in detail or in a particular embodiment can be referred to in the relevant descriptions of other embodiments. Furthermore, the above embodiments can be freely combined as needed.

Claims

1. A method for generating a resistor network model, characterized in that, include: The circuit design file is read and parsed to obtain the attribute information of multiple target ports. The attribute information includes: the component information, physical location information, network information, and corresponding node number information of the target port. Based on the attribute information of the multiple target ports, an initial improved node analysis matrix corresponding to the multiple target ports is constructed; A virtual reference node is created in the initial improved node analysis matrix, and the port excitation variables and constraint relationships between the target port and the virtual reference node are introduced to determine the target improved node analysis matrix; Based on a preset excitation sequence, port excitation is performed on multiple target ports respectively, and the target improved node analysis equation set corresponding to each port excitation is determined; Solve the set of analytical equations for each of the target improved nodes to determine the response current variables of the multiple target ports under port excitation; Based on the response current variables of the multiple target ports under different port excitations, a port admittance matrix is ​​constructed to characterize the electrical relationship between the multiple target ports; A conductance network is generated between multiple target ports based on the port admittance matrix, and a resistance network is generated between multiple target ports based on the conductance network. A circuit simulation netlist file is generated based on the resistor network.

2. The method for generating a resistor network model according to claim 1, characterized in that, A virtual reference node is created in the initial improved node analysis matrix, and port excitation variables and constraint relationships between the target port and the virtual reference node are introduced to determine the target improved node analysis matrix, including: For each target port, determine the port relationship between the target port and the virtual reference node; Add matrix rows and columns to the initial improved node analysis matrix corresponding to the port excitation variables of the port relationship; By configuring constraint coefficients to characterize the port relationships in the matrix rows and columns, the target improved node analysis matrix is ​​obtained.

3. The method for generating a resistor network model according to claim 2, characterized in that, Based on a preset excitation sequence, port excitation is performed on multiple target ports respectively, and the target improved node analysis equation set corresponding to each port excitation is determined, including: According to the preset excitation order, one of the multiple target ports is determined as the current excitation port in sequence; Set the current excitation port to the excitation state, and set the remaining target ports (excluding the current excitation port) among the multiple target ports to the non-excitation state; Based on the excitation state of the current excitation port, the non-excitation states of the other target ports, and the target improvement node analysis matrix, the target improvement node analysis equation set corresponding to the current excitation port is determined.

4. The method for generating a resistor network model according to claim 3, characterized in that, Solve the analysis equations for each of the target improved nodes to determine the response current variables of the multiple target ports under port excitation, including: Solve the target improved node analysis equations corresponding to the current excitation port to obtain the solution vector of the target improved node analysis equations. Extract the response current variables corresponding to multiple target ports from the solution vector; The response current variable is used to represent the response current of the target port when the current excitation port is subjected to port excitation.

5. The method for generating a resistor network model according to claim 3, characterized in that, During the process of stimulating multiple target ports according to a preset stimulation order, the target improvement node analysis matrix remains unchanged, and the stimulation terms in the target improvement node analysis equation set are adjusted based on the target port that is currently stimulated.

6. The method for generating a resistor network model according to claim 3, characterized in that, Generating a conductance network among multiple target ports based on the port admittance matrix, and generating a resistance network among multiple target ports based on the conductance network, including: Based on the off-diagonal elements in the port admittance matrix, the mutual conductance between the multiple target ports is determined, and the conductance network is generated. By performing a reciprocal conversion on the mutual conductance in the conductance network, the equivalent resistance between the multiple target ports is obtained; The resistor network is generated based on the equivalent resistance between the multiple target ports.

7. The method for generating a resistor network model according to claim 6, characterized in that, The circuit simulation netlist file generated based on the resistor network includes: Based on the multiple equivalent resistances, multiple resistance connection relationships are generated; Based on the multiple resistor connection relationships, model connection point information, coordinate unit information, network information, and resistance value information corresponding to the resistor network, the circuit simulation netlist file is generated.

8. The method for generating a resistor network model according to any one of claims 1 to 7, characterized in that, After reading the circuit design file and parsing the attribute information of multiple target ports, the process also includes: Based on the network information of the multiple target ports, the multiple target ports are grouped to obtain at least one target port group; For each target port group, an initial improved node analysis matrix corresponding to the target port group is constructed.

9. A device for generating a resistor network model, characterized in that, include: The parsing unit is used to read the circuit design file and parse it to obtain the attribute information of multiple target ports. The attribute information includes: the component information, physical location information, network information, and corresponding node number information of the target port. A matrix construction unit is used to construct an initial improved node analysis matrix corresponding to the multiple target ports based on the attribute information of the multiple target ports; The port processing unit is used to create a virtual reference node in the initial improved node analysis matrix, and introduce the port excitation variables and constraint relationships between the target port and the virtual reference node to determine the target improved node analysis matrix; The excitation processing unit is used to excite multiple target ports according to a preset excitation sequence and determine the target improved node analysis equation set corresponding to each port excitation. The solving unit is used to solve the set of analytical equations for each of the target improved nodes and determine the response current variables of the multiple target ports under port excitation. The network generation unit is used to construct a port admittance matrix to characterize the electrical relationship between the multiple target ports based on the response current variables corresponding to the multiple target ports under different port excitations, generate an electrical conductance network between the multiple target ports based on the port admittance matrix, and generate a resistance network between the multiple target ports based on the electrical conductance network. The file generation unit is used to generate a circuit simulation netlist file based on the resistor network.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method for generating a resistor network model according to any one of claims 1 to 8.

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