An LDMOS hybrid device model construction method and device, and electronic equipment

Abstract

The application provides a LDMOS hybrid device model construction method and device and electronic equipment, relates to the integrated circuit simulation technical field, and the method comprises the following steps: constructing and calibrating a reference model suitable for adapting a LDMOS device; forming a temporary simulation circuit by circumscribing an adjustable resistor on the reference model, determining a sampling calibration resistor by adjusting the adjustable resistor to simulate the temporary simulation circuit; constructing a sample data set based on the sampling calibration resistor, training a neural network model by using the sample data set, and enabling the neural network model to predict the drift region equivalent resistance of the LDMOS device; encapsulating the trained neural network model into a subcircuit by using a simulation hardware description language, connecting the subcircuit in series to the drain branch of the reference model, and forming a LDMOS hybrid device model. By using the LDMOS hybrid device model construction method, device and electronic equipment, the workload of parameter adjustment is shortened, and the problem of long device model modeling period is solved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit simulation technology, and more specifically, to a method, apparatus, and electronic device for constructing an LDMOS hybrid device model. Background Technology

[0002] Laterally diffused metal-oxide-semiconductor (LDMOS) is a commonly used high-voltage power device widely applied in power management, radio frequency integrated circuits, and other fields. During the circuit design phase, SPICE simulation tools are needed to simulate the electrical characteristics of the device. The accuracy of the compact device model directly determines the reliability of the circuit simulation results. Currently, BSIM4 (Berkeley Short-channel IGFET Model 4) is the industry-standard MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device model, accurately characterizing the electrical behavior of the intrinsic channel under the MOSFET gate. However, the physical framework of BSIM4 only covers the channel region and does not include the high-voltage drift region structure at the LDMOS drain. Therefore, it cannot natively characterize the nonlinear resistance effect, quasi-saturation effect, and depletion modulation effect caused by the drift region. Directly using the BSIM4 model to simulate LDMOS will result in large deviations between the current curve and the measured device data, leading to insufficient simulation accuracy.

[0003] Currently, hybrid compensation modeling schemes are mainly used to improve the modeling accuracy of LDMOS models. For example, multiple sets of voltage-controlled resistors and voltage-controlled current sources are externally connected to the BSIM4 reference model, and the nonlinearity of the drift region is compensated by manually adjusting a large number of circuit parameters. However, the drift region characteristics of LDMOS exhibit strong nonlinearity with gate-source voltage and drain-source voltage. When multiple physical effects such as quasi-saturation, self-heating, and impulse ionization are superimposed, a large number of sub-circuits and fitting parameters need to be added, resulting in a huge workload for parameter adjustment and a long modeling cycle. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a method, apparatus and electronic device for constructing an LDMOS hybrid device model, so as to overcome at least one of the above-mentioned defects.

[0005] In a first aspect, embodiments of this application provide a method for constructing an LDMOS hybrid device model, including: Construct and calibrate a reference model adapted to LDMOS devices so that the model simulation current output by the reference model is greater than the actual measured current of the device. The reference model refers to the MOSFET reference model used to describe the intrinsic channel electrical characteristics of LDMOS. An adjustable resistor is connected to the baseline model to form a temporary simulation circuit. The sampling calibration resistor is determined by simulating the temporary simulation circuit by adjusting the adjustable resistor. A sample dataset is constructed based on the sampling calibration resistor. The sample dataset is then used to train the neural network model so that the neural network model can predict the equivalent resistance of the drift region of the LDMOS device. The trained neural network model is encapsulated into a sub-circuit using an analog hardware description language. The sub-circuit is then connected in series to the drain branch of the reference model to form an LDMOS hybrid device model.

[0006] In an optional implementation, the step of training the neural network model using a sample dataset includes: using the product of the sampling calibration resistor and the measured current of the device as the drift region voltage, and using the drift region voltage and the gate-source voltage as input data; using the input data and the sampling calibration resistor to train the neural network model until the error between the drift region equivalent resistance predicted by the neural network model and the sampling calibration resistor meets the preset accuracy requirements.

[0007] In an optional implementation, the step of training the neural network model using input data and a sampling calibration resistor until the error between the drift region equivalent resistance predicted by the neural network model and the sampling calibration resistor meets the preset accuracy requirements includes: determining the mean square error between the drift region equivalent resistance and the sampling calibration resistor; and determining that the preset accuracy requirements are met when the mean square error is less than a set error threshold.

[0008] In an optional implementation, the step of determining the sampling calibration resistor by simulating the temporary simulation circuit by adjusting the adjustable resistor includes: determining the resistance value of the adjustable resistor as the sampling calibration resistor when the circuit simulation current is equal to the measured current of the device.

[0009] In an optional implementation, the neural network model is a multilayer perceptron, which includes an input layer, a hidden layer, and an output layer. The hidden layer is a multi-level hidden layer, and each level of the hidden layer includes multiple neurons.

[0010] In an optional implementation, after constructing the sample dataset based on the sampling calibration resistor, the method further includes: preprocessing the data in the sample dataset to train the neural network model using the preprocessed sample dataset. The preprocessing includes logarithmic transformation and normalization.

[0011] In an optional implementation, the method further includes: performing inverse normalization and exponential restoration processing on the normalized predicted resistance output by the neural network model to obtain the drift region equivalent resistance with real physical dimensions.

[0012] Secondly, embodiments of this application also provide an LDMOS hybrid device model construction apparatus, the apparatus comprising: The reference model building module is used to build and calibrate a reference model adapted to LDMOS devices so that the model simulation current output by the reference model is greater than the actual measured current of the device. The reference model refers to the MOSFET reference model used to describe the intrinsic channel electrical characteristics of LDMOS. The calibration resistor determination module is used to connect an adjustable resistor to the reference model to form a temporary simulation circuit. The sampling calibration resistor is determined by simulating the temporary simulation circuit by adjusting the adjustable resistor. The network model training module is used to construct a sample dataset based on the sampled calibration resistor, and to train the neural network model using the sample dataset so that the neural network model can predict the equivalent resistance of the drift region of the LDMOS device. The device model building module is used to encapsulate the trained neural network model into sub-circuits using an analog hardware description language, and connect the sub-circuits in series to the drain branch of the reference model to form an LDMOS hybrid device model.

[0013] Thirdly, embodiments of this application also provide an electronic device, including: a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, the steps of the LDMOS hybrid device model construction method described above are performed.

[0014] Fourthly, embodiments of this application also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the steps of the LDMOS hybrid device model construction method described above.

[0015] The embodiments of this application bring the following beneficial effects: This application provides a method, apparatus, and electronic device for constructing an LDMOS hybrid device model. The method includes constructing and calibrating a reference model adapted to an LDMOS device, such that the model simulation current output by the reference model is greater than the measured current of the device. The reference model refers to a MOSFET reference model used to describe the intrinsic channel electrical characteristics of LDMOS. An adjustable resistor is connected externally to the reference model to form a temporary simulation circuit. The sampling calibration resistor is determined by simulating the temporary simulation circuit by adjusting the adjustable resistor. A sample dataset is constructed based on the sampling calibration resistor. The sample dataset is used to train a neural network model so that the neural network model can predict the equivalent resistance of the drift region of the LDMOS device. The trained neural network model is encapsulated into a sub-circuit using an analog hardware description language. The sub-circuit is connected in series to the drain branch of the reference model to form an LDMOS hybrid device model.

[0016] This application's embodiments can automatically fit the nonlinear equivalent resistance of the drift region using a neural network, eliminating the need for manual adjustments to multiple sets of compensation sub-circuit parameters, significantly reducing modeling workload and shortening the modeling cycle. Simultaneously, using a physically based benchmark model as a carrier, and only employing a neural network sub-circuit to compensate for the drift region effect, it balances model physical interpretability and simulation accuracy, avoiding the poor simulation convergence problem caused by complex equivalent circuits. Compared to existing LDMOS hybrid device model construction methods, it shortens the workload of parameter adjustment and solves the problem of long modeling cycles.

[0017] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A schematic diagram of the structure of the LDMOS model provided for the prior art; Figure 2 A flowchart illustrating the LDMOS hybrid device model construction method provided in this application embodiment is shown; Figure 3 A schematic diagram of the structure of the LDMOS hybrid device model provided in the embodiments of this application is shown; Figure 4 A schematic diagram illustrating the simulation effect of an existing LDMOS device model is shown. Figure 5 A schematic diagram illustrating the simulation effect of the LDMOS hybrid device model provided in the embodiments of this application is shown; Figure 6 A schematic diagram of the LDMOS hybrid device model building apparatus provided in this application embodiment is shown; Figure 7 A schematic diagram of the structure of the electronic device provided in the embodiments of this application is shown. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. Based on the embodiments of this application, every other embodiment obtained by those skilled in the art without inventive effort falls within the scope of protection of this application.

[0021] The following reference Figure 1 This section introduces existing LDMOS modeling methods.

[0022] Figure 1 A schematic diagram of the LDMOS model provided for existing technology. (e.g.) Figure 1 As shown, the LDMOS model includes a BSIM4 model 100, a source-side voltage-controlled resistor 110, a drain-side voltage-controlled resistor 120, and a voltage-controlled current source 130. S represents the source of the LDMOS, D represents the drain of the LDMOS, and G represents the gate of the LDMOS. Indicates intrinsic source poles, This indicates the intrinsic leak electrode.

[0023] As can be seen, the existing LDMOS model is composed of the BSIM4 intrinsic model, source-side voltage-controlled resistors, drain-side voltage-controlled resistors, and voltage-controlled current sources. It is based on multiple sets of discrete passive / active sub-circuits to compensate for drift region nonlinearity. Because it requires manual adjustment of multiple sets of voltage-controlled device parameters to compensate for drift region nonlinearity, the modeling workload is large and the cycle is long. Moreover, fixed fitting parameters cannot adapt to different process and device operating conditions, resulting in poor generalization ability. At the same time, the large number of compensation sub-circuits makes the circuit topology complex, which easily leads to problems such as poor simulation convergence and slow simulation speed. Furthermore, simple polynomials cannot fully reproduce the strong nonlinearity of the drift region, resulting in insufficient simulation fitting accuracy across the entire bias range.

[0024] To facilitate understanding of this embodiment, the following describes each of the exemplary steps provided in this embodiment using the LDMOS hybrid device model construction method provided in this application embodiment as an example of its application to a terminal device.

[0025] Please see Figure 2 , Figure 2 This is a flowchart illustrating a method for constructing a hybrid LDMOS device model, as provided in an embodiment of this application. Figure 2 As shown in the embodiments of this application, the method for constructing an LDMOS hybrid device model includes: Step S201: Construct and calibrate a reference model adapted to the LDMOS device so that the simulated current output by the reference model is greater than the measured current of the device.

[0026] A benchmark model refers to a MOSFET benchmark model used to describe the intrinsic channel electrical characteristics of LDMOS. For example, the benchmark model can be the BSIM4 model. BSIM4 is an industry-standard physical model that can be directly called by mainstream SPICE simulators. It can fully characterize the basic electrical characteristics of the intrinsic channel under the gate of the MOS transistor, such as threshold voltage, mobility, short-channel effect, channel current, intrinsic parasitic capacitance, etc.

[0027] Based on the process parameters and layout dimensions (such as channel length and device width) of the LDMOS device to be modeled, a basic BSIM4 device instance is built in the SPICE simulation environment to complete the baseline model construction. This baseline model only includes the MOS intrinsic channel physical equations and does not introduce the equivalent structure related to the high voltage drift region at the LDMOS drain, thus failing to characterize the nonlinear voltage drop, quasi-saturation, and depletion modulation effects brought about by the drift region.

[0028] After constructing the baseline model, DC IV testing (current-voltage characteristic testing) was performed on the actual LDMOS device, scanning multiple sets of different gate-source bias voltages. Drain-source bias voltage Operating conditions, complete acquisition of measured device current across the entire bias range. (Measured drain current of the device). In addition, the TCAD device simulation tool can be used to obtain current data under corresponding operating conditions, ensuring that the dataset covers the entire operating range of high and low voltage and large and small current, with sufficient data sample size, to avoid underfitting problems when calibrating the equivalent resistance of the drift region later.

[0029] In one embodiment, since the LDMOS drain drift region can be equivalent to a variable resistor, current flowing through the drift region will generate voltage drop losses, ultimately resulting in a measured device current lower than the intrinsic channel current without drift region losses. Therefore, the reference model can be calibrated to a higher simulated current, reserving adjustment space for the voltage drop caused by the drift region resistor. Subsequently, only an equivalent resistor needs to be connected in series to match the higher simulated current to the measured device current, thus allowing for the reverse calculation of the drift region sampling calibration resistor for each bias condition. It is understood that the calibration goal is: when running the reference model alone for simulation, any identical... , At the bias point, the model simulation current output by the reference model Always greater than the measured current of the device under the same operating conditions .

[0030] When performing calibration via parameter tuning, the intrinsic channel current can be increased by adjusting relevant parameters of the BSIM4 intrinsic channel, such as carrier mobility, saturation velocity, threshold voltage, and channel length modulation coefficient. During the calibration process, the intrinsic channel conduction current is continuously compared point by point under the same bias condition. and Until all scanning conditions meet the requirements. Greater than Complete the calibration of the baseline model.

[0031] The calibrated baseline model serves as the physical foundation of the LDMOS hybrid device model, fully preserving the physical mechanism of the MOS channel and possessing good physical interpretability. At the same time, by leveraging the uniformly large simulation current characteristics of the model, it provides the basic conditions for subsequent construction of temporary adjustable simulation circuits and solving the sampling calibration resistors in the drift region under various operating conditions. It is a necessary prerequisite step for constructing a neural network training sample dataset.

[0032] Step S202: Connect an adjustable resistor to the reference model to form a temporary simulation circuit, and perform simulation on the temporary simulation circuit by adjusting the adjustable resistor to determine the sampling calibration resistor.

[0033] After completing the baseline model calibration, a temporary simulation circuit with adjustable resistors can be built, and the corresponding drift region sampling calibration resistors can be solved by traversing all bias conditions. All data can then be integrated to construct a sample dataset that can be used to train the neural network.

[0034] When building the temporary simulation circuit, the calibrated reference model is used as the core component. A continuously adjustable resistor is connected in series outside the drain branch of the reference model to form an independent temporary simulation circuit. The adjustable resistor can be parametrically modeled using a SPICE subcircuit (Subckt), allowing the simulation program to automatically and continuously adjust its resistance value. The SPICE simulator is then called through the Subckt model to obtain the circuit simulation current value. This temporary simulation circuit consists only of the reference model and a single adjustable resistor, resulting in a simple topology and good simulation convergence. The input of the temporary simulation circuit is the gate-source voltage. Drain-source voltage The output is the circuit simulation current. This refers to the drain simulation current, which is used to reproduce the complete current characteristics of an LDMOS device, including the drift region voltage drop loss.

[0035] When solving for the sampling calibration resistor, the method used is completely consistent with that used for DC IV testing. , The scanning range covers the entire operating range of high and low gate voltage, high and low drain voltage, and large and small current, ensuring that the samples cover the complete operating state of the LDMOS device. For each fixed group... , The adjustable resistor value is continuously modified and SPICE simulation is performed to read the circuit simulation current output by the temporary simulation circuit in real time.

[0036] The baseline model only characterizes the intrinsic channel current of the LDMOS and does not account for the drift region voltage drop loss, resulting in an overestimation of the current obtained from the simulation alone. With an adjustable resistor connected in series with the drain, the adjustable resistor generates voltage division loss, reducing the overall output current. Therefore, when the simulated circuit current perfectly matches the measured device current, the resistance value of the adjustable resistor is exactly equivalent to the equivalent loss resistance caused by the drift region under the current bias condition. Thus, when the simulated circuit current output by the temporary simulation circuit under the current bias condition is equal to the measured device current under that condition, the adjustment of the adjustable resistor is stopped, and the resistance value of the adjustable resistor at this point is determined as the sampling calibration resistor.

[0037] Step S203: Construct a sample dataset based on the sampled calibration resistor, and use the sample dataset to train the neural network model so that the neural network model can predict the equivalent resistance of the drift region of the LDMOS device.

[0038] In one embodiment, after determining the sampling calibration resistor, a sample dataset can be constructed based on the sampling calibration resistor.

[0039] The sample dataset includes input data and sampling calibration resistors. The input data includes drift region voltage and gate-source voltage.

[0040] Specifically, for each bias combination, the following three sets of data are recorded simultaneously, including: gate-source voltage. Drift region voltage The sampling calibration resistor corresponding to the current operating condition Among them, the voltage in the drift region For sampling calibration resistor Measured current of the device The product of all input data under all scanning conditions. , ) and sampling calibration resistor The data are compiled in a one-to-one correspondence to form a sample dataset, which serves as the data foundation for training the neural network model.

[0041] In one embodiment, due to the large numerical range and wide dynamic range, directly using the sample dataset for training can easily lead to slow network convergence and poor fitting accuracy. Therefore, the input data and the sampling calibration resistor can be preprocessed, and then the preprocessed sample dataset can be used to train the neural network model.

[0042] Preprocessing includes logarithmic transformation and normalization. Logarithmic transformation refers to taking the logarithm of the data to compress the numerical range and weaken the weight differences of large samples; normalization refers to mapping the logarithmically transformed data to a uniform range to eliminate dimensional differences and accelerate the convergence speed of gradient descent in multilayer perceptron neural networks.

[0043] Normalization can be performed using the minimum-maximum method. For example, the maximum value of all sampled calibration resistors can be denoted as: The minimum value of all sampling calibration resistors is denoted as: Then the sampling calibration resistor The corresponding normalized sampling calibration resistor It can be represented as: .

[0044] In one embodiment, the neural network model is a multilayer perceptron, which is a multilayer nonlinear mathematical mapping model constructed by mimicking the connection rules of biological neurons. The neural network model includes an input layer, hidden layers, an output layer, weight bias parameters, and activation functions. The hidden layers are multi-level hidden layers, with each level including multiple neurons. For example, the input layer of the neural network model includes 2 neurons, and the multi-level hidden layers include a first-level hidden layer, a second-level hidden layer, and a third-level hidden layer. The first-level hidden layer includes 32 neurons, the second-level hidden layer includes 32 neurons, and the third-level hidden layer includes 16 neurons. The output layer includes 1 neuron. All hidden layers uniformly use the tanh activation function.

[0045] In one embodiment, when iteratively training a neural network model using a sample dataset, the sampling calibration resistor can be used. Measured current of the device The product of these is used as the drift region voltage. , the voltage of the drift region and gate-source voltage This serves as the input data. Then, the input data and the sampling calibration resistor are used... The neural network model is trained until the error between the drift region equivalent resistance predicted by the neural network model and the sampling calibration resistance meets the preset accuracy requirements.

[0046] The neural network model directly outputs the normalized predicted resistance (i.e., the preprocessed drift region resistance). This predicted resistance needs to be inversely normalized and exponentially restored to obtain the drift region equivalent resistance with true physical dimensions. Then, the mean square error (MSE) between the drift region equivalent resistance and the sampled calibration resistance is determined. If the MSE is less than a set error threshold, the preset accuracy requirement is met; if the MSE is greater than or equal to the set error threshold, the preset accuracy requirement is not met, and the neural network model continues iterative training until the preset accuracy requirement is met.

[0047] The trained neural network model can accurately predict the equivalent resistance of the drift region, and this neural network model can be used to construct an LDMOS hybrid device model.

[0048] Step S204: The neural network model is encapsulated into a sub-circuit using an analog hardware description language, and the sub-circuit is connected in series to the drain branch of the reference model to form an LDMOS hybrid device model.

[0049] Analog hardware description language refers to a dedicated hardware description language for analog / mixed-signal integrated circuits and continuous-time physical systems. It is a standard modeling language in the field of EDA (Electronic Design Automation). For example, analog hardware description language can refer to Verilog-A. Verilog-A can be recognized by mainstream SPICE simulators, supports custom nonlinear electrical behavior, various mathematical operations, and voltage / current physical signal reading, and is suitable for the development of compact power LDMOS device models.

[0050] When constructing the LDMOS hybrid device model, firstly, the weight parameters of the trained neural network model are extracted, and then the mathematical operation links of the neural network model's forward inference and output reconstruction are all encapsulated into the Subckt sub-circuit using Verilog-A code to form a complete operation path.

[0051] The operational logic of the sub-circuit includes: a real-time input signal acquisition port, a multilayer perceptron forward computation module, and an output post-processing and restoration module. The real-time input signal acquisition port refers to two sets of reserved input electrical ports within the sub-circuit, which read the gate-source voltage of the nodes within the hybrid model in real time during circuit simulation. Drift region voltage This serves as the input data for the neural network model. The multilayer perceptron forward computation module refers to the computational flow in Verilog-A that defines the matrix operations, bias superposition, and activation functions for each layer to output a normalized predicted resistance. The output post-processing restoration module refers to the built-in inverse normalization and exponential restoration operation logic, used to convert the normalized predicted resistance output by the neural network model into the drift region equivalent resistance with physical dimensions.

[0052] Then, using Verilog-A, the equivalent resistance of the drift region predicted by this neural network model is added as a resistor to the drain terminal of the reference model. This means the sub-circuit is connected in series with the drain branch of the BSIM4 reference model, assembling the LDMOS hybrid device model. Here, this application transforms the entire set of neural network calculation rules into a sub-circuit that can be directly called by SPICE, enabling joint simulation of the neural network and the reference model with the same circuit.

[0053] The following reference Figure 3 This section introduces the structure of the LDMOS hybrid device model.

[0054] Figure 3 A schematic diagram of the structure of the LDMOS hybrid device model provided in the embodiments of this application is shown, as follows: Figure 3 As shown, the LDMOS hybrid device model includes a baseline model 100 and a sub-circuit 140 corresponding to the neural network model.

[0055] The following reference Figure 4 and Figure 5 This paper will introduce the different simulation effects between the traditional LDMOS device model and the LDMOS hybrid device model of this application.

[0056] Figure 4 This diagram illustrates the simulation results of an existing LDMOS device model, such as... Figure 4 As shown in the figure, the thick line represents the measured current value of the device, and the thin line represents the simulated current value of the model. It can be seen that the simulated values ​​of the traditional LDMOS device model do not perfectly match the measured values ​​of the device.

[0057] Figure 5 The following is a schematic diagram illustrating the simulation effect of the LDMOS hybrid device model provided in the embodiments of this application: Figure 5As shown in the figure, the thick line represents the measured current value of the device, and the thin line represents the simulated current value of the model. It can be seen that the simulated current value of the LDMOS device model provided in this application perfectly matches the measured current value of the device. Compared with the existing LDMOS device models, the simulation curve of the LDMOS hybrid device model constructed in this application closely matches the measured characteristics of the device, and the simulation fitting accuracy is significantly improved.

[0058] The LDMOS hybrid device model construction method provided in this application has the following technical effects: First, the model simulation fitting accuracy is high and the error control is excellent: The LDMOS hybrid device model of BSIM4 and neural network constructed in this application can control the error between the current simulation results and the actual device data within a low range. Compared with the existing LDMOS model that relies on multiple sets of voltage-controlled compensator circuits, the simulation curve and the actual device curve fit better across the entire bias range. It can accurately reproduce electrical effects that BSIM4 cannot characterize natively, such as drift region nonlinearity and quasi-saturation, and significantly reduce the deviation between simulation and measurement.

[0059] Secondly, the modeling process is simplified, significantly reducing modeling difficulty and shortening the development cycle: Existing LDMOS modeling requires the design and debugging of multiple sets of voltage-controlled resistor / current source compensation sub-circuits for various nonlinear effects in the drift region, resulting in numerous parameters, a large workload of manual parameter tuning, and the need to re-derive and adapt physical formulas after changes in device process structure, leading to lengthy project cycles. This application only requires a single external neural network sub-circuit to uniformly represent all coupling effects in the drift region, eliminating the need to manually build multiple sets of discrete compensation modules, saving a significant amount of manual parameter tuning and physical formula development work, effectively reducing modeling difficulty and shortening the device modeling iteration cycle.

[0060] Third, the model simulation has better convergence and takes into account physical interpretability: On the one hand, the underlying model relies on the mature BSIM4 benchmark model, which fully preserves the intrinsic channel semiconductor physical mechanism of the device, has clear physical interpretability, and is more suitable for industrial chip simulation engineering; on the other hand, compared with the full neural network black box device model, this hybrid model circuit solution has stronger stability, is less prone to non-convergence and iteration error problems during transient simulation, is compatible with mainstream commercial simulation tools, and has stronger engineering practicality.

[0061] Based on the same inventive concept, this application also provides an LDMOS hybrid device model construction device corresponding to the LDMOS hybrid device model construction method. Since the principle of the device in this application is similar to the LDMOS hybrid device model construction method described above in this application, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be described again.

[0062] Please see Figure 6, Figure 6 This is a schematic diagram of a structural apparatus for constructing an LDMOS hybrid device model, provided in an embodiment of this application. Figure 6 As shown, the LDMOS hybrid device model building apparatus 300 includes: The reference model construction module 301 is used to construct and calibrate a reference model adapted to LDMOS devices so that the model simulation current output by the reference model is greater than the actual measured current of the device. The reference model refers to the MOSFET reference model used to describe the intrinsic channel electrical characteristics of LDMOS. The calibration resistor determination module 302 is used to connect an adjustable resistor to the reference model to form a temporary simulation circuit, and to determine the sampling calibration resistor by simulating the temporary simulation circuit by adjusting the adjustable resistor. The network model training module 303 is used to construct a sample dataset based on the sampled calibration resistor, and to train the neural network model using the sample dataset so that the neural network model can predict the equivalent resistance of the drift region of the LDMOS device. The device model building module 304 is used to encapsulate the trained neural network model into a sub-circuit using an analog hardware description language, and connect the sub-circuit in series to the drain branch of the reference model to form an LDMOS hybrid device model.

[0063] Please see Figure 7 , Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 7 As shown, the electronic device 400 includes a processor 410, a memory 420, and a bus 430.

[0064] The memory 420 stores machine-readable instructions executable by the processor 410. When the electronic device 400 is running, the processor 410 communicates with the memory 420 via the bus 430. When the machine-readable instructions are executed by the processor 410, they can perform the operations described above. Figure 2 The steps of the LDMOS hybrid device model construction method in the method embodiment shown are described in detail in the method embodiment, and will not be repeated here.

[0065] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, can perform the above-described actions. Figure 2 The steps of the LDMOS hybrid device model construction method in the method embodiment shown are described in detail in the method embodiment, and will not be repeated here.

[0066] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0067] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the shown or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0068] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0069] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0070] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0071] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The scope of protection of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for constructing a hybrid LDMOS device model, characterized in that, include: Construct and calibrate a reference model adapted to LDMOS devices so that the model simulation current output by the reference model is greater than the actual measured current of the device. The reference model refers to a MOSFET reference model used to describe the intrinsic channel electrical characteristics of LDMOS. An adjustable resistor is connected to the reference model to form a temporary simulation circuit. All bias conditions are traversed, and the resistance value of the adjustable resistor is adjusted so that the circuit simulation current output by the temporary simulation circuit matches the measured current of the device. The resistance value of the adjustable resistor corresponding to the matching is used as the sampling calibration resistor under the bias condition to obtain multiple sampling calibration resistors covering the complete working range of LDMOS. A sample dataset is constructed based on the sampling calibration resistor, wherein the product of the sampling calibration resistor and the measured current of the device is used as the drift region voltage, the drift region voltage and the gate-source voltage are used as input data, and the sampling calibration resistor is used as tag data. The neural network model is trained using the sample dataset so that it can predict the equivalent resistance of the drift region of the LDMOS device. The trained neural network is encapsulated into a sub-circuit using a simulated hardware description language, and the sub-circuit is connected in series to the drain branch of the reference model to form an LDMOS hybrid device model. The steps of training the neural network model using the sample dataset include: The neural network model is trained using the input data and the sampling calibration resistor until the error between the drift region equivalent resistance predicted by the neural network model and the sampling calibration resistor meets the preset accuracy requirements.

2. The method according to claim 1, characterized in that, The steps of training the neural network model using the input data and the sampling calibration resistor until the error between the drift region equivalent resistance predicted by the neural network model and the sampling calibration resistor meets the preset accuracy requirement include: Determine the mean square error between the equivalent resistance of the drift region and the sampling calibration resistance; When the mean square error is less than a set error threshold, the preset accuracy requirement is determined to be met.

3. The method according to claim 1, characterized in that, The neural network model is a multilayer perceptron, which includes an input layer, a hidden layer, and an output layer. The hidden layer is a multi-level hidden layer, and each level of the hidden layer includes multiple neurons.

4. The method according to claim 1, characterized in that, After constructing the sample dataset based on the sampling calibration resistor, the following is also included: The data in the sample dataset are preprocessed to train the neural network model using the preprocessed sample dataset. The preprocessing includes logarithmic transformation and normalization.

5. The method according to claim 1, characterized in that, The method further includes: The normalized predicted resistance output by the neural network model is inversely normalized and exponentially restored to obtain the drift region equivalent resistance with real physical dimensions.

6. An apparatus for constructing a hybrid LDMOS device model, characterized in that, include: The reference model construction module is used to construct and calibrate a reference model adapted to LDMOS devices so that the model simulation current output by the reference model is greater than the actual measured current of the device. The reference model refers to a MOSFET reference model used to describe the intrinsic channel electrical characteristics of LDMOS. The calibration resistor determination module is used to connect an adjustable resistor to the reference model to form a temporary simulation circuit, traverse all bias conditions, adjust the resistance value of the adjustable resistor so that the circuit simulation current output by the temporary simulation circuit matches the measured current of the device, and take the resistance value of the adjustable resistor corresponding to the matching as the sampling calibration resistor under the bias condition to obtain multiple sampling calibration resistors covering the complete working range of LDMOS. The network model training module is used to construct a sample dataset based on the sampling calibration resistor, wherein the product of the sampling calibration resistor and the measured current of the device is used as the drift region voltage, the drift region voltage and the gate-source voltage are used as input data, and the sampling calibration resistor is used as label data. The network model training module is also used to train the neural network model using the sample dataset so that the neural network model can predict the drift region equivalent resistance of the LDMOS device. The device model construction module is used to encapsulate the trained neural network model into a sub-circuit using an analog hardware description language, and connect the sub-circuit in series to the drain branch of the reference model to form an LDMOS hybrid device model. The device model building module is specifically used for: The neural network model is trained using the input data and the sampling calibration resistor until the error between the drift region equivalent resistance predicted by the neural network model and the sampling calibration resistor meets the preset accuracy requirements.

7. An electronic device, characterized in that, include: The device includes a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus, and the processor executes the machine-readable instructions to perform the steps of the LDMOS hybrid device model construction method as described in any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the steps of the LDMOS hybrid device model construction method as described in any one of claims 1 to 5.

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