A power strip-oriented layout optimization method, device, equipment and product

Abstract

The application discloses a power strip-oriented layout optimization method, device, equipment and product, which is used for laying multiple power strips on a chip. The layout optimization method comprises the following steps: acquiring an available wiring area of the chip; converting the available wiring area into multiple rectangular strips based on geometric characteristics of the available wiring area; constructing multiple candidate sets of a first power strip based on a preset layout constraint rule and the multiple rectangular strips; and laying multiple power strips based on candidate sets meeting a preset phase requirement in the multiple candidate sets. The method aims to provide a layout optimization method for an available wiring area which is non-rectangular, has steps or holes, and can ensure that the starting phase of the power strip and the area geometry are coordinated and optimal when the layout is performed.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and specifically to a layout optimization method, apparatus, device, and product for power strips. Background Technology

[0002] In integrated circuit physical design, chip power / ground networks are often constructed using metal ground stripes (PGs) that are repeatedly arranged according to rules within a designated wiring area. Design objectives typically include maximizing the effective coverage length of the PGs within the available area (e.g., the cumulative height of vertical stripes in the Y direction or the cumulative width of horizontal stripes in the X direction) under given process and design rules (such as line width, spacing, and alignment with standard cell tracks) to meet engineering requirements such as IR drop, electromigration, and power supply uniformity. Summary of the Invention

[0003] The present invention aims to propose a layout optimization method for non-rectangular, stepped, or hollow available wiring areas, which can ensure optimal coordination between the starting phase of the power strip and the area geometry when laying out the wiring.

[0004] According to a first aspect, one embodiment provides a layout optimization method for power strips, used to lay out multiple power strips on a chip, the layout optimization method comprising:

[0005] Obtain the available wiring area of ​​the chip; wherein, the available wiring area is a target area for laying out power strips, the outer boundary of which is non-rectangular and / or the interior contains one or more power strip wiring blocking areas, the power strip wiring blocking areas are used to prohibit the laying of power strips within them, and the remaining part of the available wiring area except for the power strip wiring blocking areas constitutes an effective area for power strip laying.

[0006] Based on the geometric features of the available wiring area, it is converted into multiple rectangular strips; wherein, when the geometric features include a power strip wiring blockage area in the available wiring area, each rectangular strip does not contain any point within the power strip wiring blockage area;

[0007] Based on the preset layout constraint rules and the multiple rectangular strips, multiple candidate sets of the first power strip are constructed; wherein, each candidate set includes at least the two boundary positions of the power strip in its arrangement direction, and the chip has a number of preset parallel and equidistant tracks, the tracks are used to define the layout position of the power strip, and the layout constraint rules include the setting of whether the power strip is attracted to the preset tracks.

[0008] Multiple power strips are arranged based on the candidate set that meets the preset phase requirements in the multiple candidate sets.

[0009] In one embodiment, constructing a multiple candidate set of the first power strip based on preset layout constraint rules and the multiple rectangular strips includes:

[0010] When the power strip is set to be attached to a preset track, multiple candidate sets of the first power strip are calculated according to the preset attachment mode; wherein, under different attachment modes, the power strip is attached to the track at different positions.

[0011] When the setting is not to attach the power strip to the preset track, multiple candidate sets of the first power strip are calculated based on the boundary of the rectangular strip.

[0012] In one embodiment, the layout of multiple power strips on the chip includes either a first mode or a second mode. In the first mode, the power strips are of the same type. In the second mode, multiple units of power strips are cyclically laid out, each unit containing multiple power strips of different types with different widths. When laying out multiple power strips in the second mode, the candidate set of the first power strip also includes the type of the first power strip. The phase requirement includes that the width of the last power strip is less than or equal to the remaining available width of the available wiring area. The remaining available width is equal to the internal width of the available wiring area minus the sum of the widths of all already laid power strips. The width of the last power strip is determined based on the type of the first power strip.

[0013] In one embodiment, when multiple power strips are arranged according to a first pattern, the step of calculating multiple candidate sets of the first power strip based on the boundary of the rectangular strip includes:

[0014] Modular operation is performed on the side length of the boundary of the rectangular strip and the preset step size, and multiple candidate sets of the first power strip are constructed based on the result of the modular operation;

[0015] When multiple power strips are laid out according to the second pattern, the step of calculating multiple candidate sets of the first power strip based on the boundary of the rectangular strip includes:

[0016] A modulo operation is performed on the side length of the boundary of the rectangular strip and the preset unit width, and multiple candidate sets of the first power strip are constructed based on the result of the modulo operation; wherein, the unit width is the sum of the width and spacing of the power strips in each unit.

[0017] In one embodiment, calculating a plurality of candidate sets for the first power strip based on a preset adsorption mode includes:

[0018] Based on the preset track offset and track spacing, the coordinate position of each track is determined;

[0019] Based on the coordinates of each track and the preset adsorption mode, multiple candidate sets of the first power strip are calculated.

[0020] In one embodiment, the adsorption modes include a leftward adsorption mode, a rightward adsorption mode, and a nearest-neighbor adsorption mode. The step of calculating multiple candidate sets of the first power strip based on the coordinate positions of each track and the preset adsorption modes includes:

[0021] When the adsorption mode is left adsorption mode, for any two adjacent tracks, the position of the smallest track is taken as the first minimum critical value of the adsorption region. The first maximum critical value of the adsorption region is calculated based on the position of the smallest track and the preset spacing. Multiple candidate sets of the first power strip are calculated based on the first minimum critical value and the first maximum critical value of the adsorption region.

[0022] When the adsorption mode is a rightward adsorption mode, for any two adjacent tracks, the position of the track with the largest value is taken as the second maximum critical value of the adsorption region. The second minimum critical value of the adsorption region is calculated based on the position of the track with the largest value and the preset spacing. Multiple candidate sets of the first power strip are calculated based on the second minimum critical value and the second maximum critical value. When any power strip is located in the adsorption region, the power strip is adsorbed to the track.

[0023] When the adsorption mode is the nearest adsorption mode, for any two adjacent tracks, the midpoint of the line connecting the two tracks is used as the boundary, and the coordinate intervals on both sides of the midpoint are respectively divided into the adsorption regions of the corresponding tracks. For the first or last track, the width of the extrapolation is determined based on the distance between it and the adjacent track, and it is extrapolated outward in the direction of the track to form the corresponding outer adsorption boundary. When any power strip is located in the adsorption region of the track, the power strip is adsorbed to the track, and multiple candidate sets of the first power strip are calculated according to the position of the track.

[0024] In one embodiment, the geometric feature of the available wiring area is that it contains one or more power strip wiring blocking areas. The step of converting the available wiring area into multiple rectangular strips based on its geometric features includes:

[0025] Obtain the boundary of the available wiring area and the boundary of the power strip wiring blockage area;

[0026] Extract the first boundary coordinates of the boundary of the available wiring area in the first direction, extract the second boundary coordinates of the boundary of the power strip wiring blockage area in the first direction, and determine the area where the scan strip is located based on the adjacent first boundary coordinates and second boundary coordinates;

[0027] The control scan line moves along a first direction starting from the boundary of the available wiring area, and when the scan line moves to the area where the scan strip is located, a plurality of projection intervals of the available wiring area in a second direction are determined according to the area where the scan strip is located;

[0028] Detect whether there are gaps between each projection interval, the gaps corresponding to the power strip wiring blockage area, take the projection intervals in the area where each scan band is located except for the gaps as sub-regions, and generate multiple rectangular strips based on multiple sub-regions.

[0029] According to a second aspect, one embodiment provides a layout optimization device for a power strip, comprising:

[0030] The region determination module is used to obtain the available wiring region of the chip; wherein, the available wiring region is a target region for laying out power strips, the outer boundary of which is non-rectangular and / or the interior contains one or more power strip wiring blocking regions, the power strip wiring blocking regions are used to prohibit the laying of power strips within them, and the remaining part of the available wiring region except for the power strip wiring blocking regions constitutes an effective region for power strip laying.

[0031] A strip conversion module is used to convert the available wiring area into multiple rectangular strips based on the geometric features of the available wiring area; wherein, when the geometric features include a power strip wiring blockage area in the available wiring area, each rectangular strip does not contain any point within the power strip wiring blockage area;

[0032] A candidate set construction module is used to construct multiple candidate sets of the first power strip based on preset layout constraint rules and the multiple rectangular strips; wherein, each candidate set includes at least the two boundary positions of the power strip in its arrangement direction, the chip has a number of preset parallel and equidistant tracks, the tracks are used to define the layout position of the power strip, and the layout constraint rules include a setting for whether the power strip is attracted to the preset tracks.

[0033] The power strip layout module is used to lay out multiple power strips based on a candidate set that meets the preset phase requirements from the multiple candidate sets.

[0034] According to a third aspect, one embodiment provides a layout optimization device for a power strip, comprising:

[0035] Memory, used to store programs;

[0036] A processor for implementing the layout optimization method by executing a program stored in the memory.

[0037] According to a fourth aspect, one embodiment provides a computer program product including a computer program and / or instructions that, when executed by a processor, implement the layout optimization method.

[0038] According to the power strip layout optimization method, apparatus, device, and computer program product described in the above embodiments, the available wiring area of ​​the chip is converted into multiple rectangular strips based on its geometric features. This facilitates the subsequent construction of multiple candidate sets for the first power strip based on preset layout constraint rules and the multiple rectangular strips, avoiding misjudgments caused by simple geometric overlap. During layout, the optimal coordination between the starting phase of the power strip and the regional geometry is ensured. Simultaneously, the layout constraint rules include settings for whether the power strip adheres to a preset track. Therefore, the construction of the candidate set considers both purely geometric cases without track adhesion and cases with track adhesion. Multiple power strips are laid out using the reference position of the first power strip, improving the efficiency of power strip layout. Attached Figure Description

[0039] Figure 1 This is a flowchart of the layout optimization method for power strips in an embodiment of this application;

[0040] Figure 2 This is a schematic diagram of the available wiring area in one embodiment;

[0041] Figure 3 This is a schematic diagram of a rectangular strip in one embodiment;

[0042] Figure 4 This is a schematic diagram of a rectangular strip in another embodiment;

[0043] Figure 5 This is a schematic diagram illustrating a scenario where the power strip does not adhere to the preset track in one embodiment;

[0044] Figure 6 This is a schematic diagram illustrating the scenario where the power strip is attracted to a preset track in one embodiment;

[0045] Figure 7 This is a flowchart illustrating, in one embodiment, the construction of multiple candidate sets of the first power strip based on preset layout constraint rules and multiple rectangular strips;

[0046] Figure 8 (a) is a layout diagram of the power strip in the second mode of one embodiment. Figure 8 (b) is a layout diagram of the power strip in the second mode of another embodiment;

[0047] Figure 9 This is a flowchart illustrating how multiple candidate sets of the first power strip are calculated based on a preset adsorption mode in one embodiment.

[0048] Figure 10 This is a flowchart of one embodiment that converts the available wiring area into multiple rectangular strips based on the geometric features of the area.

[0049] Figure 11 This is a schematic diagram illustrating the layout of the power strip in a second mode in one embodiment;

[0050] Figure 12 This is a schematic diagram of the layout optimization device for power strips in an embodiment of this application. Detailed Implementation

[0051] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of the invention. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to the present invention are not shown or described in the specification. This is to avoid obscuring the core parts of the invention with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0052] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0053] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this invention, unless otherwise specified, include both direct and indirect connections (linkages).

[0054] The related technologies have the following disadvantages when laying out power strips: (1) When using rule-driven or manual experience to lay out the strips, the strips are laid out from the chip boundary or fixed origin according to a fixed pitch, which relies on manual fine-tuning. For non-rectangular, stepped or hollow available areas, it is difficult to ensure that the starting phase and the area geometry are optimally coordinated, and it is difficult to quantify the optimal "total effective strip length". (2) Dense sampling or numerical search in continuous intervals, the starting coordinates of the first PG are in [x min xmax Scan with a fixed step size, or continuously optimize the objective function. The defects of the above methods include: the step size and accuracy / time consumption are contradictory. If the objective function is derived from piecewise geometry, there may be a large number of local plateaus. A coarse step size is easy to miss the optimal, while a fine step size will significantly increase the amount of computation. (3) Treat the available area as a whole polygon and directly perform point sampling. For each PG strip, directly intersect the original polygon with vertical lines in the X direction to obtain the height. It is feasible on complex polygons, but there are many repeated calculations and the combination with periodic repeated placement (fixed pitch, multiple roots in a group of unit patterns) is not structured enough. In engineering, it often needs to be combined with rectangle decomposition or strip algorithm. (4) Estimate the strip height by simple rectangle overlap. If the area is divided into axis-aligned rectangle pieces, the PG height in the strip is represented only by the interval intersection of overlapping rectangles in the Y direction. When there are holes or the strip is not connected, the connection height will be overestimated or a physically unrealizable continuous strip assumption will be produced. (5) General optimizers (heuristic, genetic algorithm, simulated annealing, etc.) can handle complex objectives and constraints, but when they lack the [periodic repetition + single-degree-of-freedom phase] structure, the search space dimension is too large or the convergence is uncertain, which is not conducive to fast deterministic solutions that are tightly coupled with layout design rules (track or mask). (6) Alignment with the manufacturing / layout mesh: In practice, PGs often need to be snapped to the lithography or wiring track mesh. If discretization is performed only after optimization in the continuous space, it may deviate from the optimal phase. It is necessary to consider the differences in mesh and multi-net width together during the candidate generation or evaluation stage.

[0055] To address the aforementioned issues, this application provides a layout optimization method for power strips, used to lay out multiple power strips on a chip. In this method, the available wiring area of ​​the chip is obtained; wherein, the available wiring area is the target area for laying out power strips, its outer boundary is non-rectangular and / or it contains one or more power strip wiring blocking areas, which are used to prevent the placement of power strips within them. The remaining portion of the available wiring area, excluding the power strip wiring blocking areas, constitutes an effective area for power strip placement; based on the geometric features of the available wiring area, it is converted into multiple rectangular strips; wherein, when the geometric features include... When the wiring area has a power strip wiring blockage area, each rectangular strip does not contain any point within the power strip wiring blockage area; multiple candidate sets of the first power strip are constructed based on preset layout constraint rules and multiple rectangular strips; wherein, each candidate set includes at least the two boundary positions of the power strip on both sides of its arrangement direction, and the chip has several preset parallel and equidistant tracks, which are used to define the layout position of the power strip, and the layout constraint rules include the setting of whether the power strip is attracted to the preset track; the candidate set that meets the preset phase requirement is selected from the multiple candidate sets as the reference position of the first power strip, and multiple power strips are laid out based on the reference position.

[0056] The layout optimization method for power strips provided in this application is described below with reference to the accompanying drawings. This layout optimization method for power strips is used to lay out multiple power strips on a chip.

[0057] Figure 1 A flowchart of a layout optimization method for power strips provided in an embodiment of this application is shown, which will be described in detail below.

[0058] Step S10: Obtain the available wiring area of ​​the chip.

[0059] In some embodiments, the available wiring area is a target area for laying out power strips, the outer boundary of which is non-rectangular and / or contains one or more power strip wiring blocking areas, which are used to prevent the laying of power strips within them, and the remaining portion of the available wiring area excluding the power strip wiring blocking areas constitutes an effective area for power strip laying.

[0060] Please refer to Figure 2 ,For example, Figure 2 Area 10 shown is the available wiring area, and area 20 in the available wiring area is the power strip wiring blockage area. Figure 2 The shape of the power strip wiring blockage area shown is rectangular, but the shape of the power strip wiring blockage area can also be a hole or a step.

[0061] Step S20: Convert the available wiring area into multiple rectangular strips based on its geometric features.

[0062] In some embodiments, the geometry of the available wiring area is that its outer boundary is non-rectangular and / or its interior contains one or more power strip wiring blocking areas. When the geometry includes a power strip wiring blocking area in the available wiring area, each rectangular strip does not contain any point within the power strip wiring blocking area.

[0063] Please refer to Figure 3 and Figure 4 ,For example, Figure 3 To represent multiple rectangular stripes based on the horizontal power bar transition, React1, React2, React3, React4, and React5 are different rectangular stripes, and similarly... Figure 4 These are multiple rectangular strips converted according to the vertical power strip.

[0064] In some embodiments, the available wiring area can be directly clipped, which is geometrically more straightforward, but the cost of repeated polygon operations is high. However, the number of calls can still be controlled by combining phase finiteness and only calling the function on subsequent candidate sets.

[0065] Step S30: Construct multiple candidate sets for the first power strip based on preset layout constraint rules and multiple rectangular strips.

[0066] In some embodiments, each candidate set includes at least the positions of the two side boundaries of the power strip in its arrangement direction. The chip has a number of parallel and equidistant tracks that define the layout position of the power strip. The layout constraint rules include settings for whether the power strip is attracted to the preset tracks.

[0067] Please refer to Figure 5 and Figure 6 ,For example, Figure 5 This is for the case where the power strip does not adhere to the preset track. Figure 6 This refers to the situation where the power strip is magnetically attached to the preset track.

[0068] In some embodiments, related technologies typically perform post-processing after continuous spatial optimization to check whether the power strips snap to the track. However, this application considers the setting of whether the power strips snap to a preset track in the layout constraint rules when constructing the candidate set. The cumulative value of the strip's height / width is used as the target metric. The evaluation function remains unchanged: when there is a snap (setting the power strip to snap to the preset track), the actual landing point after the snap is used for calculation; when there is no snap (setting the power strip not to snap to the preset track), the original geometric position is used for calculation. This ensures that the same set of evaluation functions simultaneously reflects geometric connectivity and manufacturable mesh positions.

[0069] In some embodiments, the multiple candidate sets of the first power strip can be divided not only based on the boundary phase partitioning of the rectangular strip, but also uniformly, for example, into N parts. The number of candidate sets is controllable, but a trade-off needs to be made between N and optimality. Partitioning based on the boundary phase partitioning of the rectangular strip is more targeted under the rectangular partitioning model.

[0070] Step S40: Layout multiple power strips based on the candidate set that meets the preset phase requirements in the multiple candidate sets.

[0071] In some embodiments, the phase requirement may be to maximize the cumulative height of the power strips in the X or Y direction when multiple power strips are laid out according to a candidate set. The reference position of the first power strip is based on the positions of the two side boundaries of the power strips in the candidate set in their arrangement direction. After the reference position of the first power strip is determined, the other power strips will be arranged sequentially after the first power strip according to a set step size.

[0072] In some embodiments, for power strips with multiple units arranged in a circular layout, where each unit contains multiple power strips of different types and different widths, taking horizontally arranged power strips as an example, in addition to specifying the maximum cumulative length, it is also possible to specify that the cumulative length of a certain type of power strip is the maximum. When the cumulative lengths are the same, secondary criteria such as minimum boundary gap area can also be used for filtering.

[0073] According to the power strip layout optimization method of the above embodiments, the available wiring area of ​​the chip is converted into multiple rectangular strips based on its geometric features. This facilitates the subsequent construction of multiple candidate sets for the first power strip based on preset layout constraint rules and multiple rectangular strips, avoiding misjudgments caused by simple geometric overlap. During layout, the method ensures optimal coordination between the starting phase of the power strip and the regional geometry. Simultaneously, the layout constraint rules include settings for whether the power strip adheres to a preset track. Therefore, the construction of the candidate set considers both purely geometric cases without track adhesion and cases with track adhesion. By placing multiple power strips at the reference position of the first power strip, the efficiency of power strip layout is improved.

[0074] Please refer to Figure 7 In some embodiments, step S30: constructing multiple candidate sets of the first power strip based on preset layout constraint rules and multiple rectangular strips, including steps S31 to S32, which are described in detail below.

[0075] When the setting is to attach the power strip to the preset track, step S31 is executed: calculate multiple candidate sets of the first power strip according to the preset attachment mode.

[0076] In some embodiments, when setting the power strip to be attached to a preset track, considering that the power strip may be attached to different tracks in different attachment modes, it is necessary to combine the attachment modes when calculating multiple candidate sets of the first power strip.

[0077] For example, adsorption modes include left-facing adsorption mode, right-facing adsorption mode, and proximity adsorption mode. In left-facing adsorption mode, a track slightly to the left or lower is chosen to adsorb the power strip; in right-facing mode, a track slightly to the right or upper is chosen; and in proximity adsorption mode, the specific track for adsorption is determined based on adjacent tracks. The candidate set can include `start_x` or `start_y`, which align the layout period with the region geometry, representing the initial coordinates in the X and Y directions, respectively. In cell mode, the candidate set also includes the type `start_slot_index` of the first power strip. However, before evaluation, each slot needs to have its center or boundary mapped to the track network of its respective net. That is, the decision variable is phase + slot, and alignment with the network is completed within the objective function calculation, not after rounding.

[0078] In some implementations, multiple candidate sets for the first power strip can be efficiently and repeatedly selected by direct enumeration, or they can be calculated by search algorithms such as genetic algorithms or simulated annealing. Such search algorithms are suitable for cases where the objective function is extremely irregular or has many constraints. However, for the finite phase structure in this application, the enumeration method is still better.

[0079] When the setting is not to attach the power strip to the preset track, step S32 is executed: calculate multiple candidate sets of the first power strip based on the boundary of the rectangular strip.

[0080] In some embodiments, when the power strip is not snapped to a preset track, it indicates a purely geometric situation where the power strip layout is not limited by track snapping. Therefore, multiple candidate sets of the first power strip are calculated based on the boundary of the rectangular strip. The candidate set also includes start_x or start_y, which aligns the layout period with the region geometry, representing the initial coordinates in the X and Y directions, respectively. In cell mode, the candidate set also includes start_slot_index, which represents the type of the first power strip.

[0081] In some embodiments, with a fixed track pitch or cell width, the layout of the entire row of power strips is still determined by the starting phase of the first power strip (in the second mode, it also includes the type of the first power strip, i.e., the slot index), reducing the continuous one-dimensional search to a comparison on a finite number of discrete candidates. It can be seen that by constructing a finite candidate set instead of the dense scanning such as uniform sampling or full-range traversal in the prior art, and by setting whether the power strips adhere to a preset track to determine the source of critical information during the candidate set construction process, the efficiency of subsequent layout is improved.

[0082] In some embodiments, the optimization of start_x in the continuous domain can be projected onto a valid grid or track. However, this approach may fall into suboptimal conditions, requiring multiple initial values ​​or multiple starting points if the objective function is non-convex.

[0083] In some embodiments, laying out multiple power strips on a chip includes laying out multiple power strips in a first mode or in a second mode. In the first mode, the multiple power strips laid out are of the same type. In the second mode, power strips in multiple units are laid out cyclically, with each unit containing multiple power strips of different types and different widths. When laying out multiple power strips in the second mode, the candidate set of the first power strip also includes the type of the first power strip. The phase requirement includes that the width of the last power strip is less than or equal to the remaining available width of the available wiring area. The remaining available width is equal to the internal width of the available wiring area minus the sum of the widths of all the power strips already laid out. The width of the last power strip is determined according to the type of the first power strip.

[0084] Please refer to Figure 8 In some embodiments, for example, Figure 8 This is a layout diagram of the power strips in the second mode (also known as the cell mode). In this mode, multiple cells of power strips are arranged in a cyclical pattern. Each cell contains red, green, and blue power strips. Different types of power strips are represented by different colors, and their widths vary. Please refer to [reference needed]. Figure 8 In example (a), a red power strip is used as the first power strip in the layout, and the last power strip in the available wiring area is also a red power strip. In this case, all the power strips are placed within the available wiring area. Please refer to [reference needed]. Figure 8 In (b) of the diagram, a green power strip is used as the first power strip in the layout. The last power strip in the available wiring area is also green, but only half of the last power strip is within the available wiring area. In this case, the last power strip is discarded, resulting in a smaller total number of power strips placed. In summary, in the second mode, the available wiring area may not be able to completely accommodate all the cells in the cyclic layout. The type of the first power strip also affects the final layout result. Therefore, when laying out multiple power strips according to the second mode, the candidate set of the first power strip should also include the type of the first power strip, so as to determine whether the phase requirement is met based on the type of the first power strip.

[0085] For example, taking the vertical direction as an example, the candidate set of the first power strip includes (start_x, start_slot_index), where start_x is the coordinate of the boundary of the first power strip, and start_slot_index is the type of the first power strip.

[0086] In some embodiments, when multiple power strips are arranged according to a first pattern, multiple candidate sets of the first power strip are calculated based on the boundaries of the rectangular strips, including:

[0087] Modular operation is performed on the side length of the rectangular strip boundary and the preset step size, and multiple candidate sets of the first power strip are constructed based on the result of the modular operation.

[0088] Please return to the reference. Figure 3 For example, for the rectangular strip React1, a modulo operation is performed based on the side length and step size of the left boundary of the rectangular strip, and then another modulo operation is performed based on the side length and step size of the right boundary of the rectangular strip. The remainder of the two modulo operations is taken as the positions of the two side boundaries of the power strip in the candidate set in its arrangement direction. The above calculation is performed sequentially on multiple rectangular strips to obtain multiple candidate sets of the first power strip. Alternatively, multiple candidate sets of the first power strip can also be calculated based on the upper and lower boundaries of the rectangular strip. The calculation steps are the same as those described above, and will not be repeated here.

[0089] In some embodiments, when multiple power strips are arranged according to the second mode, multiple candidate sets of the first power strip are calculated based on the boundaries of the rectangular strips, including:

[0090] Modular operation is performed on the boundary length of the rectangular strip and the preset cell width, and multiple candidate sets of the first power strip are constructed based on the result of the modular operation.

[0091] In some embodiments, when multiple power strips are laid out according to the second mode, the method of calculating multiple candidate sets of the first power strip based on the boundary of the rectangular strip is similar to the method of calculating multiple candidate sets of the first power strip based on the boundary of the rectangular strip when multiple power strips are laid out according to the first mode, and will not be repeated here. However, it should be noted that in this embodiment, the side length of the boundary of the rectangular strip and the unit length are moduloed, where the unit width is the sum of the widths of the power strips in each unit.

[0092] Please refer to Figure 9 In some embodiments, step S31: calculate multiple candidate sets of the first power strip according to the preset adsorption mode, including steps S311 to S312, which are described in detail below.

[0093] Step S311: Determine the coordinate position of each track based on the preset track offset and track spacing.

[0094] In some embodiments, the preset track offset is the starting distance of the first track relative to the origin of the coordinate system (generally the boundary of the chip), and the track pitch is the distance between two adjacent tracks. The coordinate position of each track can be calculated based on the preset track offset and track pitch.

[0095] For example, the orbital offset is 0.2. The track spacing is 1. The coordinates of each track are expressed as follows: Track 0: 0.2 + 0 × 1.0 = 0.2 The first track: 0.2 + 1 × 1.0 = 1.2 The second track: 0.2 + 2 × 1.0 = 2.2 The third track: 0.2 + 3 × 1.0 = 3.2 And so on.

[0096] Step S312: Calculate multiple candidate sets of the first power strip based on the coordinate positions of each track and the preset adsorption mode.

[0097] In some embodiments, the power strip can be adsorbed onto different tracks under different adsorption modes. Therefore, multiple candidate sets of the first power strip are calculated by combining the coordinate positions of each track and the adsorption mode. The adsorption modes include left-facing adsorption mode, right-facing adsorption mode, and proximity adsorption mode, in [x... min x max Within the [unit_width], the maximum and minimum critical values ​​are determined based on different adsorption modes. The critical coordinates and the geometric relationship of the rectangular strips are calculated together as a phase consistent with the unit_width, generating a finite number of candidate sets. This ensures compatibility with the layout mesh during the candidate stage, avoiding the contradiction of achieving geometric optimization first, followed by adsorption deviation. min x is the x-coordinate of the left boundary of the available wiring area. max The x-coordinate of the right boundary of the available wiring area.

[0098] In some embodiments, a multiple candidate set of the first power strip is calculated based on the coordinate positions of each track and a preset adsorption mode, including:

[0099] When the adsorption mode is left adsorption mode, for any two adjacent tracks, the position of the smallest track is taken as the first minimum critical value of the adsorption region. The first maximum critical value of the adsorption region is calculated based on the position of the smallest track and the preset spacing. Multiple candidate sets of the first power strip are calculated based on the first minimum critical value and the first maximum critical value of the adsorption region.

[0100] When the adsorption mode is right-side adsorption mode, for any two adjacent tracks, the position of the track with the largest value is taken as the second maximum critical value of the adsorption region. The second minimum critical value of the adsorption region is calculated based on the position of the track with the largest value and the preset spacing. Multiple candidate sets of the first power strip are calculated based on the second minimum critical value and the second maximum critical value. When any power strip is located in the adsorption region, the power strip is adsorbed to the track.

[0101] When the adsorption mode is the nearest adsorption mode, for any two adjacent tracks, the midpoint of the line connecting the two tracks is used as the boundary, and the coordinate intervals on both sides of the midpoint are respectively divided into the adsorption regions of the corresponding tracks. For the first or last track, the extrapolation width is determined based on its distance from the adjacent track, and it is extrapolated outward in the direction of the track to form the corresponding outer adsorption boundary. When any power strip is located in the adsorption region of the track, the power strip is adsorbed to the track, and multiple candidate sets of the first power strip are calculated based on the position of the track.

[0102] In some embodiments, when the adsorption mode is left-biased, adsorption typically occurs on tracks slightly to the left or lower. The first minimum critical value is equal to the position T of the track. i T i When the center adheres to the nearest track less than or equal to the geometric center, the left-edge related critical value, the first maximum critical value = T i +pitch, closer to the next track side. When the adsorption mode is right-facing, the second minimum threshold = T. i -pitch, second maximum threshold = T i When the adsorption mode is the nearest adsorption mode, the midpoint of the adjacent track is used as the nearest adsorption boundary, and the outer edges of the first and last tracks are extrapolated by half the adjacent spacing. The phase is obtained by taking the remainder of the critical coordinates (the union of the maximum critical value critical_max_x and the minimum critical value critical_min_x) with unit_width, and finally restored to start_x.

[0103] For example, when the adsorption mode is the nearest adsorption mode, for the first or last orbital, the distance between the orbital and its adjacent orbital is assumed to be 5. We can take 2.5 as the width and push this width outward to the outside of the orbital to form the adsorption boundary.

[0104] Please refer to Figure 10 In some embodiments, the geometric features of the available wiring area are that the available wiring area contains one or more power strip wiring blocking areas. Step S20: Based on the geometric features of the available wiring area, it is converted into multiple rectangular strips, including steps S21 to S24, which are described in detail below.

[0105] Step S21: Obtain the boundaries of the available wiring area and the boundaries of the power strip wiring blockage area.

[0106] In some embodiments, the upper and lower boundaries of the available wiring area and the upper and lower boundaries of the power strip wiring blocking area are obtained, or the left and right boundaries of the available wiring area and the left and right boundaries of the power strip wiring blocking area are obtained.

[0107] Step S22: Extract the first boundary coordinates of the boundary of the available wiring area in the first direction, extract the second boundary coordinates of the boundary of the power strip wiring blockage area in the first direction, and determine the area where the scan strip is located based on the adjacent first boundary coordinates and second boundary coordinates.

[0108] For example, if the first direction is the X direction and the second direction is the Y direction, extract the first boundary coordinates of the left and right boundaries of the available wiring area in the X direction, and extract the left and right boundaries of the power strip wiring blockage area to the left of the second boundary in the X direction. The area enclosed by the boundary where the adjacent first boundary coordinates are located and the boundary where the adjacent second boundary coordinates are located is taken as the area where the scan strip is located.

[0109] Step S23: Control the scan line to move along the first direction from the boundary of the available wiring area, and determine multiple projection intervals of the available wiring area in the second direction according to the area where the scan strip is located when the scan line moves to the area where the scan strip is located.

[0110] In some embodiments, the control scan line moves along the X direction starting from the left boundary of the available wiring area, and when the scan line moves to the area where the scan band is located, its projection interval in the Y direction is determined according to the area where the scan band is located. Each area where the scan band is located can correspond to a projection interval, and each projection interval does not overlap with each other.

[0111] Step S24: Detect whether there are gaps between each projection interval. The gaps correspond to the power strip wiring blockage area. Take the projection intervals in the area where each scan strip is located, excluding the gaps, as sub-regions, and generate multiple rectangular strips based on multiple sub-regions.

[0112] In some embodiments, since the gaps correspond to the power strip wiring blockage area, the continuous projection intervals (excluding the gaps) within the area where each scan strip is located are regarded as sub-regions. Sub-regions that are adjacent along the first direction and have overlapping or continuous projection intervals in the second direction are merged to obtain multiple rectangular strips.

[0113] In some embodiments, the available wiring area is converted into multiple rectangular strips, so that subsequent layout can be completed on discrete rectangular strips, improving layout efficiency and accuracy.

[0114] In some embodiments, in the second mode, to avoid omissions when the head boundary of the available wiring area truncates the repeating unit, an additional repeating unit can be laid before the current starting position when generating the candidate power strip set, and then intersected with the available wiring area. This ensures that the power strips falling within the head boundary of the available wiring area are fully preserved, without the need to manually specify additional trimming parameters. For example, please refer to... Figure 11 In the second mode, there exists a unit_spec=[2, 3, 1, 2, 2], unit_width=10. Assume the available wiring area in the X direction is [100, 128]. If start_x=105 (refer to...) Figure 11 (as shown by the blue dotted line in the image), start_slot_index=1. Starting from 105, power strips are laid out to the right, resulting in a series of laid-out strips from 105. However, there is still a layout area to the left of 105. Therefore, an extra unit is laid forward to maximize the use of the space to be laid out, avoid omissions in the unit layout, and eliminate the need to manually specify additional trimming parameters.

[0115] In some embodiments, when laying out multiple power strips, the relevant technical methods typically only retain the layout positions as an internal geometry list, JSON, or tool-specific format, and then manually enter them one by one in the layout editor. This is disconnected from standard physical design exchange formats, such as Design Exchange Format (DEF), which is not conducive to placement and routing, Design Rule Check (DRC) / layout and circuitry. Figure 1 The consistency check (Layout Versus Schematic, LVS) or subsequent power delivery network (PDN) toolchain is automatically integrated. After obtaining the optimal (or specified candidate) pg_list (each PG segment is an axis-aligned rectangle with attributes such as slots and masks), this application can convert it into a text netlist conforming to DEF 5.8 (such as the Cadence LEF / DEF reference convention). This directly maps the discrete PG rectangles output by the algorithm to a DEF file readable by downstream tools, realizing a closed loop from phase optimization to layout data exchange.

[0116] In some embodiments, this application addresses the optimization of power / ground metal strip placement within available wiring areas in integrated circuit physical design. Given periodic repetition rules (such as fixed pitch, grouped multi-strand widths and spacing, and optional layout track grids), it automatically determines the starting phase and slot positions within the cells of the entire row of power strips. This ensures that the effective coverage length of the power strips within the area (target metrics such as cumulative vertical height or cumulative horizontal width) is optimized within acceptable engineering complexity. Simultaneously, available wiring areas containing holes, steps, or non-rectangular sections are uniformly represented as rectangular partitions. During the evaluation phase, segments are accumulated using horizontal (or vertical) through-sections within the strips, avoiding misjudgments caused by simple geometric overlaps. Furthermore, it supports two types of candidate and evaluation paths—those with pure geometric and those with consistent track adsorption—within the same framework.

[0117] Please refer to Figure 12 In some embodiments, a layout optimization device for a power strip is provided, comprising:

[0118] The region determination module 100 is used to obtain the available wiring area of ​​the chip; wherein, the available wiring area is the target area for laying out power strips, the outer boundary of which is non-rectangular and / or the interior contains one or more power strip wiring blocking areas, the power strip wiring blocking areas are used to prohibit the laying of power strips within them, and the remaining part of the available wiring area excluding the power strip wiring blocking areas constitutes the effective area for power strip laying.

[0119] The strip conversion module 200 is used to convert the available wiring area into multiple rectangular strips based on the geometric features of the available wiring area; wherein, when the geometric features include a power strip wiring blockage area in the available wiring area, each rectangular strip does not contain any point within the power strip wiring blockage area.

[0120] The candidate set construction module 300 is used to construct multiple candidate sets of the first power strip based on preset layout constraint rules and multiple rectangular strips; wherein, each candidate set includes at least the two boundary positions of the power strip in its arrangement direction, and the chip has a number of preset parallel and equidistant tracks, which are used to limit the layout position of the power strip, and the layout constraint rules include the setting of whether the power strip is attracted to the preset tracks.

[0121] The power strip layout module 400 is used to select a candidate set that meets the preset phase requirements from multiple candidate sets as the reference position of the first power strip, and to lay out multiple power strips based on the reference position.

[0122] In some embodiments, the candidate set construction module 300 is used to construct multiple candidate sets for the first power strip based on preset layout constraint rules and multiple rectangular strips, as described in detail below.

[0123] When the power strip is set to be attached to a preset track, the candidate set construction module 300 calculates multiple candidate sets of the first power strip according to the preset attachment mode; wherein, the power strip is attached to the track at different positions under different attachment modes; when the power strip is set not to be attached to the preset track, the candidate set construction module 300 calculates multiple candidate sets of the first power strip according to the boundary of the rectangular strip.

[0124] In some embodiments, laying out multiple power strips on a chip includes laying out multiple power strips in a first mode or in a second mode. In the first mode, the multiple power strips laid out are of the same type. In the second mode, power strips in multiple units are laid out cyclically, with each unit containing multiple power strips of different types and different widths. When laying out multiple power strips in the second mode, the candidate set of the first power strip also includes the type of the first power strip. The phase requirement includes that the width of the last power strip is less than or equal to the remaining available width of the available wiring area. The remaining available width is equal to the internal width of the available wiring area minus the sum of the widths of all the power strips already laid out. The width of the last power strip is determined according to the type of the first power strip.

[0125] In some embodiments, when multiple power strips are laid out according to the first pattern, the candidate set construction module 300 is also used to calculate multiple candidate sets of the first power strip based on the boundary of the rectangular strip, as described in detail below.

[0126] The candidate set construction module 300 is also used to perform a modulo operation on the side length of the rectangular strip boundary and the preset step size, and construct multiple candidate sets of the first power strip based on the result of the modulo operation.

[0127] In some embodiments, when multiple power strips are laid out according to the second mode, the candidate set construction module 300 is used to calculate multiple candidate sets for the first power strip based on the boundary of the rectangular strip, as described in detail below.

[0128] The candidate set construction module 300 is also used to perform a modulo operation on the side length of the boundary of the rectangular strip and the preset cell width, and construct multiple candidate sets of the first power strip based on the result of the modulo operation; wherein, the cell width is the sum of the widths of the power strips in each cell.

[0129] In some embodiments, the candidate set construction module 300 is further configured to calculate multiple candidate sets of the first power strip according to a preset adsorption mode, including: determining the coordinate position of each track based on a preset track offset and track spacing; and calculating multiple candidate sets of the first power strip according to the coordinate position of each track and the preset adsorption mode.

[0130] In some embodiments, the adsorption modes include a left-facing adsorption mode, a right-facing adsorption mode, and a proximity adsorption mode. The candidate set construction module 300 is also used to calculate multiple candidate sets of the first power strip based on the coordinate positions of each track and the preset adsorption modes, as described in detail below.

[0131] When the adsorption mode is left-facing, for any two adjacent tracks, the position of the track with the smallest value is taken as the first minimum critical value of the adsorption region. The first maximum critical value of the adsorption region is calculated based on the position of the smallest track and a preset spacing. Multiple candidate sets of the first power strip are then calculated based on the first minimum and first maximum critical values. When the adsorption mode is right-facing, for any two adjacent tracks, the position of the track with the largest value is taken as the second maximum critical value of the adsorption region. The second minimum critical value of the adsorption region is calculated based on the position of the largest track and a preset spacing. Multiple candidate sets of the first power strip are then calculated based on the second minimum and second maximum critical values. Multiple candidate sets of the first power strip are generated; when any power strip is located within the adsorption region, the power strip is adsorbed onto the track; when the adsorption mode is the nearest adsorption mode, for any two adjacent tracks, the midpoint of the line connecting the two tracks is used as the boundary, and the coordinate intervals on both sides of the midpoint are respectively divided into the adsorption regions of the corresponding tracks. For the first or last track, the extrapolation width is determined based on its distance from the adjacent track, and it is extrapolated outward in the direction of the track to form the corresponding outer adsorption boundary. When any power strip is located within the adsorption region of the track, the power strip is adsorbed onto the track, and multiple candidate sets of the first power strip are calculated based on the position of the track.

[0132] In some embodiments, the geometric features of the available wiring area are that the available wiring area contains one or more power strip wiring blocking areas. The strip conversion module 200 is used to convert the available wiring area into multiple rectangular strips based on the geometric features of the available wiring area, as described in detail below. The strip conversion module 200 is used to obtain the boundary of the available wiring area and the boundary of the power strip wiring blocking area; extract the first boundary coordinates of the boundary of the available wiring area in a first direction, extract the second boundary coordinates of the boundary of the power strip wiring blocking area in a first direction, and determine the area where the scan strip is located based on the adjacent first boundary coordinates and second boundary coordinates; control the scan line to move along the first direction from the boundary of the available wiring area, and when the scan line moves to the area where the scan strip is located, determine multiple projection intervals of the available wiring area in a second direction based on the area where the scan strip is located; detect whether there are gaps between each projection interval, the gaps correspond to power strip wiring blocking areas, take the projection intervals in the area where each scan strip is located excluding the gaps as sub-regions, and generate multiple rectangular strips based on multiple sub-regions.

[0133] In some embodiments, a layout optimization device for power strips is provided, comprising:

[0134] Memory, used to store programs;

[0135] A processor is used to implement layout optimization methods by executing programs stored in memory.

[0136] In some embodiments, a computer program product is provided, including a computer program and / or instructions, which implement a layout optimization method when executed by a processor.

[0137] In the above embodiments, implementation can be achieved, in whole or in part, by software, hardware, firmware, or any combination thereof. Furthermore, as those skilled in the art will understand, the principles herein can be reflected in a computer program product on a computer-readable storage medium pre-loaded with computer-readable program code. Any tangible, non-transitory computer-readable storage medium may be used, including magnetic storage devices (hard disks, floppy disks, etc.), optical storage devices (CDs, DVDs, Blu-ray discs, etc.), flash memory, and / or the like. These computer program instructions can be loaded onto a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to form a machine, such that instructions executing on the computer or other programmable data processing apparatus can generate means for performing a specified function. These computer program instructions can also be stored in a computer-readable storage medium that can instruct the computer or other programmable data processing apparatus to operate in a particular manner, such that instructions stored in the computer-readable storage medium can form an article of manufacture, including means for implementing the specified function. The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to perform a series of operational steps on the computer or other programmable apparatus to produce a computer-implemented process, such that instructions executing on the computer or other programmable apparatus can provide steps for implementing the specified function.

[0138] This document describes various exemplary embodiments with reference to them. However, those skilled in the art will recognize that changes and modifications can be made to the exemplary embodiments without departing from the scope of this document. For example, various operational steps and components for performing operational steps can be implemented in different ways depending on the specific application or considering any number of cost functions associated with the operation of the system (e.g., one or more steps can be deleted, modified, or combined with other steps).

[0139] While the principles herein have been illustrated in various embodiments, numerous modifications to the structures, arrangements, proportions, elements, materials, and components, particularly suited to specific environments and operational requirements, may be used without departing from the principles and scope of this disclosure. These modifications and other alterations or alterations will be included within the scope of this document. Those skilled in the art will recognize that many changes can be made to the details of the above embodiments without departing from the fundamental principles of the invention.

Claims

1. A layout optimization method for power strips, used to lay out multiple power strips on a chip, characterized in that, The layout optimization method includes: Obtain the available wiring area of ​​the chip; wherein, the available wiring area is a target area for laying out power strips, the outer boundary of which is non-rectangular and / or the interior contains one or more power strip wiring blocking areas, the power strip wiring blocking areas are used to prohibit the laying of power strips within them, and the remaining part of the available wiring area except for the power strip wiring blocking areas constitutes an effective area for power strip laying. Based on the geometric features of the available wiring area, it is converted into multiple rectangular strips; wherein, when the geometric features include a power strip wiring blockage area in the available wiring area, each rectangular strip does not contain any point within the power strip wiring blockage area; Based on the preset layout constraint rules and the multiple rectangular strips, multiple candidate sets of the first power strip are constructed; wherein, each candidate set includes at least the two boundary positions of the power strip in its arrangement direction, and the chip has a number of preset parallel and equidistant tracks, the tracks are used to define the layout position of the power strip, and the layout constraint rules include the setting of whether the power strip is attracted to the preset tracks. Multiple power strips are arranged based on the candidate set that meets the preset phase requirements in the multiple candidate sets.

2. The layout optimization method as described in claim 1, characterized in that, The process of constructing multiple candidate sets for the first power strip based on preset layout constraint rules and the multiple rectangular strips includes: When the power strip is set to be attached to a preset track, multiple candidate sets of the first power strip are calculated according to the preset attachment mode; wherein, under different attachment modes, the power strip is attached to the track at different positions. When the setting is not to attach the power strip to the preset track, multiple candidate sets of the first power strip are calculated based on the boundary of the rectangular strip.

3. The layout optimization method as described in claim 2, characterized in that, The process of laying out multiple power strips on the chip includes laying out multiple power strips in either a first mode or a second mode. In the first mode, the multiple power strips laid out are of the same type. In the second mode, multiple units of power strips are laid out cyclically, with each unit containing multiple power strips of different types and widths. When laying out multiple power strips in the second mode, the candidate set of the first power strip also includes the type of the first power strip. The phase requirement includes that the width of the last power strip is less than or equal to the remaining available width of the available wiring area. The remaining available width is equal to the internal width of the available wiring area minus the sum of the widths of all the power strips already laid out. The width of the last power strip is determined based on the type of the first power strip.

4. The layout optimization method as described in claim 3, characterized in that, When multiple power strips are laid out according to the first pattern, the step of calculating multiple candidate sets of the first power strip based on the boundary of the rectangular strip includes: Modular operation is performed on the side length of the boundary of the rectangular strip and the preset step size, and multiple candidate sets of the first power strip are constructed based on the result of the modular operation; When multiple power strips are laid out according to the second mode, the step of calculating multiple candidate sets of the first power strip based on the boundary of the rectangular strip includes: A modulo operation is performed on the side length of the boundary of the rectangular strip and the preset unit width, and multiple candidate sets of the first power strip are constructed based on the result of the modulo operation; wherein, the unit width is the sum of the width and spacing of the power strips in each unit.

5. The layout optimization method as described in claim 2, characterized in that, The calculation of multiple candidate sets for the first power strip based on a preset adsorption mode includes: Based on the preset track offset and track spacing, the coordinate position of each track is determined; Based on the coordinates of each track and the preset adsorption mode, multiple candidate sets of the first power strip are calculated.

6. The layout optimization method as described in claim 5, characterized in that, The adsorption modes include a leftward adsorption mode, a rightward adsorption mode, and a proximity adsorption mode. The calculation of multiple candidate sets for the first power strip based on the coordinate positions of each track and the preset adsorption modes includes: When the adsorption mode is left adsorption mode, for any two adjacent tracks, the position of the smallest track is taken as the first minimum critical value of the adsorption region. The first maximum critical value of the adsorption region is calculated based on the position of the smallest track and the preset spacing. Multiple candidate sets of the first power strip are calculated based on the first minimum critical value and the first maximum critical value of the adsorption region. When the adsorption mode is a rightward adsorption mode, for any two adjacent tracks, the position of the track with the largest value is taken as the second maximum critical value of the adsorption region. The second minimum critical value of the adsorption region is calculated based on the position of the track with the largest value and the preset spacing. Multiple candidate sets of the first power strip are calculated based on the second minimum critical value and the second maximum critical value. When any power strip is located in the adsorption region, the power strip is adsorbed to the track. When the adsorption mode is the nearest adsorption mode, for any two adjacent tracks, the midpoint of the line connecting the two tracks is used as the boundary, and the coordinate intervals on both sides of the midpoint are respectively divided into the adsorption regions of the corresponding tracks. For the first or last track, the width of the extrapolation is determined based on the distance between it and the adjacent track, and it is extrapolated outward in the direction of the track to form the corresponding outer adsorption boundary. When any power strip is located in the adsorption region of the track, the power strip is adsorbed to the track, and multiple candidate sets of the first power strip are calculated according to the position of the track.

7. The layout optimization method as described in claim 1, characterized in that, The geometric feature of the available wiring area is that it contains one or more power strip wiring blocking areas. The process of converting the available wiring area into multiple rectangular strips based on its geometric features includes: Obtain the boundary of the available wiring area and the boundary of the power strip wiring blockage area; Extract the first boundary coordinates of the boundary of the available wiring area in the first direction, extract the second boundary coordinates of the boundary of the power strip wiring blockage area in the first direction, and determine the area where the scan strip is located based on the adjacent first boundary coordinates and second boundary coordinates; The control scan line moves along a first direction starting from the boundary of the available wiring area, and when the scan line moves to the area where the scan strip is located, a plurality of projection intervals of the available wiring area in a second direction are determined according to the area where the scan strip is located; Detect whether there are gaps between each projection interval, the gaps corresponding to the power strip wiring blockage area, take the projection intervals in the area where each scan band is located except for the gaps as sub-regions, and generate multiple rectangular strips based on multiple sub-regions.

8. A layout optimization device for power strips, characterized in that, include: The region determination module is used to obtain the available wiring region of the chip; wherein, the available wiring region is a target region for laying out power strips, the outer boundary of which is non-rectangular and / or the interior contains one or more power strip wiring blocking regions, the power strip wiring blocking regions are used to prohibit the laying of power strips within them, and the remaining part of the available wiring region except for the power strip wiring blocking regions constitutes an effective region for power strip laying. A strip conversion module is used to convert the available wiring area into multiple rectangular strips based on the geometric features of the available wiring area; wherein, when the geometric features include a power strip wiring blockage area in the available wiring area, each rectangular strip does not contain any point within the power strip wiring blockage area; A candidate set construction module is used to construct multiple candidate sets of the first power strip based on preset layout constraint rules and the multiple rectangular strips; wherein, each candidate set includes at least the two boundary positions of the power strip in its arrangement direction, the chip has a number of preset parallel and equidistant tracks, the tracks are used to define the layout position of the power strip, and the layout constraint rules include a setting for whether the power strip is attracted to the preset tracks. The power strip layout module is used to lay out multiple power strips based on a candidate set that meets the preset phase requirements from the multiple candidate sets.

9. A layout optimization device for power strips, characterized in that, include: Memory, used to store programs; A processor for implementing the layout optimization method as described in any one of claims 1-7 by executing a program stored in the memory.

10. A computer program product comprising a computer program and / or instructions, characterized in that, When the computer program and / or instructions are executed by the processor, they implement the layout optimization method as described in any one of claims 1-7.

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