Method, device and computing equipment for generating a circuit schematic

Abstract

This application provides a method, apparatus, and computing device for generating circuit schematics. It includes: responding to a user's input operation on an interactive interface for a target circuit project, acquiring circuit design constraint information; acquiring multiple candidate devices from a first database based on the circuit design constraint information; generating corresponding prompts based on the circuit design constraint information and the attribute information of the candidate devices; inputting the prompts into a target large-scale model to obtain inference results; and generating a corresponding circuit schematic based on the attribute information, device location, and circuit structure information of at least one target device. By combining the inference capabilities of the target large-scale model with rule constraints to recommend devices, this method avoids manual circuit schematic design from scratch, improving the accuracy and device compatibility of generated circuit schematics, reducing design rework caused by improper device selection or unreasonable circuit structure, and improving the quality of generated circuit schematics.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design technology, and in particular to a method, apparatus and computing device for generating circuit schematics. Background Technology

[0002] In the design and manufacturing process of electronic products, the soldering of printed circuit boards (PCBs) usually needs to be based on a pre-designed electronic design automation (EDA) circuit schematic. The EDA circuit schematic describes the types, parameters, and electrical connections between various electronic components in the circuit, thus providing a design basis for subsequent PCB layout and routing as well as circuit board production.

[0003] In existing technologies, circuit schematics are typically drawn electronically by engineers using design tools. During the design process, engineers need to select components based on the circuit's functional requirements and establish the electrical connections between these components. For example, engineers often need to manually consult component datasheets to analyze and screen the parameters, package types, and compatibility of different component models to determine the appropriate component models and complete the circuit design.

[0004] However, the above methods rely on the professional experience of engineers, and omissions or unreasonable situations are prone to occur during the design process, resulting in errors or incompatibility issues in the design results. This leads to rework of the circuit design, resulting in poor quality circuit schematics that are difficult to apply directly to actual PCB design. Summary of the Invention

[0005] This application provides a method, apparatus, and computing device for generating circuit schematics. By combining the reasoning capabilities of a target large model with rule constraints to recommend and select devices, the circuit schematic design can be avoided from scratch. This can improve the accuracy of the generated circuit schematics and the compatibility between devices, reduce design rework caused by improper device selection or unreasonable circuit structure, and improve the quality of generated circuit schematics.

[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions: In a first aspect, embodiments of this application provide a method for generating circuit schematics. The method includes: responding to a user's input operation on a target circuit project in an interactive interface, acquiring circuit design constraint information; the circuit design constraint information is used to limit the types of functional modules required for the circuit schematic to be generated and their corresponding electrical parameter requirements; based on the circuit design constraint information, acquiring multiple candidate devices from a first database; generating corresponding prompt words based on the circuit design constraint information and the attribute information corresponding to the candidate devices; inputting the prompt words into a target large model to obtain a reasoning result; wherein the reasoning result includes attribute information of at least one target device, the device location corresponding to the target device, and circuit structure information; and generating a circuit schematic corresponding to the target circuit project based on the attribute information, device location, and circuit structure information of at least one target device.

[0007] Based on this scheme, components in the database are filtered based on circuit design constraints. A target large-scale model is constructed by combining candidate component attribute information with prompts for inference, thereby obtaining the target component's attribute information, location, and circuit structure information. Based on this, a circuit schematic corresponding to the target circuit project is generated. This allows circuit schematic generation to be performed under clear design constraints. By combining database retrieval with target large-scale model inference, a comprehensive analysis of component selection and circuit structure is conducted, automatically determining the required components and their structural relationships, thus achieving automated circuit schematic generation. Simultaneously, the intelligent recommendation mechanism of the target large-scale model makes the component selection process more accurate and efficient, reducing reliance on individual engineer experience and improving the efficiency of circuit schematic generation and overall design quality.

[0008] In one possible implementation, in response to a user's input operation on the target circuit project in the interactive interface, circuit design constraint information is obtained, including: in response to a user's modular configuration operation in the interactive interface, at least one logical function module and its corresponding module configuration information are obtained to determine the circuit design constraint information; wherein, the logical function module is a functional abstract unit independent of physical devices, used to characterize a specific logical function in the circuit; the module configuration information includes the signal input-output relationship and functional performance parameters of the logical function module.

[0009] Based on this approach, by abstracting circuit design requirements into logical functional modules and configuring them in conjunction with the signal input / output relationships and functional performance parameters of each module, circuit design constraints can be clearly expressed in a structured manner. This allows for the clarification of the system's required functional goals and performance indicators in the early stages of circuit design. Furthermore, since the logical functional modules are independent of specific physical devices, designers can directly describe circuit behavior at the functional level without delving into the complex configurations of underlying devices. This significantly reduces the technical threshold and operational complexity of circuit design, and improves the efficiency of circuit diagram generation.

[0010] In another possible implementation, based on circuit design constraint information, multiple candidate devices from a first database are obtained, including: obtaining a first screening result from the first database based on the functional module type in the circuit design constraint information; wherein the first screening result is used to characterize devices that conform to the same device category corresponding to the functional module type; comparing the key electrical parameters in the circuit design constraint information with the specification parameters of each device in the first screening result by numerical range to obtain a second screening result; wherein the second screening result is used to characterize devices that meet the key electrical parameters; performing semantic analysis on the circuit design constraint information to extract application scenario identifiers; wherein the target scenario identifier is used to characterize the application scenario category corresponding to the circuit design constraint information; and matching the application scenario identifier with the feature tags of each device in the second screening result to determine multiple candidate devices from the second screening result.

[0011] Based on this scheme, a multi-layered screening mechanism based on device category matching, electrical parameter screening, and application scenario matching enables the candidate device determination process to comprehensively filter from multiple dimensions such as functional category, electrical performance, and application environment. This effectively improves the matching degree between device screening results and actual circuit design requirements, reduces the entry of irrelevant or incompatible devices into the subsequent reasoning process, reduces computational complexity, and improves device screening efficiency.

[0012] In another possible implementation, based on at least one target device attribute information, device location, and circuit structure information, a circuit schematic diagram corresponding to the target circuit project is generated. This includes: generating an initial circuit structure diagram in response to a first editing operation based on the target device, device location, and circuit structure information; and verifying the connection relationships indicated by the connection instructions based on interface matching rules and signal connection constraint rules stored in a preset rule base, obtaining a verification result. If the verification result indicates that the verification passed, a structured block diagram is generated based on the connection relationships and the target device to be used; and a circuit schematic diagram corresponding to the target circuit project is generated based on the structured block diagram.

[0013] Based on this solution, by introducing a rule base during the circuit structure generation process to verify interface matching relationships and signal connection constraints, the connection relationships between logical functional modules can be effectively verified during the generation stage. This prevents connections that do not meet electrical connection rules or interface matching requirements from entering the final circuit schematic, improving the standardization and accuracy of circuit structure generation. Simultaneously, by generating structured block diagrams and visually displaying the circuit logic structure, users can intuitively understand the logical relationships between various functional modules, reducing the complexity of circuit design. Furthermore, by constructing circuits through visual assembly and block diagram connections, users do not need to focus on the underlying details of specific components; they only need to define the overall logic structure of the circuit to complete the design, further improving the efficiency and accuracy of circuit design.

[0014] In another possible implementation, based on at least one target device attribute information, device location, and circuit structure information, a circuit schematic diagram corresponding to the target circuit project is generated, including: in response to a user's selection operation, determining at least one target device to be used from at least one target device, and obtaining the target device location and target circuit structure information corresponding to the target device to be used to generate an initial circuit structure diagram; calling the interface matching rules and signal connection constraint rules stored in the preset rule base to verify the initial circuit structure diagram, and generating a structured block diagram if the verification result indicates that the verification passed; and generating a circuit schematic diagram corresponding to the target circuit project based on the structured block diagram.

[0015] Based on this solution, by automatically confirming the devices to be used based on the recommended target devices, the system can directly generate the final selection result from multiple candidate devices according to design requirements without user intervention, thereby achieving automation and high adaptability in device selection. Simultaneously, by using a rule base to verify the interface matching relationships and signal connection relationships in the initial circuit structure diagram, the connection relationships between logic functional modules can be effectively verified during the generation stage, preventing connections that do not meet electrical connection rules or interface matching requirements from entering the final circuit schematic. Furthermore, the system directly generates a structured block diagram and displays it to the user, allowing the user to intuitively view the complete circuit logic structure without needing to focus on the underlying details of specific devices, thus significantly improving the efficiency and accuracy of circuit schematic generation.

[0016] In another possible implementation, a circuit schematic corresponding to the target circuit project is generated based on the structured block diagram. This includes: verifying the structured block diagram based on preset network topology rules, preset input integrity rules, and preset device library matching rules. The network topology rules are used to determine whether the electrical connections in the structured block diagram are continuous; the input integrity rules are used to determine whether the port signals and attribute information of the target device to be used in the structured block diagram are accurate; and the device library matching rules are used to determine whether the parameter information of the target device to be used in the structured block diagram is consistent with the definitions in the device library. If the structured block diagram verification passes, the circuit schematic corresponding to the target circuit project is generated.

[0017] Based on this solution, by performing multi-dimensional rule verification after the structured block diagram is generated, the electrical connectivity, signal integrity, and consistency of device parameters can be guaranteed during the generation stage of the circuit schematic. This effectively avoids unreasonable connections, incomplete signals, or incorrect device parameters from entering the final schematic, thereby improving the standardization and reliability of the circuit schematic. At the same time, the combination of automated verification and schematic generation eliminates the need for repeated manual checks during the design process, improving the efficiency and accuracy of circuit schematic generation.

[0018] In another possible implementation, generating the circuit schematic corresponding to the target circuit project includes: responding to the user's tool selection operation in the interactive interface, generating the circuit schematic corresponding to the target circuit project under the target tool based on the structured block diagram; wherein, the tool selection operation corresponds one-to-one with the target tool.

[0019] Based on this solution, by introducing user-selectable tool types, the generated circuit schematics can directly match the formats and requirements of different design tools, thereby achieving cross-tool compatibility and adaptability. At the same time, by combining structured block diagrams as the generation basis, the schematics maintain logical consistency and structural integrity under different tools, reducing the workload of manual conversion or adjustment, and improving the efficiency, accuracy, and user convenience of circuit schematic generation.

[0020] Another possible implementation includes: acquiring multiple devices and historical circuit schematics; classifying multiple devices based on their corresponding attribute information to generate multiple logic function modules; extracting device information, module schematic netlists, and multi-dimensional scoring tables from historical circuit schematics; and constructing a first database based on multiple logic function modules, device information, module schematic netlists, and multi-dimensional scoring tables.

[0021] Based on this scheme, by integrating device attribute information with historical schematic data, a structured logical function module and a multi-dimensional database are formed. This enables the first database to comprehensively and accurately reflect device characteristics, module structure, and historical design experience, providing a reliable data foundation for the automatic generation of subsequent circuit schematics. At the same time, by introducing modular classification and scoring information, intelligent management and rapid retrieval of devices and modules are achieved, thereby improving device selection efficiency, enhancing the reference value of design schemes, and providing standardized and high-quality data support for automated circuit design.

[0022] Secondly, embodiments of this application also provide a circuit schematic generation apparatus, which includes: an interaction module, used to respond to a user's input operation on a target circuit project in an interactive interface to obtain circuit design constraint information; the circuit design constraint information is used to limit the functional module types required for the circuit schematic to be generated and their corresponding electrical parameter requirements; an acquisition module, used to acquire multiple candidate devices in a first database based on the circuit design constraint information; a generation module, used to generate corresponding prompt words based on the circuit design constraint information and the attribute information corresponding to the candidate devices; a reasoning module, used to input the prompt words into a target large model to obtain a reasoning result; wherein, the reasoning result includes attribute information of at least one target device, the device position corresponding to the target device, and circuit structure information; the generation module is also used to generate a corresponding circuit schematic based on the attribute information, device position, and circuit structure information of at least one target device.

[0023] In one possible implementation, an acquisition module is used to acquire at least one logical function module and its corresponding module configuration information in response to a user's modular configuration operation in the interactive interface, so as to determine circuit design constraint information; wherein, the logical function module is a functional abstraction unit independent of physical devices, used to characterize a specific logical function in the circuit; the module configuration information includes the signal input-output relationship and functional performance parameters of the logical function module.

[0024] In one possible implementation, an acquisition module is used to obtain a first screening result from a first database based on the functional module type in the circuit design constraint information; wherein the first screening result is used to characterize devices that conform to the same device category corresponding to the functional module type; based on the key electrical parameters in the circuit design constraint information, the key electrical parameters are compared with the specification parameters of each device in the first screening result to obtain a second screening result; wherein the second screening result is used to characterize devices that meet the key electrical parameters; semantic analysis is performed on the circuit design constraint information to extract application scenario identifiers; wherein the target scenario identifier is used to characterize the application scenario category corresponding to the circuit design constraint information; the application scenario identifiers are matched with the feature tags of each device in the second screening result to determine multiple candidate devices from the second screening result.

[0025] In one possible implementation, a generation module is used to generate an initial circuit structure diagram in response to a first editing operation, based on the target device, device location, and circuit structure information; and in response to a second editing operation, to verify the connection relationships indicated by the connection instructions based on interface matching rules and signal connection constraint rules stored in a preset rule base, and obtain a verification result. If the verification result indicates that the verification passed, a structured block diagram is generated based on the connection relationships and the target device to be used; and a circuit schematic diagram corresponding to the target circuit project is generated based on the structured block diagram.

[0026] In one possible implementation, a generation module, in response to a user's selection operation, determines at least one target device to be used from at least one target device, and obtains the target device location and target circuit structure information corresponding to the target device to be used, so as to generate an initial circuit structure diagram; calls the interface matching rules and signal connection constraint rules stored in the preset rule base to verify the initial circuit structure diagram, and generates a structured block diagram if the verification result indicates that the verification is passed; and generates the circuit schematic diagram corresponding to the target circuit project based on the structured block diagram.

[0027] In one possible implementation, a generation module is used to verify the structured block diagram based on preset network topology rules, preset input integrity rules, and preset device library matching rules. The network topology rules are used to determine whether the electrical connections in the structured block diagram are continuous; the input integrity rules are used to determine whether the port signals and attribute information of the target device to be used in the structured block diagram are accurate; and the device library matching rules are used to determine whether the parameter information of the target device to be used in the structured block diagram is consistent with the definitions in the device library. If the structured block diagram verification passes, a circuit schematic corresponding to the target circuit project is generated.

[0028] In one possible implementation, a generation module is used to generate a circuit schematic corresponding to the target circuit item under the target tool based on a structured block diagram, in response to the user's tool selection operation in the interactive interface; wherein, the tool selection operation corresponds one-to-one with the target tool.

[0029] In one possible implementation, the acquisition module is further used to acquire multiple devices and historical circuit schematics; the classification module is used to classify multiple devices based on their corresponding attribute information, generating multiple logical function modules; the extraction module is used to extract device information, module schematic netlists, and multi-dimensional scoring tables from historical circuit schematics; and the construction module is used to construct a first database based on the multiple logical function modules, device information, module schematic netlists, and multi-dimensional scoring tables.

[0030] Thirdly, embodiments of this application also provide a computing device, including: a processor and a memory; the processor and the memory are coupled; the memory is used to store program instructions; the processor is used to execute the program instructions to perform the method as described in any of the first aspects above.

[0031] Fourthly, embodiments of this application provide a chip for performing the methods described in any of the first aspects above.

[0032] Fifthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a computer, implement the method as described in any of the first aspects.

[0033] In a sixth aspect, embodiments of this application provide a program product including a computer program that, when executed by a processor, implements the method as described in any of the first aspects. Attached Figure Description

[0034] Figure 1 This is a scenario diagram of generating a PCB board based on an EDA circuit schematic provided in an embodiment of this application; Figure 2 This is a schematic diagram of a circuit schematic design process provided in an embodiment of this application; Figure 3 This is a schematic diagram of a circuit schematic generation framework provided in an embodiment of this application; Figure 4 This is a schematic diagram illustrating a deployment method of a generation framework provided in an embodiment of this application; Figure 5 This is a schematic diagram of the execution logic of a generation framework provided in an embodiment of this application; Figure 6 This is a flowchart illustrating a method for generating a circuit schematic diagram according to an embodiment of this application; Figure 7 This is a signaling interaction diagram of a circuit schematic generation method provided in an embodiment of this application; Figure 8 This is a schematic diagram of an interactive interface provided in an embodiment of this application; Figure 9 This is a schematic flowchart of a method for generating a structured block diagram provided in an embodiment of this application; Figure 10 This is a schematic diagram of another interactive interface provided in an embodiment of this application; Figure 11 This is a schematic diagram of another method for generating structured block diagrams provided in an embodiment of this application; Figure 12 This is a schematic flowchart of a circuit schematic generation method provided in an embodiment of this application; Figure 13 This is a schematic diagram of a method for constructing a first database provided in an embodiment of this application; Figure 14 This is a schematic diagram of a circuit schematic generation device provided in an embodiment of this application; Figure 15 This is a schematic diagram of a computing device provided in an embodiment of this application. Detailed Implementation

[0035] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. To facilitate a clear description of the technical solutions of the embodiments of this application, the use of terms such as "first," "second," etc., in the embodiments of this application is for illustrative purposes and to distinguish the objects being described. There is no particular order between them, nor does it indicate a specific limitation on the number of devices in the embodiments of this application, and they do not constitute any limitation on the embodiments of this application.

[0036] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of this application.

[0037] It should be noted that many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Therefore, the scope of protection of this application is not limited to the specific embodiments disclosed below.

[0038] The following explanations of the technical terms mentioned in the embodiments of this application are provided to facilitate understanding by those skilled in the art.

[0039] A printed circuit board (PCB) is a physical circuit carrier that is based on an insulating substrate, on which conductive lines and soldering structures are formed on and / or inside the insulating substrate to mount electronic devices and realize electrical connections between electronic devices.

[0040] A circuit diagram is a graphical representation of the electrical connections between electronic devices. It uses pre-defined circuit symbols and lines to describe the connections and circuit structure between electronic devices.

[0041] Electronic design automation (EDA) refers to a class of technologies that use computer technology to assist in the design of electronic circuits or electronic systems. It is used to realize circuit schematic design, simulation verification, printed circuit board design, and related design processes. Within this technological framework, specific circuit diagram software tools can be used to complete operations at different design stages.

[0042] Circuit diagram generation tools are software tools used to generate electronic circuit diagrams on a computer. They achieve the selection, wiring, and layout of electronic components and circuit structures through graphical interfaces or automated algorithms. Depending on their functions or implementation methods, these tools can achieve partial or full automation of generation and can be integrated with PCB design. Common tools include Altium Designer, Cadence OrCAD / Allegro, Mentor Graphics PADS / Xpedition, KiCad, and Proteus.

[0043] Large language models (LLMs) are deep learning-based natural language processing models that, through training on massive amounts of text data, can understand human language and generate coherent, context-sensitive text. These models typically contain billions or even hundreds of billions of parameters, possess strong generalization and multi-task processing capabilities, and can be applied to various scenarios such as question answering, translation, writing, and code generation. In this embodiment, the large language model serves as the target large model, and through fine-tuning on a first database, it is used to generate recommendation results; alternatively, resources in the first database are used to semantically enhance the model's output, thereby obtaining the final recommendation results.

[0044] The embodiments of this application will now be described with reference to the accompanying drawings.

[0045] In the design and manufacturing process of electronic products, the assembly of printed circuit boards (PCBs) usually needs to be based on the pre-designed EDA circuit schematic. The EDA circuit schematic describes in detail the parameters of various types of electronic components in the circuit and their electrical connection relationships, providing a key design basis for subsequent PCB layout, routing and production.

[0046] Figure 1 This is a scenario diagram of generating a PCB board based on an EDA circuit schematic provided in an embodiment of this application.

[0047] like Figure 1 As shown, based on EDA circuit principles Figure 11This can generate a PCB layout that is strictly consistent with it. The electronic components (including but not limited to integrated circuits, resistors, capacitors, inductors, and connectors) arranged on this PCB are completely matched with the design defined in the EDA circuit schematic in terms of type, electrical parameters, package form, and network connection relationship between them, ensuring accurate conversion from logic design to physical implementation.

[0048] Therefore, before designing a PCB, it is necessary to accurately design the circuit schematic.

[0049] Figure 2 This is a schematic diagram of a circuit schematic design process provided in an embodiment of this application.

[0050] like Figure 2 As shown, the entire circuit schematic design process can be summarized as: requirements analysis → concept generation → scheme evaluation → circuit schematic design. Specifically, the design goals are first clarified based on the requirements proposed by the user or market, such as performance indicators, power consumption requirements, and size constraints. This is the foundational stage of the design, ensuring that subsequent design directions match market demands. Based on the results of the requirements analysis, various preliminary design schemes are generated through brainstorming meetings and other methods. This stage emphasizes creativity and innovation, aiming to explore various possible design paths to meet the identified requirements. After concept generation is completed, these preliminary design schemes are comprehensively evaluated in conjunction with budget, time, and process constraints. The goal of this stage is to select the optimal design scheme, ensuring that it not only meets technical requirements but is also feasible within the given resource limits. Once the best scheme is selected, the schematic design stage begins. EDA tools are used to draw the specific circuit schematic. Figure 11 This ensures that all electronic components and their electrical connections are accurately represented on the schematic diagram.

[0051] In the design process of electronic products, the design of circuit schematics is a core step, mainly used to define the types, parameters, and electrical connections between electronic components. Based on this crucial stage, this application proposes a circuit schematic generation framework.

[0052] Figure 3 This is a schematic diagram of a circuit schematic generation framework provided in an embodiment of this application.

[0053] like Figure 3As shown, the generation framework is not based on system hierarchy, but rather on the logical flow of circuit schematic generation, divided into four functionally cooperating software layers. These include: a fusion database layer 31 (also known as the first database layer), a block diagram assembly layer 32, an intelligent recommendation layer 33, and a tool output layer 34. Through the interaction of these four functionally cooperating software layers, an efficient, intelligent, and automated schematic design process is constructed, significantly lowering the design threshold and enabling non-professional users to participate. Simultaneously, it achieves "zero rework" and comprehensively improves the efficiency and quality of schematic drawing.

[0054] Among them, the integrated database layer 31 serves as the data foundation for the entire process, used to modularize complex circuits according to function, forming reusable logic function modules. Simultaneously, by performing structured analysis and annotation of historical schematic diagrams, a module schematic diagram annotation library and a component information annotation library are constructed. Furthermore, a multi-dimensional scoring rule table is established by combining multi-dimensional scoring rules. These multiple core data resources—functional module library, annotation library, and scoring rule table—are organically integrated to form a unified, structured, and intelligently accessible first database.

[0055] The block diagram assembly layer 32 serves as the core link for user interaction in the entire process. It provides an intuitive and efficient graphical operation interface, supporting users to complete the entire design operation process of "logical function module selection - parameter configuration - position placement - block diagram connection".

[0056] The intelligent recommendation layer 33 serves as the intelligent decision-making hub in the entire process. It receives "component attributes + functional descriptions" information from the block diagram assembly layer and combines it with the fine-tuned electronic domain large language model and the structured knowledge in the first database to perform semantic understanding and contextual reasoning, thereby outputting accurate recommendation results.

[0057] The tool output layer 34 plays a crucial execution role in the overall process, handling the structured block diagram data passed from the block diagram assembly layer. By calling the self-developed circuit diagram generation tool, it automatically transforms this data into complete circuit schematics.

[0058] Optionally, the above-mentioned generation framework can be deployed in different ways according to actual needs. The following section combines... Figure 4 An example is provided.

[0059] Figure 4 This is a schematic diagram illustrating a deployment method of a generation framework provided in an embodiment of this application.

[0060] The framework can be deployed on a single computing device or on different computing devices. For example, such as... Figure 4As shown in (a), the integrated database layer 31, the block diagram assembly layer 32, the intelligent recommendation layer 33, and the tool output layer 34 can be deployed on the same computing device, such as computing device A.

[0061] like Figure 4 As shown in (b), the fusion database layer 31, block diagram assembly layer 32, intelligent recommendation layer 33, and tool output layer 34 can be deployed on different computing devices. For example, the fusion database layer 31 is deployed in the first computing device B1 for centralized management of the first database; the block diagram assembly layer 32 is deployed in the second computing device B2 for providing a user interface; the intelligent recommendation layer 33 is deployed in the third computing device B3 for intelligent reasoning based on the target large model and database in the electronics field; and the tool output layer 34 is in the second computing device B4 for calling self-developed generation tools to complete the automated output of schematic diagrams. The layers interact efficiently through standardized interfaces and network communication protocols, supporting flexible resource scheduling and expansion while ensuring the stability and maintainability of the overall process.

[0062] The specific execution logic of each of the above layers is explained below.

[0063] Figure 5 This is a schematic diagram of the execution logic of a generation framework provided in an embodiment of this application.

[0064] like Figure 5 As shown, in the data preparation phase, the first database is constructed using the integrated database layer 31. Specifically, the acquired components are categorized, and metadata, such as verification rules and relationships between ports, is defined. This information is then abstracted into different logical functional modules. Simultaneously, historical circuit schematics are acquired, and information is extracted from these schematics to generate component information, module schematic netlists, and multi-dimensional scoring tables. These various types of structured data collectively constitute the core components of the first database. This first database serves as a crucial data reference for the subsequent intelligent recommendation layer's reasoning and decision-making, providing support for achieving high-quality, high-efficiency automated schematic generation.

[0065] During the interactive design phase, the block diagram assembly layer 32 establishes a mapping relationship between the logical function modules in the first database and the user interface, enabling users to build the circuit logic structure through graphical operations. Specifically, users can perform input operations such as dragging and dropping logical function modules and configuring parameters on the interface to obtain design constraint information for the target circuit. This constraint information includes the required functional module types and key electrical parameter requirements (such as voltage, current, and frequency), which are then passed as context to the intelligent recommendation layer 33. The intelligent recommendation layer 33 receives the circuit design constraint information from the block diagram assembly layer 32 and retrieves multiple candidate devices from the first database. Furthermore, based on the circuit design constraint information and the attribute information corresponding to the candidate devices, it automatically generates structured prompts and inputs them into the fine-tuned electronic domain target model for reasoning. The reasoning results output by the target model include: recommended target devices, corresponding device scores, suggested device locations, and circuit structure information. This result is fed back to the block diagram assembly layer 32. Based on the recommendation results (at least one target device, the device score, the device location, and the circuit structure information), the block diagram assembly layer 32, under rule constraints, draws the relationships between devices, generates a detailed structured block diagram in response to user operations, and stores it. This storage can be in JOSN format. Further, the structured block diagram is transmitted to the tool output layer 34. The tool output layer 34 performs pre-validation on the generated circuit schematic, including network rule validation, input integrity validation, and device selection validation. Then, the structured block diagram is parsed, retaining only the devices and their connections required to generate the circuit schematic, and the parsed content is imported into the specified EDA tool to generate the corresponding circuit schematic.

[0066] In summary, by combining the reasoning capabilities of the target large model with rule constraints to recommend and select components, and avoiding designing circuit schematics from scratch, the accuracy of generated circuit schematics and the compatibility between components can be improved. This reduces design rework caused by improper component selection or unreasonable circuit structure, and improves the quality of generated circuit schematics.

[0067] The following section, with reference to the accompanying drawings, explains the specific implementation process of the method for generating circuit schematics.

[0068] Figure 6 This is a flowchart illustrating a method for generating a circuit schematic diagram according to an embodiment of this application.

[0069] like Figure 6 As shown, the generation framework applied in the circuit schematic generation method, taking deployment on a computing device as an example, includes the following steps: S1: The computing device responds to the user's input operation on the target circuit project in the interactive interface and obtains circuit design constraint information.

[0070] Among them, the target circuit project refers to the circuit design task created or selected by the user in the circuit design, which is used to characterize the task scheme corresponding to the circuit schematic to be generated. For example, the target circuit project can be a functional subsystem design project in a certain electronic device, such as a signal acquisition circuit project or a power management circuit project.

[0071] Circuit design constraint information is used to define the types of functional modules required for the generated circuit schematic and their corresponding electrical parameter requirements. This information includes at least one logical functional module and its corresponding module configuration information. A logical functional module is a functional abstraction unit independent of physical devices, used to characterize a specific logical function in the circuit, such as power management, storage, or interface control. The module configuration information consists of electrical parameters that meet the electrical parameter requirements; these are the configuration constraints describing the logical functional module, including its signal input / output relationships and functional performance parameters, such as module attributes, port attributes, interface type, operating voltage range, and communication rate.

[0072] Figure 7 This is a signaling interaction diagram of a circuit schematic generation method provided in an embodiment of this application.

[0073] like Figure 7 As shown, S1 includes step S1001.

[0074] S1001: The block diagram assembly layer of the computing device responds to the user's modular configuration operation for the target circuit project in the interactive interface, and obtains at least one logical function module and the corresponding module configuration information to determine the circuit design constraint information.

[0075] Figure 8 This is a schematic diagram of an interactive interface provided in an embodiment of this application.

[0076] like Figure 8 As shown in (a), in response to a user's input action when opening an interactive interface in browser page 1 (such as entering "locallhost / ........html"), the following is displayed: Figure 8The first interactive interface 8 is shown in (b) above. The first interactive interface 8 includes a module library area 81, a drawing area 82, and a module configuration area 83. The module library area 81 displays a pre-built logic function module library, which includes various logic function modules such as Power Module, Clock Module, Temperature Module, Memory Module, GPIO expansion module, and I2C interface control module. Users can select the desired logic function module from the module library area 81. The drawing area 82 displays the selected logic function module and allows users to add logic function modules to the drawing area 82 by dragging and dropping to form the functional module layout structure of the circuit to be designed. The module configuration area 83 is used to configure the parameters of the selected logic function module to obtain module configuration information. For example, users can set module attributes, port attributes, interface type, power input type, signal direction, and related electrical parameters in the module configuration area 83.

[0077] For example, such as Figure 8 As shown in (c), taking the signal acquisition circuit project as an example, in response to the drag-and-drop operation of the logic function modules related to the signal acquisition function from the module library area 81, such as the power supply module, sensor interface module, and signal conditioning module, logic function modules Q1, Q2, Q3, Q4, and Q5 are added to the drawing area 82 to form the initial functional module structure of the signal acquisition circuit.

[0078] Furthermore, parameter values ​​are set for logic function modules in module configuration area 83 to obtain corresponding module configuration information. For example, for logic function module Q1 (power supply module), parameters such as its input voltage range, output voltage value, maximum output current, and power supply type can be set. For instance, the input voltage range is 9V to 12V, the output voltage value is 5V, the maximum output current is 1A, and the power supply type is a step-down regulated power supply. Similarly, parameter values ​​are set for other logic function modules Q2-Q5. After completing the above parameter configuration, the circuit design constraint information M is obtained.

[0079] It should be noted that the above interface is only an example and does not impose any specific limitations on the layout.

[0080] It should be noted that after obtaining the circuit design constraint information, the block diagram assembly layer passes the circuit design constraint information as context information to the intelligent recommendation layer for use in subsequent circuit generation processing. This process will be explained in detail below with reference to step S1002.

[0081] S1002: The block diagram assembly layer sends circuit design constraint information to the intelligent recommendation layer.

[0082] Following the example above, the block diagram assembly layer sends circuit design constraint information M to the intelligent recommendation layer.

[0083] For ease of explanation, we will take the logic function module Q1 as an example for specific illustrative explanation.

[0084] S2: The computing device obtains multiple candidate devices from the first database based on circuit design constraint information.

[0085] Continue to combine Figure 7 As shown, step S2 includes steps S1003-S1006.

[0086] S1003: The intelligent recommendation layer filters from the first database based on the functional module types in the circuit design constraint information to obtain the first filtering result.

[0087] The first database is a pre-built comprehensive data resource library used to support automated circuit design and component selection. It contains the following core data resources: a module library for logic functions, a component table for component information, a historical module schematic netlist, and a multi-dimensional scoring table. The module library stores abstract descriptions of defined standard functional modules (such as power modules, communication modules, clock modules, etc.), including their input / output interfaces, functional semantics, and typical application scenarios. The component table records detailed parameters of specific electronic components, including component ID, component category, core electrical parameters (such as voltage, current, and power consumption), package type, scenario feature tags, cost, and supplier information. The module schematic netlist is derived from structured netlist data describing the internal component connections of standard functional modules in historical module implementation schemes or datasheets from successful past design projects, providing experience reference and reuse support. For a detailed explanation of the specific construction method of the first database, please refer to subsequent embodiments.

[0088] The first screening result is used to characterize at least one candidate device that matches the device category corresponding to the functional module type. Specifically, the transformation is performed through a pre-established "functional module type - device category" mapping relationship. For example, if the functional module type is "power module", it is mapped to the device category "power management", and based on this, all device records whose device category field matches "power management" are screened from the device table in the first database.

[0089] Specifically, a standardized "device category" attribute field can be set in the device table of device information, and an equal-value matching filter can be performed using a database query mechanism.

[0090] Continuing with the example above, when the functional module type is a power module, the system first finds that its corresponding device category is "Power Management," and then performs conditional filtering in the device table: "SELECT..." The command "FROM device_listWHERE device_category='Power_Management_'" is used to obtain a list of candidate devices including LDO-001, LDO-002, LDO-003, and LDO-005, which serves as the first screening result.

[0091] S1004: The intelligent recommendation layer compares the key electrical parameters in the circuit design constraint information with the numerical range of the specification parameters of each device in the first screening result to obtain the second screening result.

[0092] The second screening result is used to characterize candidate devices that, based on functional category matching, further meet specific electrical performance requirements. Key electrical parameters include, but are not limited to, at least one of the following: input voltage range, output voltage value, output current, power consumption parameters, or operating temperature range. Specific parameters can be dynamically determined according to actual circuit design needs and are not limited to the examples above.

[0093] Specifically, the key electrical parameters specified in the circuit design constraint information can be used as screening thresholds, and the numerical ranges of each parameter can be matched with the corresponding specification parameters of each device in the device table in the first screening result.

[0094] Continuing with the example above, when the functional module type is a power module, the first screening result already includes all "power management" devices. If the circuit design constraints further limit the key electrical parameters to: input voltage range 5V~12V, output voltage 3.3V, output current ≥500mA, and operating temperature range -40℃~+85℃, then the block diagram assembly layer sequentially checks each device in the first screening result for whether the device's rated input voltage covers [5V, 12V], whether the device's adjustable or fixed output voltage is equal to or configurable to 3.3V, whether the device's maximum output current is not less than 500mA, and whether the device's operating temperature range includes [-40℃, +85℃]. Only when all relevant specifications of the device meet the above constraints will the device be included in the second screening result, such as LDO-001, LDO-003, and LDO-005.

[0095] S1005: The intelligent recommendation layer performs semantic analysis on circuit design constraint information and extracts application scenario identifiers.

[0096] The target scenario identifier is used to characterize the application scenario category corresponding to the circuit design constraint information.

[0097] Specifically, the block diagram assembly layer performs natural language semantic parsing on the unstructured or semi-structured descriptions (such as "suitable for industrial control", "suitable for battery-powered equipment", "requires support for automotive electronic environments") contained in the circuit design constraint information, identifies and extracts keywords or phrases that characterize the target application domain, and uses them as application scenario identifiers; these identifiers are used to reflect the actual usage environment, industry domain, or typical platform that the circuit is intended for.

[0098] Continuing with the example above, if the functional module type is a power supply module, and the key electrical parameters are limited to input 5V~12V, output 3.3V, output current ≥500mA, and operating temperature -40℃~+85℃, and the circuit design constraint information further specifies "used for powering STM32 microcontrollers and deployed in industrial automation equipment", then the application scenario identifier, such as "industrial automation" and "STM32 power supply", can be extracted through semantic analysis.

[0099] S1006: The intelligent recommendation layer matches the application scenario identifier with the feature labels of each device in the second screening result to determine multiple candidate devices from the second screening result.

[0100] The feature labels of each device are structured fields that are pre-marked and fixed in the device table when the first database is built.

[0101] Specifically, the matching of application scenario identifiers and device feature labels in the block diagram assembly layer can be achieved through keyword precision matching or semantic similarity calculation.

[0102] In one example, in the current embodiment, a precise matching strategy based on a standardized keyword set is preferred. First, the application scenario identifiers are standardized. For example, application scenario identifiers (such as "industrial automation" and "STM32 power supply") are standardized into unified terminology: "industrial automation" → "industrial control", "STM32 power supply" → "MCU power supply". Next, each device in the second filtering results is traversed, and its "feature tag" field is read. According to the configuration strategy, it is determined whether all or part of the standardized application scenario identifiers are included in the tag set of the device. Optionally, the configuration strategy can be set to "all must be satisfied" or "only the core items need to be satisfied," and the core items can be customized according to user needs. If the matching conditions are met, the device is retained.

[0103] Continuing with the example above, after completing the electrical parameter screening, the second screening result may contain multiple LDOs or DC-DC devices that meet the requirements of 3.3V / 500mA / -40℃~+85℃. If the extracted application scenario is identified as "industrial automation" and "STM32 power supply," the system will only retain devices that are explicitly marked with corresponding feature tags such as "industrial control" (or "industrial automation"), "MCU power supply," "embedded power supply," or "STM32 compatible" in the device list. For example, if the feature tags of a certain LDO device are ["industrial control", "low quiescent current", "STM32 power supply"], then the match is successful. Finally, through this matching mechanism, two highly compatible candidate devices are identified from the second screening result: LDO-001 and LDO-003.

[0104] After using traditional matching recommendations as described above, a secondary recommendation process is needed.

[0105] S3: The computing device generates corresponding prompts based on circuit design constraints and the attribute information of candidate devices.

[0106] Continue to combine Figure 7 As shown, step S3 includes S1007.

[0107] S1007: The intelligent recommendation layer generates corresponding prompts based on circuit design constraints and the attribute information of candidate devices.

[0108] Among them, prompt words refer to structured natural language input text constructed to drive intelligent analysis and decision-making of the target large model.

[0109] The intelligent recommendation layer structurally integrates circuit design constraint information (such as functional module type, key electrical parameters, application scenarios, PCB layout constraints, heat dissipation conditions, cost budget, reliability requirements, etc.) with the attribute information of candidate devices stored in the first database (including device model, device category, core electrical parameters, package form, typical application cases, implicit characteristics (such as ripple, quiescent current, startup time), delivery cycle, unit price, environmental adaptability, industry certification, etc.) and organizes it into a clear, complete, and context-aware prompt text according to a preset template, which is the input prompt word for the target large model.

[0110] Continuing with the example above, in the power module selection, the prompt M1 might be described as follows: "Currently, a 3.3V power supply circuit needs to be designed for an STM32F103 microcontroller, with an input voltage of 5V±0.5V, a load current ≥1A, operating in an industrial environment (-40℃~+85℃), using a double-layer PCB with limited heat dissipation space. Candidate devices include LDO_001 (AMS1117-3.3, SOT-223, quiescent current 5mA, ripple 20mV) and LDO_003 (TC1185-3.3, SOT-23-5, quiescent current 1.2mA, ripple 8mV). Please recommend the better solution and explain your reasoning, considering power consumption, heat dissipation, cost, and long-term supply stability." S4: The computing device inputs the prompt words into the target large model and obtains the reasoning results.

[0111] Continue to combine Figure 7 As shown, step S4 includes S1008.

[0112] S1008: The intelligent recommendation layer uses prompt words as input to the target large model and uses the target large model to obtain the reasoning result.

[0113] The target large model is a specialized model built upon the general large language model (LLM). It is constructed through domain-specific fine-tuning of a large amount of device attribute data, historical circuit design cases, module schematic netlists, device manual reference circuits, and various design constraints contained in the first database. This fine-tuning process enables the target large model to understand the semantics of electronic circuits, accurately analyze engineering requirements, and perform multi-dimensional reasoning and recommendations in conjunction with structured knowledge.

[0114] Optionally, during the inference process, the target large model can also dynamically access the first database to achieve retrieval-augmented generation (RAG). For example, when the prompt words involve specific application scenarios or new devices, the target large model can retrieve relevant historical module schematic netlists or reference circuits from the official datasheets of the devices from the first database in real time, integrating real engineering data into the generation logic to improve the accuracy and feasibility of the inference results.

[0115] The reasoning results include at least one target device's attribute information, the device location corresponding to the target device, and circuit structure information.

[0116] The target device is one or more highly adaptable devices selected from the candidate devices, which are recommended as the devices for the current design task.

[0117] Device ratings are comprehensive scores generated based on multi-dimensional weighted evaluations (such as electrical performance matching, cost, package compatibility, supply stability, and environmental reliability) to quantify the overall suitability of the device under current constraints. For example, the rating can be a numerical value (such as 92 / 100) or a grade (such as "high", "medium", or "low").

[0118] Device location refers to the logical role or topological position of the target device within a functional module, such as "main voltage regulator unit" or "located after the input filter capacitor and before the MCU power supply pin".

[0119] Circuit structure information describes the complete peripheral circuit configuration around the target device, including required passive components (such as input / output capacitors, feedback resistors, pull-up resistors), typical connection methods, protection circuits (such as TVS, fuses), and layout suggestions. Optionally, if a historical circuit matching the target circuit project exists, that historical circuit will be used as the output circuit structure information; if no historical circuit matching the target circuit project exists, the reference design circuit of the target device in the official datasheet will be automatically extracted as the output circuit structure information.

[0120] Following the example above, input the prompt word M1 into the target large model to obtain the recommended result M2: Target device: LDO_003, Device score: 92 points, Device location: Main power supply regulator, directly driving the MCU core power domain, Circuit structure information: Adopting the "Typical Application Circuit" structure on page 8 of the TC1185 datasheet—VIN is connected to a 10μF + 100nF parallel capacitor, VOUT is connected to a 22μF low ESR tantalum capacitor, and the EN pin is pulled up to VIN through a 10kΩ resistor, enabled by default; It is recommended to add an SMAJ5.0A TVS at the VIN input to improve industrial noise immunity.

[0121] After generating the recommendation results, the block diagram assembly layer is returned to the intelligent recommendation layer. (Combined with step S1009) S1009: The intelligent recommendation layer sends recommendation results to the block diagram assembly layer.

[0122] Continuing with the example above, the block diagram assembly layer sends the recommendation result M2 to the intelligent recommendation layer.

[0123] S5: The computing device generates a circuit schematic corresponding to the target circuit project based on the attribute information, device location, and circuit structure information of at least one target device.

[0124] Continue to combine Figure 7 As shown, step S5 includes steps S1010-S1012.

[0125] S1010: The block diagram assembly layer generates a structured block diagram based on the attribute information, device location, and circuit structure information of at least one target device.

[0126] Optionally, the block diagram assembly layer utilizes the attribute information, device location, and circuit structure information of at least one target device to create a structured block diagram representation. The method of generating structured block diagrams is flexible; they can be constructed under the constraints of a preset rule base through user interaction and in response to their editing or selection operations, or they can be automatically generated based on recommended results (including target device, device location, and circuit structure information) under the same rule base constraints.

[0127] In one implementation, rules are constructed by interacting with the user and responding to their editing or selection actions, under the constraints of a preset rule base.

[0128] Figure 9 This is a schematic diagram of a method for generating a structured block diagram provided in an embodiment of this application.

[0129] like Figure 9 As shown, the methods for generating structured block diagrams include: S901: The block diagram assembly layer generates an initial circuit structure diagram based on the target device, device location, and circuit structure information in response to the first editing operation.

[0130] The first editing operation represents the user's selection of a logic function module and the configuration operation of the devices associated with that module. The initial circuit structure diagram serves as a logic schematic, illustrating the connection relationship between the target device corresponding to the logic function module and the peripheral devices.

[0131] Continue to combine Figure 8 As shown in (b), the module configuration area 83 also includes a device selection control 831. The intelligent recommendation layer responds to the user's trigger operation on the device selection control corresponding to the logical function module, displaying the second interactive interface 10 (e.g., ...). Figure 10 (As shown). The second interactive interface 10 is the device recommendation interface, used to present recommendation results to the user. This interface includes a device list area and a device preview area. The device list area is used to display the relevant attribute information, device location, and circuit structure information of each recommended target device. The attribute information may include the target device's code, classification, description, recommendation score, and corresponding symbol file, etc. Among them, the symbol file is used to represent the graphical representation of the target device.

[0132] The device preview area is used to display the package symbol diagram of the selected device in real time for users to visually confirm.

[0133] Following the example above, in response to the user's selection of the logic function module of the signal acquisition circuit and triggering the corresponding device selection control 831, the second interactive interface 10 is displayed. Based on the target device (e.g., LDO_003) selected by the user in the second interactive interface, an initial circuit structure diagram is generated according to the device's location and circuit structure information.

[0134] It is worth noting that at this stage, the circuit connections may not be fully determined or drawn yet, which means that users still have the opportunity to further adjust and optimize the circuit layout. The following will provide a further explanation in conjunction with step S902.

[0135] S902: The block diagram assembly layer responds to the second editing operation by verifying the connection relationship indicated by the connection command based on the interface matching rules and signal connection constraint rules stored in the preset rule base.

[0136] The second editing operation is used to characterize the connection relationships between various logical function modules. Each logical function module contains multiple interface information, and only interfaces of the same type are allowed to connect to each other. The connection instructions are specifically used to indicate the connection relationships between the interfaces of different logical function modules in the initial circuit structure diagram. The verification result includes two scenarios: verification success and verification failure. If the verification is successful, the connection is allowed to be established; if the verification fails, the cause of the conflict is determined according to the rules (such as interface type mismatch, signal direction conflict, etc.), and the corresponding prompt information is displayed to the user in the drawing area to guide the user to make corrections.

[0137] Continuing with the example above, let's combine... Figure 8 As shown in (b), after completing the layout of logical function modules Q1, Q2, Q3, Q4, and Q5, the system receives the second editing operation executed by the user, obtains the corresponding connection instructions, and immediately verifies the requested connection based on the interface matching rules and signal connection constraint rules in the preset rule base. For example, when the user attempts to establish a connection between logical function modules Q1 and Q2, if the interface type does not match or the signal constraint conditions are violated, the verification will fail. The system will then highlight the connection in the drawing area and pop up an error message to clearly inform the user that "the interface types between Q1 and Q2 are incompatible and cannot be connected," thereby guiding the user to adjust the connection scheme. This ensures that the final connection relationships built between these logical function modules all comply with the interface type matching rules and signal constraint requirements.

[0138] S903: When the verification result is used to indicate that the verification has passed, the block diagram assembly layer generates a structured block diagram based on the connection relationship and the target device to be used.

[0139] Following the example above, after the connection relationships of logical function modules Q1, Q2, Q3, Q4, and Q5 have been verified and confirmed to be correct, the system will automatically generate a detailed structured block diagram M3 (e.g., ...) based on the connection methods between these modules and their respective functional attributes. Figure 8 (as shown in (c)).

[0140] In another implementation, the system automatically integrates and generates rules based on the recommended results, under the constraints of a preset rule base.

[0141] Figure 11 This is a schematic diagram of another method for generating structured block diagrams provided in this application embodiment.

[0142] like Figure 11 As shown, the methods for generating structured block diagrams include: S111: In response to the user's selection operation, the block diagram assembly layer determines at least one target device to be used from at least one target device, and obtains the target device location and target circuit structure information corresponding to the target device to be used, so as to generate an initial circuit structure diagram.

[0143] The specific details of step S111 can be found in step S901 above, and will not be repeated here.

[0144] S112: The block diagram assembly layer calls the interface matching rules and signal connection constraint rules stored in the preset rule library to verify the initial circuit structure diagram. If the verification result is used to indicate that the verification is passed, a structured block diagram is generated.

[0145] The specific details of step S112 can be found in step S903 above, and will not be repeated here.

[0146] It should be noted that the relationships between modules can be drawn based on a preset rule base before device recommendations are made, and there is no specific restriction on the order in which this is done.

[0147] S1011: The block diagram assembly layer sends a structured block diagram to the tool output layer.

[0148] Following the example above, the block diagram assembly layer sends the structured block diagram M3 to the tool output layer.

[0149] S1012: The tool output layer generates the circuit schematic corresponding to the target circuit project based on the structured block diagram.

[0150] Figure 12 This is a schematic flowchart of a circuit diagram generation method provided in an embodiment of this application.

[0151] like Figure 12 As shown, step S1012 includes S121-S122.

[0152] S121: The tool output layer verifies the structured block diagram based on preset network topology rules, preset input integrity rules, and preset device library matching rules, and obtains the verification results.

[0153] Among them, network topology rules are used to determine whether the electrical connections in the structured block diagram are connected; input integrity rules are used to determine whether the port signals and attribute information of the target device to be used in the structured block diagram are accurate; and device library matching rules are used to determine whether the parameter information of the target device to be used in the structured block diagram is consistent with the definition in the device library.

[0154] The verification result includes two scenarios: successful verification and verification failure. Successful verification occurs when all connections form a valid path, all device ports are configured correctly, and the device information perfectly matches the library definition. Verification fails if any of the above criteria are not met. For example, if the EN pin of LDO_003 is not connected, the BOOT0 pin of MCU_STM32F4 is floating, or the selected MCU model does not exist in the device library, verification will fail.

[0155] The following explanation will use a successful verification result as an example.

[0156] S122: The tool output layer generates the circuit schematic corresponding to the target circuit project if the verification results are used to characterize the structured block diagram verification.

[0157] Continue to combine Figure 12 As shown, step S122 includes step S1221.

[0158] S1221: When the verification result is used to characterize the structured block diagram verification, the tool output layer responds to the user's tool selection operation in the interactive interface and generates the circuit schematic corresponding to the target circuit project under the target tool based on the structured block diagram.

[0159] The tool selection operation corresponds one-to-one with the target tool. Optionally, the tool selection operation refers to the user selecting the circuit design tool to use (such as Altium Designer, Cadence OrCAD, EAGLE, KiCad, etc.) on the interactive interface.

[0160] Specifically, the tool's output layer automatically analyzes all elements in the structured block diagram, including components and their connections. Based on the specific file format and specifications of the selected circuit design tool, the tool's output layer converts the above analysis results into the corresponding circuit schematic file, i.e., the circuit schematic corresponding to the target circuit project.

[0161] Following the example above, the tool output layer responds to the tool selection operation of the KiCad tool and generates the circuit schematic M4 corresponding to the target circuit project under the target tool.

[0162] In summary, by combining the reasoning capabilities of the target large model with rule constraints to recommend and select components, and avoiding designing circuit schematics from scratch, the accuracy of generated circuit schematics and the compatibility between components can be improved. This reduces design rework caused by improper component selection or unreasonable circuit structure, and improves the quality of generated circuit schematics.

[0163] In contrast to the above embodiments, the first database is pre-built, as will be described below.

[0164] Figure 13 This is a schematic diagram of a method for constructing a first database provided in an embodiment of this application.

[0165] like Figure 13 As shown, the method for constructing the first database includes the following steps: S131: Obtain multiple device and historical circuit schematics.

[0166] Optionally, a large number of electronic devices (such as LDOs, MCUs, capacitors, etc.) and their related historical circuit schematics can be collected from actual engineering designs.

[0167] S132: Based on the electrical and attribute information of the devices, classify multiple devices and generate multiple logical function modules.

[0168] The attribute information includes, but is not limited to, electrical characteristics such as operating voltage range, rated current, and power loss. In addition, it also covers non-electrical characteristics such as the device's application scenario (e.g., industrial control, consumer electronics), package type, and manufacturer.

[0169] For example, the attribute information can be shown in Table 1. ; The device identifier (ID) is a unique identifier used to distinguish different devices. Device type refers to the functional category of the device, such as LDO (Low Dropout Regulator), DC / DC Converter, etc. Parameters (input / output voltage / current) describe the main electrical performance indicators of the device, including input voltage range, output voltage, output current, etc. The rating indicates the reliability or application level of the device, usually represented by letters (e.g., A / B / C / D), with A being high-level and D being low-level. Cost reflects the economic efficiency of the device. Scenario characteristics describe the specific fields and environmental conditions in which the device is applicable. For example: "Industrial Control," "Consumer Electronics," "Automotive Electronics," "MCU Power Supply," etc. Package type refers to the physical package form, commonly such as SOT-23, TO-252, TO-263, etc. Symbol name is the filename of the symbol used in the circuit diagram tool, used for calling during schematic drawing.

[0170] Following the example above, based on the electrical and attribute information of the devices, multiple devices are classified and multiple logical function modules are generated, such as Power Module, Clock Module, Temperature Module, Memory Module, GPIO expansion module, and I2C interface control module.

[0171] S133: Based on historical circuit schematics, extract device information, module schematic netlists, and multi-dimensional scoring tables from historical circuit schematics.

[0172] Following the example above, a structured analysis of the historical circuit schematic is performed to extract three types of key data: first, device information, including device model, package, pin definitions, and electrical parameters supplemented from the datasheet via OCR; second, the module schematic netlist, which is a typical sub-circuit automatically decomposed based on functional boundaries (such as LDO power modules, I...). 2 The system includes three main components: (1) the C interface and its internal connection topology and interface signal definition; (2) a multi-dimensional scoring table covering quantitative indicators such as cost, reliability level, operating temperature range, design friendliness and supply chain stability, to support subsequent intelligent selection and recommendation.

[0173] S134: Construct the first database based on multiple logic function modules, device information, module schematic netlists, and multi-dimensional scoring tables.

[0174] Following the example above, the logical function modules, structured device information, module schematic netlists, and multi-dimensional scoring tables generated in the previous steps are integrated and organized to construct a unified first database.

[0175] Optionally, the database can be physically divided into three interconnected sub-databases: a device information annotation database, a module principle diagram annotation database, and a multi-dimensional scoring rule table. Alternatively, an integrated data model can be used for unified management.

[0176] In summary, by abstracting and solidifying complex circuit design experience into a reusable, evaluable, and configurable "logic functional module" knowledge system, the system achieves a paradigm shift from traditional "device-level" design to "module-level" design. Users no longer need to select and connect individual devices from scratch in subsequent circuit development; instead, they can quickly assemble and combine verified functional modules (such as power management modules and communication interface modules), significantly lowering the technical threshold for circuit design and improving design efficiency.

[0177] Corresponding to the above embodiments, this application also provides a circuit schematic generation apparatus.

[0178] Figure 14 This is a schematic diagram of a circuit schematic generation device provided in an embodiment of this application.

[0179] like Figure 14 As shown, the circuit schematic generation device 1400 includes an interaction module 1401, an acquisition module 1402, a generation module 1403, a reasoning module 1404, a classification module 1405, an extraction module 1406, and a construction module 1407.

[0180] The interaction module 1401 is used to respond to the user's input operation on the target circuit project in the interactive interface and obtain circuit design constraint information. The circuit design constraint information is used to limit the functional module types and their corresponding electrical parameter requirements required for the circuit schematic diagram to be generated. The acquisition module 1402 is used to search the first database based on the circuit design constraint information and obtain at least one candidate device. The generation module 1403 is used to generate corresponding prompt words based on the circuit design constraint information and the attribute information corresponding to the candidate devices. The reasoning module 1404 is used to input the prompt words into the target large model and obtain the reasoning result. The reasoning result includes the attribute information of at least one target device, the device position of the target device, and the circuit structure information. The generation module 1403 is also used to generate the corresponding circuit schematic diagram based on the attribute information, device position, and circuit structure information of at least one target device.

[0181] In one possible implementation, the acquisition module 1402 is used to acquire at least one logical function module and corresponding module configuration information in response to the user's modular configuration operation in the interactive interface, so as to determine the circuit design constraint information; wherein, the logical function module is a functional abstract unit independent of physical devices, used to characterize a specific logical function in the circuit; the module configuration information includes the signal input-output relationship and functional performance parameters of the logical function module.

[0182] In one possible implementation, the acquisition module 1402 is used to obtain a first screening result from a first database based on the functional module type in the circuit design constraint information; wherein the first screening result is used to characterize devices that conform to the same device category corresponding to the functional module type; based on the key electrical parameters in the circuit design constraint information, the key electrical parameters are compared with the specification parameters of each device in the first screening result to obtain a second screening result; wherein the second screening result is used to characterize devices that meet the key electrical parameters; semantic analysis is performed on the circuit design constraint information to extract application scenario identifiers; wherein the target scenario identifier is used to characterize the application scenario category corresponding to the circuit design constraint information; the application scenario identifier is matched with the feature tags of each device in the second screening result to determine at least one candidate device from the second screening result.

[0183] In one possible implementation, the generation module 1403 is used to generate an initial circuit structure diagram in response to a first editing operation, based on the target device, device location, and circuit structure information; and in response to a second editing operation, to verify the connection relationships indicated by the connection instructions based on interface matching rules and signal connection constraint rules stored in a preset rule base, and obtain a verification result. If the verification result indicates that the verification passed, a structured block diagram is generated based on the connection relationships and the target device to be used; and a circuit schematic diagram corresponding to the target circuit item is generated based on the structured block diagram.

[0184] In one possible implementation, the generation module 1403 is used to, in response to the user's selection operation, determine at least one target device to be adopted from at least one target device, and obtain the target device location and target circuit structure information corresponding to the target device to be adopted, so as to generate an initial circuit structure diagram; call the interface matching rules and signal connection constraint rules stored in the preset rule base to verify the initial circuit structure diagram, and generate a structured block diagram if the verification result is used to indicate that the verification is passed; and generate the circuit schematic diagram corresponding to the target circuit project based on the structured block diagram.

[0185] In one possible implementation, the generation module 1403 is used to verify the structured block diagram based on preset network topology rules, preset input integrity rules, and preset device library matching rules. The network topology rules are used to determine whether the electrical connections in the structured block diagram are continuous; the input integrity rules are used to determine whether the port signals and attribute information of the target device to be used in the structured block diagram are accurate; and the device library matching rules are used to determine whether the parameter information of the target device to be used in the structured block diagram is consistent with the definitions in the device library. If the structured block diagram verification passes, a circuit schematic corresponding to the target circuit project is generated.

[0186] In one possible implementation, the generation module 1403 is used to generate the circuit schematic corresponding to the target circuit item under the target tool based on the structured block diagram in response to the user's tool selection operation in the interactive interface; wherein, the tool selection operation corresponds one-to-one with the target tool.

[0187] In one possible implementation, the acquisition module 1402 is further used to acquire multiple devices and historical circuit schematics; the classification module 1405 is used to classify multiple devices based on their corresponding attribute information, generating multiple logical function modules. The extraction module 1406 is used to extract device information, module schematic netlists, and multi-dimensional scoring tables from historical circuit schematics. The construction module 1407 is used to construct a first database based on multiple logical function modules, device information, module schematic netlists, and multi-dimensional scoring tables.

[0188] Figure 15 This is a schematic diagram of a computing device provided in an embodiment of this application.

[0189] like Figure 15 As shown, the computing device 1500 includes a processor 1501 and a memory 1502. Exemplarily, the computing device 1500 may also include a communications interface 1503 and a communications bus 1504.

[0190] The processor 1501, memory 1502, and communication interface 1503 communicate with each other via communication bus 1504. The communication interface 1503 may include a transmitter and receiver for communicating with other devices or communication networks, and may be a wired interface (port), such as a fiber distributed data interface (FDDI) or a gigabit Ethernet interface (GE).

[0191] In some embodiments, the processor 1501 is used to execute program 1505, specifically performing the relevant steps in the above-described embodiment of the circuit schematic generation method. Specifically, program 1505 may include program code, which includes computer-executable instructions.

[0192] For example, processor 1501 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement some embodiments of this application. Computing device 1500 may include one or more processors, which may be processors of the same type, such as one or more CPUs; or processors of different types, such as one or more CPUs and one or more ASICs. The CPU may be a single-core CPU or a multi-core CPU.

[0193] In some embodiments, memory 1502 is used to store program 1505. Memory 1502 may include high-speed random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage device.

[0194] Specifically, program 1505 can be called by processor 1501 to cause computing device 1500 to perform the circuit schematic generation operation.

[0195] Some embodiments of this application provide a computer-readable storage medium storing at least one executable instruction that, when executed on a computing device 1500, causes the computing device 1500 to perform the circuit schematic generation method described in the above embodiments.

[0196] For example, the computer-readable storage medium can be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), magnetic tape, a floppy disk, and an optical data storage device.

[0197] This application provides a chip system for use in a server. The chip system includes one or more interface circuits and one or more processors. The interface circuits and processors are interconnected via lines. The interface circuits are used to receive signals from the server's memory and send signals to the processors, the signals including computer instructions stored in the memory. When the server processor executes the computer instructions, the server performs the various steps in the method for generating the circuit schematic shown in the above-described method embodiments.

[0198] The beneficial effects that the readable storage medium provided in some embodiments of this application can achieve can be referred to the beneficial effects in the corresponding inference task execution method provided above, and will not be repeated here.

[0199] It should be noted that, in this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0200] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the apparatus embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0201] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus or device (such as a computer-based system, a processor-included system or other system that can fetch and execute instructions from, an instruction execution system, apparatus or device).

[0202] For the purposes of this specification, "computer-readable medium" can mean any means that can contain, store, communicate, propagate, or transmit programs for use by or in conjunction with an instruction execution system, apparatus, or device.

[0203] More specific examples of computer-readable media (a non-exhaustive list) include the following: electrical connections having one or more wires (electronic devices), portable computer disks (magnetic devices), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM).

[0204] Furthermore, the computer-readable medium can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory. It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof.

[0205] In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc. The above embodiments are merely specific embodiments of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made based on the technical solutions of this application should be included within the scope of protection of this application.

Claims

1. A method for generating a circuit schematic, characterized in that, include: In response to user input on the target circuit project in the interactive interface, obtain circuit design constraint information; The circuit design constraint information is used to limit the types of functional modules required for the circuit schematic to be generated and their corresponding electrical parameter requirements. Based on the circuit design constraint information, multiple candidate devices in the first database are obtained; Based on the circuit design constraints and the attribute information of the candidate devices, corresponding prompt words are generated. The prompt words are input into the target large model to obtain the reasoning result; wherein, the reasoning result includes the attribute information of at least one target device, the device location corresponding to the target device, and the circuit structure information; Based on the attribute information of the at least one target device, the location of the device, and the circuit structure information, a circuit schematic diagram corresponding to the target circuit project is generated.

2. The method for generating circuit schematics according to claim 1, characterized in that, The process of responding to user input on a target circuit project within the interactive interface and obtaining circuit design constraint information includes: In response to the user's modular configuration operation in the interactive interface, at least one logical function module and its corresponding module configuration information are obtained to determine the circuit design constraint information; wherein, the logical function module is a functional abstract unit independent of physical devices, used to characterize a specific logical function in the circuit; the module configuration information includes the signal input-output relationship and functional performance parameters of the logical function module.

3. The method for generating circuit schematics according to claim 1, characterized in that, Based on the circuit design constraint information, multiple candidate devices are obtained, including: Based on the functional module type in the circuit design constraint information, a first filtering result is obtained from the first database; wherein, the first filtering result is used to characterize devices that conform to the same device category corresponding to the functional module type; Based on the key electrical parameters in the circuit design constraint information, the key electrical parameters are compared with the specification parameters of each device in the first screening result to obtain a second screening result; wherein, the second screening result is used to characterize the devices that meet the key electrical parameters; Semantic analysis is performed on the circuit design constraint information to extract application scenario identifiers; wherein, the application scenario identifiers are used to characterize the application scenario category corresponding to the circuit design constraint information; The application scenario identifier is matched with the feature tags of each device in the second screening result to determine a plurality of candidate devices from the second screening result.

4. The method for generating circuit schematics according to any one of claims 1-3, characterized in that, The step of generating a circuit schematic corresponding to the target circuit project based on the attribute information of the at least one target device, the device location, and the circuit structure information includes: Based on the target device, the device location, and the circuit structure information, an initial circuit structure diagram is generated in response to the first editing operation; In response to the second editing operation, based on the interface matching rules and signal connection constraint rules stored in the preset rule base, the connection relationship indicated by the connection command is verified, and the verification result is obtained; If the verification result indicates that the verification passed, a structured block diagram is generated based on the connection relationship and the target device to be used. Based on the structured block diagram, the circuit schematic corresponding to the target circuit project is generated.

5. The method for generating circuit schematics according to any one of claims 1-3, characterized in that, The step of generating a circuit schematic corresponding to the target circuit project based on the attribute information of the at least one target device, the device location, and the circuit structure information includes: In response to the user's selection operation, at least one target device to be used is determined from the at least one target device, and the target device location and target circuit structure information corresponding to the target device to be used are obtained to generate an initial circuit structure diagram; The interface matching rules and signal connection constraint rules stored in the preset rule base are called to verify the initial circuit structure diagram. If the verification result is used to indicate that the verification is passed, a structured block diagram is generated. Based on the structured block diagram, the circuit schematic corresponding to the target circuit project is generated.

6. The method for generating a circuit schematic according to claim 4 or 5, characterized in that, The step of generating the circuit schematic corresponding to the target circuit project based on the structured block diagram includes: The structured block diagram is validated based on preset network topology rules, preset input integrity rules, and preset device library matching rules. Specifically, the network topology rules determine whether the electrical connections in the structured block diagram are continuous; the input integrity rules determine whether the port signals and attribute information of the target device to be used in the structured block diagram are accurate; and the device library matching rules determine whether the parameter information of the target device to be used in the structured block diagram is consistent with the definitions in the device library. If the structured block diagram passes verification, the circuit schematic corresponding to the target circuit project is generated.

7. The method for generating circuit schematics according to any one of claims 4-6, characterized in that, The generation of the circuit schematic corresponding to the target circuit project includes: In response to the user's tool selection operation in the interactive interface, the circuit schematic corresponding to the target circuit item under the target tool is generated based on the structured block diagram; wherein, the tool selection operation corresponds one-to-one with the target tool.

8. The method for generating circuit schematics according to any one of claims 1-7, characterized in that, Also includes: Acquire schematics of multiple components and historical circuits; Based on the attribute information corresponding to the device, the multiple devices are classified to generate multiple logical function modules; Based on historical circuit schematics, device information, module schematic netlists, and multi-dimensional scoring tables are extracted from the historical circuit schematics. The first database is constructed based on the multiple logical function modules, the device information, the module schematic netlist, and the multi-dimensional scoring table.

9. A circuit schematic generation device, characterized in that, include: The interaction module is used to respond to user input operations on the target circuit project in the interactive interface and obtain circuit design constraint information; The circuit design constraint information is used to limit the types of functional modules required for the circuit schematic to be generated and their corresponding electrical parameter requirements. The acquisition module is used to acquire multiple candidate devices from the first database based on the circuit design constraint information; The generation module is used to generate corresponding prompt words based on the circuit design constraint information and the attribute information of the candidate devices; The reasoning module is used to input the prompt words into the target large model and obtain the reasoning result; wherein, the reasoning result includes the attribute information of at least one target device, the device location corresponding to the target device, and the circuit structure information; The generation module is further configured to generate a corresponding circuit schematic based on the attribute information of the at least one target device, the device location, and the circuit structure information.

10. A computing device, characterized in that, The computing device includes a memory and a processor; the memory and the processor are coupled; the memory is used to store computer program code, the computer program code including computer instructions, which, when executed by the processor, cause the computing device to apply the circuit schematic generation method as described in any one of claims 1 to 8.

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