3D integrated circuit static ir drop predictor based on physically constrained 3D U-Net

Abstract

The application provides a 3D integrated circuit static IR voltage drop predictor based on a physical constraint 3D U-Net, and a construction method thereof comprises the following steps: step one: data acquisition and unified voxelization representation, specifically, a three-dimensional Cartesian coordinate system is established, an integrated circuit is mapped to a three-dimensional voxel grid with a preset resolution, and a multi-channel voxel tensor is generated as an input of the model; step two: a three-dimensional neural network prediction model is constructed; step three: physical mapping from a voxel field to a node field; step four: semi-supervised training based on a physical constraint; and step five: static IR voltage drop inference prediction; the application can quickly evaluate the static IR voltage drop risk under different power network topologies, different through silicon via layouts and different load distributions; can be used for quickly locating high-voltage-drop hot spot areas and high-temperature areas, and providing a basis for power line widening, via insertion, through silicon via position adjustment and thermal design optimization; and can also be used as a rapid screening means before a high-precision simulation tool, and improves analysis efficiency.

Description

Technical Field

[0001] This invention relates to the field of electronic design automation (EDA) technology, and in particular to a 3D integrated circuit static IR voltage drop predictor based on physically constrained 3D U-Net, specifically a method for predicting static IR voltage drop and temperature distribution in power integrity analysis of 3D integrated circuits. Background Technology

[0002] As semiconductor process nodes shrink, power supply voltage decreases while current density increases, leading to increasingly severe power integrity issues. IR drop refers to the voltage loss that occurs when current flows through the parasitic resistance of the power distribution network. It compresses voltage margins, causing timing violations and even functional failures.

[0003] In modern 3D integrated circuits, vertical stacking achieved through through-silicon vias (TSVs) and microbumps introduces complex electrothermal coupling effects. Joule heating raises the metal temperature, which in turn increases resistance and further worsens the IR voltage drop. Traditional analysis methods mainly rely on commercial simulation tools (such as COMSOL or SPICE), which, while highly accurate, involve enormous computational demands and simulation times of several hours, making them unsuitable for the iterative needs of design space exploration.

[0004] Most existing machine learning methods are designed for 2D, lack a unified 2D / 3D modeling framework, and often ignore electrothermal coupling effects. In addition, purely data-driven methods rely heavily on large amounts of expensive labeled data and have poor generalization ability. Summary of the Invention

[0005] This invention proposes a 3D integrated circuit static IR drop predictor based on a physically constrained 3D U-Net. It can be used to predict static IR drop and temperature distribution in 3D integrated circuit power integrity analysis. In the early design space exploration stage of a chip, it can quickly assess the static IR drop risk under different power network topologies, different through-silicon via (TSV) layouts, and different load distributions. In the layout optimization stage, this invention can be used to quickly locate high-voltage drop hotspots and high-temperature regions, providing a basis for power line widening, via insertion, TSV position adjustment, and thermal design optimization. In the pre-approval analysis stage, this invention can serve as a rapid screening method before high-precision simulation tools, improving analysis efficiency.

[0006] The present invention adopts the following technical solution.

[0007] A 3D integrated circuit static IR voltage drop predictor based on physically constrained 3D U-Net, the method for constructing the predictor includes the following steps;

[0008] Step 1: Data Acquisition and Unified Voxelization Characterization. Specifically, this involves: first, acquiring the layout file, netlist file, and process layer information of the integrated circuit to be analyzed. The layout file includes the geometric information of metal interconnect layers, vias, through-silicon vias, microbumps, and chip stacking layers. A unified three-dimensional Cartesian coordinate system is established based on the layout coordinates and inter-layer connectivity. The 2D integrated circuit or 3D stacked integrated circuit is mapped onto a three-dimensional voxel grid of a preset resolution, generating a multi-channel voxel tensor as input to the three-dimensional convolutional neural network model. This multi-channel voxel tensor at least characterizes the geometric distribution of the power distribution network, the distribution of conductive structures, the current load distribution, and the distribution of thermally related structures. In other words, the metal interconnect layers, vias, through-silicon vias, microbumps, and load distribution are mapped onto a unified three-dimensional Cartesian coordinate system and encoded as multi-channel voxel tensors, forming a unified input representation for both two-dimensional and three-dimensional stacking designs.

[0009] Step 2: Construct a 3D neural network prediction model, specifically: Construct a 3D convolutional neural network based on 3D U-Net. The 3D convolutional neural network includes an input layer, a multi-level encoder, a bottleneck layer, a multi-level decoder, and an output layer. The input layer receives multi-channel voxel tensors. The encoder extracts multi-scale spatial features from the multi-channel voxel tensors through multi-level 3D convolutional units and downsampling units to obtain local geometric features, global topological features, and inter-layer interconnection features at different resolutions. The bottleneck layer aggregates low-resolution deep features. The decoder maps the fused features to voltage field prediction results and temperature field prediction results corresponding one-to-one with the 3D voxel grid. That is, through step-by-step upsampling, skip connections, and feature fusion operations, deep semantic features are fused with shallow detail features to restore the spatial resolution corresponding to the input voxel grid. The output layer maps the final fused features to voltage field prediction results and temperature field prediction results corresponding one-to-one with the voxel grid through 3D convolution.

[0010] Step 3: Physical mapping from voxel field to node field: Based on the physical coordinates of the power distribution network nodes in the three-dimensional Cartesian coordinate system, the voxel-level voltage field and voxel-level temperature field output in step S2 are sampled using the voxel-to-node mapping operator to obtain the node-level voltage prediction value and the node-level temperature prediction value. That is, based on the coordinates of the power distribution network nodes, the voxel-level voltage field and voxel-level temperature field are sampled using trilinear interpolation to obtain the node-level voltage prediction value and the node-level temperature prediction value.

[0011] Step 4: Semi-supervised training based on physical constraints: Construct a power distribution network graph based on netlist connections, and train the 3D convolutional neural network by combining supervised loss for labeled samples and physical constraint loss for unlabeled and / or labeled samples. The physical constraint loss includes one or more of Kirchhoff's current law constraint, branch Ohm's law constraint, and heat conduction constraint. That is: establish a power distribution network graph based on netlist connections, and introduce supervised loss, Kirchhoff's current law constraint, branch Ohm's law constraint, and heat conduction constraint in combination during training to perform semi-supervised training on the neural network, so as to improve the prediction accuracy and physical consistency under limited labeled data conditions.

[0012] Step 5: Static IR drop inference prediction: Convert the integrated circuit under test into the multi-channel voxel tensor and input it into the trained three-dimensional convolutional neural network. Output the node-level voltage distribution, temperature distribution and corresponding static IR drop distribution results. That is, after the three-dimensional convolutional neural network model is trained, input the circuit to be analyzed into the model, and the node voltage distribution, temperature distribution and static IR drop distribution can be quickly output, and high-risk hot spot areas can be identified.

[0013] In step one, the multi-channel voxel tensor includes at least one of the following feature channels: power network occupied channel, ground network occupied channel, metal density channel, current load distribution channel, through-silicon via / microbump distribution channel, equivalent resistance characterization channel, and heat source distribution channel; in step one, for 2D integrated circuits, only the actual device layers and interconnect layers are voxel-filled, and the voxel positions in other depth directions are filled with zero or a preset background value, so as to achieve a unified input representation for 2D and 3D designs.

[0014] like Figure 1 As shown, the layout file (such as GDSII / LEF / DEF) and netlist file of the integrated circuit are first read. A three-dimensional Cartesian coordinate system is established, and the chip's metal layers, TSVs, microbumps, and other geometric structures are mapped to this space.

[0015] Define a size as The voxel tensor X. For 2D designs, only a portion of the depth layers are filled; for 3D stacked designs, multiple layers are filled. The input feature channel C_in includes the power planning graph, geometry density graph, etc. This step achieves unified encoding for different topologies.

[0016] In step two, the 3D convolutional neural network based on 3D U-Net includes a multi-level encoder, a bottleneck layer, a multi-level decoder, and an output head, with skip connections between each level of encoder and the corresponding level of decoder. Each level of encoder includes at least two 3D convolutional units and one downsampling unit. The 3D convolutional units are used to perform convolution operations on the voxel neighborhood at the current scale to extract spatial structure features, and the downsampling unit is used to reduce the feature map resolution and expand the receptive field. The bottleneck layer is used to perform global semantic aggregation on the lowest resolution features. Each level of decoder includes at least one upsampling unit, one feature fusion module, and at least one 3D convolutional unit. The sampling unit is used to restore spatial resolution. The feature fusion module is used to concatenate or weightedly fuse the upsampled decoded features with the corresponding level encoder features. The three-dimensional convolution unit is used to generate fused features at the current scale. The spatial attention module is set in the decoding stage and / or after feature fusion to weight and enhance high current density regions, high heat density regions, and the neighborhood of through-silicon vias. The output head uses one or more three-dimensional convolutions to map the final fused features to at least two output channels with the same size as the input voxel grid. The first output channel corresponds to the voltage field prediction result, and the second output channel corresponds to the temperature field prediction result.

[0017] The three-dimensional convolutional unit includes a three-dimensional convolutional layer, a normalization layer, and a non-linear activation layer; the downsampling unit is implemented using a three-dimensional convolution or pooling operation with a stride greater than 1; the upsampling unit is implemented using any one of transposed convolution, interpolation upsampling combined with three-dimensional convolution.

[0018] like Figure 2 As shown, a 3D U-Net network for 3D voxel data is constructed. The network includes an input layer, a multi-level encoder, a bottleneck layer, a multi-level decoder, a spatial attention module, and an output head. The input layer receives data of size [size missing]. The multichannel voxel tensor, in which The number of input feature channels, , , These represent the dimensions of the voxel mesh in the depth, height, and width directions, respectively.

[0019] The encoder consists of a multi-stage cascaded structure, with each stage including at least two 3D convolutional units and one downsampling unit. The 3D convolutional units are used to extract spatially relevant features within the voxel neighborhood at the current resolution, while the downsampling unit is used to reduce the feature map resolution and expand the receptive field, thereby progressively obtaining multi-scale feature representations at different scales.

[0020] The bottleneck layer is positioned between the encoder and decoder to aggregate deep features at the lowest resolution, thereby characterizing the global topology, load distribution, and inter-layer coupling information of the power distribution network.

[0021] The decoder and encoder are configured in a hierarchical manner, with each decoder level including an upsampling unit, skip connections, a feature fusion module, and a 3D convolutional unit. The upsampling unit is used to improve the resolution of the feature map; the skip connections are used to pass the shallow features output by the corresponding encoder level to the decoder; the feature fusion module is used to concatenate, weight, or compress the upsampled deep features and shallow detail features to simultaneously preserve global semantic information and local detail information.

[0022] Furthermore, a spatial attention module is set up during the decoding stage and / or after feature fusion to assign higher weights to high current density regions, high heat density regions, through-silicon via neighborhoods, and microbump neighborhoods to enhance the characterization ability of hotspot regions.

[0023] The output head is located after the last stage decoder, and the output head adopts... The 3D convolution ultimately fuses the feature maps into a two-channel output tensor with the same size as the input voxel grid, where the first channel represents the voltage field prediction result. The second channel shows the predicted temperature field results. This allows us to obtain the voxel-level voltage and temperature distributions corresponding to each point on the voxel grid.

[0024] During training, the network parameters are updated via backpropagation using supervised loss based on labeled samples and physical constraint loss, enabling the network to learn the mapping relationship from multi-channel voxel tensors to voltage and temperature fields.

[0025] Multi-scale spatial feature extraction refers to obtaining feature maps at different spatial resolutions through stepwise downsampling in the encoder, so as to represent local interconnection details, regional power distribution and global stacking topology respectively; feature fusion refers to the joint processing of feature maps at different scales in the decoder through skip connections and feature fusion modules, so as to take into account both global semantic information and local detail information.

[0026] This prediction model is not a general-purpose language model, but rather a 3D U-Net convolutional neural network built for 3D voxel data. The network includes an encoder, a bottleneck layer, and a decoder. The encoder consists of multiple layers of 3D convolutional units and downsampling units to extract spatial structural features at different scales; the bottleneck layer aggregates deep semantic information; the decoder consists of multiple layers of upsampling units and 3D convolutional units to restore spatial resolution and reconstruct voltage and temperature fields. Skip connections are set between the encoder and decoder to preserve shallow geometric details. Furthermore, feature fusion modules are set at the skip connections to fuse global topological information with local fine-grained structural information; a spatial attention module is set in the decoding stage to enhance the response in high-power, high-blocking, high-thermal-density, and via-silicon via neighborhoods. The model output is a dual-channel or multi-channel tensor of the same size as the input voxel mesh, including at least a voltage field prediction channel and a temperature field prediction channel.

[0027] The voxel-to-node mapping operator described in step three is implemented using trilinear interpolation, specifically including: normalizing the physical coordinates of the power distribution network node to the voxel grid coordinate system; determining the eight neighboring voxels around the voxel cell where the node is located; and weighting and summing the predicted values ​​of the eight neighboring voxels according to the relative distance of the node in the three coordinate directions to obtain the voltage and temperature predicted values ​​of the corresponding node.

[0028] The supervision loss in step four is used to constrain the consistency between the predicted node values ​​of the labeled samples and the reference node values. The supervision loss includes voltage error terms and temperature error terms.

[0029] The physical constraint training in step four specifically involves:

[0030] like Figure 3 and Figure 4 As shown, the training process adopts a semi-supervised mode.

[0031] Downsampling mapping: Using algorithms to convert voxel-level output Mapped to specific PDN node coordinates via trilinear interpolation ,get .

[0032] Constructing the PDN graph: Based on the netlist connections, construct a graph G=(V,E) and calculate the temperature-dependent resistance of each edge. .

[0033] Calculate the loss:

[0034] For labeled samples (from COMSOL simulation), calculate the L1 loss between the predicted and true values.

[0035] For all samples (including unlabeled samples), calculate the physical residuals. For example, for node i, calculate the algebraic sum of the currents in all its connected branches; the absolute value of this sum is the KCL residual.

[0036] Backpropagation: Minimize the total loss function and update the network parameters.

[0037] For labeled samples, reference labels are generated by circuit simulation tools or electrothermal co-simulation tools and serve as supervised ground truth for node voltage and node temperature. For unlabeled samples, only their layout structure, netlist connectivity, and material parameters are used for physical constraint training. During training, the samples are first converted into multi-channel voxel tensors and input into the 3D U-Net network to obtain voxel-level voltage and temperature field predictions. Then, the voxel-to-node mapping operator is used to obtain node-level predictions. Subsequently, a power distribution network graph is constructed based on the netlist connectivity, and the supervised loss, Kirchhoff's current law residual loss, branch Ohm's law residual loss, and heat conduction residual loss are jointly calculated. Finally, the network parameters are updated through backpropagation until the loss function converges or the preset number of training rounds is reached.

[0038] In this invention, the training objective function can be expressed as:

[0039]

[0040] in, To monitor losses, The loss is constrained by Kirchhoff's current law. The loss is constrained by Ohm's law for the branch. For heat conduction confinement loss, , , and These are the corresponding weighting coefficients.

[0041] The Kirchhoff's Current Law constraint in step four is used to ensure that the algebraic sum of the inflow and outflow currents at the nodes within the power distribution network satisfies the conservation relationship. The nodal residuals are expressed as:

[0042]

[0043] in, Represents a node The set of adjacent nodes, Indicates a branch Conductivity under temperature-dependent conditions Represents a node The predicted voltage, Represents a node The injected current.

[0044] The Ohm's law constraint in step four is used to ensure that the predicted voltage difference across the branch, the branch current, and the temperature-dependent resistance satisfy the Ohm's law. The branch residual is expressed as:

[0045]

[0046] in, Indicates a branch The estimated current, Indicates a branch Temperature-dependent resistance.

[0047] The resistance under temperature-dependent conditions satisfies the following relationship:

[0048]

[0049] in, Indicates reference temperature The branch resistance below, This represents the temperature coefficient of resistance of the branch material. and These represent the predicted temperatures at the two ends of the branch.

[0050] The physical nature of the static IR voltage drop follows Kirchhoff's Current Law (KCL) and Ohm's Law. For any node in a PDN, the sum of the current flowing in and out should be zero. Where G is the conductance matrix, V is the node voltage, and I is the current source.

[0051] In 3D-ICs, resistance is significantly affected by temperature, following...

[0052] .

[0053] A deep neural network (3D U-Net) is used to approximate the mapping relationship between voltage field V(x,y,z) and temperature field T(x,y,z).

[0054] To ensure that the output of the neural network conforms to the laws of physics, a physical constraint loss function is introduced, specifically:

[0055] KCL loss: The residual that penalizes non-conservation of node current.

[0056] Ohmic loss: penalizes branch voltage drop and inconsistency residuals.

[0057] Thermal smoothing loss: Based on the heat conduction equation, it penalizes non-physical abrupt changes in the temperature field.

[0058] Through this semi-supervised learning approach that combines "data-driven + physics-driven" learning, the model can learn the correct physical mechanisms even when data is scarce.

[0059] The heat conduction constraint in step four is established based on the steady-state heat conduction equation under the three-dimensional stacked structure. The steady-state heat conduction equation satisfied by the temperature field is:

[0060]

[0061] in, This represents the thermal conductivity at different material locations in a three-dimensional stacked structure, where the different materials include at least silicon, metal interconnects, dielectric layers, microbumps, and through-silicon vias. Represents the temperature field. The heat source term per unit volume is represented; by discretizing the steady-state heat conduction equation, a heat conduction residual loss is constructed to constrain the continuity of the predicted temperature field in the vertical stacking direction and the intralayer direction;

[0062] Under electrothermal coupling conditions, the heat source term originates from the Joule heat generated by the current passing through the resistive network, and is expressed as:

[0063]

[0064] in, For branch current, This represents the temperature-dependent resistance. For the discretized 3D voxel mesh, the nodes... The discrete residual of heat conduction at a certain point can be written as:

[0065]

[0066] in, , , These represent the equivalent thermal conductivity in three directions, respectively. , , These represent the dimensions of the voxel mesh in three directions. By minimizing the aforementioned thermal conduction residuals, the intralayer diffusion and interlayer conduction behavior of the predicted temperature field in a multilayer stacked structure can be constrained, making the prediction results more consistent with actual thermal conduction laws.

[0067] The heat source term under temperature-dependent conditions consists of Joule heat in the power distribution network and satisfies:

[0068]

[0069] Or, equivalently, in the form of branch power consumption:

[0070]

[0071] in, For electrical conductivity, For electric potential, For branch current, This is the temperature-dependent resistor for the branch circuit.

[0072] The prediction method of the 3D integrated circuit static IR voltage drop predictor is used in static power integrity analysis scenarios of two-dimensional integrated circuits, 2.5D packaged integrated circuits, 3D stacked circuits with through-silicon via interconnects, and chip-chip heterogeneous circuits to predict chip voltage distribution and hot spot areas during the design implementation stage, layout optimization stage, or pre-approval evaluation stage.

[0073] When using the prediction method of the 3D integrated circuit static IR drop predictor, the trained model is deployed in the EDA design flow, specifically as follows:

[0074] Input: Import the new 3D chip layout to be tested.

[0075] Prediction: The model outputs a thermal map of the voltage and temperature distribution of the entire chip within seconds.

[0076] Analysis: Identify hotspots where the IR drop exceeds the threshold.

[0077] Optimization: Designers adjust the TSV position or widen the power cable based on the prediction results to achieve design optimization.

[0078] The above implementation methods can greatly accelerate the power integrity approval process for 3D integrated circuits while ensuring physical consistency.

[0079] This invention can be used to predict static IR drop and temperature distribution in 3D integrated circuit power integrity analysis. In the early design space exploration stage of the chip, it can quickly assess the static IR drop risk under different power network topologies, different through-silicon via (TSV) layouts, and different load distributions. In the layout optimization stage, this invention can be used to quickly locate high voltage drop hotspots and high temperature regions, providing a basis for power line widening, via insertion, TSV position adjustment, and thermal design optimization. In the pre-approval analysis stage, this invention can serve as a rapid screening method before high-precision simulation tools, improving analysis efficiency.

[0080] The technological innovation of this invention lies in:

[0081] 1. A unified 3D voxel representation was constructed: The layout geometry information and PDN topology of 2D SoC or 3D stacked chips were mapped to a unified 3D voxel mesh, which solved the problem of incompatibility between heterogeneous data formats.

[0082] 2. A customized 3D U-Net model was constructed: A 3DU-Net model was designed that includes a TopFusion module and a spatial attention mechanism, which can effectively capture long-range dependencies and local hotspot features.

[0083] 3. Enables physical mapping from voxels to nodes: A downsampling operator is proposed to accurately map the voxel field output by the neural network back to the nodes of the circuit netlist in order to apply circuit law constraints.

[0084] 4. Enables semi-supervised training with physical constraints: Combines a small amount of labeled data (from the simulator) with a large amount of unlabeled data, and uses KCL (Kirchhoff's Current Law), Ohm's Law and the heat conduction equation as regularization terms for joint training.

[0085] 5. Enables rapid prediction: The voltage and temperature distribution of the entire chip can be directly inferred using a trained model.

[0086] Compared with the prior art, the present invention has the following advantages:

[0087] Extremely fast: Compared to commercial tools like COMSOL, it achieves a speedup of 88-405 times.

[0088] High accuracy: Outperforms existing state-of-the-art methods in worst-case IR drop performance.

[0089] Physical consistency: Taking into account electrothermal coupling and circuit laws, the prediction results conform to physical laws.

[0090] High versatility: The unified voxel representation makes it applicable to both 2D and 3D designs. Attached Figure Description

[0091] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0092] Appendix Figure 1 This is a schematic diagram of the overall data flow and preprocessing process of the prediction method of the predictor in an embodiment of the present invention (the diagram shows the transformation process from the original design file to the voxel tensor).

[0093] Appendix Figure 2 This is a schematic diagram of the customized 3D U-Net network architecture in an embodiment of the present invention;

[0094] Appendix Figure 3 This is a schematic diagram of the voxel-to-node downsampling operator and PDN graph construction in an embodiment of the present invention;

[0095] Appendix Figure 4 This is a schematic diagram of the framework for physical constraint training in an embodiment of the present invention. Detailed Implementation

[0096] As shown in the figure, a 3D integrated circuit static IR voltage drop predictor based on physically constrained 3D U-Net is described. The method for constructing the predictor includes the following steps.

[0097] Step 1: Data Acquisition and Unified Voxelization Characterization. Specifically, this involves: first, acquiring the layout file, netlist file, and process layer information of the integrated circuit to be analyzed. The layout file includes the geometric information of metal interconnect layers, vias, through-silicon vias, microbumps, and chip stacking layers. A unified three-dimensional Cartesian coordinate system is established based on the layout coordinates and inter-layer connectivity. The 2D integrated circuit or 3D stacked integrated circuit is mapped onto a three-dimensional voxel grid of a preset resolution, generating a multi-channel voxel tensor as input to the three-dimensional convolutional neural network model. This multi-channel voxel tensor at least characterizes the geometric distribution of the power distribution network, the distribution of conductive structures, the current load distribution, and the distribution of thermally related structures. In other words, the metal interconnect layers, vias, through-silicon vias, microbumps, and load distribution are mapped onto a unified three-dimensional Cartesian coordinate system and encoded as multi-channel voxel tensors, forming a unified input representation for both two-dimensional and three-dimensional stacking designs.

[0098] Step 2: Construct a 3D neural network prediction model, specifically: Construct a 3D convolutional neural network based on 3D U-Net. The 3D convolutional neural network includes an input layer, a multi-level encoder, a bottleneck layer, a multi-level decoder, and an output layer. The input layer receives multi-channel voxel tensors. The encoder extracts multi-scale spatial features from the multi-channel voxel tensors through multi-level 3D convolutional units and downsampling units to obtain local geometric features, global topological features, and inter-layer interconnection features at different resolutions. The bottleneck layer aggregates low-resolution deep features. The decoder maps the fused features to voltage field prediction results and temperature field prediction results corresponding one-to-one with the 3D voxel grid. That is, through step-by-step upsampling, skip connections, and feature fusion operations, deep semantic features are fused with shallow detail features to restore the spatial resolution corresponding to the input voxel grid. The output layer maps the final fused features to voltage field prediction results and temperature field prediction results corresponding one-to-one with the voxel grid through 3D convolution.

[0099] Step 3: Physical mapping from voxel field to node field: Based on the physical coordinates of the power distribution network nodes in the three-dimensional Cartesian coordinate system, the voxel-level voltage field and voxel-level temperature field output in step S2 are sampled using the voxel-to-node mapping operator to obtain the node-level voltage prediction value and the node-level temperature prediction value. That is, based on the coordinates of the power distribution network nodes, the voxel-level voltage field and voxel-level temperature field are sampled using trilinear interpolation to obtain the node-level voltage prediction value and the node-level temperature prediction value.

[0100] Step 4: Semi-supervised training based on physical constraints: Construct a power distribution network graph based on netlist connections, and train the 3D convolutional neural network by combining supervised loss for labeled samples and physical constraint loss for unlabeled and / or labeled samples. The physical constraint loss includes one or more of Kirchhoff's current law constraint, branch Ohm's law constraint, and heat conduction constraint. That is: establish a power distribution network graph based on netlist connections, and introduce supervised loss, Kirchhoff's current law constraint, branch Ohm's law constraint, and heat conduction constraint in combination during training to perform semi-supervised training on the neural network, so as to improve the prediction accuracy and physical consistency under limited labeled data conditions.

[0101] Step 5: Static IR drop inference prediction: Convert the integrated circuit under test into the multi-channel voxel tensor and input it into the trained three-dimensional convolutional neural network. Output the node-level voltage distribution, temperature distribution and corresponding static IR drop distribution results. That is, after the three-dimensional convolutional neural network model is trained, input the circuit to be analyzed into the model, and the node voltage distribution, temperature distribution and static IR drop distribution can be quickly output, and high-risk hot spot areas can be identified.

[0102] In step one, the multi-channel voxel tensor includes at least one of the following feature channels: power network occupied channel, ground network occupied channel, metal density channel, current load distribution channel, through-silicon via / microbump distribution channel, equivalent resistance characterization channel, and heat source distribution channel; in step one, for 2D integrated circuits, only the actual device layers and interconnect layers are voxel-filled, and the voxel positions in other depth directions are filled with zero or a preset background value, so as to achieve a unified input representation for 2D and 3D designs.

[0103] like Figure 1 As shown, the layout file (such as GDSII / LEF / DEF) and netlist file of the integrated circuit are first read. A three-dimensional Cartesian coordinate system is established, and the chip's metal layers, TSVs, microbumps, and other geometric structures are mapped to this space.

[0104] Define a size as The voxel tensor X. For 2D designs, only a portion of the depth layers are filled; for 3D stacked designs, multiple layers are filled. The input feature channel C_in includes the power planning graph, geometry density graph, etc. This step achieves unified encoding for different topologies.

[0105] In step two, the 3D convolutional neural network based on 3D U-Net includes a multi-level encoder, a bottleneck layer, a multi-level decoder, and an output head, with skip connections between each level of encoder and the corresponding level of decoder. Each level of encoder includes at least two 3D convolutional units and one downsampling unit. The 3D convolutional units are used to perform convolution operations on the voxel neighborhood at the current scale to extract spatial structure features, and the downsampling unit is used to reduce the feature map resolution and expand the receptive field. The bottleneck layer is used to perform global semantic aggregation on the lowest resolution features. Each level of decoder includes at least one upsampling unit, one feature fusion module, and at least one 3D convolutional unit. The sampling unit is used to restore spatial resolution. The feature fusion module is used to concatenate or weightedly fuse the upsampled decoded features with the corresponding level encoder features. The three-dimensional convolution unit is used to generate fused features at the current scale. The spatial attention module is set in the decoding stage and / or after feature fusion to weight and enhance high current density regions, high heat density regions, and the neighborhood of through-silicon vias. The output head uses one or more three-dimensional convolutions to map the final fused features to at least two output channels with the same size as the input voxel grid. The first output channel corresponds to the voltage field prediction result, and the second output channel corresponds to the temperature field prediction result.

[0106] The three-dimensional convolutional unit includes a three-dimensional convolutional layer, a normalization layer, and a non-linear activation layer; the downsampling unit is implemented using a three-dimensional convolution or pooling operation with a stride greater than 1; the upsampling unit is implemented using any one of transposed convolution, interpolation upsampling combined with three-dimensional convolution.

[0107] like Figure 2 As shown, a 3D U-Net network for 3D voxel data is constructed. The network includes an input layer, a multi-level encoder, a bottleneck layer, a multi-level decoder, a spatial attention module, and an output head. The input layer receives data of size [size missing]. The multichannel voxel tensor, in which The number of input feature channels, , , These represent the dimensions of the voxel mesh in the depth, height, and width directions, respectively.

[0108] The encoder consists of a multi-stage cascaded structure, with each stage including at least two 3D convolutional units and one downsampling unit. The 3D convolutional units are used to extract spatially relevant features within the voxel neighborhood at the current resolution, while the downsampling unit is used to reduce the feature map resolution and expand the receptive field, thereby progressively obtaining multi-scale feature representations at different scales.

[0109] The bottleneck layer is positioned between the encoder and decoder to aggregate deep features at the lowest resolution, thereby characterizing the global topology, load distribution, and inter-layer coupling information of the power distribution network.

[0110] The decoder and encoder are configured in a hierarchical manner, with each decoder level including an upsampling unit, skip connections, a feature fusion module, and a 3D convolutional unit. The upsampling unit is used to improve the resolution of the feature map; the skip connections are used to pass the shallow features output by the corresponding encoder level to the decoder; the feature fusion module is used to concatenate, weight, or compress the upsampled deep features and shallow detail features to simultaneously preserve global semantic information and local detail information.

[0111] Furthermore, a spatial attention module is set up during the decoding stage and / or after feature fusion to assign higher weights to high current density regions, high heat density regions, through-silicon via neighborhoods, and microbump neighborhoods to enhance the characterization ability of hotspot regions.

[0112] The output head is located after the last stage decoder, and the output head adopts... The 3D convolution ultimately fuses the feature maps into a two-channel output tensor with the same size as the input voxel grid, where the first channel represents the voltage field prediction result. The second channel shows the predicted temperature field results. This allows us to obtain the voxel-level voltage and temperature distributions corresponding to each point on the voxel grid.

[0113] During training, the network parameters are updated via backpropagation using supervised loss based on labeled samples and physical constraint loss, enabling the network to learn the mapping relationship from multi-channel voxel tensors to voltage and temperature fields.

[0114] Multi-scale spatial feature extraction refers to obtaining feature maps at different spatial resolutions through stepwise downsampling in the encoder, so as to represent local interconnection details, regional power distribution and global stacking topology respectively; feature fusion refers to the joint processing of feature maps at different scales in the decoder through skip connections and feature fusion modules, so as to take into account both global semantic information and local detail information.

[0115] This prediction model is not a general-purpose language model, but rather a 3D U-Net convolutional neural network built for 3D voxel data. The network includes an encoder, a bottleneck layer, and a decoder. The encoder consists of multiple layers of 3D convolutional units and downsampling units to extract spatial structural features at different scales; the bottleneck layer aggregates deep semantic information; the decoder consists of multiple layers of upsampling units and 3D convolutional units to restore spatial resolution and reconstruct voltage and temperature fields. Skip connections are set between the encoder and decoder to preserve shallow geometric details. Furthermore, feature fusion modules are set at the skip connections to fuse global topological information with local fine-grained structural information; a spatial attention module is set in the decoding stage to enhance the response in high-power, high-blocking, high-thermal-density, and via-silicon via neighborhoods. The model output is a dual-channel or multi-channel tensor of the same size as the input voxel mesh, including at least a voltage field prediction channel and a temperature field prediction channel.

[0116] The voxel-to-node mapping operator described in step three is implemented using trilinear interpolation, specifically including: normalizing the physical coordinates of the power distribution network node to the voxel grid coordinate system; determining the eight neighboring voxels around the voxel cell where the node is located; and weighting and summing the predicted values ​​of the eight neighboring voxels according to the relative distance of the node in the three coordinate directions to obtain the voltage and temperature predicted values ​​of the corresponding node.

[0117] The supervision loss in step four is used to constrain the consistency between the predicted node values ​​of the labeled samples and the reference node values. The supervision loss includes voltage error terms and temperature error terms.

[0118] The physical constraint training in step four specifically involves:

[0119] like Figure 3 and Figure 4 As shown, the training process adopts a semi-supervised mode.

[0120] Downsampling mapping: Using algorithms to convert voxel-level output Mapped to specific PDN node coordinates via trilinear interpolation ,get .

[0121] Constructing the PDN graph: Based on the netlist connections, construct a graph G=(V,E) and calculate the temperature-dependent resistance of each edge. .

[0122] Calculate the loss:

[0123] For labeled samples (from COMSOL simulation), calculate the L1 loss between the predicted and true values.

[0124] For all samples (including unlabeled samples), calculate the physical residuals. For example, for node i, calculate the algebraic sum of the currents in all its connected branches; the absolute value of this sum is the KCL residual.

[0125] Backpropagation: Minimize the total loss function and update the network parameters.

[0126] For labeled samples, reference labels are generated by circuit simulation tools or electrothermal co-simulation tools and serve as supervised ground truth for node voltage and node temperature. For unlabeled samples, only their layout structure, netlist connectivity, and material parameters are used for physical constraint training. During training, the samples are first converted into multi-channel voxel tensors and input into the 3D U-Net network to obtain voxel-level voltage and temperature field predictions. Then, the voxel-to-node mapping operator is used to obtain node-level predictions. Subsequently, a power distribution network graph is constructed based on the netlist connectivity, and the supervised loss, Kirchhoff's current law residual loss, branch Ohm's law residual loss, and heat conduction residual loss are jointly calculated. Finally, the network parameters are updated through backpropagation until the loss function converges or the preset number of training rounds is reached.

[0127] In this invention, the training objective function can be expressed as:

[0128]

[0129] in, To monitor losses, The loss is constrained by Kirchhoff's current law. The loss is constrained by Ohm's law for the branch. For heat conduction confinement loss, , , and These are the corresponding weighting coefficients.

[0130] The Kirchhoff's Current Law constraint in step four is used to ensure that the algebraic sum of the inflow and outflow currents at the nodes within the power distribution network satisfies the conservation relationship. The nodal residuals are expressed as:

[0131]

[0132] in, Represents a node The set of adjacent nodes, Indicates a branch Conductivity under temperature-dependent conditions Represents a node The predicted voltage, Represents a node The injected current.

[0133] The Ohm's law constraint in step four is used to ensure that the predicted voltage difference across the branch, the branch current, and the temperature-dependent resistance satisfy the Ohm's law. The branch residual is expressed as:

[0134]

[0135] in, Indicates a branch The estimated current, Indicates a branch Temperature-dependent resistance.

[0136] The resistance under temperature-dependent conditions satisfies the following relationship:

[0137]

[0138] in, Indicates reference temperature The branch resistance below, This represents the temperature coefficient of resistance of the branch material. and These represent the predicted temperatures at the two ends of the branch.

[0139] In this example, the physical nature of the static IR voltage drop follows Kirchhoff's Current Law (KCL) and Ohm's Law. For any node in the PDN, the sum of the current flowing in and out should be zero: Where G is the conductance matrix, V is the node voltage, and I is the current source.

[0140] In 3D-ICs, resistance is significantly affected by temperature, following...

[0141] .

[0142] This example uses a deep neural network (3D U-Net) to approximate the mapping relationship between the voltage field V(x,y,z) and the temperature field T(x,y,z).

[0143] To ensure that the output of the neural network conforms to the laws of physics, this example introduces a physical constraint loss function, specifically:

[0144] KCL loss: The residual that penalizes non-conservation of node current.

[0145] Ohmic loss: penalizes branch voltage drop and inconsistency residuals.

[0146] Thermal smoothing loss: Based on the heat conduction equation, it penalizes non-physical abrupt changes in the temperature field.

[0147] Through this semi-supervised learning approach that combines "data-driven + physics-driven" learning, the model can learn the correct physical mechanisms even when data is scarce.

[0148] The heat conduction constraint in step four is established based on the steady-state heat conduction equation under the three-dimensional stacked structure. The steady-state heat conduction equation satisfied by the temperature field is:

[0149]

[0150] in, This represents the thermal conductivity at different material locations in a three-dimensional stacked structure, where the different materials include at least silicon, metal interconnects, dielectric layers, microbumps, and through-silicon vias. Represents the temperature field. The heat source term per unit volume is represented; by discretizing the steady-state heat conduction equation, a heat conduction residual loss is constructed to constrain the continuity of the predicted temperature field in the vertical stacking direction and the intralayer direction;

[0151] Under electrothermal coupling conditions, the heat source term originates from the Joule heat generated by the current passing through the resistive network, and is expressed as:

[0152]

[0153] in, For branch current, This represents the temperature-dependent resistance. For the discretized 3D voxel mesh, the nodes... The discrete residual of heat conduction at a certain point can be written as:

[0154]

[0155] in, , , These represent the equivalent thermal conductivity in three directions, respectively. , , These represent the dimensions of the voxel mesh in three directions. By minimizing the aforementioned thermal conduction residuals, the intralayer diffusion and interlayer conduction behavior of the predicted temperature field in a multilayer stacked structure can be constrained, making the prediction results more consistent with actual thermal conduction laws.

[0156] The heat source term under temperature-dependent conditions consists of Joule heat in the power distribution network and satisfies:

[0157]

[0158] Or, equivalently, in the form of branch power consumption:

[0159]

[0160] in, For electrical conductivity, For electric potential, For branch current, This is the temperature-dependent resistor for the branch circuit.

[0161] The prediction method of the 3D integrated circuit static IR voltage drop predictor is used in static power integrity analysis scenarios of two-dimensional integrated circuits, 2.5D packaged integrated circuits, 3D stacked circuits with through-silicon via interconnects, and chip-chip heterogeneous circuits to predict chip voltage distribution and hot spot areas during the design implementation stage, layout optimization stage, or pre-approval evaluation stage.

[0162] When using the prediction method of the 3D integrated circuit static IR drop predictor, the trained model is deployed in the EDA design flow, specifically as follows:

[0163] Input: Import the new 3D chip layout to be tested.

[0164] Prediction: The model outputs a thermal map of the voltage and temperature distribution of the entire chip within seconds.

[0165] Analysis: Identify hotspots where the IR drop exceeds the threshold.

[0166] Optimization: Designers adjust the TSV position or widen the power cable based on the prediction results to achieve design optimization.

[0167] The above implementation methods can greatly accelerate the power integrity approval process for 3D integrated circuits while ensuring physical consistency.

[0168] This example provides a method for predicting the static IR voltage drop of 3D integrated circuits based on physically constrained 3D U-Net. The method first acquires the layout file, netlist file, and process layer information of the integrated circuit. It then maps the metal interconnect layers, vias, through-silicon vias, microbumps, and load distribution to a unified three-dimensional Cartesian coordinate system and encodes them as multi-channel voxel tensors, thereby achieving a unified input representation for both two-dimensional and three-dimensional stacked designs.

[0169] Based on this, a 3D convolutional neural network based on 3D U-Net is constructed. The network includes an input layer, a multi-level encoder, a bottleneck layer, a multi-level decoder, and an output layer. The input layer receives multi-channel voxel tensors. The encoder extracts multi-scale spatial features from the input voxel tensors through progressive 3D convolution operations and downsampling to obtain local geometric features, global topological features, and inter-layer interconnection features at different resolutions. The bottleneck layer aggregates deep features. The decoder fuses deep semantic features with shallow detail features through progressive upsampling, skip connections, and feature fusion operations to restore the spatial resolution corresponding to the input voxel grid. The output layer maps the final fused features to voltage and temperature field predictions corresponding one-to-one with the voxel grid through 3D convolution. Subsequently, based on the coordinates of the power distribution network nodes, trilinear interpolation is used to sample the voxel-level voltage and temperature fields, thereby obtaining node-level voltage and temperature predictions.

[0170] Furthermore, a power distribution network graph is established based on the netlist connection relationship. During the training process, supervised loss, Kirchhoff's current law constraint, branch Ohm's law constraint, and heat conduction constraint are jointly introduced to perform semi-supervised training on the neural network, so as to improve the prediction accuracy and physical consistency under the condition of limited labeled data.

[0171] After training, the circuit to be analyzed is input into the model, which can quickly output the node voltage distribution, temperature distribution, and static IR voltage drop distribution, and identify high-risk hotspot areas.

[0172] The main steps in this example are as follows:

[0173] 1. Construct a unified 3D voxel representation: Map the layout geometry and PDN topology of 2D SoC or 3D stacked chips to a unified 3D voxel mesh, solving the problem of incompatibility between heterogeneous data formats.

[0174] 2. Construct a customized 3D U-Net model: Design a 3DU-Net that includes a TopFusion module and a spatial attention mechanism to effectively capture long-range dependencies and local hotspot features.

[0175] 3. Physical mapping from voxels to nodes: A downsampling operator is proposed to accurately map the voxel field output by the neural network back to the nodes of the circuit netlist in order to apply circuit law constraints.

[0176] 4. Semi-supervised training with physical constraints: Combine a small amount of labeled data (from the simulator) with a large amount of unlabeled data, and use Kirchhoff's Current Law (KCL), Ohm's Law, and the heat conduction equation as regularization terms for joint training.

[0177] 5. Rapid prediction: The voltage and temperature distribution of the entire chip can be directly inferred using a trained model.

Claims

1. A 3D integrated circuit static IR drop predictor based on physically constrained 3D U-Net, characterized in that: The method for constructing a predictor includes the following steps; Step 1: Data Acquisition and Unified Voxelization Characterization. Specifically, the layout file, netlist file, and process layer information of the integrated circuit to be analyzed are first acquired. The layout file includes the geometric information of metal interconnect layers, vias, through-silicon vias, microbumps, and chip stacking layers. A unified three-dimensional Cartesian coordinate system is established based on the layout coordinates and inter-layer connection relationships. The 2D integrated circuit or 3D stacked integrated circuit is mapped to a three-dimensional voxel grid of a preset resolution. A multi-channel voxel tensor is generated as the input to the three-dimensional convolutional neural network model. The multi-channel voxel tensor represents the geometric distribution of the power distribution network, the distribution of the conduction structure, the distribution of the current load, and the distribution of the thermally related structure. Step 2: Construct a 3D neural network prediction model, specifically: construct a 3D convolutional neural network based on 3D U-Net. The 3D convolutional neural network includes an input layer, a multi-level encoder, a bottleneck layer, a multi-level decoder, and an output layer. The input layer is used to receive multi-channel voxel tensors. The encoder extracts multi-scale spatial features from the multi-channel voxel tensors through multi-level 3D convolutional units and downsampling units. The bottleneck layer aggregates low-resolution deep features. The decoder maps the fused features into voltage field prediction results and temperature field prediction results that correspond one-to-one with the three-dimensional voxel grid; Step 3: Physical mapping from voxel field to node field: Based on the physical coordinates of the power distribution network nodes in the three-dimensional Cartesian coordinate system, the voxel-to-node mapping operator is used to sample the voxel-level voltage field and voxel-level temperature field output in step S2 to obtain the node-level voltage prediction value and the node-level temperature prediction value. Step 4: Semi-supervised training based on physical constraints: Construct a power distribution network graph based on the netlist connection relationship, and train the three-dimensional convolutional neural network by combining the supervision loss of labeled samples and the physical constraint loss of unlabeled samples and / or labeled samples. The physical constraint loss includes one or more of Kirchhoff's current law constraint, branch Ohm's law constraint and heat conduction constraint. Step 5: Static IR drop inference prediction: Convert the integrated circuit under test into the multi-channel voxel tensor and input it into the trained three-dimensional convolutional neural network to output the node-level voltage distribution, temperature distribution and corresponding static IR drop distribution results.

2. The 3D integrated circuit static IR drop predictor based on physically constrained 3D U-Net according to claim 1, characterized in that: In step one, the multi-channel voxel tensor includes the following characteristic channels: power network occupied channel, ground network occupied channel, metal density channel, current load distribution channel, silicon via / microbump distribution channel, equivalent resistance characterization channel, and heat source distribution channel. In step one, for 2D integrated circuits, only the actual device layers and interconnect layers are voxel-filled, and the voxel positions in other depth directions are filled with zero or a preset background value, so as to achieve a unified input representation for 2D and 3D designs.

3. The 3D integrated circuit static IR drop predictor based on physically constrained 3D U-Net according to claim 1, characterized in that: In step two, the 3D convolutional neural network based on 3D U-Net includes a multi-level encoder, a bottleneck layer, a multi-level decoder, and an output head, with skip connections between each level of encoder and the corresponding level of decoder. Each level of encoder includes two 3D convolutional units and one downsampling unit. The 3D convolutional units perform convolution operations on the voxel neighborhood at the current scale to extract spatial structure features, and the downsampling unit reduces the feature map resolution and expands the receptive field. The bottleneck layer performs global semantic aggregation on the lowest resolution features. Each level of decoder includes at least one upsampling unit, one feature fusion module, and at least one 3D convolutional unit. The unit is used to restore spatial resolution. The feature fusion module is used to concatenate or weightedly fuse the upsampled decoded features with the corresponding level encoder features. The three-dimensional convolution unit is used to generate fused features at the current scale. The spatial attention module is set in the decoding stage and / or after feature fusion to weightedly enhance high current density regions, high heat density regions, and the neighborhood of through-silicon vias. The output head uses one or more three-dimensional convolutions to map the final fused features into at least two output channels with the same size as the input voxel grid. The first output channel corresponds to the voltage field prediction result, and the second output channel corresponds to the temperature field prediction result. The three-dimensional convolutional unit includes a three-dimensional convolutional layer, a normalization layer, and a non-linear activation layer; the downsampling unit uses a three-dimensional convolution or pooling operation with a stride greater than 1; the upsampling unit uses any one of transposed convolution, interpolation upsampling combined with three-dimensional convolution.

4. A 3D integrated circuit static IR drop predictor based on physically constrained 3D U-Net according to claim 1, characterized in that: The voxel-to-node mapping operator described in step three is implemented using trilinear interpolation, specifically including: normalizing the physical coordinates of the power distribution network node to the voxel grid coordinate system; determining the eight neighboring voxels around the voxel cell where the node is located; and weighting and summing the predicted values ​​of the eight neighboring voxels according to the relative distance of the node in the three coordinate directions to obtain the voltage and temperature predicted values ​​of the corresponding node. The supervision loss in step four is used to constrain the consistency between the predicted node values ​​of the labeled samples and the reference node values. The supervision loss includes voltage error terms and temperature error terms.

5. A 3D integrated circuit static IR drop predictor based on physically constrained 3D U-Net according to claim 4, characterized in that: The Kirchhoff's Current Law constraint in step four is used to ensure that the algebraic sum of the inflow and outflow currents at the nodes within the power distribution network satisfies the conservation relationship. The nodal residuals are expressed as: in, Represents a node The set of adjacent nodes, Indicates a branch Conductivity under temperature-dependent conditions Represents a node The predicted voltage, Represents a node The injected current.

6. A 3D integrated circuit static IR drop predictor based on physically constrained 3D U-Net according to claim 4, characterized in that: The Ohm's law constraint in step four is used to ensure that the predicted voltage difference across the branch, the branch current, and the temperature-dependent resistance satisfy the Ohm's law. The branch residual is expressed as: in, Indicates a branch The estimated current, Indicates a branch Temperature-dependent resistance.

7. A 3D integrated circuit static IR drop predictor based on physically constrained 3D U-Net according to claim 5, characterized in that: The resistance under temperature-dependent conditions satisfies the following relationship: in, Indicates reference temperature The branch resistance below, This represents the temperature coefficient of resistance of the branch material. and These represent the predicted temperatures at the two ends of the branch.

8. A 3D integrated circuit static IR drop predictor based on physically constrained 3D U-Net according to claim 4, characterized in that: The heat conduction constraint in step four is established based on the steady-state heat conduction equation under the three-dimensional stacked structure. The steady-state heat conduction equation satisfied by the temperature field is: in, This represents the thermal conductivity at different material locations in a three-dimensional stacked structure, where the different materials include at least silicon, metal interconnects, dielectric layers, microbumps, and through-silicon vias. Represents the temperature field. The term represents the heat source per unit volume; by discretizing the steady-state heat conduction equation, a heat conduction residual loss is constructed to constrain the continuity of the predicted temperature field in the vertical stacking direction and the intralayer direction.

9. A 3D integrated circuit static IR drop predictor based on physically constrained 3D U-Net according to claim 7, characterized in that: The heat source term under temperature-dependent conditions consists of Joule heat in the power distribution network and satisfies: Or, equivalently, in the form of branch power consumption: in, For electrical conductivity, For electric potential, For branch current, This is the temperature-dependent resistor for the branch circuit.

10. A 3D integrated circuit static IR drop predictor based on physically constrained 3D U-Net according to claim 1, characterized in that: The prediction method of the 3D integrated circuit static IR voltage drop predictor is used in static power integrity analysis scenarios of two-dimensional integrated circuits, 2.5D packaged integrated circuits, 3D stacked circuits with through-silicon via interconnects, and chip-chip heterogeneous circuits to predict chip voltage distribution and hot spot areas during the design implementation stage, layout optimization stage, or pre-approval evaluation stage.

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