Layout optimization method, device and equipment for mixed height warehouse unit and product

Abstract

A layout optimization method, device, equipment and product for a mixed-height library unit, a first reference layout of a chip is generated based on at least two types of standard cells with different heights; the standard cells are clustered to obtain a second reference layout and first layout legalization is performed; a critical path group and a first timing slack thereof are obtained based on the first reference layout, a second timing slack of the critical path group is calculated according to a result of the first layout legalization; when the second timing slack of a timing path in the critical path group is less than a first preset value, the weight of the timing path is adjusted and taken as a constraint to re-execute the clustered layout until the third timing slack of each timing path in the critical path group is greater than or equal to the first preset value, the timing path is optimized based on the first timing slack and the third timing slack of the critical path group, and an optimized layout is obtained. The above method aims to avoid timing deterioration without destroying the legalization result when performing layout on the mixed-height library unit.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and specifically to a layout optimization method, apparatus, device, and product for mixed-height library cells. Background Technology

[0002] A mixed-height standard cell library contains at least two types of cells, belonging to two different heights. Higher-height cells have higher frequencies but also higher power consumption and larger areas, while lower-height cells have lower frequencies but lower power consumption and smaller areas. Layout optimization of mixed-height library cells is a digital integrated circuit layout optimization technique that achieves an optimal solution balancing operating frequency, power consumption, and chip area by ensuring compatibility with standard cells of different heights. Summary of the Invention

[0003] The present invention aims to avoid timing deterioration when laying out hybrid height library units without compromising the legalization results.

[0004] According to a first aspect, one embodiment provides a layout optimization method for mixed-height library cells, used to lay out at least two types of standard cells of different heights on a chip, the layout optimization method comprising:

[0005] A first reference layout of the chip is generated based on at least two types of standard cells of different heights; wherein, each type of standard cell includes a standard cell of single height, a standard cell of double height, and a standard cell of multiple heights, and each row in the first reference layout is allocated with at least one type of standard cell;

[0006] Clustering layout steps: Based on the height of the standard units allocated in each row of the first reference layout, the standard units of at least two different heights are clustered to obtain multiple cluster sets. The standard units in each cluster set are allocated to the row corresponding to the centroid of the cluster set to obtain the second reference layout and the first layout legalization is performed to obtain the first layout legalization result.

[0007] Based on the first reference layout, a critical path group and its corresponding first time margin are obtained. The time margin of the critical path group is recalculated according to the first layout legalization result to obtain the second time margin of the critical path group. The critical path group includes multiple time paths, and the time margin of each time path is less than a preset threshold.

[0008] When the second temporal margin of any temporal path in the critical path group is less than the first preset value, the weight of the temporal path is adjusted, and the temporal path with the adjusted weight is used as a constraint to re-execute the clustering layout step until the third temporal margin of each temporal path in the critical path group is greater than or equal to the first preset value. Then, the temporal paths are optimized based on the first and third temporal margins of the critical path group to obtain an optimized layout. The third temporal margin of each temporal path is calculated based on the new layout legitimization result obtained after re-executing the clustering layout step.

[0009] In one embodiment, the timing paths are optimized based on the first and third timing margins of the critical path group to obtain an optimized layout, including:

[0010] For each time-series path in the critical path group, calculate the absolute value of the difference between its first time-series margin and its third time-series margin to obtain the margin difference.

[0011] When the margin difference is greater than the second preset value, the timing path is optimized and the second layout legalization is performed to obtain the second layout legalization result; wherein, the second layout legalization result includes the second total displacement, which is the sum of the absolute values ​​of the displacements of all standard elements when the second layout legalization is performed;

[0012] If the second total displacement is less than the preset first threshold, and the timing margin of each timing path in the critical path group recalculated according to the second layout legalization result is greater than or equal to the preset second threshold, then the layout after optimizing the timing path is taken as the optimized layout.

[0013] In one embodiment, optimizing the timing path and performing a second layout legalization includes:

[0014] Incremental optimization is performed on the timing path, and incremental layout legalization is executed; wherein, the incremental optimization includes optimization methods such as size optimization, cell decomposition, and small-scale resynthesis.

[0015] In one embodiment, the step of clustering the at least two types of standard cells with different heights based on the height of the standard cells allocated in each row of the first reference layout to obtain multiple cluster sets includes:

[0016] The height type of a row is determined based on the proportion of standard units of different heights allocated to each row in the first reference layout.

[0017] Based on the height of each standard unit, at least two types of standard units of different heights are grouped to obtain multiple unit groups; wherein, each unit group contains standard units of one height, and each type of standard unit is any one of standard units of single height, double height, and multiple height;

[0018] Calculate the centroid of each unit group, and assign the multiple unit groups to different rows according to the height type of each row and the centroid of each unit group. The standard units assigned to each row constitute a cluster set, so as to obtain multiple cluster sets.

[0019] In one embodiment, the first layout legalization result includes a first total displacement, which is the sum of the absolute values ​​of the displacements of all standard cells when performing the first layout legalization; the layout optimization method further includes:

[0020] When the first total displacement is greater than the third preset value, calculate the absolute value of the difference between the first total displacement and the third preset value;

[0021] The weight of the total displacement is adjusted according to the absolute value of the difference and the pre-constructed correspondence table of circuit delay and displacement. The adjusted weight of the total displacement is used as a constraint to re-execute the clustering layout step until the first total displacement is less than or equal to the third preset value.

[0022] In one embodiment, when the first total displacement is greater than a third preset value, the layout optimization method further includes:

[0023] For a standard cell that is N times higher, add a constraint of N consecutive neighboring rows. Based on the added constraint of N consecutive neighboring rows, re-execute the clustering layout step until the first total displacement is less than or equal to the third preset value; where N is a positive integer greater than or equal to 2.

[0024] In one embodiment, for standard cells with double the height and standard cells with multiple times the height, when the second timing margin of any timing path in the critical path group is less than a first preset value, the layout optimization method further includes:

[0025] Reduce the displacement of the load unit in the timing path, or optimize the size of the drive unit in the timing path to increase the drive strength of the drive unit.

[0026] According to a second aspect, one embodiment provides a layout optimization apparatus for mixed-height library cells, used to lay out at least two types of standard cells of different heights on a chip, including:

[0027] A layout generation module is used to generate a first reference layout of a chip based on at least two types of standard cells of different heights; wherein, each type of standard cell includes a standard cell of single height, a standard cell of double height, and a standard cell of multiple heights, and each row in the first reference layout is assigned at least one type of standard cell;

[0028] The clustering layout module is used to cluster the standard units of at least two different heights according to the height of the standard units allocated in each row of the first reference layout, to obtain multiple cluster sets, to allocate the standard units in each cluster set to the row corresponding to the centroid of the cluster set, to obtain the second reference layout and to perform the first layout legalization to obtain the first layout legalization result.

[0029] The margin calculation module is used to obtain the critical path group and its corresponding first temporal margin based on the first reference layout, and recalculate the temporal margin of the critical path group according to the first layout legalization result to obtain the second temporal margin of the critical path group; wherein, the critical path group includes multiple temporal paths, and the temporal margin of each temporal path is less than a preset threshold.

[0030] The layout optimization module is used to adjust the weight of any time-series path when the second time-series margin of any time-series path in the critical path group is less than the first preset value, and use the time-series path with adjusted weight as a constraint to re-execute the clustering layout step until the third time-series margin of each time-series path in the critical path group is greater than or equal to the first preset value. Then, the time-series paths are optimized based on the first time-series margin and the third time-series margin of the critical path group to obtain an optimized layout. The third time-series margin of each time-series path is calculated based on the new layout legitimization result obtained after re-executing the clustering layout step.

[0031] According to a third aspect, one embodiment provides a layout optimization device for hybrid height library units, comprising:

[0032] Memory, used to store programs;

[0033] A processor for implementing the layout optimization method by executing a program stored in the memory.

[0034] According to a fourth aspect, one embodiment provides a computer program product including a computer program and / or instructions that, when executed by a processor, implement the layout optimization method.

[0035] According to the above embodiments of the layout optimization method, apparatus, device, and computer program product for mixed-height library cells, a first reference layout of the chip is generated based on at least two types of standard cells with different heights. The standard cells are clustered based on the first reference layout to obtain a second reference layout. Upon obtaining the second reference layout, a first layout legalization is performed to obtain the first layout legalization result. A first timing margin for the critical path group is obtained based on the first reference layout. The timing margin for the critical path group is recalculated based on the first layout legalization result to obtain a second timing margin for the critical path group. When the second timing margin of any timing path in the critical path group is less than a first preset value, the weight of that timing path is adjusted, and the adjusted timing path is used as a constraint to re-execute the clustering layout step until the third timing margin of each timing path in the critical path group is greater than or equal to the first preset value. For timing degradation phenomena remaining in the layout legalization step, the clustering layout step is re-executed by adjusting the weights of the timing paths without destroying the first layout legalization result, thereby solving the timing degradation problem. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of the layout of a hybrid height standard unit in one embodiment;

[0037] Figure 2 This is a schematic diagram illustrating the power / ground network requirements of a multi-height standard cell in one embodiment.

[0038] Figure 3 This is a flowchart of the layout optimization method for hybrid height library units in the embodiments of this application;

[0039] Figure 4 This is a flowchart illustrating how timing paths are optimized based on the first and third timing margins of the critical path group in one embodiment to obtain an optimized layout.

[0040] Figure 5 A flowchart of an embodiment showing how to cluster at least two types of standard cells with different heights based on the height of the standard cells allocated in each row of a first reference layout to obtain multiple cluster sets;

[0041] Figure 6 This is a flowchart of a layout optimization method for hybrid height library units in one embodiment;

[0042] Figure 7 This is a schematic diagram of the layout optimization device for a hybrid height library unit in one embodiment. Detailed Implementation

[0043] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of the invention. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to the present invention are not shown or described in the specification. This is to avoid obscuring the core parts of the invention with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0044] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0045] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this invention, unless otherwise specified, include both direct and indirect connections (linkages).

[0046] In integrated circuit design, the number of routing channels per standard row steadily decreases with each new technology node, for example, from 10 to 7.5. For complex circuit elements, such as flip-flops and multiplexers, it becomes increasingly difficult to design current circuits using methods previously used for standard cells while meeting performance and routing requirements. Therefore, the design of advanced technology nodes has begun to enable multi-row-height standard cells for such complex circuit elements. Furthermore, multi-bit flip-flops are becoming increasingly important for reducing power consumption and area, which also typically leads to the introduction of multi-row-height cells in designs. To further reduce design area, power consumption, and cost, placement density can sometimes reach 90%, making it difficult to address local routing congestion without proper placement detail. Traditional placement legalization algorithms typically assign cells to placement rows and perform row-based algorithms to eliminate overlaps. The presence of multi-row-height cells disrupts the independence of cells on a single row, making placement placement legalization even more challenging. These emerging challenges make detailed placement and layout legalization crucial to support multi-row-height cells and produce non-overlapping placement solutions with optimized wireless length and congestion reduction.

[0047] The use of multi-row height cells introduces special constraints on the alignment of power lines, such as... Figure 1 As shown, Figure 1 This is an example layout of mixed-height standard cells, where two cells occupy odd-numbered rows and five cells occupy even-numbered rows. Cells in even-numbered rows must be placed in alternate rows because they have power (VDD) and ground (GND) rails at the top and bottom, respectively, while the GND / VDD rail is in the middle. For example, the bottom of cell a must be aligned with the row with the bottom VDD rail, and the bottom of cell c must be aligned with the row with the bottom GND rail. However, cells occupying odd-numbered rows do not have this constraint because cell flipping allows for fixed alignment.

[0048] Previous research has shown that in 28nm LP wafer foundry technology, attempting to use mixed non-integer standard cell groups (12T and 8T) can achieve a 25% reduction in area compared to using pure 12T cells while maintaining the same operating frequency, and a 20% performance improvement compared to pure 8T cells while maintaining a similar total cell area. In this work, 8T and 12T cells are finely planned in a checkerboard-shaped rectangular grid, with isolation cells added at each boundary. The overall process is as follows:

[0049] First, analyze the Register Transfer Level (RTL) and timing constraints of the given input design, and synthesize them with free files at the height of all available cells, which have been provided to the logic synthesis tool;

[0050] 2. To resolve the loop of mutual determination between layout and cell height selection, the Library Exchange Format (LEF) file for standard cells was modified to ensure all cells have the same height—the minimum available cell height—while preserving the original area of ​​each cell. Then, commercial placement tools were used to "freely" place circuit cells of uniform height. In other words, based on a composite netlist containing various cell heights, layout planning was performed using the modified LEF file to ensure all cell rows have the same height (i.e., the minimum available cell height). This was done while maintaining the original area of ​​each standard cell.

[0051] 3. Use commercial tools to perform placement and post-placement optimization;

[0052] IV. The placement solution from the previous step is legalized under a checkerboard layout by the following methods: 1) cell displacement (i.e., placement perturbation) and 2) swapping cells of different heights (i.e., gate size). The placement solution is legal until each cell instance is placed in an area with the same height attribute;

[0053] 5. Once all placement schemes are valid, update the layout, insert isolation cells, and update timing information. Therefore, the space occupied by isolation cells needs to be included in the total circuit cell area overhead.

[0054] VI. When the timing information meets the requirements, the original standard element LEF file is used to map the elements to the element rows of the updated planar diagram;

[0055] 7. Finally, the clock tree is synthesized and the wiring is designed.

[0056] This layout optimization ensures that the optimization algorithm makes the correct trade-off between timing, power, and area. While modifying the cell height, the original area of ​​each standard cell must remain unchanged. In this way, circuit cells on the critical path will have a standard (minimum) height and a significantly larger width, while circuit cells on non-critical paths will generally be narrower. After mapping the cells to the cell rows of the updated planar diagram using the original standard cell LEF file, a validation step is required because new invalid regions may be generated by the circuit cells.

[0057] Existing research has shown that taller cells offer higher pin accessibility, higher drive strength, and shorter latency. Conversely, smaller heights result in lower area, pin capacitance, and power consumption. Such non-integer multiple-cell-height (NIMCH) designs must satisfy additional layout constraints that existing toolflows cannot handle well. A row-based NIMCH placement algorithm is proposed, comprising: (1) a k-means-based clustering method to assign a height to each row to define a region of a specific cell height; and (2) a legalization method to move cells to satisfy NIMCH constraints. Experimental results show that this method significantly reduces average wiring length and average total power consumption compared to existing methods. It is suggested that, based on the initial layout results, the block region be divided into rows of specific cell heights. Then, a clustering algorithm is used to assign a specific height to each row. Compared to methods based on checkerboard distributions, the row-based method reduces wiring length and power consumption. However, there is a significant difference between the initial placement results and the final layout legalization solution. This means that wire lengths, carefully optimized in the global layout, can be significantly disrupted during final legalization. The workflow includes:

[0058] First, analyze the RTL and time constraints of the given input design and synthesize them with a free file of all available cell heights;

[0059] Second, by modifying the library exchange format file of the standard cells, all cells are made to have the same height. This height is obtained by weighting the height values ​​of all cells according to their area occupied by the chip region. At the same time, the width of the standard cells is modified to maintain the original area of ​​each cell. Then, commercial placement tools are used to "freely" place circuit cells of uniform height.

[0060] 3. After obtaining the initial layout, based on the distribution of various cell height values ​​in the layout result, analyze which type the majority of standard cells in each standard cell row belong to, and then assign a height to this row. Considering factors such as manufacturability and N-well sharing, the height allocation needs to follow the constraints that "there must be at least two cell rows in each region" and "there must be an even number of cell rows in each region at a specific cell height";

[0061] Fourth, the placement result is validated by moving standard circuit cells to rows with the same height while minimizing cell displacement. The standard cell width used here is the original width. In this step, a detailed height allocation is performed on each row to define the region for a specific cell height. To reduce cell movement, cost functions have been reported to evaluate the score of each row.

[0062] 5. If the placement result is infeasible, some parameters will be adjusted and a new iteration will be performed. If there is not enough space to accommodate a few cells, the threshold parameters can be adjusted using the cost function adjustment algorithm. Furthermore, if an infeasible solution occurs because the cell movement distance exceeds the maximum displacement constraint, the height of the few cells will be increased by one, and then the process will return to step 3.

[0063] VI. Finally, the cost of the circuit breaker unit is modeled by updating the layout diagram through space insertion. In the preceding steps, rows and cells were converted to the same height value. In this stage, each row is restored to its original height based on the row allocation result, and each cell is also restored to its original height and width. Since the original width was used in the validation stage, it is now safe to shrink each cell back to its original height and width without any overlap. For each pair of adjacent rows with different heights, additional space is inserted to simulate the cost of the circuit breaker unit.

[0064] In the aforementioned techniques, optimization primarily focuses on bus length and displacement, with timing relaxation receiving lower priority. Furthermore, adhering to the rule of at least two cell rows only applies to single-height circuit cells. When dealing with multi-height cells, it's impossible to simultaneously and correctly place standard circuit cells externally mounted to NWOUT-N-wells and internally mounted to NWIN-N-wells due to positional constraints imposed by the PG network layout; see details below. Figure 2 , Figure 2 This diagram illustrates the power / ground network requirements for a multi-height standard unit.

[0065] In the optimization process for hybrid height library cells, the timing relaxation values ​​of different timing paths vary under their respective clock frequency constraints, resulting in different criticality weights for these circuit cells in the placement and legalization steps. For circuit cells with smaller relaxation values, even a small positional change can affect the timing bottleneck of the entire design, leading to a deterioration of the design's upper frequency limit. Conversely, a unit with relatively relaxed timing values ​​has greater flexibility in its position selection during placement and legalization. When a design has a high area utilization rate, such as above 60%, the utilization rate of the initial placement result is also close to or higher than this value. In the above situation, it is often difficult to meet the positional requirements of every standard circuit cell in the subsequent planning of row height and legalization steps. At this time, it is necessary to consider the timing relaxation of standard cells with the same positional requirements and prioritize meeting the requirements of units with smaller timing relaxation. From another perspective, the changes and increases in interconnect lengths caused by unmet positional requirements can turn some non-critical path circuit cells into critical path cells. Therefore, it is necessary to establish a table of correspondences between circuit delay degradation and displacement, and then quantitatively estimate the requirements of units with smaller relaxation values. Experiments showed that the above work achieves better results when executed iteratively. After the goal is achieved, the iteration is completed. Due to the inherent displacement and deformation aimed at restoring the original cell height, the timing of each circuit cell will be affected to varying degrees. After completing the iteration, this application adds an iterative timing optimization step to obtain better results. Addressing the power / ground line issues reported in existing research regarding potential problems in two cell rows, this application adds an additional cell row optimization step in the iteration of planning standard cell rows and legalization. When there are some standard cells that are several times taller locally, the local row pattern is optimized so that these cells can be legalized.

[0066] To address the aforementioned issues, this application proposes a layout optimization method for mixed-height standard cells, used to lay out at least two types of standard cells with different heights on a chip. In the layout optimization method, a first reference layout of the chip is generated based on at least two types of standard cells with different heights; wherein, each type of standard cell includes single-height standard cells, double-height standard cells, and multi-height standard cells, and each row in the first reference layout is allocated with at least one type of standard cell; a clustering layout step: the standard cells of at least two different heights are clustered according to the height of the standard cells allocated in each row of the first reference layout, resulting in multiple cluster sets; the standard cells in each cluster set are assigned to the row corresponding to the centroid of that cluster set, resulting in a second reference layout, and the first layout is validated to obtain the first layout validation result; based on the first reference layout, a second reference layout is obtained. A critical path group and its corresponding first temporal margin are taken. The temporal margin of the critical path group is recalculated based on the first layout legalization result to obtain the second temporal margin of the critical path group. The critical path group includes multiple temporal paths, and the temporal margin of each temporal path is less than a preset threshold. When the second temporal margin of any temporal path in the critical path group is less than the first preset value, the weight of the temporal path is adjusted, and the temporal path with the adjusted weight is used as a constraint to re-execute the clustering layout step until the third temporal margin of each temporal path in the critical path group is greater than or equal to the first preset value. Then, the temporal paths are optimized based on the first and third temporal margins of the critical path group to obtain the optimized layout. The third temporal margin of each temporal path is calculated based on the new layout legalization result obtained after re-executing the clustering layout step.

[0067] The layout optimization method for mixed-height library cells provided in this application is described below with reference to the accompanying drawings. This layout optimization method for mixed-height library cells is used to lay out at least two types of standard cells with different heights on a chip.

[0068] Figure 3 A flowchart of a layout optimization method for hybrid height library units provided in an embodiment of this application is shown, which will be described in detail below.

[0069] Step S10: Generate a first reference layout for the chip based on at least two types of standard cells of different heights.

[0070] In some embodiments, a process-independent logic netlist recognizable by a synthesis tool is generated based on a file containing the RTL and timing constraints of a given input design. The process-independent logic netlist is mapped to a specific process standard cell netlist using a process logic library containing timing, area, and power consumption information for all available standard cells. Timing optimization iterations are performed based on the mapped netlist and timing constraints to generate a final gate-level netlist that meets setup and hold time requirements. This netlist is then combined with the Liberty file to generate the first reference layout of the chip. Each type of standard cell height includes single-height, double-height, and multi-height standard cells, and each row in the first reference layout is allocated at least one type of standard cell height.

[0071] For example, for a standard unit of height 7T, the height of a single-height standard unit is 7T, and the height of a double-height standard unit is 14T. For a standard unit of height 9T, the height of a single-height standard unit is 9T, and the height of a double-height standard unit is 18T, and so on.

[0072] Step S20: Clustering layout step: Based on the height of the standard units allocated in each row of the first reference layout, cluster at least two types of standard units with different heights to obtain multiple cluster sets. Assign the standard units in each cluster set to the row corresponding to the centroid of the cluster set to obtain the second reference layout and perform the first layout legalization to obtain the first layout legalization result.

[0073] In some embodiments, the proportion of standard units of different heights in each row of the first reference layout to the total number of standard units in that row is calculated. When calculating the number of standard units of a certain height, the number of standard units of single height, double height, and multiple heights in that row needs to be considered. The proportions of standard units of different heights are compared, and the height type of the category with the largest proportion is taken as the height type of that row. Clustering is performed based on the height type of each row and the physical centroid of the standard units under each height type. The optimization objective during clustering is to minimize the total displacement. Constraints during the clustering process include the unit density of each row, evaluating whether a preset utilization rate is exceeded, and also including the legalization requirements for locally multiple height units.

[0074] In some embodiments, during the first layout validation, each standard cell is placed on the nearest row that matches its own height type. To achieve better timing and bus length, when multiple candidate standard cells exist near a target location, their timing margins and offset values ​​are evaluated. Standard cells with lower timing margins and lower offset values ​​are given higher priority. Layout validation is repeatedly attempted until all standard cells are placed in valid positions within the rows.

[0075] For example, in the first row of the first reference layout, there are five standard cells in sequence: 7T, 7T, 14T, 9T, and 7T. Considering that for a standard cell of height 7T, the height of a single-height standard cell is 7T and the height of a double-height standard cell is 14T, there are four standard cells in the first row with height 7T, while there is only one standard cell with height 9T. Therefore, the height type specified in the first row is 7T.

[0076] Step S30: Obtain the critical path group and its corresponding first time margin based on the first reference layout, and recalculate the time margin of the critical path group according to the first layout legalization result to obtain the second time margin of the critical path group.

[0077] In some embodiments, the critical path group includes multiple timing paths, each with a timing margin less than a preset threshold. A first timing margin for the critical path group is obtained based on the positions of standard cells determined in the first reference layout. After obtaining the first layout legalization result, the result is checked. Since performing layout legalization itself changes the positions and connection lengths of the standard cells, the timing margin of the critical path group needs to be recalculated based on the first layout legalization result to obtain a second timing margin for the critical path group.

[0078] Step S40: Determine whether there is any timing margin less than the first preset value for any timing path in the critical path group.

[0079] When the second time margin of any time path in the critical path group is less than the first preset value, step S50 is executed: the weight of the time path is adjusted, and the time path with the adjusted weight is used as a constraint to re-execute the clustering layout step until the third time margin of each time path in the critical path group is greater than or equal to the first preset value. Then, the time path is optimized based on the first time margin and the third time margin of the critical path group to obtain the optimized layout.

[0080] In some embodiments, when the second time margin of any time path in the critical path group is less than the first preset value, the weight of the time path needs to be adjusted, for example, by increasing the weight of the time path, so that the time path can be given priority consideration when the clustering layout step is re-executed. After the clustering layout step is re-executed, a new layout legalization result will be obtained. Based on the new layout legalization result, the third time margin of each time path can be recalculated, and it can be further determined whether the third time margin of each time path is greater than or equal to the first preset value, until the third time margin of each time path in the critical path group is greater than or equal to the first preset value. At this time, the time margin has reached the preset requirement.

[0081] In some embodiments, the timing paths are optimized based on the first and third timing margins of the critical path group to obtain an optimized layout. This optimization is incremental, which can further optimize some critical paths in the critical path group and solve the timing deterioration problem as much as possible.

[0082] For example, the first preset value is -10ns.

[0083] According to the layout optimization method for mixed-height library cells in the above embodiments, a first reference layout of the chip is generated based on at least two types of standard cells with different heights. The standard cells are clustered based on the first reference layout to obtain a second reference layout. When the second reference layout is obtained, a first layout legalization is performed to obtain the first layout legalization result. A first timing margin for the critical path group is obtained based on the first reference layout. The timing margin for the critical path group is recalculated based on the first layout legalization result to obtain a second timing margin for the critical path group. When the second timing margin of any timing path in the critical path group is less than a first preset value, the weight of that timing path is adjusted, and the timing path with the adjusted weight is used as a constraint to re-execute the clustering layout step until the third timing margin of each timing path in the critical path group is greater than or equal to the first preset value. For timing degradation phenomena remaining in the layout legalization step, the clustering layout step is re-executed by adjusting the weight of the timing paths without destroying the first layout legalization result, thereby solving the timing degradation problem.

[0084] Please refer to Figure 4 In some embodiments, step S50: optimize the timing path based on the first timing margin and the third timing margin of the critical path group to obtain the optimized layout, including steps S51 to S55, which are described in detail below.

[0085] Step S51: For each time-series path in the critical path group, calculate the absolute value of the difference between its first time-series margin and its third time-series margin to obtain the margin difference.

[0086] Step S52: Determine whether the margin difference is greater than the second preset value.

[0087] When the margin difference is greater than the second preset value, step S53 is executed: the timing path is optimized and the second layout legalization is performed to obtain the second layout legalization result.

[0088] In some embodiments, the second layout legalization result includes a second total displacement, which is the sum of the absolute values ​​of the displacements of all standard elements when performing the second layout legalization.

[0089] Step S54: Determine whether the second total displacement is less than the preset first threshold, and whether the timing margin of each timing path in the critical path group recalculated based on the second layout legalization result is greater than or equal to the preset second threshold.

[0090] When the second total displacement is less than the preset first threshold, and the timing margin of each timing path in the critical path group recalculated according to the second layout legalization result is greater than or equal to the preset second threshold, step S55 is executed: the layout after optimizing the timing path is taken as the optimized layout.

[0091] In some embodiments, optimizing the timing path and performing a second layout legitimization includes:

[0092] Incremental optimization is performed on the timing path, and incremental layout legalization is executed.

[0093] In some embodiments, incremental optimization includes optimization methods such as size optimization, cell decomposition, and small-scale resynthesis. By incrementally optimizing timing paths with margin differences greater than a second preset value, timing can be further optimized to address the timing deterioration problem left over from the legitimization process.

[0094] Please refer to Figure 5 In some embodiments, step S20: clustering at least two types of standard cells with different heights according to the height of the standard cells allocated in each row of the first reference layout to obtain multiple cluster sets, including steps S21 to S23, which are described in detail below.

[0095] Step 21: Determine the height type of the row based on the proportion of standard cells of different heights allocated to each row in the first reference layout.

[0096] In some embodiments, the height type of each row is determined with reference to the specific implementation in step S20, which will not be elaborated here.

[0097] Step 22: Group at least two types of standard cells with different heights based on the height of each standard cell to obtain multiple cell groups.

[0098] In some embodiments, standard units are grouped according to different types of single height, double height, and multiple height to obtain multiple unit groups. Each unit group contains standard units of one height, and the standard units of each height are any one of the single height, double height, and multiple height standard units.

[0099] For example, one unit group contains standard units with heights of 7T, 14T, and 21T, while another unit group contains standard units with heights of 9T, 18T, and 27T.

[0100] Step 23: Calculate the centroid of each unit group. Based on the height type of each row and the centroid of each unit group, assign multiple unit groups to different rows. The standard units assigned to each row constitute a cluster set, resulting in multiple cluster sets.

[0101] In some embodiments, for each cell group, its geometric centroid is calculated, and then, based on the height type of each row, rows whose centroids are spatially adjacent and whose heights match are selected as the rows that the cell group can be assigned to.

[0102] Please refer to Figure 6 In some embodiments, the first layout legalization result includes a first total displacement, which is the sum of the absolute values ​​of the displacements of all standard cells when performing the first layout legalization; the layout optimization method also includes steps S60 to S80, which are described in detail below.

[0103] Step S60: Determine whether the first total displacement is greater than the third preset value.

[0104] When the first total displacement is greater than the third preset value, step S70 is executed: calculate the absolute value of the difference between the first total displacement and the third preset value.

[0105] For example, the third preset value is 10000um.

[0106] Step S80: Adjust the weight of the total displacement according to the absolute value of the difference and the pre-built correspondence table of circuit delay and displacement, and use the adjusted weight of the total displacement as a constraint to re-execute the clustering layout step until the first total displacement is less than or equal to the third preset value.

[0107] In some embodiments, the weight of total displacement is increased, and when the clustering layout step is re-executed in a subsequent step, the total displacement metric will be given more attention, thus increasing the priority of total displacement and reducing the focus on the timing margin of timing paths.

[0108] In some embodiments, when the first total displacement is greater than a third preset value, the layout optimization method further includes:

[0109] For standard cells that are N times higher, add N consecutive rows of neighboring constraints. Based on the added N consecutive rows of neighboring constraints, re-execute the clustering layout steps until the first total displacement is less than or equal to the third preset value.

[0110] Where N is a positive integer greater than or equal to 2. That is, for standard cells with double the height and standard cells with multiple times the height, two or more adjacent consecutive rows of constraints will be added.

[0111] In some embodiments, for standard cells with double the height and standard cells with multiple times the height, when the second timing margin of any timing path in the critical path group is less than a first preset value, the layout optimization method further includes:

[0112] Reduce the displacement of the load unit in the timing path, or optimize the size of the drive unit in the timing path to increase the drive strength of the drive unit.

[0113] For existing research reports on schemes where standard cells with different timing relaxations compete for the same legalization target position, this application uses a circuit delay-displacement relationship table to evaluate the priority of competitors, thereby obtaining the legalization scheme with the least impact on critical path timing relaxation. For clustering results where the row pattern is an even multiple of various row types, the power and ground line location limitations prevent support for multi-height cells in advanced process circuits. This application proposes a method to automatically detect multi-height cells during the clustering stage and adaptively allocate more row resources. When using standard cells of average height for layout and legalization, and then restoring the original height and shape of the standard cells, the legalization state of the standard cells may be disrupted. This phenomenon is common in advanced processes when the area utilization rate is higher than 60% or there are many complex cells with large individual areas, and this disruption often affects the convergence of optimization results. This application adopts an optimization step of restoring the original height before legalization, combined with a method of reserving area space when calculating the average height, which greatly reduces the potential risk of timing convergence-legalization-height restoration-re-legalization-timing disruption in existing research reports. Solving the legalization problem involves addressing timing slack caused by cell shifting, while resolving the timing issue may render the legalization result invalid. This is because optimizations are performed on two different objectives in different steps of an optimization loop, leading to inconsistencies and non-convergence. This application uses a two-layer nested optimization loop to solve these problems. Steps S10 to S20 form the inner loop, primarily targeting clustering and legalization, prioritizing the resolution of global routing length issues during legalization. Steps S30 to S50 form the outer loop, primarily targeting the timing slack remaining in the legalized layout, resolving timing slack without compromising the legalization result. Several improvements in this application, compared to existing optimization methods for mixed-height library cells, enhance the convergence of the optimization loop and support more common scenarios in advanced processes.

[0114] Please refer to Figure 7 One embodiment provides a layout optimization apparatus for mixed-height library cells, used to lay out at least two types of standard cells of different heights on a chip, including:

[0115] The layout generation module 10 is used to generate a first reference layout of the chip based on at least two types of standard cells of different heights; wherein, each type of standard cell includes a standard cell of single height, a standard cell of double height, and a standard cell of multiple heights, and each row in the first reference layout is assigned at least one type of standard cell.

[0116] The clustering layout module 20 is used to cluster at least two types of standard units with different heights according to the height of the standard units allocated in each row of the first reference layout, to obtain multiple cluster sets, to allocate the standard units in each cluster set to the row corresponding to the centroid of the cluster set, to obtain the second reference layout, and to perform the first layout legalization to obtain the first layout legalization result.

[0117] The margin calculation module 30 is used to obtain the critical path group and its corresponding first time margin based on the first reference layout, and recalculate the time margin of the critical path group according to the first layout legalization result to obtain the second time margin of the critical path group; wherein, the critical path group includes multiple time paths, and the time margin of each time path is less than a preset threshold.

[0118] The layout optimization module 40 is used to adjust the weight of any time-series path when the second time-series margin of any time-series path in the critical path group is less than the first preset value, and use the time-series path with adjusted weight as a constraint to re-execute the clustering layout step until the third time-series margin of each time-series path in the critical path group is greater than or equal to the first preset value. Then, the time-series paths are optimized based on the first time-series margin and the third time-series margin of the critical path group to obtain the optimized layout. The third time-series margin of each time-series path is calculated based on the new layout legitimization result obtained after re-executing the clustering layout step.

[0119] The layout optimization module 40 is used to optimize the timing path based on the first and third timing margins of the critical path group to obtain the optimized layout, which is explained in detail below.

[0120] For each time-series path in the critical path group, calculate the absolute value of the difference between its first and third time-series margins to obtain the margin difference. Determine whether the margin difference is greater than a second preset value. If the margin difference is greater than the second preset value, optimize the time-series path and perform second layout legalization to obtain the second layout legalization result. Determine whether the second total displacement is less than a preset first threshold, and recalculate whether the time-series margin of each time-series path in the critical path group based on the second layout legalization result is greater than or equal to the preset second threshold. If the second total displacement is less than the preset first threshold, and the time-series margin of each time-series path in the critical path group recalculated based on the second layout legalization result is greater than or equal to the preset second threshold, then the layout after optimizing the time-series path is taken as the optimized layout.

[0121] In some embodiments, the layout optimization module 40 is further configured to optimize the timing path and perform a second layout legalization, including: incrementally optimizing the timing path and performing incremental layout legalization.

[0122] The clustering layout module 20 is used to cluster at least two types of standard cells with different heights according to the height of the standard cells allocated in each row of the first reference layout, so as to obtain multiple cluster sets, which are described in detail below.

[0123] The height type of a row is determined based on the proportion of standard units of different heights allocated to each row in the first reference layout. At least two types of standard units of different heights are grouped based on the height of each standard unit to obtain multiple unit groups. The centroid of each unit group is calculated. Multiple unit groups are allocated to different rows according to the height type of each row and the centroid of each unit group. The standard units allocated to each row are a cluster set to obtain multiple cluster sets.

[0124] In some embodiments, the layout optimization device for the mixed height library unit further includes a displacement optimization module 50. The displacement optimization module 50 is used to determine whether the first total displacement is greater than a third preset value. When the first total displacement is greater than the third preset value, the absolute value of the difference between the first total displacement and the third preset value is calculated. The weight of the total displacement is adjusted according to the absolute value of the difference and the pre-built correspondence table of circuit delay and displacement. The adjusted weight of the total displacement is used as a constraint to re-execute the clustering layout step until the first total displacement is less than or equal to the third preset value.

[0125] In some embodiments, the layout optimization device for mixed height library cells further includes a cell constraint module 60, which is used to add adjacent consecutive N rows of constraints to the standard cell that is N times higher, and re-execute the clustering layout step based on the added adjacent consecutive N rows of constraints until the first total displacement is less than or equal to a third preset value.

[0126] In some embodiments, for standard units of double height and standard units of multiple height, when the second timing margin of any timing path in the critical path group is less than the first preset value, the unit constraint module 60 is further used to reduce the displacement of the load unit in the timing path, or optimize the size of the drive unit in the timing path to increase the driving strength of the drive unit.

[0127] One embodiment provides a layout optimization device for hybrid height library units, comprising:

[0128] Memory, used to store programs;

[0129] A processor is used to implement layout optimization methods by executing programs stored in memory.

[0130] One embodiment provides a computer program product including a computer program and / or instructions, which implement a layout optimization method when executed by a processor.

[0131] In the above embodiments, implementation can be achieved, in whole or in part, by software, hardware, firmware, or any combination thereof. Furthermore, as those skilled in the art will understand, the principles herein can be reflected in a computer program product on a computer-readable storage medium pre-loaded with computer-readable program code. Any tangible, non-transitory computer-readable storage medium may be used, including magnetic storage devices (hard disks, floppy disks, etc.), optical storage devices (CDs, DVDs, Blu-ray discs, etc.), flash memory, and / or the like. These computer program instructions can be loaded onto a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to form a machine, such that instructions executing on the computer or other programmable data processing apparatus can generate means for performing a specified function. These computer program instructions can also be stored in a computer-readable storage medium that can instruct the computer or other programmable data processing apparatus to operate in a particular manner, such that instructions stored in the computer-readable storage medium can form an article of manufacture, including means for implementing the specified function. The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to perform a series of operational steps on the computer or other programmable apparatus to produce a computer-implemented process, such that instructions executing on the computer or other programmable apparatus can provide steps for implementing the specified function.

[0132] This document describes various exemplary embodiments with reference to them. However, those skilled in the art will recognize that changes and modifications can be made to the exemplary embodiments without departing from the scope of this document. For example, various operational steps and components for performing operational steps can be implemented in different ways depending on the specific application or considering any number of cost functions associated with the operation of the system (e.g., one or more steps can be deleted, modified, or combined with other steps).

[0133] While the principles herein have been illustrated in various embodiments, numerous modifications to the structures, arrangements, proportions, elements, materials, and components, particularly suited to specific environments and operational requirements, may be used without departing from the principles and scope of this disclosure. These modifications and other alterations or alterations will be included within the scope of this document. Those skilled in the art will recognize that many changes can be made to the details of the above embodiments without departing from the fundamental principles of the invention.

Claims

1. A layout optimization method for mixed-height library cells, used to lay out at least two types of standard cells with different heights on a chip, characterized in that, The layout optimization method includes: A first reference layout of the chip is generated based on at least two types of standard cells of different heights; wherein, each type of standard cell includes a standard cell of single height, a standard cell of double height, and a standard cell of multiple heights, and each row in the first reference layout is allocated with at least one type of standard cell; Clustering layout steps: Based on the height of the standard units allocated in each row of the first reference layout, the standard units of at least two different heights are clustered to obtain multiple cluster sets. The standard units in each cluster set are allocated to the row corresponding to the centroid of the cluster set to obtain the second reference layout and the first layout legalization is performed to obtain the first layout legalization result. Based on the first reference layout, a critical path group and its corresponding first time margin are obtained. The time margin of the critical path group is recalculated according to the first layout legalization result to obtain the second time margin of the critical path group. The critical path group includes multiple time paths, and the time margin of each time path is less than a preset threshold. When the second temporal margin of any temporal path in the critical path group is less than the first preset value, the weight of the temporal path is adjusted, and the temporal path with the adjusted weight is used as a constraint to re-execute the clustering layout step until the third temporal margin of each temporal path in the critical path group is greater than or equal to the first preset value. Then, the temporal paths are optimized based on the first and third temporal margins of the critical path group to obtain an optimized layout. The third temporal margin of each temporal path is calculated based on the new layout legitimization result obtained after re-executing the clustering layout step.

2. The layout optimization method as described in claim 1, characterized in that, The timing paths are optimized based on the first and third timing margins of the critical path group to obtain an optimized layout, including: For each time-series path in the critical path group, calculate the absolute value of the difference between its first time-series margin and its third time-series margin to obtain the margin difference. When the margin difference is greater than the second preset value, the timing path is optimized and the second layout legalization is performed to obtain the second layout legalization result; wherein, the second layout legalization result includes the second total displacement, which is the sum of the absolute values ​​of the displacements of all standard elements when the second layout legalization is performed; If the second total displacement is less than the preset first threshold, and the timing margin of each timing path in the critical path group recalculated according to the second layout legalization result is greater than or equal to the preset second threshold, then the layout after optimizing the timing path is taken as the optimized layout.

3. The layout optimization method as described in claim 2, characterized in that, The optimization of the timing path and the execution of the second layout legalization include: Incremental optimization is performed on the timing path, and incremental layout legalization is executed; wherein, the incremental optimization includes optimization methods such as size optimization, cell decomposition, and small-scale resynthesis.

4. The layout optimization method as described in claim 1, characterized in that, The at least two types of standard cells with different heights are clustered according to the height of the standard cells allocated in each row of the first reference layout to obtain multiple cluster sets, including: The height type of a row is determined based on the proportion of standard units of different heights allocated to each row in the first reference layout. Based on the height of each standard unit, at least two types of standard units of different heights are grouped to obtain multiple unit groups; wherein, each unit group contains standard units of one height, and each type of standard unit is any one of standard units of single height, double height, and multiple height; Calculate the centroid of each unit group, and assign the multiple unit groups to different rows according to the height type of each row and the centroid of each unit group. The standard units assigned to each row constitute a cluster set, so as to obtain multiple cluster sets.

5. The layout optimization method as described in claim 1, characterized in that, The first layout legalization result includes a first total displacement, which is the sum of the absolute values ​​of the displacements of all standard elements when performing the first layout legalization; the layout optimization method further includes: When the first total displacement is greater than the third preset value, calculate the absolute value of the difference between the first total displacement and the third preset value; The weight of the total displacement is adjusted according to the absolute value of the difference and the pre-constructed correspondence table of circuit delay and displacement. The adjusted weight of the total displacement is used as a constraint to re-execute the clustering layout step until the first total displacement is less than or equal to the third preset value.

6. The layout optimization method as described in claim 5, characterized in that, When the first total displacement is greater than a third preset value, the layout optimization method further includes: For a standard cell that is N times higher, add a constraint of N consecutive neighboring rows. Based on the added constraint of N consecutive neighboring rows, re-execute the clustering layout step until the first total displacement is less than or equal to the third preset value; where N is a positive integer greater than or equal to 2.

7. The layout optimization method as described in claim 1, characterized in that, For standard cells with double the height and standard cells with multiple the height, when the second timing margin of any timing path in the critical path group is less than the first preset value, the layout optimization method further includes: Reduce the displacement of the load unit in the timing path, or optimize the size of the drive unit in the timing path to increase the drive strength of the drive unit.

8. A layout optimization apparatus for mixed-height library cells, used to lay out at least two types of standard cells of different heights on a chip, characterized in that, include: A layout generation module is used to generate a first reference layout of a chip based on at least two types of standard cells of different heights; wherein, each type of standard cell includes a standard cell of single height, a standard cell of double height, and a standard cell of multiple heights, and each row in the first reference layout is assigned at least one type of standard cell; The clustering layout module is used to cluster the standard units of at least two different heights according to the height of the standard units allocated in each row of the first reference layout, to obtain multiple cluster sets, to allocate the standard units in each cluster set to the row corresponding to the centroid of the cluster set, to obtain the second reference layout and to perform the first layout legalization to obtain the first layout legalization result. The margin calculation module is used to obtain the critical path group and its corresponding first temporal margin based on the first reference layout, and recalculate the temporal margin of the critical path group according to the first layout legalization result to obtain the second temporal margin of the critical path group; wherein, the critical path group includes multiple temporal paths, and the temporal margin of each temporal path is less than a preset threshold. The layout optimization module is used to adjust the weight of any time-series path when the second time-series margin of any time-series path in the critical path group is less than the first preset value, and use the time-series path with adjusted weight as a constraint to re-execute the clustering layout step until the third time-series margin of each time-series path in the critical path group is greater than or equal to the first preset value. Then, the time-series paths are optimized based on the first time-series margin and the third time-series margin of the critical path group to obtain an optimized layout. The third time-series margin of each time-series path is calculated based on the new layout legitimization result obtained after re-executing the clustering layout step.

9. A layout optimization device for mixed-height library units, characterized in that, include: Memory, used to store programs; A processor for implementing the layout optimization method as described in any one of claims 1-7 by executing a program stored in the memory.

10. A computer program product comprising a computer program and / or instructions, characterized in that, When the computer program and / or instructions are executed by the processor, they implement the layout optimization method as described in any one of claims 1-7.

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