File generation method, apparatus, device, storage medium, and product

Abstract

The application discloses a file generation method, device and equipment, a storage medium and a product; the method comprises the following steps: dividing a chip design task into a fixed task and a dynamic task according to a preset division rule; wherein the fixed task is a task whose execution logic is fixed in a design flow; the dynamic task is a task whose execution logic changes in the design flow; determining an initial dependency relationship link between the fixed task and the dynamic task according to a preset task dependency relationship; instantiating the dynamic task into a plurality of executable instance design tasks according to a preset parameter configuration of the dynamic task, replacing the corresponding dynamic task with the instance design task in the initial dependency relationship link to obtain a target dependency relationship link, and constructing a construction script file corresponding to the chip design flow based on the target dependency relationship link. The application can automatically construct the construction script file corresponding to the chip design flow, and provides great convenience for chip designers.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and in particular to document generation methods, apparatus, devices, storage media, and products. Background Technology

[0002] Chip design is a massive and time-consuming system process. To improve design efficiency, the dependencies between various design tasks are often recorded in the build script files (e.g., Makefiles) corresponding to the chip design flow, thereby integrating scattered design tasks into an ordered execution flow. However, how to efficiently construct Makefiles has become a key focus of current research and practice.

[0003] Currently, existing technologies often require chip designers to manually build makefiles. This not only consumes a lot of the designer's time, but also means that the dependencies between various design tasks are not fixed during the actual design process. When the dependencies change, the makefile needs to be manually modified again, which can easily lead to process errors. Therefore, there is an urgent need for a more efficient file generation method to accurately build makefiles in the chip design process. Summary of the Invention

[0004] This invention provides a file generation method, apparatus, device, storage medium, and product to automate the construction of makefiles in the chip design process.

[0005] According to one aspect of the present invention, a file generation method is provided, characterized in that it includes: According to a preset division rule, chip design tasks are divided into fixed tasks and dynamic tasks; wherein, fixed tasks are tasks whose execution logic is fixed in the design flow; and dynamic tasks are tasks whose execution logic changes in the design flow. Determine the initial dependency chain between the fixed task and the dynamic task based on the preset task dependency relationship; Based on the configuration of the preset parameters of the dynamic task, the dynamic task is instantiated into several executable instance design tasks, and the corresponding dynamic task is replaced by the instance design task in the initial dependency relationship link to obtain the target dependency relationship link. Based on the target dependency relationship link, the build script file corresponding to the chip design process is constructed.

[0006] According to another aspect of the present invention, a document generation apparatus is provided, comprising: The task partitioning module is used to divide chip design tasks into fixed tasks and dynamic tasks according to preset partitioning rules; wherein, the fixed tasks are tasks whose execution logic is fixed in the design flow; and the dynamic tasks are tasks whose execution logic changes in the design flow. An initial link generation module is used to determine the initial dependency link between the fixed task and the dynamic task based on a preset task dependency relationship. The target dependency link generation module is used to instantiate the dynamic task into several executable instance design tasks according to the configuration of preset parameters of the dynamic task, and replace the corresponding dynamic task with the instance design task in the initial dependency relationship link to obtain the target dependency relationship link, and build the build script file corresponding to the chip design process based on the target dependency relationship link.

[0007] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the file generation method according to any embodiment of the present invention.

[0008] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the file generation method described in any embodiment of the present invention.

[0009] According to another aspect of the present invention, a computer program product is provided, the computer program product comprising a computer program that, when executed by a processor, implements the file generation method described in any embodiment of the present invention.

[0010] The technical solution of this invention divides chip design tasks into fixed tasks and dynamic tasks according to preset partitioning rules. Fixed tasks are those whose execution logic remains constant throughout the design flow; dynamic tasks are those whose execution logic changes throughout the design flow. This classification of chip design tasks allows for targeted adjustments to dependencies based on task type when they change. By determining the initial dependency chain between fixed and dynamic tasks based on preset task dependencies, the dependencies between tasks are preliminarily established, providing a foundation for determining the connection relationships between instance design tasks and other tasks. Based on the configuration of preset parameters for dynamic tasks… The invention instantiates a dynamic task into several executable instance design tasks, and replaces the corresponding dynamic task with the instance design task in the initial dependency chain to obtain the target dependency chain. Based on the target dependency chain, a build script file corresponding to the chip design flow is constructed. The above steps realize the automated construction of the Makefile file in the chip design flow. Moreover, during the chip design process, as the task stage or task parameters change, the instance design task obtained after instantiating the dynamic task can replace the original dynamic task, realizing the dynamic adjustment of the dependency relationship between various tasks and avoiding the error-prone problem of manual modification. The invention efficiently and accurately constructs the Makefile file in the chip design flow.

[0011] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a flowchart of a file generation method provided according to Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the initial dependency chain applicable to Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of the target dependency relationship link applicable to Embodiment 1 of the present invention; Figure 4 This is a flowchart of a file generation method provided according to Embodiment 2 of the present invention; Figure 5 This is a schematic diagram of an initial dependency relationship link applicable to Embodiment 2 of the present invention; Figure 6 This is a schematic diagram of a target dependency relationship link applicable to Embodiment 2 of the present invention; Figure 7 This is a schematic diagram of another target dependency relationship link applicable to Embodiment 2 of the present invention; Figure 8 This is a schematic diagram of another initial dependency relationship link applicable to Embodiment 2 of the present invention; Figure 9 This is a schematic diagram of another target dependency relationship link applicable to Embodiment 2 of the present invention; Figure 10 This is a schematic diagram of a document generation device according to Embodiment 3 of the present invention; Figure 11 This is a schematic diagram of the structure of an electronic device that implements the file generation method of Embodiment 4 of the present invention. Detailed Implementation

[0014] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0015] It should be noted that the terms "first," "second," "initial," and "target," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0016] Example 1 Figure 1This is a flowchart illustrating a file generation method provided in Embodiment 1 of the present invention. This embodiment is applicable to the construction of a Makefile file corresponding to a chip design process. This method can be executed by a file generation device, which can be implemented in hardware and / or software and can be configured in an electronic device. Figure 1 As shown, the method includes: S101. Divide the chip design task into fixed tasks and dynamic tasks according to the preset division rules; among them, fixed tasks are tasks whose execution logic is fixed in the design flow; dynamic tasks are tasks whose execution logic changes in the design flow.

[0017] In this embodiment, a configuration file can be set for the chip design task to record the configuration parameters corresponding to the chip design task (e.g., the current stage of the chip design task, the required chip type, and the manufacturing process, etc.). Based on the parameters in the configuration file, the type of the chip design task can be determined according to a preset classification rule. This preset classification rule can be pre-defined; for example, it can classify the chip design tasks based on parameters such as chip type and manufacturing process to determine whether these parameters change in different design flows. Fixed tasks can be understood as tasks whose execution logic is fixed in the design flow; that is, the required chip type and manufacturing process generally do not change in different chip design stages. Dynamic tasks can be understood as tasks whose execution logic may change in the design flow; that is, the required chip type and manufacturing process may change in different chip design stages.

[0018] For example, for each chip design task, the configuration parameters can be obtained by reading the configuration file corresponding to the current chip design task, and the current chip design task can be determined as a fixed task or a dynamic task according to the preset division rules.

[0019] S102. Determine the initial dependency chain between fixed tasks and dynamic tasks based on the preset task dependency relationship.

[0020] In this embodiment, the preset task dependency relationship can include the temporal dependency relationship of each chip design task, which can reflect the constraints of each chip design task in execution logic. This preset task dependency relationship can be pre-defined based on the configuration parameters corresponding to each chip design task. For example, the module type to which the task belongs can be determined based on the functional configuration parameters corresponding to the first chip design task, and the dependent modules of the current module can be determined based on the input parameters and / or output parameters of the current module. The second chip design task corresponding to the dependent module can then be identified as a task that has a dependency relationship with the first chip design task. Alternatively, the dependency relationship between each chip design task can be determined based on the interface parameters corresponding to the chip design task. The specific method for determining the dependency relationship can be set according to the actual scenario.

[0021] For example, the dependencies between fixed tasks and dynamic tasks can be determined based on preset task dependencies, and the fixed tasks and dynamic tasks can be connected according to the order of the dependencies to obtain an initial dependency chain; such as Figure 2 As shown, the initial dependency chain can be used to characterize the dependencies between various fixed and dynamic tasks.

[0022] S103. Based on the configuration of the preset parameters of the dynamic task, the dynamic task is instantiated into several executable instance design tasks, and the corresponding dynamic task is replaced with the instance design task in the initial dependency relationship link to obtain the target dependency relationship link, and the build script file corresponding to the chip design process is built based on the target dependency relationship link.

[0023] In this embodiment, the preset parameters can be parameters that reflect the chip type, the stage of the task, and the manufacturing process. An instance design task can be understood as a task that, after specifically configuring the preset parameters of a dynamic task, can be actually scheduled to complete a specific function. The build script file corresponding to the chip design flow can be a Makefile.

[0024] For example, for a specific dynamic task, after configuring its preset parameters, it can be instantiated into several instance design tasks according to the specific configuration. For instance, for Figure 2 The dynamic task D in the code can be instantiated into two instance design tasks based on parameters related to the chip type, each instance design task corresponding to a different chip type. Based on the connection relationships between dynamic task D and other tasks in the initial dependency chain, the two instantiated instance design tasks are used to replace dynamic task D, thus obtaining... Figure 3The target dependency relationship chain is then recorded in the target dependency relationship chain. The dependency relationships between each task recorded in the target dependency relationship chain are then recorded in the makefile file. For example, each task in the target dependency relationship chain is converted into a target in the makefile file, and the connection relationship between each task in the target dependency relationship chain is converted into a dependency in the makefile file. The specific conversion process can be set according to the actual application scenario.

[0025] This invention provides a file generation method that divides chip design tasks into fixed tasks and dynamic tasks according to preset partitioning rules. Fixed tasks are those whose execution logic remains constant throughout the design flow, while dynamic tasks are those whose execution logic changes throughout the design flow. This classification of chip design tasks allows for targeted adjustments to dependencies based on task type when they change. By determining the initial dependency chain between fixed and dynamic tasks based on preset task dependencies, the initial dependencies between tasks are established, providing a foundation for determining the connection relationships between instance design tasks and other tasks. The method also considers the configuration of preset parameters for dynamic tasks. In this invention, a dynamic task is instantiated into several executable instance design tasks. The corresponding dynamic task is then replaced with an instance design task in the initial dependency chain to obtain the target dependency chain. Based on this target dependency chain, a build script file corresponding to the chip design flow is constructed. These steps automate the construction of the Makefile in the chip design flow. Furthermore, during the chip design process, as task stages or parameters change, the instance design tasks obtained after instantiating the dynamic task can replace the original dynamic task, enabling dynamic adjustment of the dependencies between tasks and avoiding the error-prone problem of manual modification. This invention efficiently and accurately constructs the Makefile in the chip design flow.

[0026] Example 2 Figure 4 This is a flowchart of a file generation method provided in Embodiment 2 of the present invention. This embodiment is a refinement based on the above embodiments. Figure 4 As shown, the method includes: S401. Chip design tasks that do not change with the selection of chip intellectual property cores, process voltage, temperature angle, operating conditions, and process stages are classified as fixed tasks.

[0027] In this embodiment, the configuration file corresponding to the chip design task can record the selection parameters of the chip intellectual property (IP) core, the parameters related to the process-voltage-temperature-angle (PVT Corner) condition, and the parameters related to the process stage for the current task. Furthermore, identification information can be added to each parameter in advance to indicate whether each parameter will change. Alternatively, for parameters that may change, the parameter change range can be set in advance in the configuration file. For example, if the chip IP core may change, all the selections of the chip IP core can be listed in advance in the configuration file. For example, recording "ip:[1.0,1.1,1.2]" in the configuration file indicates that there are 3 selections of the chip IP core, which indicates that the parameter may change. Conversely, if the selection parameter of the chip IP core recorded in the configuration file is "ip:[1.0]", it indicates that there is only 1 selection of the chip IP core, which indicates that the parameter will not change.

[0028] For example, for a certain chip design task, the selection parameters of the corresponding chip IP core, the parameters related to the PVTCorner operating conditions, and the parameters related to the process stage are read respectively. It is determined whether the above parameters are variable parameters. For example, if the selection parameters of the chip IP core are "ip:[1.0,1.1,1.2]", then it means that the parameter is a variable parameter, and the chip design task can be determined as a dynamic task. Correspondingly, if none of the above parameters are variable parameters, the chip design task can be determined as a fixed task.

[0029] S402. Chip design tasks that change with the selection of chip intellectual property cores, process voltage, temperature angle, and any of the process stages are classified as dynamic tasks.

[0030] For example, for a certain chip design task, the selection parameters of the corresponding chip IP core, the parameters related to the PVTCorner operating conditions, and the parameters related to the process stage are read respectively. If any of the above parameters is a variable parameter, then the chip design task can be determined as a dynamic task.

[0031] S403. Determine the initial dependency chain between fixed tasks and dynamic tasks based on the preset task dependency relationship.

[0032] S404. Based on the selection of the chip intellectual property core, process voltage, temperature angle, and operating conditions of the dynamic task, and the process stage, the dynamic task is instantiated into several executable instance design tasks.

[0033] For example, for dynamic tasks, the selection parameters of the chip IP core, the parameters related to the PVT Corner condition, and the parameters related to the process stage may be variable parameters. That is, a certain parameter may have multiple options. Then, according to the specific selection of the parameter, the dynamic task can be instantiated into several executable instance design tasks. Instance design tasks generally do not have variable parameters. For example, if the chip IP core of a certain dynamic task is a variable parameter and has 3 options: 1.0, 1.1, and 1.2, then according to the various selection parameters of the chip IP core, the dynamic task can be instantiated into 3 instance design tasks, and the chip IP core of each instance design task corresponds to 1.0, 1.1, and 1.2 respectively.

[0034] S405. In the initial dependency chain, based on the first task type of the target predecessor task and the second task type of the target successor task of the dynamic task, determine the connection relationship between each instance design task obtained after the instantiation of the dynamic task and the target predecessor and successor tasks, and determine the target dependency chain based on the connection relationship.

[0035] In this embodiment, the target preceding task can be understood as the task in the initial dependency chain that is one level above the current dynamic task, for example... Figure 2 In this context, fixed tasks B and C are both preceding tasks to the target of dynamic task D. The first task type is the type of the preceding task; for example, if the preceding task is a dynamic task, then the first task type is dynamic; similarly, if the preceding task is a fixed task, then the first task type is fixed. The subsequent task can be understood as the task in the initial dependency chain that is the next level below the current dynamic task. Figure 2 In this context, the fixed task E is the target successor task of the dynamic task D. Correspondingly, the second task type is the type of the target successor task. If the target successor task is a dynamic task, then the second task type is a dynamic type. If the target successor task is a fixed task, then the second task type is a fixed type.

[0036] Optionally, determining the connection relationship between each instance design task obtained after instantiation of the dynamic task and the target preceding task and the target following task, based on the first task type of the target preceding task and the second task type of the target following task of the dynamic task, includes the following steps A1 to A2: A1. In response to the fact that both the first task type of the target preceding task of the dynamic task and the second task type of the target following task of the dynamic task are fixed types, the target preceding task is determined as the preceding task of each instance design task obtained after the dynamic task is instantiated, and the target following task is determined as the following task of each instance design task.

[0037] For example, such as Figure 2 and Figure 3 As shown, the target prerequisite tasks of dynamic task D are fixed tasks B and C, both of which are of fixed type. The target successor task of dynamic task D is fixed task E, which is also of fixed type. After instantiation of dynamic task D, two instance design tasks are obtained, namely instance design task D1 and instance design task D2. Therefore, fixed task B can be used as the prerequisite task of instance design task D1 and instance design task D2, fixed task C can be used as the prerequisite task of instance design task D1 and instance design task D2, and fixed task E can be used as the successor task of instance design task D1 and instance design task D2, thus obtaining Figure 3 The target dependency relationship chain in the middle.

[0038] A2. In response to the first task type of the target preceding task of the dynamic task being dynamic and / or the second task type of the target following task of the dynamic task being dynamic, according to preset judgment conditions, it is determined whether the dynamic task and the target preceding task and / or the target following task are of the same type of task, and the connection relationship between each instance design task obtained after the instantiation of the dynamic task and the target preceding task and / or the target following task is determined according to the judgment result; wherein, the preset judgment conditions include at least one of whether the selection of chip intellectual property core is consistent, whether the process voltage, temperature angle and operating conditions are consistent, and whether the process stages are consistent.

[0039] Specifically, in response to the first task type of the target preceding task of the dynamic task being dynamic and the second task type of the target following task of the dynamic task being fixed, the dynamic task and the target preceding task are determined to be of the same type according to the preset judgment conditions. Based on the judgment result, the connection relationship between each instance design task obtained after the dynamic task is instantiated and the target preceding task is determined, and the target following task is determined as the following task of each instance design task obtained after the dynamic task is instantiated.

[0040] In response to the first task type of the target preceding task of the dynamic task being a fixed type and the second task type of the target following task of the dynamic task being a dynamic type, the system determines whether the dynamic task and the target following task are of the same type based on preset judgment conditions. Based on the judgment result, the system determines the connection relationship between each instance design task obtained after the dynamic task is instantiated and the target following task, and determines the target preceding task as the preceding task of each instance design task obtained after the dynamic task is instantiated.

[0041] Since both the first task type of the target preceding task and the second task type of the target following task of the dynamic task are dynamic, the dynamic task is judged according to the preset judgment conditions to determine whether the dynamic task is the same type of task as the target preceding task and the target following task. Based on the judgment results, the connection relationship between each instance task obtained after the instantiation of the dynamic task and the target preceding task, as well as the connection relationship between the instance task and the target following task, are determined respectively.

[0042] In this embodiment, the judgment conditions may include at least one of the following: whether the selection of the chip intellectual property core is consistent, whether the process voltage, temperature angle, and operating conditions are consistent, and whether the process stages are consistent. Based on the preset judgment conditions, it is determined whether the dynamic task and the target preceding task and / or the target following task are of the same type. Specifically, taking the judgment condition of whether the selection of the chip intellectual property core is consistent as an example, it is determined whether the chip intellectual property core of the dynamic task and the target preceding task and / or the target following task are the same. If the chip intellectual property core of the dynamic task and the target preceding task are the same, then the dynamic task and the target preceding task can be determined as the same type of task. For example, the chip intellectual property core of the dynamic task is "ip:[1.0, If the chip intellectual property core of the target preceding task is also "ip:[1.0,1.1]", then the dynamic task and the target preceding task can be identified as the same type of task. If the chip intellectual property cores of the dynamic task and the target preceding task are different, then the dynamic task and the target preceding task can be identified as different types of tasks. Correspondingly, it is also possible to determine whether the dynamic task and the target following task are the same type of task, which will not be elaborated here. Correspondingly, if the judgment conditions also include whether the process voltage, temperature angle, and operating conditions are consistent, and whether the process stages are consistent, then for the same type of task, it is also possible to continue to judge whether its process voltage, temperature angle, and operating conditions, and process stages are consistent with the dynamic task, and then obtain the judgment result.

[0043] Optionally, determining the connection relationship between each instance design task obtained after the instantiation of the dynamic task and the target preceding task and / or the following succeeding task based on the judgment result includes the following B1 to B2: B1. In response to the dynamic task and the target preceding task being of the same type, the preceding task of each instance design task obtained after instantiating the dynamic task is determined as the instance design task obtained after instantiating the target preceding task, which has the same chip intellectual property core selection type or the same process voltage temperature angle condition.

[0044] For example, such as Figure 5 and Figure 6 As shown, with Figure 5 Taking dynamic task D as an example, its target preceding task is... Figure 5Dynamic task C in the middle, through the Figure 5 After instantiating the dynamic task C in the middle, we get Figure 6 The example design tasks C1 and C2 in the example are designed by... Figure 5 After instantiating the dynamic task D in the middle, we get Figure 6 If instance design tasks D1 and D2 are in the same context, and dynamic tasks D and C are of the same type, then the preceding task of instance design task D1 is determined to be instance design task C1, which has the same intellectual property rights or the same process voltage temperature angle conditions as instance design task D1. Similarly, the preceding task of instance design task D2 is determined to be instance design task C2, which has the same chip intellectual property rights or the same process voltage temperature angle conditions as instance design task D2.

[0045] Optionally, if the preceding task of a dynamic task includes a first fixed task of a fixed type, then the preceding task of each instance design task obtained after instantiating the dynamic task also includes the first fixed task. For example... Figure 5 The preceding tasks of dynamic task D also include a first fixed task of a fixed type (i.e., fixed task B), so if Figure 6 As shown, the preceding tasks of the example design tasks D1 and D2 also include this fixed task B.

[0046] B2. In response to the dynamic task and the target subsequent task being of the same type, the subsequent tasks of each instance design task obtained after instantiating the dynamic task are determined as instance design tasks with the same chip intellectual property core selection type or the same process voltage temperature angle condition obtained after instantiating the target subsequent task.

[0047] For example, Figure 5 The target successor task corresponding to dynamic task D is dynamic task G. After dynamic task G is instantiated, it corresponds to... Figure 6 If instance design tasks G1 and G2, and dynamic tasks D and G are of the same type, then the subsequent task of instance design task D1 will be determined as instance design task G1, which has the same intellectual property rights or the same process voltage temperature angle conditions as instance design task D1. Similarly, the subsequent task of instance design task D2 will be determined as instance design task G2, which has the same chip intellectual property rights or the same process voltage temperature angle conditions as instance design task D2.

[0048] Optionally, if the subsequent tasks of a dynamic task include a second fixed task of a fixed type, then the subsequent tasks of each instance design task obtained after instantiating the dynamic task also include the second fixed task. For example... Figure 5 The subsequent tasks of dynamic task D also include a second fixed task of a fixed type (i.e., fixed task F), so if Figure 6As shown, the fixed task F is also included in the subsequent tasks of the example design tasks D1 and D2.

[0049] Optionally, determining the connection relationship between each instance design task obtained after the dynamic task instantiation and the target preceding task and / or the following succeeding task based on the judgment result further includes the following C1 to C2: C1. In response to the fact that the dynamic task and the target preceding task are not of the same type, the preceding tasks of each instance design task obtained after instantiating the dynamic task are determined as all instance design tasks obtained after instantiating the target preceding task.

[0050] For example, if Figure 5 Dynamic task D and dynamic task C are not the same type of task, so if Figure 7 As shown, the preceding tasks of instance design task D1 are defined as all instance design tasks obtained after the instantiation of dynamic task C, i.e. Figure 7 The example design tasks C1 and C2 are defined. Correspondingly, the prerequisite tasks for example design task C2 are all the example design tasks obtained after instantiating dynamic task C, i.e. Figure 7 Example design task C1 and example design task C2.

[0051] C2. In response to the fact that the dynamic task and the target subsequent task are not of the same type, the subsequent tasks of each indeterminate design task obtained after instantiating the dynamic task are determined as all instance design tasks obtained after instantiating the target subsequent task.

[0052] For example, if Figure 5 If dynamic task D and dynamic task G are not of the same type, then... Figure 7 As shown, the subsequent tasks of instance design task D1 are determined as all instance design tasks obtained after the instantiation of dynamic task G, i.e. Figure 7 The example design tasks G1 and G2 are defined. Correspondingly, the subsequent tasks of example design task G2 are determined as all example design tasks obtained after instantiating the dynamic task G, i.e. Figure 7 Example design tasks G1 and G2 in the example.

[0053] The above steps accurately adapt the dependencies between tasks during the dynamic task instantiation process. By distinguishing between fixed and dynamic types of preceding and subsequent tasks, different methods can be used to determine the connection relationship between the instance design task and the preceding and subsequent tasks. For dynamic types, the system further determines whether the dynamic task and its preceding and subsequent tasks are of the same type based on whether the selection of the chip intellectual property core is consistent, whether the process voltage, temperature angle and operating conditions are consistent, and whether the process stages are consistent. Different processing methods are used for different types of tasks to determine the connection relationship between each instance design task, ensuring that the dependency relationship between instance design tasks conforms to the actual constraint relationship, thereby ensuring that the invention has stronger stability and can adapt to various application scenarios.

[0054] S406, Build script files corresponding to the chip design process based on target dependency relationship links.

[0055] This invention provides a file generation method that, based on the selection of chip intellectual property cores, process voltage, temperature angle, and operating conditions, as well as the process stage, divides chip design tasks into fixed tasks and dynamic tasks, achieving precise classification of chip design tasks. Furthermore, by instantiating dynamic tasks according to the selection of chip intellectual property cores, process voltage, temperature angle, and operating conditions, as well as the process stage, abstract tasks can be decomposed into multiple directly executable instance design tasks, improving process adaptability and scalability. Moreover, based on the sequential task types of dynamic tasks, the connection relationships between various tasks can be adaptively determined, thereby automatically constructing target dependency relationship links, ensuring the accuracy and rationality of task dependencies, avoiding redundant configurations and erroneous associations, and improving the generation efficiency of Makefiles in the chip design process.

[0056] For example, in chip design, the placement of a chip containing 5 functional blocks involves the following chip design tasks: GetData, BuildTech, ImportBlocks (which can be instantiated as 5 blocks), Floorplan, PinAssignment (which can be instantiated as 5 blocks), InsertFeedthru, FeedthruAssignment (which can be instantiated as 5 blocks), CommitPartition (which can be instantiated as 5 modules), and CollectedData. The ImportBlocks, PinAssignment, FeedthruAssignment, and CommitPartition tasks vary depending on the block; therefore, these tasks can be classified as dynamic tasks, while the remaining tasks are fixed tasks. The initial dependency chain is as follows: Figure 8 As shown, by replacing the original dynamic task with a task designed using the instantiated instance according to the method disclosed in this invention, the following can be obtained: Figure 9 The target dependency chain shown is used to generate the Makefile file corresponding to the chip design flow. This invention avoids designers manually building the Makefile, saving them significant time in constructing the design flow; it also avoids errors caused by less capable designers manually building the Makefile; and it significantly improves the speed of building Makefile files for chip design flows with numerous design tasks.

[0057] Example 3 Figure 10 This is a schematic diagram of a document generation device provided in Embodiment 3 of the present invention. Figure 10 As shown, the device includes: a task partitioning module 1001, an initial link generation module 1002, and a target link generation module 1003.

[0058] The task partitioning module is used to divide chip design tasks into fixed tasks and dynamic tasks according to preset partitioning rules; wherein, the fixed tasks are tasks whose execution logic is fixed in the design flow; and the dynamic tasks are tasks whose execution logic changes in the design flow. An initial link generation module is used to determine the initial dependency link between the fixed task and the dynamic task based on a preset task dependency relationship. The target dependency link generation module is used to instantiate the dynamic task into several executable instance design tasks according to the configuration of preset parameters of the dynamic task, and replace the corresponding dynamic task with the instance design task in the initial dependency relationship link to obtain the target dependency relationship link, and build the build script file corresponding to the chip design process based on the target dependency relationship link.

[0059] This invention provides a file generation device that divides chip design tasks into fixed tasks and dynamic tasks according to a preset partitioning rule. Fixed tasks are those whose execution logic remains constant throughout the design flow, while dynamic tasks are those whose execution logic changes throughout the design flow. This classification of chip design tasks allows for targeted adjustments to dependencies based on task type when they change. By determining the initial dependency chain between fixed and dynamic tasks according to preset task dependencies, the device initially establishes the dependencies between tasks, providing a foundation for determining the connection relationships between instance design tasks and other tasks. The device also configures preset parameters for dynamic tasks. In this invention, a dynamic task is instantiated into several executable instance design tasks. The corresponding dynamic task is then replaced with an instance design task in the initial dependency chain to obtain the target dependency chain. Based on this target dependency chain, a build script file corresponding to the chip design flow is constructed. These steps automate the construction of the Makefile in the chip design flow. Furthermore, during the chip design process, as task stages or parameters change, the instance design tasks obtained after instantiating the dynamic task can replace the original dynamic task, enabling dynamic adjustment of the dependencies between tasks and avoiding the error-prone problem of manual modification. This invention efficiently and accurately constructs the Makefile in the chip design flow.

[0060] Optionally, the task partitioning module includes: The fixed task division unit is used to divide chip design tasks that do not change with the selection of chip intellectual property cores, process voltage, temperature angle conditions, and process stages into fixed tasks. The dynamic task partitioning unit is used to divide chip design tasks into dynamic tasks that vary depending on the selection of the chip intellectual property core, process voltage, temperature angle, and any stage of the process.

[0061] Optionally, the target link generation module includes: The instantiation unit is used to instantiate the dynamic task into several executable instance design tasks based on the selection of the chip intellectual property core, process voltage, temperature angle, and process stage of the dynamic task. The target dependency link determination unit is used to determine, in the initial dependency link, the connection relationship between each instance design task obtained after the instantiation of the dynamic task and the target pre-task and the target post-task, according to the first task type of the target pre-task of the dynamic task and the second task type of the target post-task of the dynamic task, and determine the target dependency link according to the connection relationship. The script file generation unit is used to construct the build script file corresponding to the chip design process based on the target dependency relationship link.

[0062] Optionally, the target dependency link determination unit includes: The first connection relationship determination subunit is used to determine, in the initial dependency relationship link, in response to the first task type of the target predecessor task of the dynamic task and the second task type of the target successor task of the dynamic task being both fixed types, the target predecessor task is determined as the predecessor task of each instance design task obtained after the instantiation of the dynamic task, and the target successor task is determined as the successor task of each instance design task. The second connection relationship determination subunit is used to determine, in the initial dependency relationship link, whether the dynamic task and the target preceding task and / or the target following task are of the same type, in response to the first task type of the target preceding task of the dynamic task being dynamic and / or the second task type of the target following task of the dynamic task being dynamic, according to preset judgment conditions, whether the dynamic task and the target preceding task and / or the target following task are tasks of the same type, and to determine the connection relationship between each instance design task obtained after the instantiation of the dynamic task and the target preceding task and / or the target following task according to the judgment result; wherein, the preset judgment conditions include at least one of whether the selection of chip intellectual property core is consistent, whether the process voltage, temperature angle and operating conditions are consistent, and whether the process stages are consistent. The target link generation subunit is used to determine the target dependency link based on the connection relationship.

[0063] Optionally, the second connection relationship determination subunit is specifically used for: in the initial dependency relationship link, in response to the first task type of the target preceding task of the dynamic task being dynamic and / or the second task type of the target following task of the dynamic task being dynamic, determining whether the dynamic task and the target preceding task and / or the target following task are of the same type of task according to a preset judgment condition; in response to the dynamic task and the target preceding task being of the same type of task, determining the preceding task of each instance design task obtained after instantiating the dynamic task as an instance design task with the same chip intellectual property core selection type or the same process voltage temperature angle condition obtained after instantiating the target preceding task; in response to the dynamic task and the target following task being of the same type of task, determining the following task of each instance design task obtained after instantiating the dynamic task as an instance design task with the same chip intellectual property core selection type or the same process voltage temperature angle condition obtained after instantiating the target following task.

[0064] Optionally, the second connection relationship determination subunit can also be specifically used for: in the initial dependency relationship link, in response to the first task type of the target predecessor task of the dynamic task being dynamic and / or the second task type of the target successor task of the dynamic task being dynamic, determining whether the dynamic task and the target predecessor task and / or the target successor task are of the same type of task according to a preset judgment condition; in response to the dynamic task and the target predecessor task not being of the same type of task, determining the predecessor tasks of each instance design task obtained after instantiating the dynamic task as all instance design tasks obtained after instantiating the target predecessor task; in response to the dynamic task and the target successor task not being of the same type of task, determining the successor tasks of each indeterminate design task obtained after instantiating the dynamic task as all instance design tasks obtained after instantiating the target successor task.

[0065] The document generation apparatus provided in the embodiments of the present invention can execute the document generation method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of executing the method.

[0066] Example 4 Figure 11A schematic diagram of an electronic device 1100 that can be used to implement embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0067] like Figure 11 As shown, the electronic device 1100 includes at least one processor 1101 and a memory, such as a read-only memory (ROM) 1102 or a random access memory (RAM) 1103, communicatively connected to the at least one processor 1101. The memory stores computer programs executable by the at least one processor. The processor 1101 can perform various appropriate actions and processes based on the computer program stored in the ROM 1102 or loaded into the RAM 1103 from storage unit 1108. The RAM 1103 may also store various programs and data required for the operation of the electronic device 1100. The processor 1101, ROM 1102, and RAM 1103 are interconnected via a bus 1104. An input / output (I / O) interface 1105 is also connected to the bus 1104.

[0068] Multiple components in electronic device 1100 are connected to I / O interface 1105, including: input unit 1106, such as keyboard, mouse, etc.; output unit 1107, such as various types of displays, speakers, etc.; storage unit 1108, such as disk, optical disk, etc.; and communication unit 1109, such as network card, modem, wireless transceiver, etc. Communication unit 1109 allows electronic device 1100 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0069] Processor 1101 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 1101 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 1101 performs the various methods and processes described above, such as file generation methods.

[0070] In some embodiments, the file generation method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 1108. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 1100 via ROM 1102 and / or communication unit 1109. When the computer program is loaded into RAM 1103 and executed by processor 1101, one or more steps of the file generation method described above may be performed. Alternatively, in other embodiments, processor 1101 may be configured to execute the file generation method by any other suitable means (e.g., by means of firmware).

[0071] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0072] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0073] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0074] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0075] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0076] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0077] This disclosure provides a computer program product, including a computer program that, when executed by a processor, implements the file generation method provided in the above embodiments.

[0078] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0079] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for generating a file, characterized in that, include: According to a preset division rule, chip design tasks are divided into fixed tasks and dynamic tasks; wherein, fixed tasks are tasks whose execution logic is fixed in the design flow; and dynamic tasks are tasks whose execution logic changes in the design flow. Determine the initial dependency chain between the fixed task and the dynamic task based on the preset task dependency relationship; Based on the configuration of the preset parameters of the dynamic task, the dynamic task is instantiated into several executable instance design tasks, and the corresponding dynamic task is replaced by the instance design task in the initial dependency relationship link to obtain the target dependency relationship link. Based on the target dependency relationship link, the build script file corresponding to the chip design process is constructed.

2. The file generation method according to claim 1, characterized in that, The process of dividing the chip design task into fixed tasks and dynamic tasks according to a preset division rule includes: Chip design tasks that do not change with the selection of chip intellectual property cores, process voltage, temperature angle, operating conditions, and process stages are classified as fixed tasks. Chip design tasks that vary depending on the selection of the chip's intellectual property core, process voltage, temperature angle, and any change in the process stage are classified as dynamic tasks.

3. The file generation method according to claim 1, characterized in that, The step of instantiating the dynamic task into several executable instance design tasks based on the configuration of preset parameters of the dynamic task, and replacing the corresponding dynamic task with the instance design tasks in the initial dependency relationship chain to obtain the target dependency relationship chain includes: Based on the selection of the chip intellectual property core, process voltage, temperature angle, and operating conditions, as well as the process stage, the dynamic task is instantiated into several executable instance design tasks. In the initial dependency chain, based on the first task type of the target predecessor task and the second task type of the target successor task of the dynamic task, the connection relationship between each instance design task obtained after the instantiation of the dynamic task and the target predecessor task and the target successor task is determined, and the target dependency chain is determined based on the connection relationship.

4. The file generation method according to claim 3, characterized in that, The step of determining the connection relationship between each instance design task obtained after the instantiation of the dynamic task and the target preceding task and the target following task, based on the first task type of the target preceding task and the second task type of the target following task of the dynamic task, includes: In response to the fact that both the first task type of the target preceding task of the dynamic task and the second task type of the target following task of the dynamic task are fixed types, the target preceding task is determined as the preceding task of each instance design task obtained after the dynamic task is instantiated, and the target following task is determined as the following task of each instance design task. In response to the first task type of the target preceding task of the dynamic task being dynamic and / or the second task type of the target following task of the dynamic task being dynamic, according to preset judgment conditions, it is determined whether the dynamic task and the target preceding task and / or the target following task are of the same type of task, and the connection relationship between each instance design task obtained after the instantiation of the dynamic task and the target preceding task and / or the target following task is determined according to the judgment result; wherein, the preset judgment conditions include at least one of whether the selection of chip intellectual property core is consistent, whether the process voltage, temperature angle and operating conditions are consistent, and whether the process stages are consistent.

5. The file generation method according to claim 4, characterized in that, The step of determining the connection relationship between each instance design task obtained after the instantiation of the dynamic task and the target preceding task and / or the following task based on the judgment result includes: In response to the dynamic task and the target preceding task being of the same type, the preceding task of each instance design task obtained after instantiating the dynamic task is determined as the instance design task obtained after instantiating the target preceding task, which has the same chip intellectual property core selection type or the same process voltage temperature angle condition. In response to the dynamic task and the target subsequent task being of the same type, the subsequent tasks of each instance design task obtained after instantiating the dynamic task are determined as instance design tasks with the same chip intellectual property core selection type or the same process voltage temperature angle condition obtained after instantiating the target subsequent task.

6. The file generation method according to claim 4, characterized in that, The step of determining the connection relationship between each instance design task obtained after the instantiation of the dynamic task and the target preceding task and / or target following task based on the judgment result further includes: In response to the fact that the dynamic task and the target preceding task are not of the same type, the preceding tasks of each instance design task obtained after instantiating the dynamic task are determined as all instance design tasks obtained after instantiating the target preceding task. In response to the dynamic task and the target subsequent task not being of the same type, the subsequent tasks of each indeterminate design task obtained after instantiating the dynamic task are determined as all instance design tasks obtained after instantiating the target subsequent task.

7. A document generation device, characterized in that, include: The task partitioning module is used to divide chip design tasks into fixed tasks and dynamic tasks according to preset partitioning rules; wherein, the fixed tasks are tasks whose execution logic is fixed in the design flow; and the dynamic tasks are tasks whose execution logic changes in the design flow. An initial link generation module is used to determine the initial dependency link between the fixed task and the dynamic task based on a preset task dependency relationship. The target dependency link generation module is used to instantiate the dynamic task into several executable instance design tasks according to the configuration of preset parameters of the dynamic task, and replace the corresponding dynamic task with the instance design task in the initial dependency relationship link to obtain the target dependency relationship link, and build the build script file corresponding to the chip design process based on the target dependency relationship link.

8. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the file generation method according to any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause a processor to execute the file generation method of any one of claims 1-6.

10. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the file generation method according to any one of claims 1-6.

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