Neural network model processing method and apparatus, processing device, product, and medium

Abstract

Embodiments of the present application provide a neural network model processing method and device, processing equipment, product and medium, which are applied to the field of semiconductor technology. The method comprises: constructing a target regularization loss function, wherein the target regularization loss function comprises a target regularization term, and the target regularization term is a constraint term based on weighted punishment of the number of network layers in the neural network model; training the neural network model based on the target regularization loss function to obtain a target neural network model; obtaining a first weight matrix of the target neural network model, and generating an index table according to the first weight matrix, wherein the index table is used to record the index position of the weight with a value of zero in the first weight matrix; and mapping the non-zero weight in the first weight matrix to the physical address of the resistive random access memory (RRAM) array according to the index table to realize in-memory computing. By using the method, the storage space of the RRAM array can be effectively reduced and the in-memory computing efficiency can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a neural network model processing method, apparatus, processing equipment, product, and medium. Background Technology

[0002] With the rapid development of artificial intelligence technology, the scale of deep neural network models has expanded dramatically, leading to an exponential increase in computational load and data throughput.

[0003] In traditional von Neumann computing architectures, computation and storage units are physically separated. Frequent data movement between memory and computation leads to the severe memory wall problem, resulting in bottlenecks such as high power consumption, high latency, and limited bandwidth. To address this, in-memory computing technology has emerged as a highly efficient solution, aiming to eliminate data movement overhead by performing computations directly at the storage end. Among these technologies, resistive random access memory (RRAM), with its high density, non-volatility, and inherent advantages in analog computing, has become an ideal hardware platform for achieving efficient in-memory computing. A 1T1R array based on RRAM utilizes Kirchhoff's current law to perform vector-matrix multiplication (MAC) in parallel within the array with extremely low energy consumption, significantly improving the energy efficiency of artificial intelligence (AI) inference and frequently used to accelerate the inference process of neural networks.

[0004] However, with the continuous development of AI, the complexity of various neural network models is constantly increasing, and mapping their massive parameters to physical RRAM arrays faces huge hardware resource overhead. Although neural networks have high sparsity, they still contain a large number of weights with values ​​of zero or close to zero. In existing in-memory computing architectures, zero weights still need to occupy RRAM physical units for storage and computation, resulting in serious waste of hardware resources.

[0005] Therefore, existing technologies suffer from the problems of large storage space requirements and low in-memory computing efficiency of RRAM arrays. Summary of the Invention

[0006] This application provides a neural network model processing method, apparatus, processing device, product, and medium, which can effectively reduce the storage space occupied by RRAM arrays and improve in-memory computing efficiency.

[0007] To solve the above-mentioned technical problems, this application is implemented as follows: One embodiment of this application provides a neural network model processing method, the method comprising: Construct a target regularization loss function, wherein the target regularization loss function includes a target regularization term, which is a constraint term that performs weighted penalties based on the number of network layers in the neural network model; Based on the target regularization loss function, the neural network model is trained to obtain the target neural network model; Obtain the first weight matrix of the target neural network model, and generate an index table based on the first weight matrix, wherein the index table is used to record the index position of the weights with a value of zero in the first weight matrix; According to the index table, the non-zero weights in the first weight matrix are mapped to the physical addresses of the resistive memory array to realize in-memory computation.

[0008] In some embodiments, constructing the target regularization loss function includes: Obtain the first in the neural network model The second weight matrix of each network layer It is a positive integer; Perform the b-th power operation on each element in the second weight matrix to obtain the third weight matrix, where b represents the layer number; Determine the L1 norm of the third weight matrix; Multiplying the L1 norm by the Nth power of the layer number yields the th... The first regularization value of each network layer, where N is an integer greater than 1; The target regularization term is obtained by summing the first regularization values ​​of all network layers in the neural network model. The target regularization loss function is determined based on the original loss function of the neural network model and the target regularization term.

[0009] In some embodiments, an index table is generated based on the first weight matrix, including: Set the weight values ​​in the first weight matrix whose absolute values ​​are less than or equal to the sparse threshold to zero to obtain the fourth weight matrix; The index table is generated based on the elements with a weight value of 0 in the fourth weight matrix.

[0010] In some embodiments, mapping the non-zero weights in the first weight matrix to physical addresses of the resistive memory array according to the index table includes: Load the index table into the register group; Initialize the address counter, with an initial value of 0; Iterate through the logical indices of each network layer in the target neural network model and perform at least one of the following: If the first logical index exists in the register group, then continue traversing the next logical index after the first logical index; If the first logical index does not exist in the register group, the non-zero weight corresponding to the first logical index is written to the first physical address of the resistive memory array, and the address counter is incremented by 1. Wherein, the first logical index is any logical index of the network layer; The first physical address is calculated based on the address counter.

[0011] In some embodiments, the word line index of the first physical address is: the result of dividing the address counter by the array width of the resistive memory array and rounding down; The bit line index of the first physical address is the remainder of the address counter modulo the array width.

[0012] In some embodiments, the method further includes: Receive at least one activation vector; If the first logical index of the first activation vector does not exist in the register group, then the first activation vector is converted into an analog voltage, wherein the first activation vector is any one of the at least one activation vector; The analog voltage is applied to the first word line so that the resistive memory cell corresponding to the first word line participates in in-memory calculation. The resistive memory array includes a plurality of the resistive memory cells, and the first word line is the word line corresponding to the first logical index in the resistive memory array.

[0013] One embodiment of this application also provides a neural network model processing apparatus, the apparatus comprising: The function construction module is used to construct the target regularization loss function, wherein the target regularization loss function includes a target regularization term, which is a constraint term that performs weighted penalty based on the number of network layers in the neural network model; The model training module is used to train the neural network model based on the target regularization loss function to obtain the target neural network model; The information acquisition module is used to acquire the first weight matrix of the target neural network model and generate an index table based on the first weight matrix, wherein the index table is used to record the index position of the weights with a value of zero in the first weight matrix; The weight mapping module is used to map the non-zero weights in the first weight matrix to the physical addresses of the resistive memory array according to the index table, so as to realize in-memory computation.

[0014] One embodiment of this application also provides a processing device, which includes a processor, a memory, and a program stored in the memory and executable on the processor. When the program is executed by the processor, it implements the neural network model processing method as described above.

[0015] One embodiment of this application also provides a computer program product, including computer instructions, which, when executed by a processor, implement the steps of the neural network model processing method described above.

[0016] One embodiment of this application also provides a readable storage medium, wherein a program is stored on the readable storage medium, and when the program is executed by a processor, it implements the steps in the neural network model processing method as described in any of the preceding claims.

[0017] At least one of the above-mentioned technical solutions of this application has the following beneficial effects: In this embodiment, a loss function containing a target regularization term based on network layer weighting penalties is constructed. This loss function guides model training, resulting in a higher proportion of zero weights and increasing model sparsity. This achieves effective model compression while ensuring model inference accuracy. Furthermore, by generating an index table recording the zero-weight index positions and mapping only non-zero weights to the physical address of the RRAM array based on this index table, the hardware space waste problem in traditional in-memory computing is overcome. This significantly improves array storage density and hardware resource utilization, thereby achieving synergistic optimization of model compression rate and hardware storage efficiency, reducing hardware consumption, and improving the efficiency of in-memory computing. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of vector-matrix multiplication based on an RRAM array according to an embodiment of this application; Figure 2 This is a schematic diagram of a 1T1R array structure for in-memory computing according to an embodiment of this application; Figure 3 This is a schematic diagram of the SET process of a 1T1R array memory cell according to an embodiment of this application; Figure 4 This is a schematic diagram of the RESET process of a 1T1R array memory cell according to an embodiment of this application; Figure 5 This is a flowchart illustrating a neural network model processing method according to an embodiment of this application; Figure 6 This is a circuit mapping effect diagram of a neural network model compressed based on hybrid regularization according to an embodiment of this application; Figure 7 This is a schematic diagram of the neural network weight mapping for a sparse index according to an embodiment of this application; Figure 8 This is a schematic diagram of the neural network weight mapping in a 1T1R RRAM array according to an embodiment of this application; Figure 9 This is a schematic diagram of the read mode of a 1T1R array memory cell according to an embodiment of this application; Figure 10 This is a schematic diagram of the computing mode of a 1T1R array memory cell according to an embodiment of this application; Figure 11 This is a schematic diagram illustrating the optimized model mapped to an RRAM array to reduce resource usage according to an embodiment of this application. Figure 12 This is a schematic diagram of the structure of a neural network model processing device according to an embodiment of this application; Figure 13 This is a schematic diagram of the structure of a processing device according to an embodiment of this application. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms "an" or "a," and similar terms, do not indicate a quantity limitation, but rather indicate the presence of at least one.

[0021] Related technical introduction: With the advent of the big data era, the amount of computing has increased dramatically, which has placed higher demands on the speed, density, power consumption and cost of high-performance computing. The computing architecture based on von Neumann is facing the memory wall problem.

[0022] In the von Neumann computing architecture, the separation of storage and computation requires frequent data transfer, resulting in significant energy loss and signal delay, which in turn leads to increased chip power consumption and reduced computational efficiency.

[0023] To address these challenges, the concept of in-memory computing emerged, which reduces data movement by performing computations directly within memory cells, thereby improving energy efficiency and accelerating data processing. Based on this, non-volatile memory, with its high density and low power consumption, has become an ideal choice for realizing in-memory computing. Here, non-volatile memory refers to phase-change random access memory (PCRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), and rRAM, among others.

[0024] like Figure 1 As shown, after the weights (i.e., weight values) are written into the RRAM array, the weights are stored in the memory cells of the RRAM array. Figure 1 In the process, the devices are organized into an array. During the in-memory calculation stage, the input voltage from one end of the array is used as the input for vector matrix multiplication. The devices in the array perform calculations using Ohm's law and Kirchhoff's law. The current obtained at the other end of the array is the sum of the vector matrix multiplication results.

[0025] To address the current leakage problem in a 1R array, a selection device (such as a transistor or selector) connected in series with the RRAM is needed to form a 1T1R array. The function of this selection device is to select a specific resistor and isolate it from the influence of other cells.

[0026] See Figure 2 This paper demonstrates a 1T1R array of resistive memory. In the 1T1R array, the word line (WL) is connected to the gate of the transistor. Applying a voltage to the word line can select a specific resistive device and also control the current flowing through the resistive device. The source line (SL) is connected to the source of the transistor. The bit line (BL) is connected to the drain of the transistor via a resistive device.

[0027] See Figure 3 This demonstrates the SET process of a 1T1R array memory cell in one embodiment. The 1T1R array can read from and write to memory cells. Here, we take writing to multiple memory cells (M11, M12, M13...M1n) simultaneously as an example, writing to the corresponding word line WL... <1> Applying a high-level voltage VWL turns on all the corresponding gating transistors (M11, M12, M13…M1n) for that row, enabling the access path to the memory cell; this is done via the bit line (BL). <0> BL <1> BL <2> …BL <n>Apply a high write voltage VBL to the source line (SL) <0> , SL <1> , SL <2> …SL <n>When grounded, the current flows from (BL) <0> BL <1> BL <2> …BL <n>The current flows through the conducting transistor and then through the corresponding RRAM device, from the source line (SL) <0> , SL <1> , SL <2> …SL <n>The current flows to ground, and the current flow generates ion migration inside the device, thereby changing the RRAM cell from a high-resistance state to a low-resistance state, completing the SET process of (M11, M12, M13...M1n) and realizing the writing of data "1".

[0028] See Figure 4 This demonstrates the RESET process of a 1T1R array memory cell in one embodiment. Similarly, the process is described in WL. <1> Apply a high level VWL to make (M11, M12, M13...M1n) all conduct, (BL) <0> BL <1> BL <2> …BL <n>All are grounded, (SL) <0> , SL <1> , SL <2> …SL <n>Connect VSL, and the current flows from the source terminal (SL). <0> , SL <1> , SL <2> …SL <n>) flows through the storage unit to the bit line end (BL) <0> BL <1> BL <2> …BL <n>The current flows to ground. At this time, the reverse current triggers the oxygen vacancy or metal wire breakage mechanism, causing the RRAM cell to change from a low resistance state to a high resistance state, completing the RESET process of (M11, M12, M13...M1n) and realizing the writing of data "0".

[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0030] This application addresses the problems of large storage space occupation and low in-memory computing efficiency of existing RRAM arrays by providing a neural network model processing method, apparatus, processing equipment, product, and medium.

[0031] like Figure 5 As shown, one embodiment of this application provides a neural network model processing method, the method comprising: Step 501: Construct a target regularization loss function, wherein the target regularization loss function includes a target regularization term, which is a constraint term that performs weighted penalties based on the number of network layers in the neural network model.

[0032] Here, the objective regularization term can force the weights in the deep network structure to become zero, so that when the weights are mapped to the RRAM array in the subsequent process, the storage and computation of these zero weights can be saved, thereby greatly reducing the number of weights mapped to the storage hardware and reducing the model's storage requirements and computational costs.

[0033] Step 502: Based on the target regularization loss function, train the neural network model to obtain the target neural network model.

[0034] Step 503: Obtain the first weight matrix of the target neural network model, and generate an index table based on the first weight matrix, wherein the index table is used to record the index position of the weights with a value of zero in the first weight matrix.

[0035] Step 504: According to the index table, map the non-zero weights in the first weight matrix to the physical addresses of the resistive memory array to realize in-memory computation.

[0036] In this embodiment, a loss function containing a target regularization term based on network layer weighting penalties is constructed. This loss function guides model training, resulting in a higher proportion of zero weights and increasing model sparsity. This achieves effective model compression while ensuring model inference accuracy. Furthermore, by generating an index table recording the zero-weight index positions and mapping only non-zero weights to the physical address of the RRAM array based on this index table, the hardware space waste problem in traditional in-memory computing is overcome. This significantly improves array storage density and hardware resource utilization, thereby achieving synergistic optimization of model compression rate and hardware storage efficiency, reducing hardware consumption, and improving the efficiency of in-memory computing.

[0037] In this embodiment of the application, the constructed target regularization loss function is a hybrid regularization function. The target regularization term contained in this function combines L1 regularization and regularization that takes into account hardware mapping (that is, a constraint term that performs weighted penalty based on the number of network layers in the neural network model).

[0038] In some specific embodiments, step 501 above, namely constructing the target regularization loss function, specifically includes the following steps: Step 5011, obtain the first... The second weight matrix of each network layer It is a positive integer.

[0039] Step 5012: Perform the b-th power operation on each element in the second weight matrix to obtain the third weight matrix, where b represents the layer number.

[0040] Step 5013: Determine the L1 norm of the third weight matrix.

[0041] Step 5014: Multiply the L1 norm by the Nth power of the layer number to obtain the th... The first regularization value of each network layer, where N is an integer greater than 1.

[0042] Step 5015: Summate the first regularization values ​​of all network layers in the neural network model to obtain the target regularization term.

[0043] For example, suppose a neural network model has Each network layer ( (where is the total number of network layers), and the weight matrix of each layer is represented as follows: Then the target regularization term can be expressed as:

[0044] in, Indicates the first The weight matrix of the layer, Indicates the number of layers in the network.

[0045] In this objective regularization term, the core regularization function uses the L1 norm to promote the sparsity of the model, and the weights are weighted hierarchically by powers of the number of network layers (i.e., the number of network layers in the neural network model).

[0046] The objective regularization term aims to improve the weight matrix by adjusting the weight matrix. Each element executes The sparsity is increased by raising the power of the term, which allows smaller weight values ​​to approach zero while retaining larger weight values. Then, the L1 norm of these weight matrices is calculated. The L1 norm tends to produce a sparse weight distribution during optimization because it imposes a large penalty on small weights, thus introducing a large number of zero weights into the model. Furthermore, the entire regularization term is multiplied... As the network depth increases, the regularization’s ability to improve weight sparsity is enhanced in a superlinear manner by powers of (e.g., squares).

[0047] This objective regularization term forces the weights in the deep network structure to become zero, so that when the weights are mapped to the RRAM array, the storage and computation of these zero weights can be saved. This significantly reduces the number of weights mapped to the storage hardware, thereby reducing the model's storage requirements and computational costs.

[0048] Step 5016: Determine the target regularization loss function based on the original loss function of the neural network model and the target regularization term.

[0049] For example, the target regularization loss function L is the original loss function. The sum of the regularization term R and the target regularization loss function L can be expressed as:

[0050] By employing this objective regularization loss function L, hybrid regularization compression of neural network models can be achieved. Compared to structured pruning, this compression process does not require repeated training; and compared to unstructured pruning, it can effectively reduce hardware overhead.

[0051] After compression, the neural network model can be retrained and evaluated. Through experiments and data analysis, the regularization coefficient b in the target regularization term can be optimized. The performance and compression effect of the compressed model can be evaluated through a validation dataset. This ensures that the compression optimization will not have a negative impact on the accuracy of the model, and provides a reliable guarantee for effectively mapping the weights to the RRAM array and achieving optimal model performance and maximum utilization of hardware resources.

[0052] See Figure 6 This paper demonstrates the ideal performance of a neural network model compression method based on hybrid regularization. The goal of this model compression is to generate more rows or columns of all zeros in the first weight matrix, thereby saving hardware resources by discarding stored zeros.

[0053] In some embodiments, an index table is generated based on the first weight matrix, including: Step 1: Set the weight values ​​in the first weight matrix whose absolute values ​​are less than or equal to the sparse threshold to zero to obtain the fourth weight matrix.

[0054] It should be noted that after performing hybrid regularization compression on the neural network model in the above embodiments, the resulting first weight matrix will still contain a small number of weight values ​​that are close to or absolutely zero. To ensure hardware compatibility, a sparsity threshold can be set to uniformly set all weight values ​​in the first weight matrix that are less than this threshold to zero.

[0055] Step 2: Generate the index table based on the elements with a weight value of 0 in the fourth weight matrix.

[0056] Here, the index table can record the weight index positions of all weight values ​​of 0, such as [0, 2, 6, 11, 100, 1023, ...].

[0057] As an optional embodiment, a binary mask array (sparse mask) can be generated as an index table, where the mask record format can be a one-dimensional Boolean array or an index array. For example, when loading into the hardware, the index table format (sparse index) is preferred to reduce the amount of data transmitted and improve the hardware parsing efficiency.

[0058] In some embodiments, mapping the non-zero weights in the first weight matrix to the physical addresses of the resistive memory array according to the index table includes the following steps: Step 1: Load the index table into the register group.

[0059] Here, when exporting the model, the index table can be parsed and written to the hardware's reg_zero_index[] register group.

[0060] Step 2: Initialize the address counter, with an initial value of 0.

[0061] Here, the address counter is initialized to 0. During the weight mapping process to the RRAM array, this address counter is used to calculate which physical address in the RRAM array the weight will be mapped to.

[0062] Step 3: Traverse the logical indices of each network layer in the target neural network model and perform at least one of the following: (1) If the first logical index exists in the register group, then continue traversing the next logical index after the first logical index. Here, the first logical index is any logical index of the network layer.

[0063] (2) If the first logical index does not exist in the register group, the non-zero weight corresponding to the first logical index is written to the first physical address of the resistive memory array, and the address counter is incremented by 1; wherein, the first logical index is any logical index of the network layer; the first physical address is calculated based on the address counter.

[0064] Here, we will take a typical 1T1R array of size 1024×1024 as an example for a detailed explanation.

[0065] Suppose that the weights of a certain layer in a neural network model are 512×512 (i.e., 262144 parameters). After compression, only about 10% of the parameters are zero (about 26214). The remaining part is written into RRAM in sequence. The specific mapping process is as follows: like Figure 7 As shown, for each logical index i∈ [0,262143], if i∈reg_zero_index[], it is skipped and not written; otherwise, the corresponding weight w[i] is written to the first physical address of the RRAM array.

[0066] In an optional example, the word line index of the first physical address is: the result of dividing the address counter by the array width of the resistive memory array and rounding down; the bit line index of the first physical address is: the remainder of the address counter modulo the array width.

[0067] Here, still taking the 1T1R array of size 1024×1024 as an example, the two-dimensional mapping of the first physical address is: row = addr_cnt / 1024 col = addr_cnt % 1024. Where 1024 is the array width of the 1T1R array, and addr_cnt is the address counter, which is initially 0 and increments by 1 after each write operation.

[0068] The following table lists relevant data for a specific embodiment, along with specific examples illustrating the data:

[0069] Taking the data shown in the table as an example, the register group contains: reg_zero_index[0] = 0; reg_zero_index[1] = 2. That is, the original indices 0 and 2 exist in the register group.

[0070] Therefore, when writing weight values ​​to the RRAM array, the traversal starts from the original index 0.

[0071] For example, if the first logical index being traversed is 0, since 0 exists in the register group, the next logical index after the first logical index is traversed, which is to traverse the original index 1; at this time, the address counter (addr_cnt) remains unchanged and is still the initial value 0.

[0072] If the first logical index of the current traversal is 1, since 1 does not exist in the register group, the non-zero weight corresponding to 1 (i.e., 2, which is the value of w[1]) is written to the first physical address of the RRAM array. At this time, addr_cnt = 0: Write w[1] → WL <0> BL <0> That is, the value of w[1] is written to the physical array coordinates (0, 0). After writing, the address counter is incremented by 1, and the address counter becomes 1.

[0073] If the first logical index being traversed is 2, since 2 exists in the register group, the next logical index after the first logical index is traversed, which is the original index 3. At this time, the address counter (addr_cnt) remains unchanged and is still 1.

[0074] If the first logical index of the current traversal is 3, since 3 does not exist in the register group, the non-zero weight corresponding to 3 (i.e., -2.1, which is the value of w[3]) is written to the first physical address of the RRAM array. At this time, addr_cnt = 1: Write w[3] → WL <0> BL <1> That is, the value of w[3] is written to the physical array coordinates (0, 1). After writing, the address counter is incremented by 1, and the address counter becomes 2.

[0075] In some embodiments, the method further includes: receiving at least one activation vector; if the first logical index of the first activation vector does not exist in the register group, converting the first activation vector into an analog voltage, wherein the first activation vector is any one of the at least one activation vector; applying the analog voltage to a first word line so that the resistive memory cell corresponding to the first word line participates in in-memory computation, wherein the resistive memory array includes a plurality of the resistive memory cells, and the first word line is: the word line corresponding to the first logical index in the resistive memory array.

[0076] In this embodiment, the sparse mask obtained through training (output in the form of an index table) works in conjunction with the hardware mapping logic to achieve minimal storage write and computation operations, which can effectively improve the system's energy efficiency ratio and computational density.

[0077] During the in-memory computation phase, the input activation vectors x[i] are loaded in logical order. The controller can determine whether the first logical index i of the current first activation vector x[i] is a valid computation channel based on the reg_zero_index[] mask table (which is the index table loaded into the register group). If i ∈ reg_zero_index[], then no WL voltage is applied; otherwise, the first activation vector x[i] is loaded into the WL channel, so that the weight at the RRAM physical address corresponding to the first activation vector x[i] participates in the computation.

[0078] Here, the main computational process can be represented in the form of matrix-vector multiplication. Utilizing this characteristic, efficient in-memory computation can be achieved through the cross-array of RRAM. See also... Figure 8 This example demonstrates how to map convolutional kernel weights in a neural network model onto an RRAM array circuit. Here, the convolutional kernel weights are sequentially unfolded into one dimension and mapped column-wise to the RRAM cross-array. Taking image data processing as an example, assuming there are three weight value types: R, G, and B, these weight values ​​are sequentially written to each cross-point of the RRAM array, and the corresponding conductance values ​​are denoted as... This mapping method ensures efficient data storage and effectively reduces data transfer requirements by performing calculations directly within the RRAM array.

[0079] In a 1T1R storage array, precise control of individual storage cells can be achieved, making read and write operations more efficient.

[0080] For details, please see Figure 3 and Figure 4 The two examples respectively demonstrate the process of writing weight value 1 and weight value 0 to the storage unit. Figure 9 Demonstrates the read modes of the 1T1R array storage unit, and... Figure 3 The SET process shown in the image is similar, where the word line WL of the memory cell to be operated on is selected, and then a small positive polarity voltage is applied between the bit line BL and the source line SL to activate the read bit line (BL). <1> BL <2> ,…,BL <n>The clamping is based on the read voltage (VREAD), and the weight is determined by the magnitude of the current flowing through the memory cell.

[0081] Please see Figure 10 This demonstrates the computational pattern of a 1T1R array memory cell. Weights Mapped to RRAM conductance value Input vector Converted to RRAM input voltage And it is sent to each row of the cross array. When x is represented by a pulse, according to Ohm's law, the current flowing through each device is: Therefore, according to Kirchhoff's current law, the total current collected in each column is: According to the mapping relationship, it can be derived from... I SL Inverse solution yields .

[0082] Here, taking digital RRAM array in-memory computing as an example, multiple storage units are stored according to certain encoding rules. bit weight data, image pixel data from (WL) <1> WL <2> ,…,WL <n>The input is periodically processed, and the selected RRAM memory cell in the calculation array is clamped at a small read voltage. Depending on the input and memory weights, each SL (Search Column) will sum the current on that column of RRAM, thus completing the in-memory calculation. Therefore, the read result of each column is compared with the input value (…). , ,……, ) and stored value ( , ,……, The vector dot product of the input vectors and the weight matrix has a certain correspondence. For the entire RRAM array, the output vector is mapped to the result of multiplying the input vector and the weight matrix.

[0083] like Figure 11 The diagram illustrates the process by which the optimized neural network model (i.e., the target neural network model) is mapped into the RRAM array circuit via a sparse index module. In this diagram, colored blocks represent convolutional kernel weights, and uncolored blocks represent data 0, visually demonstrating the effective saving of storage resources after hybrid regularization optimization and compression using the neural network model processing method provided in this embodiment. This method effectively integrates the regularized optimized neural network model into RRAM technology, saving storage resources and improving computational efficiency.

[0084] The following provides specific examples illustrating the solutions provided in the embodiments of this application.

[0085] In a specific embodiment of this application, with general image classification as the target, the neural network model processing method provided in this application is used to perform hybrid regularized neural network model compression, and combined with 1T1R RRAM in-memory computing circuit, to achieve high sparsity, low power consumption, and high energy efficiency neural network inference. The specific process is as follows: First, ResNet18 can be selected as the image classification model (i.e., the neural network model in the above embodiments). During training, a standard dataset (such as CIFAR-10) is used, and the input resolution is set. Data augmentation methods (such as random cropping, flipping, normalization, etc.) can be used to improve the model's generalization ability to adapt to image classification needs in different scenarios.

[0086] In the target neural network model, the hyperparameter λ of the L1 regularization term can be set to a range of 0.01~0.05, and the sparse coefficients of the weights in the deep network increase proportionally to the square of the layer number; the optimizer can be Adam, with an initial learning rate set to 10. -3 The input image is normalized to 8-bit fixed-point numbers, and its decay is reduced to 0.5 times every 30 epochs.

[0087] Retraining and evaluation are performed on the compressed model (i.e., the target neural network model) to ensure that the model compression process does not significantly affect the model accuracy. Testing on the validation set ensures that the compressed model achieves the required accuracy during inference.

[0088] After model training is complete, the target neural network model automatically generates a sparse mask to identify the index positions where all weights are zero. This mask is exported in an index table format, resulting in the aforementioned index table. The index table is loaded into the reg_zero_index[] register group on the hardware side via an interface. This index table can guide the hardware to skip the write operation and subsequent calculation at the positions corresponding to weights with zero values, effectively reducing the number of writes, hardware storage usage, and computational power consumption.

[0089] In this embodiment, an optional implementation of the hardware mapping and in-memory computing circuitry is as follows: The 1T1R array has an array size of 1024×1024 (i.e., an array width of 1024), a word line (WL) drive voltage range of 3~3.3 V, and a bit line / source line voltage range of 2~2.5 V.

[0090] In weighted write operations, a step-by-step control strategy can be adopted: For non-zero weight writes (SET process), a voltage of 3.3V can be applied to the word line, a voltage of 2.0 to 2.5V can be applied to the bit line, the source line can be grounded, and a programming pulse of 50 to 100ns can be applied; for zero weight writes (RESET process), a voltage of 3.3V can be applied to the word line, a voltage of 2.5 to 2.8V can be applied to the source line, the bit line can be grounded, and an erase pulse of 100 to 200ns can be applied.

[0091] Here, in order to optimize system performance, a sparse index mapping module can be combined to implement a sparse write strategy, which means skipping the zero-weight positions marked in the mask (i.e., the index table) to reduce the number of writes and energy consumption.

[0092] The regularized compressed model weights (i.e., the first weight matrix mentioned above) are mapped to a resistive memory (such as RRAM) array. See [link to relevant documentation] for details. Figure 8 The weights of each network layer can be unfolded into a one-dimensional vector and mapped column-wise to the intersections of the RRAM array, where each intersection represents the conductance value of an RRAM cell, through the SET process described above (see...). Figure 3 ) and the RESET procedure (see Figure 4 Write to the hardware array.

[0093] In-memory calculation process as follows Figure 10 As shown, the system can employ an 8-bit digital-to-analog converter (DAC) to convert the input pixel data into an analog voltage signal in the range of 0–1V, and input it to the array word lines to perform matrix multiplication and addition operations. Specifically, the current signal output from the bit lines is converted into a voltage signal via a gain-adjustable transimpedance amplifier. In the post-processing stage, the system uses a comparator circuit with a threshold set on the order of 0.1V to implement an activation function (such as ReLU).

[0094] Preliminary validation was performed on typical networks (ResNet18, VGG16, etc.) and typical datasets (CIFAR10, MNIST, CIFAR100). Through the hardware encoding module, the accuracy loss can be controlled within the range of approximately 1% to 2%, achieving 80% to 90% storage compression.

[0095] In the above embodiments, the chaotic principle of neural networks is utilized, and special regularization is used to adjust the distribution of network weights. While ensuring network accuracy, the sparsity of weights is significantly enhanced, and the weights with a value of 0 tend to be concentrated in the distribution. This reduces the storage requirements when mapped to the hardware RRAM circuit, reduces the consumption of hardware resources, and maps the compressed model to a non-volatile memory array for more efficient in-memory computation.

[0096] For the compressed sparse structure model, this application further proposes a sparse index mapping module to quickly identify zero-weight positions on the hardware side and skip their writing and computation, thereby further improving system efficiency in terms of hardware resource management and power consumption. This module, based on the sparse mask (i.e., index table) output from the training side, loads the positions of zero-value weights into the control register in index form, and selectively activates effective weight paths during RRAM writing and computation stages, realizing a hardware-software co-operational sparse acceleration mechanism. Thus, after processing the neural network model using the neural network model processing method provided in this application, most of the hardware requirements can be reduced. Only a small number of weights need to be stored to complete the inference process based on in-memory computation. This is suitable for in-memory computation using non-volatile memory and can effectively improve the efficiency of in-memory computation.

[0097] The neural network model processing method described in this application takes into account the hardware mapping requirements during model training. By constructing a loss function that includes a target regularization term based on network layer weighting penalties, it effectively overcomes the constraints of high-dimensional complexity in neural networks. This method directionally induces network weights to cluster towards a large number of zero values, eliminating the need for storing and calculating these zero-value weights during weight mapping without affecting network accuracy. Thus, the hardware mapping-oriented constraint design introduced during the training phase eliminates the need for repeated iterative training of the compressed model, achieving extreme sparsity of weights while ensuring model inference accuracy. This solves the problems of rapid accuracy degradation in traditional unstructured pruning and poor hardware adaptability in structured pruning. Furthermore, by parsing the sparse mask of the training output into an index table and loading it into the hardware control register, it achieves the elimination of zero weights in physical storage space and the continuous and compact arrangement of non-zero weights, significantly improving the storage density and hardware resource utilization of the RRAM array. During the in-memory computation phase, the controller can quickly identify zero-weight channels based on the sparse index table and selectively skip the computation and writing of invalid paths. This hardware-software co-operational sparse acceleration mechanism not only eliminates the invalid energy consumption and dynamic computing power consumption corresponding to zero weights in the RRAM array from the physical source, but also achieves a comprehensive improvement in the storage compactness, system energy efficiency ratio and computing throughput of the neural network inference system by significantly reducing the physical occupation of hardware resources.

[0098] like Figure 12 As shown, one embodiment of this application also provides a neural network model processing device, the device comprising: The function construction module 1210 is used to construct a target regularization loss function, wherein the target regularization loss function includes a target regularization term, which is a constraint term that performs weighted penalty based on the number of network layers in the neural network model; The model training module 1230 is used to train the neural network model based on the target regularization loss function to obtain the target neural network model; The information acquisition module 1230 is used to acquire the first weight matrix of the target neural network model and generate an index table based on the first weight matrix, wherein the index table is used to record the index position of the weights with a value of zero in the first weight matrix; The weight mapping module 1240 is used to map the non-zero weights in the first weight matrix to the physical addresses of the resistive memory array according to the index table, so as to realize in-memory computation.

[0099] In this embodiment, a loss function containing a target regularization term based on network layer weighting penalties is constructed. This loss function guides model training, resulting in a higher proportion of zero weights and increasing model sparsity. This achieves effective model compression while ensuring model inference accuracy. Furthermore, by generating an index table recording the zero-weight index positions and mapping only non-zero weights to the physical address of the RRAM array based on this index table, the hardware space waste problem in traditional in-memory computing is overcome. This significantly improves array storage density and hardware resource utilization, thereby achieving synergistic optimization of model compression rate and hardware storage efficiency, reducing hardware consumption, and improving the efficiency of in-memory computing.

[0100] In some embodiments, the function construction module 1210 includes: The matrix acquisition unit is used to acquire the matrix of the neural network model. The second weight matrix of each network layer It is a positive integer; The first processing unit is used to perform a power b operation on each element in the second weight matrix to obtain a third weight matrix, where b represents the layer number. The norm solving unit is used to determine the L1 norm of the third weight matrix; The second processing unit is used to multiply the L1 norm by the Nth power of the layer number to obtain the first... The first regularization value of each network layer, where N is an integer greater than 1; The third processing unit is used to sum the first regularization values ​​of all network layers in the neural network model to obtain the target regularization term. The fourth processing unit is used to determine the target regularization loss function based on the original loss function of the neural network model and the target regularization term.

[0101] In some embodiments, the information acquisition module 1230 includes: A matrix processing unit is used to set the weight values ​​in the first weight matrix whose absolute values ​​are less than or equal to the sparse threshold to zero, thereby obtaining a fourth weight matrix. The index table generation unit is used to generate the index table based on the elements with a weight value of 0 in the fourth weight matrix.

[0102] In some embodiments, the weight mapping module 1240 includes: An index table loading unit is used to load the index table into the register group; An initialization unit is used to initialize an address counter, wherein the initial value of the address counter is 0; The fifth processing unit is used to traverse the logical indices of each network layer in the target neural network model and perform at least one of the following: If the first logical index exists in the register group, then continue traversing the next logical index after the first logical index; If the first logical index does not exist in the register group, the non-zero weight corresponding to the first logical index is written to the first physical address of the resistive memory array, and the address counter is incremented by 1. Wherein, the first logical index is any logical index of the network layer; The first physical address is calculated based on the address counter.

[0103] In some embodiments, the word line index of the first physical address is: the result of dividing the address counter by the array width of the resistive memory array and rounding down; The bit line index of the first physical address is the remainder of the address counter modulo the array width.

[0104] In some embodiments, the apparatus further includes: A vector receiving module for receiving at least one activation vector; A vector conversion module is used to convert the first activation vector into an analog voltage if the first logical index of the first activation vector does not exist in the register group, wherein the first activation vector is any one of the at least one activation vector; A voltage application module is used to apply the analog voltage to a first word line so that the resistive memory cell corresponding to the first word line participates in in-memory calculation. The resistive memory array includes a plurality of the resistive memory cells, and the first word line is the word line corresponding to the first logical index in the resistive memory array.

[0105] The apparatus provided in this application embodiment can execute the above method embodiment, and its implementation principle and technical effect are similar, so it will not be described again here.

[0106] Please refer to Figure 13 This disclosure also provides a processing device 1300, including a processor 1301, a memory 1302, and a computer program stored in the memory 1302 and executable on the processor 1301. When the computer program is executed by the processor 1301, it implements the various processes of the above-described neural network model processing method embodiments and achieves the same technical effect. To avoid repetition, it will not be described again here.

[0107] This disclosure also provides a computer-readable storage medium storing a computer program. When executed by a processor, the computer program implements the various processes of the above-described neural network model processing method embodiments and achieves the same technical effects. To avoid repetition, it will not be described again here. The computer-readable storage medium may include, for example, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0108] This application also provides a computer program product, including computer instructions. When these computer instructions are executed by a processor, they implement the various processes of the above method embodiments and achieve the same technical effects. To avoid repetition, they will not be described again here.

[0109] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0110] It should be noted that many of the functional components described in this specification are referred to as modules / submodules in order to more specifically emphasize the independence of their implementation.

[0111] In this application embodiment, the module / submodule can be implemented in software so that it can be executed by various types of processors. For example, an identified executable code module may include one or more physical or logical blocks of computer instructions, which may be constructed as objects, procedures, or functions. Nevertheless, the executable code of the identified module does not need to be physically located together, but may include different instructions stored in different bits, which, when logically combined, constitute the module and achieve the module's intended purpose.

[0112] In practice, an executable code module can be a single instruction or many instructions, and can even be distributed across multiple different code segments, different programs, and across multiple memory devices. Similarly, operational data can be identified within the module and can be implemented in any suitable form and organized within any suitable data structure. This operational data can be collected as a single dataset or distributed across different locations (including different storage devices), and can exist, at least in part, solely as electronic signals within the system or network.

[0113] When a module can be implemented using software, considering the current level of hardware technology, modules that can be implemented in software can be implemented using hardware circuits by those skilled in the art to achieve the corresponding functions, without considering cost. These hardware circuits include conventional very-large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors such as logic chips and transistors, or other discrete components. Modules can also be implemented using programmable hardware devices, such as field-programmable gate arrays, programmable array logic, and programmable logic devices.

[0114] The above describes the preferred embodiments of this application. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles described in this application, and these improvements and modifications should also be considered within the scope of protection of this application.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A method for processing neural network models, characterized in that, The method includes: Construct a target regularization loss function, wherein the target regularization loss function includes a target regularization term, which is a constraint term that performs weighted penalties based on the number of network layers in the neural network model; Based on the target regularization loss function, the neural network model is trained to obtain the target neural network model; Obtain the first weight matrix of the target neural network model, and generate an index table based on the first weight matrix, wherein the index table is used to record the index position of the weights with a value of zero in the first weight matrix; According to the index table, the non-zero weights in the first weight matrix are mapped to the physical addresses of the resistive memory array to realize in-memory computation.

2. The neural network model processing method according to claim 1, characterized in that, The construction of the target regularization loss function includes: Obtain the first in the neural network model The second weight matrix of each network layer It is a positive integer; Perform the b-th power operation on each element in the second weight matrix to obtain the third weight matrix, where b represents the layer number; Determine the L1 norm of the third weight matrix; Multiplying the L1 norm by the Nth power of the layer number yields the th... The first regularization value of each network layer, where N is an integer greater than 1; The target regularization term is obtained by summing the first regularization values ​​of all network layers in the neural network model. The target regularization loss function is determined based on the original loss function of the neural network model and the target regularization term.

3. The neural network model processing method according to claim 1 or 2, characterized in that, The step of mapping the non-zero weights in the first weight matrix to the physical addresses of the resistive memory array according to the index table includes: Load the index table into the register group; Initialize the address counter, with an initial value of 0; Iterate through the logical indices of each network layer in the target neural network model and perform at least one of the following: If the first logical index exists in the register group, then continue traversing the next logical index after the first logical index; If the first logical index does not exist in the register group, the non-zero weight corresponding to the first logical index is written to the first physical address of the resistive memory array, and the address counter is incremented by 1. Wherein, the first logical index is any logical index of the network layer; The first physical address is calculated based on the address counter.

4. The neural network model processing method according to claim 3, characterized in that, The word line index of the first physical address is the result of dividing the address counter by the array width of the resistive memory array and rounding down. The bit line index of the first physical address is the remainder of the address counter modulo the array width.

5. The neural network model processing method according to claim 3, characterized in that, The method further includes: Receive at least one activation vector; If the first logical index of the first activation vector does not exist in the register group, then the first activation vector is converted into an analog voltage, wherein the first activation vector is any one of the at least one activation vector; The analog voltage is applied to the first word line so that the resistive memory cell corresponding to the first word line participates in in-memory calculation. The resistive memory array includes a plurality of the resistive memory cells, and the first word line is the word line corresponding to the first logical index in the resistive memory array.

6. The neural network model processing method according to claim 1 or 2, characterized in that, Based on the first weight matrix, an index table is generated, including: Set the weight values ​​in the first weight matrix whose absolute values ​​are less than or equal to the sparse threshold to zero to obtain the fourth weight matrix; The index table is generated based on the elements with a weight value of 0 in the fourth weight matrix.

7. A neural network model processing device, characterized in that, The device includes: The function construction module is used to construct the target regularization loss function, wherein the target regularization loss function includes a target regularization term, which is a constraint term that performs weighted penalty based on the number of network layers in the neural network model; The model training module is used to train the neural network model based on the target regularization loss function to obtain the target neural network model; The information acquisition module is used to acquire the first weight matrix of the target neural network model and generate an index table based on the first weight matrix, wherein the index table is used to record the index position of the weights with a value of zero in the first weight matrix; The weight mapping module is used to map the non-zero weights in the first weight matrix to the physical addresses of the resistive memory array according to the index table, so as to realize in-memory computation.

8. A processing apparatus, characterized in that, It includes a processor, a memory, and a program stored in the memory and executable on the processor, wherein the program, when executed by the processor, implements the neural network model processing method as described in any one of claims 1 to 6.

9. A computer program product, characterized in that, It includes computer instructions that, when executed by a processor, implement the steps of the neural network model processing method as described in any one of claims 1 to 6.

10. A readable storage medium, characterized in that, The readable storage medium stores a program that, when executed by a processor, implements the steps of the neural network model processing method as described in any one of claims 1 to 6.

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