Method and device for diagnosing silicon wafer edge chamfer, model training method and medium

Abstract

This disclosure provides a diagnostic method, apparatus, model training method, and medium for chamfering the edge of a silicon wafer. The method includes acquiring a time-series signal of the edge of a target silicon wafer, wherein the time-series signal is an edge morphology feature signal acquired synchronously with the rotation angle of the silicon wafer; inputting the time-series signal into a preset time-series pattern recognition model to obtain a defect diagnosis result for the edge of the target silicon wafer, wherein the defect diagnosis result includes at least a defect classification label and the angle range corresponding to the defect classification label in the time-series signal; wherein the time-series pattern recognition model is obtained through progressive training using a multi-stage training dataset, and the data complexity of the multi-stage training dataset exhibits a phased increasing trend based on the signal-to-noise ratio and mixing degree of the silicon wafer edge defect signal.

Description

Technical Field

[0001] This disclosure relates to the field of defect detection technology, and in particular to a diagnostic method, apparatus, model training method and medium for chamfering the edge of a silicon wafer. Background Technology

[0002] In semiconductor manufacturing processes, the quality of silicon wafer edge chamfering directly affects the stability and product yield of subsequent processes such as grinding, polishing, and cleaning. It is one of the key processes affecting the overall yield of silicon wafer products and the stability of subsequent grinding processes. Currently, the industry generally uses automated optical inspection methods to detect the quality of silicon wafer edge chamfering. This involves acquiring silicon wafer edge contour or image data through devices such as laser displacement sensors and vision sensors, and then comparing the detection data with preset geometric tolerance thresholds, outputting only a binary judgment result of pass or fail.

[0003] Existing detection methods have significant technical limitations. They can only determine whether the chamfering of silicon wafer edges is out of tolerance, but cannot identify the specific type of defect, resulting in a lack of targeted process adjustments and troubleshooting. The utilization of raw signals collected by sensors is low, with only a small number of geometric features extracted, leaving a large amount of effective information unused. In industrial scenarios with a small number of defect samples, uneven distribution of defect types, and large differences in signal-to-noise ratio, the learning effect and recognition performance of the detection model are poor. The fixed thresholds or parameters used in the detection are difficult to adapt to data changes caused by fluctuations in production processes, equipment aging, and batch differences in materials, resulting in insufficient adaptability to operating conditions. Summary of the Invention

[0004] The technical solution disclosed herein is implemented as follows: In a first aspect, this disclosure provides a diagnostic method for silicon wafer edge chamfering, including: Acquire the timing signal of the edge of the target silicon wafer. The timing signal is the edge morphology feature signal acquired synchronously with the rotation angle of the silicon wafer. The timing signal is input into a preset timing pattern recognition model to obtain the defect diagnosis result of the target silicon wafer edge. The defect diagnosis result includes at least the defect classification label and the angle range corresponding to the defect classification label in the timing signal. The temporal pattern recognition model is obtained by progressive training using a multi-stage training dataset. The data complexity of the multi-stage training dataset shows a progressively increasing trend based on the signal-to-noise ratio and mixing degree of the silicon wafer edge defect signal.

[0005] Secondly, this disclosure provides a training method for a diagnostic model of silicon wafer edge chamfer defects, including: Obtain the initial model and a historical training sample library containing silicon wafer edge synchronization timing signals of a preset size; The signal-to-noise ratio and defect mixing complexity of each time series signal in the historical training sample library are evaluated based on the preset quantization rules. Based on the evaluation results, the historical training sample library is divided into multiple stage training sets from easy to difficult. Following an order from easy to difficult, the initial model is iteratively updated with multiple stages of training sets until the preset convergence condition is met, thus obtaining the target temporal pattern recognition model. The target time-series pattern recognition model can decouple silicon wafer edge defect features from the input time-series signal.

[0006] Thirdly, this disclosure provides a diagnostic device for chamfering the edge of a silicon wafer, comprising: The signal synchronization acquisition module is used to acquire the timing signal of the target silicon wafer edge, which is collected synchronously with the silicon wafer rotation angle. The timing signal contains the morphological features of the target silicon wafer edge. The intelligent pattern reasoning module is used to input the timing signal into the preset timing pattern recognition model, analyze the features of the timing signal based on the timing pattern recognition model, and output the defect diagnosis result of the target silicon wafer edge. Among them, the defect diagnosis results include at least the defect classification label and the angle range corresponding to the defect classification label in the time-series signal; The temporal pattern recognition model is obtained by progressively training a multi-stage training dataset through a course learning strategy. The data complexity of the multi-stage training dataset increases progressively with the signal-to-noise ratio and mixing degree of the silicon wafer edge defect signal.

[0007] Fourthly, this disclosure provides an electronic device including a processor and a memory, wherein the memory stores a computer program that, when executed by the processor, implements the method as described in the first or second aspect.

[0008] Fifthly, this disclosure provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method as described in the first or second aspect. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of the overall architecture of a silicon wafer edge chamfering intelligent diagnostic system provided in this disclosure.

[0010] Figure 2 This is a flowchart illustrating a silicon wafer edge chamfering diagnostic method provided in this disclosure.

[0011] Figure 3 This is a schematic diagram of a timing signal segmentation window provided in this disclosure.

[0012] Figure 4This is a schematic diagram of the structure of a one-dimensional convolutional neural network-long short-term memory hybrid model provided in this disclosure.

[0013] Figure 5 This is a schematic diagram of a visual marker for the angular position of a defect provided in this disclosure.

[0014] Figure 6 This is a schematic diagram of a process root cause correlation process provided in this disclosure.

[0015] Figure 7 This is a schematic diagram of the three-stage training process of a silicon wafer edge chamfer defect diagnosis model provided in this disclosure.

[0016] Figure 8 This is a schematic diagram of the structure of a smart diagnostic device for beveling the edge of a silicon wafer provided in this disclosure.

[0017] Figure 9 This is a structural block diagram of an electronic device provided in this disclosure. Detailed Implementation

[0018] The technical solutions in this disclosure will now be clearly and completely described with reference to the accompanying drawings.

[0019] The disclosed intelligent diagnostic system for silicon wafer edge chamfering uses an appendix... Figure 1 To achieve full-process functionality, the system is divided into three layers: data acquisition layer 1, model training and inference layer 2, and application interaction layer 3. These three layers work together to complete the entire process of signal acquisition, model training, intelligent inference, result output, and root cause correlation for silicon wafer edge chamfer defects.

[0020] Data acquisition layer 1 is the system's signal input unit, used to acquire the edge morphology features of the silicon wafer. Data acquisition layer 1 includes a silicon wafer rotation platform 11 and a sensor assembly 12. The sensor assembly 12 can be any one of a laser displacement sensor, a confocal sensor, or an optical profilometer, or a combination of multiple sensors can be used according to the detection requirements. The workflow of data acquisition layer 1 is as follows: the sensor assembly 12 remains fixed in its installation state, the silicon wafer to be inspected is stably fixed on the silicon wafer rotation platform 11, the silicon wafer rotation platform 11 drives the silicon wafer to rotate at a constant speed, a high-precision encoder collects and outputs the rotation angle θ of the silicon wafer in real time, and the sensor assembly 12 continuously collects the contour height information or light intensity information of the silicon wafer edge according to a preset fixed sampling rate, ultimately generating a one-dimensional time-series signal S that is strictly synchronized with the rotation angle θ. θ This timing signal completely covers all edge morphology features of the silicon wafer rotated 360 degrees without any feature loss. It serves as the data source for subsequent defect diagnosis, fully preserving all effective information such as minute defects, mixed defects, and noise interference, thus solving the problem of shallow signal utilization in existing technologies.

[0021] Model Training and Inference Layer 2 is the system's processing unit, undertaking the dual functions of model training and real-time inference. Internally, it houses a course learning scheduler 21, a time-series signal diagnostic model 22, and a model database 23. During model training, the course learning scheduler 21 controls the input order of the training dataset according to preset difficulty quantification rules, strictly following an easy-to-difficult approach to progressively train the time-series pattern recognition model, avoiding overfitting and adapting to the scarce and imbalanced defect samples characteristic of industrial scenarios. During model inference, the course learning scheduler 21 stops data scheduling, and the trained time-series signal diagnostic model 22 calls upon the weight parameters stored in the model database 23 to perform feature analysis and defect identification on the time-series signals transmitted in real-time from data acquisition layer 1, quickly outputting defect diagnosis results. The model database 23 stores the model weights, model parameters, and diagnostic rules completed at each training stage, ensuring the stability and consistency of model inference.

[0022] Application Interaction Layer 3 is the system's human-machine interaction and data output unit, enabling the visualization of diagnostic results and interconnection with the production line system. Application Interaction Layer 3 includes a human-machine interface 31 and a manufacturing execution system interface 32. The human-machine interface 31 generates and displays a visualized diagnostic report. The report includes information such as defect classification labels, defect angle and location, diagnostic confidence level, timing signal waveforms, process root cause hypotheses, and equipment maintenance recommendations. Process engineers can intuitively obtain all diagnostic information through the human-machine interface without manual analysis of raw data. The manufacturing execution system interface 32 establishes a data connection with external manufacturing execution systems, transmitting defect diagnostic results, process optimization suggestions, and equipment status prompts to the production line control end. This achieves closed-loop linkage between detection data and production processes, supports statistical process control and equipment pre-maintenance, and transforms detection results into a direct basis for production optimization.

[0023] This disclosed intelligent diagnostic method for silicon wafer edge chamfering is supported by a system architecture and strictly follows the steps of signal acquisition, signal preprocessing, model inference, defect result output, and process root cause correlation to form a closed-loop intelligent diagnostic process. Each step specifically addresses a defect in existing technologies, and the logic is coherent and practically implementable. (Refer to...) Figure 2 The intelligent diagnostic method for silicon wafer edge chamfering may include steps S210 to S220.

[0024] In step S210, the timing signal of the edge of the target silicon wafer is acquired. The timing signal is the edge morphology feature signal acquired synchronously with the rotation angle of the silicon wafer.

[0025] In some exemplary embodiments of this disclosure, the target silicon wafer to be tested is stably placed and fixed on the silicon wafer rotation platform 11 of the data acquisition layer 1 to ensure that the silicon wafer does not shift or shake during rotation, thus ensuring the stability of signal acquisition. The silicon wafer rotation platform 11 is started to keep the silicon wafer rotating at a constant speed. A high-precision encoder synchronously and in real time acquires the rotation angle θ of the silicon wafer, ensuring that the angle data corresponds exactly to the signal acquisition time. The sensor assembly 12 continuously acquires edge morphology feature signals at a preset fixed sampling frequency. The edge morphology feature signals may include the contour height data or light intensity data of the silicon wafer edge. The acquisition process completely covers the 360-degree cycle of one rotation of the silicon wafer, and finally obtains the original one-dimensional time-series signal S corresponding one-to-one with the rotation angle θ. θ This timing signal is raw data that has not undergone any processing, and it fully preserves all the defect features of the silicon wafer edge chamfer.

[0026] In step S220, the timing signal is input to the preset timing pattern recognition model to obtain the defect diagnosis result of the target silicon wafer edge.

[0027] The defect diagnosis results include at least the defect classification label and the angle range corresponding to the defect classification label in the time-series signal.

[0028] The temporal pattern recognition model is obtained by progressive training using a multi-stage training dataset. The data complexity of the multi-stage training dataset shows a progressively increasing trend based on the signal-to-noise ratio and mixing degree of the silicon wafer edge defect signal.

[0029] In some exemplary embodiments of this disclosure, the previously acquired edge morphology feature time-series signal, which is synchronously acquired with the silicon wafer rotation angle, is input into a pre-trained time-series pattern recognition model to obtain the defect diagnosis result of the target silicon wafer edge. The defect diagnosis result includes at least a defect classification label for distinguishing different defect types, and the angular range corresponding to the defect classification label in the time-series signal for locating the specific position of the defect on the circumference of the silicon wafer. The time-series pattern recognition model is trained progressively using a multi-stage training dataset. The data complexity of these multi-stage training datasets will show a phased increasing trend according to the signal-to-noise ratio of the silicon wafer edge defect signal, that is, the ratio of the effective feature component to the noise component in the defect signal, and the degree of mixing, that is, the degree of superposition of multiple defect features in a single signal.

[0030] By acquiring the temporal signal of the edge morphology synchronously with the rotation angle of the silicon wafer, and inputting this signal into a temporal pattern recognition model progressively trained with a training dataset of increasing complexity in multiple stages, the model directly outputs defect classification labels and corresponding angle ranges. This approach can completely preserve the temporal feature information of silicon wafer edge defects, fully explore the defect feature value of the original signal, and adapt to the characteristics of scarce defect samples, uneven types, and varying signal-to-noise ratios in industrial scenarios. It effectively avoids model overfitting, improves the model's accuracy and generalization ability in defect identification, and can directly realize defect type identification and angle localization. This breaks through the diagnostic limitations of traditional detection, which can only determine whether a defect is qualified or unqualified, and significantly improves the accuracy and diagnostic depth of silicon wafer edge chamfer defect detection.

[0031] In some example embodiments of this disclosure, after acquiring the timing signal, signal preprocessing operations can be performed. The purpose of preprocessing is to eliminate invalid noise, correct the signal baseline, unify the signal value range, and improve the accuracy and stability of model inference. Preprocessing can include three core steps: filtering, baseline drift removal, and normalization.

[0032] The filtering process employs industry-standard signal filtering algorithms to eliminate high-frequency invalid signals caused by sensor noise, equipment vibration, and environmental interference, while retaining valid signals related to defect features and preventing noise from interfering with the model's feature learning. Baseline drift removal corrects signal reference offsets caused by sensor temperature drift and minor optical path disturbances, ensuring a unified baseline for all acquired time-series signals and eliminating signal deviations caused by non-defect factors. Normalization maps the time-series signal values ​​to a fixed numerical range, eliminating signal value differences caused by different sensors, testing equipment, and material batches, ensuring the consistency and standardization of the model's input data.

[0033] After preprocessing, the time-series signal can be segmented according to the needs of micro-defect detection. The complete 360-degree time-series signal is divided into multiple local time-series signal segments with overlapping data along the silicon wafer rotation axis according to a preset angle step size and overlap rate. Each local time-series signal segment is used as an independent input batch and is sequentially input into the time-series pattern recognition model. The technical effect of signal segmentation is that it can amplify the features of local micro-defects, avoid the micro-defect features being submerged when the complete signal is input, and significantly improve the model's detection sensitivity and positioning accuracy for micro-defects of 50 micrometers to 200 micrometers, solving the problem of poor micro-defect recognition capability in existing technologies.

[0034] For example, refer to Figure 3 Three local timing signal segments were obtained by setting the angle step size to 90°, the width of the angle window to 120°, and the overlap rate to 30°.

[0035] The temporal pattern recognition model used in this disclosure is a hybrid model of a one-dimensional convolutional neural network (1D-CNN) and a long short-term memory network (LSTM), and the model structure is shown in the attached figure. Figure 4 As shown. The model input is the normalized time-series signal segment S. θ The length corresponds to a 360° rotation of the silicon wafer. The model inference process is divided into three core steps: local feature extraction, global time-series dependency capture, and probability distribution generation. Each step specifically mines the defect features in the time-series signal to achieve end-to-end intelligent diagnosis.

[0036] The first step involves the one-dimensional convolutional neural network module 41 performing local feature extraction. The preprocessed temporal signal 40 is input into the module, which consists of multiple stacked convolutional layers 411 and pooling layers 412. The convolutional layers scan the temporal signal using kernels of different sizes to accurately extract local abrupt features, including pulse-like features corresponding to edge chipping defects, periodic fluctuation features corresponding to ripple defects, slow baseline drift features corresponding to shape deviations, and local signal anomalies corresponding to contamination defects. The pooling layers perform dimensionality reduction on the features extracted by the convolutions, reducing the computational load of the model and improving inference speed while preserving core defect features. The final output is a feature sequence 413 reflecting local edge morphological abrupt changes, solving the problem that existing technologies cannot mine local defect features.

[0037] The second step involves the Long Short-Term Memory (LSTM) network module 42 capturing global temporal context dependencies. The feature sequence output from the one-dimensional convolutional neural network module is input into the LTM network module. The LTM network possesses the ability to remember and learn long-distance temporal information, enabling it to learn the global correlation of feature sequences along the silicon wafer's rotation angle axis. This allows for accurate determination of whether a local feature is an isolated defect signal or part of a continuous defect, effectively distinguishing the feature differences between single and mixed defects. The output is a final state vector 421 containing global temporal features, thus solving the problem of existing technologies being unable to learn temporal context dependencies.

[0038] The third step involves the fully connected classification layer 43 generating a defect probability distribution vector. Based on the final state vector output by the Long Short-Term Memory (LSTM) network module, the fully connected classification layer calculates the probability distribution of predefined defect categories. These predefined categories include normal, type A (edge ​​chipping), type B (scratches), type C (roughness), and type D (contamination). The category corresponding to the dimension with the largest value in the probability distribution vector is the final defect classification label determined by the model. Simultaneously, the model outputs the confidence score of this classification result, directly reflecting the reliability of the diagnostic result.

[0039] During model inference, an interpretability module can be enabled. This module employs a one-dimensional gradient-weighted class activation mapping technique, which can visualize the signal region in the time-series signal that contributes most to the model's classification decision, i.e., the angle interval corresponding to the defect, generating the result as shown in the attached figure. Figure 5 The visual markers indicating the defect angle positions highlight the starting angle θ0 and ending angle θ1 of the defect on the timing signal waveform and the silicon wafer circumference unfolded diagram. This visually shows the specific location of the defect on the silicon wafer circumference, improving the reliability and interpretability of the diagnostic results and providing process engineers with an intuitive basis for defect location.

[0040] After model inference is completed, the system outputs defect diagnosis results for the edge of the target silicon wafer. These results include at least a defect classification label and the corresponding angle range, and can also output auxiliary information such as diagnostic confidence and defect size range. The defect classification label clearly identifies the specific type of defect, accurately distinguishing between normal conditions and defect categories such as chipping, scratches, contamination, and roughness, thus solving the problem of existing technologies being unable to identify defect types. The corresponding angle range precisely locates the defect's position on the circumference of the silicon wafer, with the angle value strictly corresponding to the wafer's rotation angle, providing a locational basis for process root cause correlation and solving the problem of existing technologies being unable to locate defect positions.

[0041] After the defect diagnosis results are output, the system performs a process root cause correlation operation. The process root cause correlation is completed based on the preset process knowledge graph. The process knowledge graph stores the causal mapping relationship between defect types and production process parameters, equipment status, and environmental factors. Production process parameters include grinding pressure, rotation speed, and polishing fluid pH value. Equipment status includes the wear degree of grinding wheel, spindle vibration amplitude, and optical path calibration status. Environmental factors include the temperature, humidity, and cleanliness of the production workshop.

[0042] See attached document Figure 6 , attached Figure 6This is a schematic diagram of the process root cause correlation process. It shows the entire process of signal acquisition 602 and preprocessing 604, model inference 606, defect diagnosis output 608, process root cause correlation, report generation, and process adjustment in a closed-loop process. The process root cause correlation module has a built-in process knowledge graph. It can use defect classification labels and angle ranges as defect feature vectors 610 as query conditions to complete causal matching retrieval. It sorts candidate abnormal factors according to probability weights. The defect classification labels and the angle ranges corresponding to the defects are used as query conditions and input into the process knowledge graph 612 for accurate matching retrieval. The system automatically filters out candidate production process abnormal parameters, candidate equipment abnormal states, and candidate environmental abnormal factors that have a direct causal relationship with the current defect. Subsequently, based on the probability weights of each node in the process knowledge graph, the selected candidate anomalies are sorted from high to low probability to generate root cause hypotheses with clear priorities. Finally, the defect diagnosis results, root cause hypotheses, process inspection suggestions, and equipment maintenance tips are integrated to generate a visualized process root cause diagnosis report 614. The diagnosis report 614 includes silicon wafer ID, defect type, diagnosis confidence level, defect angle range, possible root causes, and process adjustment suggestions. It is displayed through the human-machine interface 31 of the application interaction layer 3 and transmitted to the production line control system 616 through the manufacturing execution system interface 32 to guide process engineers to conduct targeted equipment inspections and parameter adjustments, significantly shortening the troubleshooting time. Actual testing showed that the engineer's troubleshooting time was reduced from an average of 2 hours to 10 minutes.

[0043] The temporal pattern recognition model disclosed herein employs a three-stage course learning strategy for training, the training process of which is attached. Figure 7 As shown, the training method is executed by the server and consists of four core steps: initial model acquisition, training dataset partitioning, three-stage progressive training, and model convergence determination. The training dataset is divided according to the data complexity from easy to difficult, which perfectly adapts to the pain points of scarce defect samples, unbalanced types, and varying signal-to-noise ratios in industrial scenarios, and solves the problems of difficult model training and poor generalization performance in existing technologies.

[0044] Specifically, step S710 is executed first to obtain the initial model and a historical training sample library containing silicon wafer edge synchronization timing signals of a preset size.

[0045] First, an initial model and a historical training sample library are acquired. The initial model employs a hybrid model combining a one-dimensional convolutional neural network and a long short-term memory network. The model structure is identical to that of the model used in the inference stage. Initial weights can be randomly initialized or fine-tuned using weights from a pre-trained model based on general time-series data to enhance the model's initial learning capability. The historical training sample library consists of synchronous time-series signals from the rotation of silicon wafer edges, actually collected from semiconductor production lines. The library includes defect-free standard signals, single-defect signals, mixed-defect signals, cross-device signals, cross-process batch signals, and extremely rare defect signals, covering all common defect types and full-process scenarios at silicon wafer edge chamfers, ensuring the comprehensiveness and completeness of the model's learning.

[0046] Then, step S720 is executed, which evaluates the signal-to-noise ratio and defect mixing complexity of each time series signal in the historical training sample library based on preset quantization rules, and divides the historical training sample library into multiple stage training sets with progressively increasing data complexity according to the evaluation results.

[0047] Based on the preset quantitative evaluation rules, the training difficulty of each time series signal in the historical training sample library is evaluated. The evaluation dimensions include signal-to-noise ratio and defect mixture complexity. According to the evaluation results, the historical training sample library is divided into three training sets from easy to difficult, namely the first training set, the second training set, and the third training set. The data complexity of the three training sets shows a progressively increasing trend, strictly following the learning logic of the course from easy to difficult.

[0048] The first training set is the basic pattern learning training set. The data consists of a large number of defect-free standard signals and a small number of clear, typical single-defect signals. These single-defect signals include clean edge chipping and scratch signals. This training set has a high signal-to-noise ratio, obvious defect features, and no mixed defects or noise interference, making it the easiest training data. The purpose of the first training set is to allow the model to learn basic discrimination capabilities, quickly distinguish between normal and defect signals, establish basic recognition of typical defect features, and complete the model's initial learning.

[0049] The second training set is a training set for complex and hybrid mode learning. The data consists of weak defect signals, hybrid defect signals within the same angular range, and background noise interference signals superimposed with simulated equipment disturbances.

[0050] Weak defect signals refer to the timing signals of silicon wafer edge chamfering where the local feature amplitude of the defect is weak, the waveform changes smoothly without obvious sharp abrupt changes, and only shows a slight waveform shift. Specifically, this includes timing signals corresponding to small-sized defects such as micro-scratches, micro-chipping, and micro-contamination. These signals are easily drowned out by noise or ignored when the complete signal is input, and need to be amplified by signal segmentation before they can be effectively identified by the model. Hybrid defect signals include composite defects where chipping and contamination exist simultaneously at the same location. Noise interference signals simulate the actual production line conditions of slight equipment vibration and minor optical path disturbances.

[0051] Specifically, micro-chipping is defined as edge defects with a radial depth less than or equal to 0.3 mm and a circumferential chord length less than or equal to 0.5 mm; micro-scratches are defined as surface linear defects with a width less than or equal to 10 μm and a depth less than or equal to 10 μm; and micro-contamination is defined as surface particles with a diameter less than or equal to 0.1 mm. Within this size range, the waveform distortion amplitude of the timing signal caused by defects is typically less than twice the sensor noise level, constituting a weak characteristic signal that is difficult to effectively identify using traditional threshold detection methods. Specific numerical definitions can also be customized based on inspection requirements, which will not be elaborated upon here.

[0052] The second training set is more challenging than the first, and is used to improve the model's sensitivity to identifying subtle defects, learn the feature decoupling ability of mixed defects, enhance the model's robustness to noise, and adapt to the characteristics of high noise in industrial scenarios.

[0053] The third training set is a domain-adaptive and generalization learning training set. The data consists of signals collected by different physical difference detection devices, signals from different batches of process consumables throughout their lifecycles, and cross-domain defect signals of extremely rare and special defect types. Different physical difference detection devices refer to silicon wafer edge detection devices with physical differences in hardware configuration, sensor model, installation accuracy, and optical path structure; different batches of process consumables throughout their lifecycles refer to production batches corresponding to different stages of use of process consumables, such as new use, mid-term wear, and final aging; extremely rare and special defect types refer to silicon wafer edge chamfer defects with extremely low probability of occurrence on the production line, weak characteristics, and special shapes; cross-domain defect signals refer to defect time-series signals collected from different devices, different batches of process consumables, and different operating environments, with differences in data distribution.

[0054] The third training set is the most challenging. During training, domain adversarial training technology is employed to separate the inherent physical characteristics of defects from cross-domain defect signals. This forces the model to learn the essential features of defects, eliminating interference from non-core features caused by differences in equipment, processes, and consumables. This significantly improves the model's cross-domain generalization ability, enabling it to adapt to minor fluctuations in different machines and process conditions on the production line, thus solving the problem of poor adaptability in existing technologies. The inherent physical characteristics of defects refer to the essential physical properties inherent in the chamfer defects at the silicon wafer edge, unaffected by external factors such as differences in the physical characteristics of the detection equipment, the lifecycle of process consumables, production environment disturbances, and signal acquisition methods. Specifically, these include the local abrupt waveform characteristics of the defect in the time-series signal synchronized with the silicon wafer rotation angle, the defect's geometric size characteristics, the angular distribution characteristics of the defect on the rotation angle axis, the defect signal amplitude offset characteristics, and the essential attributes of the defect type. These are the core features separated from the cross-domain defect signals through domain adversarial training, used to force the model to learn the essential features of defects and improve its cross-domain generalization ability.

[0055] Then, step S730 is executed, in which the initial model is iteratively updated in multiple stages using the multiple stage training sets in order of increasing data complexity, until the preset convergence condition is met, and the target temporal pattern recognition model is obtained.

[0056] Following a training order from easy to difficult, the initial model is iteratively updated with weights using three phased training sets. Each phase of training uses the model weights from the previous phase as the initial values, achieving progressive feature learning and avoiding overfitting issues.

[0057] The first stage of training is the basic model learning stage. The first training set is input into the initial model. The course learning scheduler 21 controls the data input order, giving priority to inputting standard signals without defects, and then inputting single defect signals. The training objective is to enable the model to master the basic discrimination ability between normal signals and defect signals. After training, the first model with basic defect recognition ability is obtained.

[0058] The second training stage is the complex and hybrid mode learning stage. The second training set is input into the first model. The course learning scheduler 21 first inputs weak single defect signals, and then gradually introduces mixed defect signals and noise interference signals. The training objective is to improve the model's ability to identify subtle defects, decouple mixed defects, and become more robust to noise. After training, a second model with stronger defect identification ability is obtained.

[0059] The third training stage is the domain adaptation and generalization learning stage. The third training set is input into the second model. During the training process, domain adversarial training technology is used to separate the inherent physical characteristics of defects. The training objective is to improve the model's cross-domain generalization ability and rare defect identification ability. After training, the final time-series diagnostic model that can be directly deployed in the production environment is obtained.

[0060] During model training, the server monitors the model's loss function value and core evaluation metrics in real time. The evaluation metrics include accuracy, recall, precision, and F1 score. When the loss function value shows no decreasing trend for several consecutive iterations and the core evaluation metrics reach the preset threshold, the model is determined to have reached convergence. Training is then stopped immediately, and the final trained model is stored in the model database 23 for subsequent online inference diagnosis.

[0061] This embodiment uses the diagnosis of edge chamfer defects on a 12-inch monocrystalline silicon polished wafer as an example.

[0062] Ten 12-inch monocrystalline silicon polished wafers were selected as the silicon wafer samples, with standard R-type chamfers. Thirty typical defects were artificially created, covering four common defect types: edge chipping, scratches, roughness, and contamination. Defect sizes ranged from 50 to 200 micrometers, with each wafer containing 2 to 3 defects. The angular interval between defects was greater than 30 degrees, simulating the actual defect distribution on a production line. Normal samples consisted of the remaining normal edges around the circumference, excluding defective areas. Approximately 3000 normal samples were obtained by angular segmentation, resulting in a total of approximately 12000 valid samples, including approximately 10000 normal samples and approximately 2000 defective samples. The severe imbalance between categories completely simulated a real production line scenario.

[0063] The training samples were divided according to the three-stage course requirements. The first training set contained 100,000 normal signals, 500 typical edge chipping signals, and 300 typical scratch signals. The second training set contained 2,000 signals including composite defects such as micro-scratches, edge chipping, and contamination. The third training set contained 5,000 signals each from three different devices, totaling 15,000 cross-domain defect signals. The test samples used were the aforementioned 12,000 valid samples to verify the diagnostic performance of the model.

[0064] Model training is performed according to a three-stage learning framework. The learning scheduler 21 strictly controls the data input order. The first stage completes basic pattern learning, the second stage completes complex hybrid pattern learning, and the third stage completes cross-domain generalization learning. During training, the same one-dimensional convolutional neural network-long short-term memory network backbone structure as conventional deep learning is used, only the training strategy differs. Training validation shows that the proposed method reduces the number of convergence rounds by 36.6% compared to conventional deep learning, and increases the model iteration speed by approximately 1.6 times, significantly improving training efficiency.

[0065] The trained final model is deployed to Model Training and Inference Layer 2 to perform online diagnostics on 12-inch silicon wafers in the test samples. Data Acquisition Layer 1 collects the time-series signal of the silicon wafer rotating one revolution. After filtering, baseline drift removal, and normalization preprocessing, the signal is input into the final model. The model outputs a diagnostic result of type A edge chipping defect, with a diagnostic confidence level of 96% and a defect angle range of 120 to 125 degrees.

[0066] In this embodiment, the technical effects of this disclosure are fully verified. Regarding detection accuracy, the F1 score reaches 94.1%, with a false negative rate of only 6.5%, a reduction of 80% compared to the traditional threshold method's false negative rate of 32.7%, and a reduction of over 50% compared to conventional deep learning. In terms of training efficiency, the number of convergence rounds is reduced by 36.6%, significantly improving model iteration speed. Regarding small sample adaptability, the F1 score still reaches 86.7% when using only 10% of the training data, and reaches 88.5% when using only 20% of the training data, surpassing the performance of conventional deep learning using 100% of the data (87.4%), reducing the effective training data requirement by 80%. Regarding generalization ability, the model can run stably on three different devices without frequent retraining, adapting to the lifecycle fluctuations of consumables in different process batches. Regarding diagnostic efficiency, the troubleshooting time for process engineers is reduced from an average of 2 hours using traditional methods to 10 minutes, improving troubleshooting efficiency by 91.7%.

[0067] To fully verify the technical advantages of this disclosure, a three-stage necessity ablation experiment was conducted, consisting of a main comparison experiment, a small sample adaptability experiment, and a course learning experiment. The experimental subject was the timing signal diagnosis task of the chamfer edge of a 12-inch silicon wafer.

[0068] The comparison methods include the traditional thresholding method M1, the conventional deep learning method M2, the conventional deep learning method M3, and the method disclosed herein M4. All four methods employ the same one-dimensional convolutional neural network-long short-term memory network backbone structure, differing only in their training strategies. Details are shown in Table 1. Table 1

[0069] The experimental results are shown in Table 2: Table 2

[0070] As shown in Tables 1 and 2, compared with the traditional threshold method, the method disclosed in this paper improves the recall rate by 26.2% and reduces the false negative rate from 32.7% to 6.5%, directly solving the problems of inaccurate detection and high false negative rate in existing technologies. Compared with conventional deep learning methods, the method disclosed in this paper significantly outperforms in accuracy, recall, and F1 score, and reduces the number of convergence rounds by 36.6%, fully demonstrating that the course learning strategy greatly improves the model's learning efficiency and final diagnostic performance.

[0071] The model was trained using 100%, 50%, 20%, and 10% of the training data, respectively, and the F1 score of each method was tested. The experimental results are shown in Table 3. Table 3

[0072] As shown in Table 3, when using only 10% of the training data, the proposed method still achieves an F1 score of 86.7%, an improvement of 18.2% over M2 and 12.4% over M3. When using only 20% of the training data, the proposed method achieves an F1 score of 88.5%, surpassing the performance of M2 (87.4%) using 100% of the data. This demonstrates that the proposed method has excellent adaptability in small sample scenarios and significantly reduces the data cost of production line deployment.

[0073] Three experimental groups were set up: no course learning (V1), two-stage course learning (V2), and three-stage complete course learning (V3) to verify the necessity of the three-stage course learning. The experimental results are shown in Table 4: Table 4

[0074] Compared to V1 without a course, the two-stage course learning V2 improved the F1 score by 4.1 percentage points and reduced the number of convergence epochs by 20%, demonstrating the effectiveness of progressive training from easy to difficult. Compared to the two-stage course learning V2, the three-stage complete course learning V3 further improved the F1 score by 2.6 percentage points, increased the recall by 3.3 percentage points, and reduced the number of convergence epochs by 23.5%, demonstrating that each stage of the three-stage course learning significantly improved the model performance.

[0075] Furthermore, this disclosure also provides a smart diagnostic device for silicon wafer edge chamfering, with reference to Figure 8 The intelligent diagnostic device 800 for silicon wafer edge chamfering includes a signal synchronization acquisition module 810 and an intelligent pattern inference module 820. The device structure and system architecture are fully aligned, and its functions and diagnostic methods are highly compatible. The signal synchronization acquisition module 810 collects timing signals from the target silicon wafer edge synchronized with the wafer's rotation angle, ensuring the synchronization and integrity of the timing signals and providing reliable data for diagnosis. The intelligent pattern inference module 820 incorporates a timing pattern recognition model trained through a three-stage learning process. It performs local feature extraction and global timing dependency analysis on the input timing signals, outputting defect classification labels and the corresponding angle ranges. Based on the learning strategy and hybrid model structure, the device possesses high-precision, high-robustness, and high-generalization diagnostic performance. It is compatible with different models of rotating silicon wafer edge inspection equipment, exhibiting wide hardware adaptability without requiring replacement of existing inspection hardware, thus reducing production line upgrade costs.

[0076] Please refer to Figure 9This illustration shows a structural block diagram of an electronic device provided in an exemplary embodiment of the present disclosure. In some examples, the electronic device 90 can be at least one of devices such as a smartphone, smartwatch, desktop computer, laptop, virtual reality terminal, augmented reality terminal, wireless terminal, and laptop computer. The electronic device 90 has communication capabilities and can access wired or wireless networks. The electronic device 90 can refer to one of a plurality of terminals, and those skilled in the art will understand that the number of such terminals can be more or less.

[0077] like Figure 9 As shown, the electronic device in this disclosure may include one or more of the following components: processor 910 and memory 920.

[0078] Optionally, the processor 910 connects various parts within the electronic device using various interfaces and lines, and performs various functions and processes data by running or executing instructions, programs, code sets, or instruction sets stored in the memory 920, and by calling data stored in the memory 920. Optionally, the processor 910 can be implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 910 can integrate one or a combination of several of the following: Central Processing Unit (CPU), Graphics Processing Unit (GPU), Neural-network Processing Unit (NPU), and baseband chip. Specifically, the CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the content required for display on the touch screen; the NPU is used to implement Artificial Intelligence (AI) functions; and the baseband chip is used for wireless communication. It is understandable that the aforementioned baseband chip may not be integrated into the processor 910, but may be implemented using a separate chip.

[0079] The memory 920 may include random access memory (RAM) or read-only memory (ROM). Optionally, the memory 920 may include a non-transitory computer-readable storage medium. The memory 920 may be used to store instructions, programs, code, code sets, or instruction sets. The memory 920 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the various method embodiments described above, etc.; the data storage area may store data created based on the use of the electronic device, etc.

[0080] In addition, those skilled in the art will understand that the structure of the electronic device shown in the above figures does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown, or combine certain components, or have different component arrangements. For example, the electronic device may also include a display screen, camera assembly, microphone, speaker, radio frequency circuit, input unit, sensors (such as accelerometer, angular velocity sensor, light sensor, etc.), audio circuit, WiFi module, power supply, Bluetooth module, etc., which will not be described in detail here.

[0081] This disclosure also provides a computer-readable storage medium storing at least one instruction, which is executed by a processor to implement the silicon wafer edge chamfering diagnosis method or the training method for a silicon wafer edge chamfering defect diagnosis model as described in the above embodiments.

[0082] This disclosure also provides a computer program product including computer instructions stored in a computer-readable storage medium; a processor of an electronic device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the electronic device to perform a diagnostic method for silicon wafer edge chamfering or a training method for a diagnostic model for silicon wafer edge chamfering defects as described in the above embodiments.

[0083] Those skilled in the art will recognize that the functions described in this disclosure in one or more of the examples above can be implemented using hardware, software, firmware, or any combination thereof. When implemented in software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium accessible to a general-purpose or special-purpose computer.

[0084] It should be noted that the technical solutions described in this disclosure can be combined arbitrarily as long as they do not conflict.

[0085] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A diagnostic method for the chamfering of silicon wafer edges, characterized in that, include: Acquire timing signals of the edge of the target silicon wafer, wherein the timing signals are edge morphology feature signals acquired synchronously with the rotation angle of the silicon wafer; The timing signal is input into a preset timing pattern recognition model to obtain the defect diagnosis result of the edge of the target silicon wafer. The defect diagnosis result includes at least a defect classification label and the angle range corresponding to the defect classification label in the timing signal. The temporal pattern recognition model is obtained by progressive training using a multi-stage training dataset. The data complexity of the multi-stage training dataset shows a phased increasing trend based on the signal-to-noise ratio and mixing degree of the silicon wafer edge defect signal.

2. The diagnostic method for silicon wafer edge chamfering according to claim 1, characterized in that, The temporal pattern recognition model includes a cascaded convolutional neural network module and a long short-term memory network module; The step of inputting the timing signal into a preset timing pattern recognition model to obtain the defect diagnosis result of the target silicon wafer edge includes: The convolutional neural network module is used to extract local features from the time-series signal to obtain a feature sequence that reflects abrupt changes in local edge morphology. The feature sequence is input into the long short-term memory network module. Based on the long short-term memory network module capturing the global temporal context dependency of the feature sequence on the rotation angle axis, the final state output by the long short-term memory network module is obtained. Based on the final state output by the Long Short-Term Memory network module, a probability distribution vector reflecting the probability of a predefined defect type is generated, and the defect classification label is determined accordingly.

3. The method according to claim 2, characterized in that, After determining the defect classification label, the method further includes: Based on the defect classification results of the time-series pattern recognition model, the target signal segment corresponding to the defect features in the time-series signal is determined; Based on the rotation angle information corresponding to the target signal segment, the target angle range corresponding to the defect classification label is marked on the visualized waveform of the time-series signal.

4. The method according to claim 1 or 2, characterized in that, The multi-stage training dataset includes at least a first training set, a second training set, and a third training set that are sequentially input into the temporal pattern recognition model in chronological order. The first training set contains standard signals without defects and single defect signals with a single defect category, which are used to train the initial model to obtain the first model; The second training set includes the single defect signal, the mixed defect signal containing multiple defect categories within the same angular range, and the interference signal superimposed with preset background noise simulating equipment disturbance, which is used to train the first model to obtain the second model. The third training set includes cross-domain defect signals collected from detection devices with physical differences or from batches of consumables in different process lifecycles, which are used to train the second model to obtain the time-series pattern recognition model.

5. The method according to claim 4, characterized in that, In the process of training the second model to obtain the temporal pattern recognition model, the method further includes: The inherent physical characteristics of the defect itself are separated from the cross-domain defect signal; The second model is trained based on the inherent physical characteristics to obtain the temporal pattern recognition model.

6. The method according to claim 1, characterized in that, After outputting the defect diagnosis results at the edge of the target silicon wafer, the method further includes: The defect classification labels and corresponding angle ranges in the defect diagnosis results are used as query conditions. The preset process knowledge graph is then used for association query matching to obtain the query matching results. Based on the query matching results, candidate abnormal production process parameters, candidate abnormal equipment states, or abnormal environmental factors that have a causal mapping relationship with the defect diagnosis results are identified. Based on the node probability weights of the process knowledge graph, the candidate abnormal parameters of the production process, the candidate abnormal state of the equipment, or the abnormal environmental factors are sorted, and a process root cause diagnosis report is generated and output.

7. The method according to claim 1, characterized in that, Before inputting the timing signal into a preset timing pattern recognition model, the method further includes: The time-series signal is divided into multiple local time-series signal segments with overlapping data according to a preset angle step size and overlap rate; The local time-series signal segments are treated as independent input batches and sequentially input into the time-series pattern recognition model.

8. A training method for a diagnostic model of chamfer defects at the edge of silicon wafers, characterized in that, Applied to a server, the method includes: Obtain the initial model and a historical training sample library containing silicon wafer edge synchronization timing signals of a preset size; The signal-to-noise ratio and defect mixing complexity of each time series signal in the historical training sample library are evaluated based on preset quantization rules. According to the evaluation results, the historical training sample library is divided into multiple stage training sets with progressively increasing data complexity. Following the order of increasing data complexity in stages, the initial model is iteratively updated with multiple stages of training sets until the preset convergence condition is met, thereby obtaining the target temporal pattern recognition model. The target time-series pattern recognition model can decouple silicon wafer edge defect features from the input time-series signal.

9. The method according to claim 8, characterized in that, The initial model comprises a cascaded one-dimensional convolutional neural network and a long short-term memory network; the multiple staged training sets sequentially include a first training set consisting of a single defect signal with a single defect category, a second training set consisting of the single defect signal and a mixed defect signal containing multiple defect categories within the same angular range, and a third training set consisting of cross-domain defect signals containing differences between different devices.

10. A diagnostic device for beveling the edges of a silicon wafer, characterized in that, include: The signal synchronization acquisition module is used to acquire the timing signal of the target silicon wafer edge, which is synchronously acquired with the silicon wafer rotation angle. The timing signal includes the morphological features of the target silicon wafer edge. The intelligent pattern reasoning module is used to input the timing signal into a preset timing pattern recognition model, perform feature analysis of the timing signal based on the timing pattern recognition model, and output the defect diagnosis result of the target silicon wafer edge. The defect diagnosis result includes at least a defect classification label and the angle range corresponding to the defect classification label in the time-series signal; The temporal pattern recognition model is obtained by progressively training a multi-stage training dataset through a course learning strategy. The data complexity of the multi-stage training dataset increases progressively with the signal-to-noise ratio and mixing degree of the silicon wafer edge defect signal.

11. An electronic device, characterized in that, It includes a processor and a memory, wherein the memory stores a computer program that, when executed by the processor, implements the method as described in any one of claims 1 to 7, or as described in any one of claims 8 to 9.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method as described in any one of claims 1 to 7, or as described in any one of claims 8 to 9.

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