Gate driving circuit of display panel, display panel and display device

Abstract

The application discloses a gate driving circuit of a display panel, a display panel and a display device, and relates to the technical field of display panels. The display panel comprises a pixel array with a plurality of pixel rows; the gate driving circuit comprises a plurality of gate driving units and a plurality of demultiplexing units connected in cascade; each gate driving unit outputs a continuous gate driving signal with an effective pulse width greater than or equal to the scanning time of at least two pixel rows; each demultiplexing unit is connected to a gate driving unit in correspondence and outputs the effective pulse of the continuous gate driving signal in time segments to form the effective pulse of the gate driving signal corresponding to different pixel rows, so that one gate driving unit drives a plurality of pixel rows. The application can reduce the number of gate driving units, reduce the circuit layout area, and adapt to the narrow frame design requirement of a high-pixel-density display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a gate driving circuit for a display panel, a display panel, and a display device. Background Technology

[0002] With the development of display technology, high pixel density (High Pixels Per Inch, PPI) has become the core development direction for high-end display products. Pixel size continues to shrink, and pixel row spacing and height are constantly being compressed, making the constraints on bezel size increasingly stringent. The Gate Driver on Array (GOA) circuit, as the core driving module of the display panel, adopts an integrated gate driving process on the array substrate. In traditional solutions, a single gate driving unit can only drive one row of pixels, requiring multiple levels of gate driving units cascaded to match the number of pixel rows to achieve line-by-line scanning.

[0003] In high PPI display panels, the number of pixel rows increases significantly, and the number of units required for traditional gate drive circuits also increases accordingly. The physical layout of the circuit occupies a significantly larger area, making it difficult to meet the requirements of narrow bezels or even bezel-less designs. Even if the bezel size is widened, a large number of gate drive units cannot be accommodated in the extremely small pixel space, which directly limits the design and mass production feasibility of high PPI display panels.

[0004] Meanwhile, traditional gate drive circuits have a large number of units and complex wiring, which can easily cause problems such as signal transmission delay and timing deviation, affecting drive stability and failing to meet the stringent requirements of high PPI panels for drive signal accuracy and reliability. There is an urgent need for a gate drive circuit solution that can reduce the number of gate drive units and reduce the layout area. Summary of the Invention

[0005] This application provides a gate driving circuit, a display panel, and a display device for a display panel, which has the advantages of saving layout space, realizing a narrow bezel design, and adapting to the needs of high pixel density display products.

[0006] In a first aspect, the gate driving circuit of the display panel provided in the embodiments of this application, wherein the display panel includes a pixel array, the pixel array including a plurality of pixel rows; the gate driving circuit includes: A cascaded plurality of gate driving units, each of the gate driving units being used to output a continuous gate driving signal, wherein the pulse width of the effective pulse of the continuous gate driving signal is greater than or equal to the scan time of at least two pixel rows; Multiple demultiplexing units are provided, each of which is connected to a gate driving unit. Each demultiplexing unit is configured to output the effective pulses of the continuous gate driving signals output by the corresponding gate driving unit in time segments to form effective pulses of the gate driving signals corresponding to different pixel rows, so that one gate driving unit drives multiple different pixel rows.

[0007] Secondly, the display panel provided in the embodiments of this application includes the gate driving circuit described above.

[0008] Thirdly, the display device provided in the embodiments of this application includes the display panel described above.

[0009] In summary, the gate driving circuit, display panel, and display device provided in this application, by setting a gate driving unit with an output effective pulse width greater than or equal to at least two pixel row scan times, and cooperating with a corresponding demultiplexing unit, outputs the effective pulses of the continuous gate driving signal in time segments. This directly reduces the total number of gate driving units, lowers the overall circuit layout area, and adapts to the narrow bezel design of high PPI display panels. One gate driving unit drives multiple pixel rows, simplifying the circuit wiring structure, reducing signal transmission nodes, improving driving timing consistency and signal stability, while reducing circuit power consumption and process implementation difficulty. This effectively solves the technical problems of insufficient gate driving layout space and difficulty in narrowing the bezel in high PPI panels, and improves the integration and adaptability of display panels. Attached Figure Description

[0010] The present invention will be further described below with reference to the accompanying drawings. It should be noted that the accompanying drawings described below are merely for illustrating some embodiments of the present invention. Those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0011] Figure 1 This is one of the schematic diagrams of a display device provided for an embodiment of this application.

[0012] Figure 2 This is a second schematic diagram of a display device provided for an embodiment of this application.

[0013] Figure 3 This is one of the schematic diagrams of the gate driving circuit of a display panel provided for an embodiment of this application.

[0014] Figure 4 This is a second schematic diagram of the gate driving circuit of the display panel provided in an embodiment of this application.

[0015] Figure 5 This is a schematic diagram of the timing waveform of the gate drive circuit provided in an embodiment of this application.

[0016] Figure 6 This is a third schematic diagram of the gate driving circuit of the display panel provided in an embodiment of this application.

[0017] Figure 7 This is a circuit diagram showing the connection between the gate driving unit and the demultiplexing unit provided in an embodiment of this application.

[0018] Figure 8 This is a schematic diagram of the timing waveforms of the reset signal and the frame start signal provided in the embodiments of this application.

[0019] Figure 9 This is a schematic diagram of the timing waveform of the clock signal corresponding to the gate driving unit provided in the embodiments of this application.

[0020] Figure 10 This is a timing diagram illustrating the coordination between the gate drive signal and the data signal provided in an embodiment of the present invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0022] The terms "first," "second," etc., used in this invention are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or modules is not limited to the listed steps or modules, but may optionally include steps or modules not listed, or may optionally include other steps or modules inherent to these processes, methods, products, or devices.

[0023] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily imply the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0024] This application provides a display device, which includes, but is not limited to, the following embodiments and combinations thereof.

[0025] In some embodiments, Figure 1One of the schematic diagrams of a display device provided for an embodiment of this application; Figure 2 A second schematic diagram of a display device is provided for embodiments of this application; in conjunction with Figure 1 and Figure 2 As shown, the display device 10 provided in the embodiments of this application can be, but is not limited to, a mobile phone, tablet computer, automotive display, virtual reality display, or augmented reality display. The display device 10 may include a display panel 100, a source driver, a gate drive circuit 1000, a timing controller, a light-emitting controller, a power management chip, a substrate, data lines for transmitting data signals DATA, gate scan lines for transmitting gate drive signals SCAN, power lines for transmitting the voltage VDD at the positive terminal of the power line or the voltage VSS at the negative terminal of the power line, light-emitting control signal lines for transmitting light-emitting control signals EM, a pixel array, a packaging layer, a polarizer, etc. In this embodiment, the display device 10 can be a passive light-emitting display device or a self-emissive display device. Passive light-emitting display devices include liquid crystal displays.

[0026] The pixel array is composed of multiple pixel units arranged in rows and columns, forming multiple pixel rows along the row direction and multiple pixel columns along the column direction. Each pixel row and each pixel column includes multiple pixel units, and each pixel unit includes multiple sub-pixels (PX). Sub-pixels include light-emitting devices and pixel circuitry. For ease of description, pixel rows and pixel columns may be referred to as "rows" and "columns" thereafter. The pixel driving circuit may include driving transistors used to control the brightness of the corresponding organic light-emitting devices in the display panel 100. In actual pixel units, driving transistors may include, but are not limited to, low-temperature polycrystalline silicon (LTPS) and thin-film transistors (TFTs) of metal-oxide-semiconductor. The TFT may employ a dual-gate structure, with the organic light-emitting device electrically connected to the first or second electrode of the TFT. The organic light-emitting device may include a light-emitting layer, an electron transport layer, a hole transport layer, a cathode, and an anode. Different organic materials can emit light of different wavelengths to achieve full-color display. The encapsulation layer includes a multilayer structure alternating between organic and inorganic materials. The gate driver on array (GOA) is mainly used for scanning and driving pixel rows. For example, the GOA circuit may include cascaded gate driver units 1001, where each gate driver unit 1001 controls one or more pixel rows to enable pixel selection. In some embodiments, the GOA can use single-sided or double-sided driving for multiple pixel rows. Single-sided driving may involve arranging the gate driver unit 1001 on only one side (e.g., left or right) and scanning and driving multiple pixel rows line by line through cascading. Double-sided driving may involve arranging driving units on both the left and right sides of the multiple pixel rows and scanning and driving multiple pixel rows line by line through coordinated operation on both sides. The source driver is used to provide data signals to the pixel units. The timing controller is used to receive externally input image data and synchronization signals, and generate the signals required by the gate driver circuit 1000 and the source driver. The power management chip is used to provide the required operating voltage to various parts of the display panel 100. It should be noted that... Figure 2 This is an illustrative diagram, and the component connections shown are only used to explain the functional logic of the display panel 100, and are not intended to limit the actual physical structure.

[0027] In one embodiment, this application provides a gate driving circuit for a display panel. Figure 3 One of the schematic diagrams of the gate driving circuit of the display panel provided for an embodiment of this application; Figure 4 A second schematic diagram of the gate driving circuit of the display panel provided for an embodiment of this application, as shown below. Figure 3 and Figure 4As shown, the display panel 100 includes a pixel array, and the pixel array 101 includes a plurality of pixel rows 1011; the gate driving circuit 1000 includes: Multiple cascaded gate driving units 1001, each gate driving unit 1001 is used to output a continuous gate driving signal, the pulse width of the effective pulse of the continuous gate driving signal is greater than or equal to the scan time of at least two pixel rows 1011. Multiple demultiplexing units 1002 are provided, each demultiplexing unit 1002 is connected to a gate driving unit 1001, and each demultiplexing unit 1002 is configured to output the effective pulse of the continuous gate driving signal output by the corresponding gate driving unit 1001 in time segments to form effective pulses of the gate driving signal corresponding to different pixel rows 1011, so that one gate driving unit 1001 drives multiple different pixel rows 1011.

[0028] Specifically, the gate driving circuit 1000 of this embodiment is applied to the display panel 100. The display panel 100 can be a flat panel display device for displaying images or videos, including a pixel array 101. The pixel array 101 is composed of a plurality of pixel rows 1011, which are arranged in a matrix for displaying images. The function of the gate driving circuit 1000 is to provide gate driving signals to the pixel array 101 of the display panel 100 and control the conduction and de-conduction of the pixel rows 1011.

[0029] The gate drive circuit 1000 includes multiple cascaded gate drive units 1001. Each gate drive unit 1001 is configured to generate and output a continuous gate drive signal. For example, each gate drive unit 1001 may be a shift register unit whose output is connected to the input of the next stage gate drive unit 1001 and generates an output according to the corresponding clock signal and the previous stage signal.

[0030] The continuous gate drive signal has a single effective pulse whose pulse width is designed to be greater than or equal to the scan time of at least two pixel rows 1011. The scan time can be the time required to drive one pixel row 1011. For example, a gate drive unit 1001 can output an effective pulse with a duration of 2H (where H represents the scan time of one pixel row 1011) or an effective pulse with a duration of 3H. This pulse width setting can be achieved by adjusting the timing logic or clock frequency within the gate drive unit 1001.

[0031] Furthermore, the gate drive circuit 1000 also includes a plurality of demultiplexing units 1002. Each demultiplexing unit 1002 is correspondingly connected to a gate drive unit 1001. For example, the signal output terminal G of each gate drive unit 1001 can be connected to the signal input terminal of a demultiplexing unit 1002. The demultiplexing unit 1002 is configured to output the effective pulses of the continuous gate drive signal output by the corresponding gate drive unit 1001 in time segments. For example, a demultiplexing unit 1002 may include a plurality of switches that are sequentially turned on at different time points, thereby dividing the effective pulses of the input continuous gate drive signal into a plurality of short pulses.

[0032] By segmenting the output over time, effective pulses of the gate drive signal corresponding to different pixel rows 1011 can be generated. For example, a continuous gate drive signal with a width of 2H can be divided into two gate drive signals with a width of 1H by the demultiplexing unit 1002, and output to two different pixel rows 1011 respectively.

[0033] Thus, one gate driving unit 1001 can drive multiple different pixel rows 1011. For example, one gate driving unit 1001 outputs a continuous gate driving signal with a duration of 3H, which is then segmented into three 1H pulses by a demultiplexing unit 1002 to drive three different pixel rows 1011 respectively. This driving method can be implemented through timing control. For example, the demultiplexing unit 1002 can receive an external clock signal and control the conduction sequence and duration of its internal switches according to the timing of the external clock signal.

[0034] As an example, the display panel 100 can be a high PPI display panel 100, including a pixel array 101 and a gate driving circuit 1000. The gate driving circuit 1000 is integrated on the array substrate using an on-array gate driving method to achieve narrow bezel driving. Figure 4As shown, the gate driving circuit 1000 of this embodiment includes multiple cascaded gate driving units 1001 and multiple demultiplexing units 1002. Each gate driving unit 1001 is connected to a demultiplexing unit 1002 in a one-to-one correspondence. The gate driving unit 1001 N outputs a continuous gate driving signal GN(n), the effective pulse width of which is greater than or equal to the scan time of at least two pixel rows 1011. The demultiplexing unit 1002 N receives GN(n) and, under the control of the first clock signals CK1, CK2, CK3, etc., outputs the effective pulse of GN(n) in time segments to form gate driving signals G1(n), G2(n), G3(n), etc., corresponding to different pixel rows 1011 respectively. Thus, one gate driving unit 1001 N can drive multiple different pixel rows 1011 simultaneously through its corresponding demultiplexing unit 1002 N, achieving the effect of reducing the number of gate driving units 1001 and reducing the circuit layout area.

[0035] For example, such as Figure 6 As shown, Figure 6 The third schematic diagram of the gate driving circuit 1000 of the display panel 100 provided for the embodiments of this application is shown below. Figure 6 As shown, the gate driving circuit 1000 in this embodiment includes multiple cascaded gate driving units 1001, specifically designated as GOA unit 1, GOA unit 2... GOA unit N, and demultiplexing units 1002, designated as demux1, demux2... demuxN, connected one-to-one with the gate driving units 1001. The gate driving units 1001 output continuous gate driving signals GN1, GN2... GNn with a pulse width equal to the scanning time of multiple rows of pixels; the demultiplexing units 1002 segment the continuous gate driving signals according to time, outputting multiple independent gate driving signals G1, G2, G3... to drive the corresponding pixel rows 1011. Figure 6 The example shown is that the demultiplexing unit 1002 (demux1), under the time-division control of the first clock signals CK1, CK2, and CK3, sequentially turns on its internal switches, segmenting the long pulse of GN1 into three gate drive signals: G1, G2, and G3. The high-level duration of each signal is equal to the scanning time of one pixel row 1011. While a conventional GOA unit width drives only one row of pixels, this embodiment employs a high-PPI GOA unit width design. One gate drive unit 1001, in conjunction with the demultiplexing unit 1002, can drive multiple rows of pixels, significantly reducing the border width.

[0036] The gate driving circuit 1000 of this embodiment effectively reduces the number of gate driving units 1001 by having one gate driving unit 1001 drive multiple rows of pixel rows 1011. As a result, the physical layout space required by the gate driving circuit 1000 in the bezel area of ​​the display panel 100 is reduced, which helps to meet the bezel size restrictions of high pixel density (PPI) display products and improves the feasibility of GO circuit layout for high PPI products.

[0037] In some embodiments of this application, how to accurately and effectively distribute the effective pulses of a long continuous gate drive signal to different pixel rows 1011 according to a preset time sequence and duration, so as to ensure that each pixel row 1011 can accurately receive its required gate drive signal, is a technical problem that needs to be specifically solved.

[0038] Based on this, in one embodiment, each demultiplexing unit 1002 includes M switching elements, each switching element being electrically connected between the signal output terminal G of the corresponding gate driving unit 1001 and a pixel row 1011; wherein, M≥2; the M switching elements in the same demultiplexing unit 1002 are configured to be turned on sequentially during the period when the continuous gate driving signal output by the corresponding gate driving unit 1001 has a valid pulse, so as to output the valid pulse of the corresponding continuous gate driving signal in time segments.

[0039] Specifically, the M switching elements are electronic switching devices used to control the on / off state of signals, such as thin-film transistors (TFTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), or other types of transistors. Each switching element has a control terminal, an input terminal, and an output terminal. The input terminal is electrically connected to the signal output terminal G of the corresponding gate driving unit 1001, and the output terminal is electrically connected to a specific pixel row 1011 in the display panel 100. The value of M is greater than or equal to 2, indicating that each demultiplexing unit 1002 can output continuous gate driving signals in segments to at least two or more pixel rows 1011.

[0040] Within the same demultiplexing unit 1002, M switching elements are designed to sequentially turn on according to a predetermined timing sequence throughout the entire period when the continuous gate drive signal output from the corresponding gate drive unit 1001 is in an effective pulse state. For example, if the effective pulse duration of the continuous gate drive signal is T, and L pixel rows 1011 need to be driven (L=M), then each switching element will be turned on for approximately T / L of a time period. When the first switching element turns on, the first time segment of the continuous gate drive signal is transmitted to its connected pixel row 1011; subsequently, the first switching element turns off, the second switching element turns on, transmitting the second time segment to its connected pixel row 1011, and so on, until all M switching elements are sequentially turned on and off. The sequential turn-on mechanism can be precisely controlled by an external clock signal or control signal to control the turn-on and turn-off times of each switching element.

[0041] This application provides a specific and efficient mechanism for precisely segmenting the effective pulses of a continuous gate drive signal according to time. By configuring M switching elements and sequentially turning them on during the effective pulse period of the continuous gate drive signal, it is ensured that each pixel row 1011 can receive an accurate gate drive signal within its specific scan time, thereby effectively solving the problem of precise control of continuous signal segmented output. This not only simplifies the overall structure of the gate drive circuit 1000 and reduces the number of required gate drive units 1001, but also ensures the normal scanning and image display quality of the display panel 100, improving the system's integration and reliability.

[0042] In some embodiments of this application, achieving precise timing control of M switching elements to ensure that they are turned on sequentially and output accurately in segments during the effective pulse period of the continuous gate drive signal may present challenges, such as how to avoid signal overlap or timing disorder, which could affect the accuracy of the gate drive signal.

[0043] Based on this, in one embodiment, the M switching elements located in the same demultiplexing unit 1002 are controlled to be turned on and off by different first clock signals; wherein, the M first clock signals corresponding to the same demultiplexing unit 1002 are configured to generate effective pulses sequentially during the period when the continuous gate drive signal output by the gate drive unit 1001 corresponding to the demultiplexing unit 1002 has effective pulses.

[0044] Specifically, to achieve precise control of the M switching elements in the demultiplexing unit 1002, this application proposes that each switching element be controlled by an independent first clock signal for turn-on and turn-off. The turn-on and turn-off timing of each switching element can be designed and adjusted independently, rather than being limited to a unified control signal. For example, the first clock signal can be a pulse signal with a specific pulse width and phase, which drives the corresponding switching element into the conduction state through its high or low level (depending on the type of switching element, such as an NMOS or PMOS transistor). This independent control method provides a foundation for subsequent precise timing segmentation.

[0045] Simultaneously, the M first clock signals corresponding to the same demultiplexing unit 1002 are configured to sequentially generate valid pulses during the period when the continuous gate drive signal output by the gate drive unit 1001 corresponding to the demultiplexing unit 1002 has valid pulses. Specifically, the aforementioned M first clock signals are not simultaneously valid, but are carefully configured to generate valid pulses "sequentially" within the valid pulse duration of the continuous gate drive signal. This "sequential" generation of valid pulses is key to achieving time segmentation of the continuous gate drive signal. For example, if the valid pulse duration of the continuous gate drive signal is T, and it needs to be segmented into M sub-pulses, the valid pulse duration of each first clock signal can be designed to be approximately T / M, and the start time of the valid pulses of adjacent first clock signals can be spaced approximately T / M apart. The sequentially generated clock signals can be precisely generated by circuit modules such as shift registers, frequency dividers, or delay lines within the timing controller (T-Con), ensuring that each switching element is turned on within a predetermined time window, thereby accurately cutting the continuous signal into M non-overlapping sub-pulses.

[0046] This application provides each switching element in the demultiplexing unit 1002 with an independent first clock signal that sequentially generates valid pulses, thereby enabling precise control over the turn-on and turn-off timing of each switching element. This refined timing control ensures that valid pulses of the continuous gate drive signal can be accurately and seamlessly segmented and output in time segments, effectively avoiding problems such as signal overlap, signal loss, or timing errors caused by inaccurate timing. Based on this, one gate drive unit 1001 can stably and efficiently drive multiple different pixel rows 1011, significantly improving the accuracy and reliability of the gate drive signal, thereby optimizing the scanning performance and display quality of the display panel 100.

[0047] In some embodiments of this application, when multiple demultiplexing units 1002 work together, if the effective pulse periods of the continuous gate drive signals output by adjacent gate drive units 1001 overlap, it may lead to signal conflict or timing disorder, thereby affecting the normal scanning and display effect of pixel row 1011.

[0048] Based on this, in one embodiment, multiple demultiplexing units 1002 and M first clock lines are electrically connected, and each first clock line is configured to transmit a first clock signal; wherein the effective pulse periods of the continuous gate drive signals output by two adjacent gate drive units 1001 do not overlap.

[0049] Specifically, the M first clock lines can be M independent physical connection paths for transmitting the first clock signal. The first clock signal is used to control the on / off state of M switching elements in the same demultiplexing unit 1002. By providing an independent control signal line for each switching element, it can be ensured that each switching element can switch precisely according to a preset timing sequence, thereby achieving precise time segmentation of the continuous gate drive signal. For example, the first clock lines can be provided by the timing controller (T-Con) of the display panel 100 or a dedicated clock drive circuit to ensure the synchronization and stability of the clock signal. Electrical connections can be the electrical paths established between the first clock lines and the corresponding switching elements in the demultiplexing unit 1002. The connection method allows the first clock signal to be effectively transmitted to the control terminal of the switching element, thereby driving the switching element to turn on or off according to the valid pulses of the clock signal. Each first clock line is configured to transmit a first clock signal; each line carries a specific clock signal, and the clock signals are coordinated in timing to achieve sequential segmented output of the continuous gate drive signal. For example, if M switching elements need to be turned on sequentially, the M first clock lines will transmit clock signals with sequentially valid pulses to ensure that each switching element is activated within the correct time window.

[0050] Two adjacent gate driving units 1001 can be two gate driving units 1001 that are physically adjacent or logically adjacent in a cascaded gate driving circuit 1000. The non-overlapping effective pulse periods of consecutive gate driving signals mean that at any given time point, only one gate driving unit 1001 outputs a continuous gate driving signal in an effective pulse state, while the continuous gate driving signal output by its adjacent gate driving unit 1001 is in an ineffective pulse state. This non-overlapping timing arrangement is crucial for ensuring stable system operation. It avoids time conflicts between the continuous gate driving signals of different gate driving units 1001, thereby preventing signal interference, power load transients, or incorrect pixel line 1011 scanning. For example, continuous gate driving signals can be generated using precise timing control circuitry to ensure they are staggered on the time axis; for instance, when the continuous gate driving signal of the Kth level gate driving unit 1001 is effective, the continuous gate driving signals of the (K-1)th and K+1th level gate driving units 1001 are both in an ineffective state.

[0051] As an example, Figure 5 This is a schematic diagram of the timing waveforms of the gate drive circuit provided in an embodiment of this application, as shown below. Figure 5 As shown, GN(n) and GN(n+1) are continuous gate drive signals, the duration of their high level is equal to the scan time of 3 pixel rows 1011, and the pulse width is greater than or equal to the scan time of 2 pixel rows 1011, corresponding to the definition of "gate drive unit 1001 outputs long pulse width signal" in claims 1 and 15; G1(n)_CK, G2(n)_CK, and G3(n)_CK are first clock signals, which generate effective pulses sequentially during the high level period of GN(n); G1(n), G2(n), and G3(n) are segmented gate drive signals, which are obtained by dividing GN(n) by time. The duration of the high level of each signal is equal to the scan time of 1 pixel row 1011, realizing that one gate drive unit 1001 drives 3 rows of pixels, and the effective pulse periods of GN(n) and GN(n+1) do not overlap.

[0052] This application provides M independent first clock lines to transmit the first clock signal for each of the M switching elements in each demultiplexing unit 1002, thereby enabling precise control of the conduction timing of each switching element and ensuring that continuous gate drive signals can be accurately segmented and output in time. Simultaneously, by ensuring that the effective pulse periods of continuous gate drive signals output by adjacent gate drive units 1001 do not overlap, signal conflicts and interference that may occur when different gate drive units 1001 output effective signals in the same time period are effectively avoided. The precise timing management and signal isolation mechanism enable each demultiplexing unit 1002 to operate independently and stably, ensuring that the segmented gate drive signals are accurately delivered to the corresponding pixel rows 1011, thereby improving the scanning accuracy and display quality of the display panel 100 and enhancing the stability and reliability of the entire gate drive circuit 1000.

[0053] In some embodiments of this application, when multiple gate drive units 1001 are cascaded, ensuring that the continuous gate drive signals output by each gate drive unit 1001 can be generated efficiently and orderly, and avoiding overlap of their effective pulse periods, is the key to achieving stable driving.

[0054] Based on this, in one embodiment, a plurality of gate driving units 1001 are electrically connected to N second clock lines, each second clock line being configured to transmit a second clock signal CK; wherein each gate driving unit 1001 outputs a continuous gate driving signal according to the corresponding second clock signal CK, and the effective pulse periods of the N second clock signals CK do not overlap.

[0055] Specifically, multiple gate driving units 1001 are electrically connected to N second clock lines, and the gate driving units 1001 are connected to a clock signal source through a specific physical path. The second clock lines are typically made of conductive material and are used to transmit electrical signals, ensuring that each gate driving unit 1001 can receive its required clock input. The N second clock lines can be arranged in parallel or connected in other topologies to accommodate the layout and wiring requirements of the display panel 100. Each second clock line is configured to output a second clock signal CK, indicating that each second clock line carries an independent clock signal with specific timing characteristics. The second clock signal CK can be a periodic voltage pulse, whose high or low level states represent valid or invalid signal periods, used to trigger or control the operation of the gate driving units 1001. For example, the second clock signal CK can be a square wave or a rectangular wave, with its frequency and duty cycle designed according to the scanning requirements of the display panel 100. The valid pulse periods of the N second clock signals CK do not overlap, meaning that at any given time, only one of the N second clock signals CK is in a valid state. The clock signals are staggered in time; for example, they can generate valid pulses sequentially to form a multiphase clock sequence. This non-overlapping timing arrangement is the basis for the orderly operation of the gate drive unit 1001.

[0056] This application utilizes multiple gate driving units 1001 to receive their respective second clock signals CK via N second clock lines. Since the effective pulse periods of the N second clock signals CK are configured to not overlap, at any given time, only one gate driving unit 1001 will output a continuous gate driving signal according to its corresponding second clock signal CK. This effectively solves the problem of potential interference or overlap between the output signals of multiple gate driving units 1001 operating in cascade, thereby ensuring that each gate driving unit 1001 can generate continuous gate driving signals in an orderly and precise manner. This not only simplifies the complexity of overall timing control and reduces system power consumption but also improves the stability and reliability of the gate driving signals, thus guaranteeing the normal scanning and image quality of the display panel 100.

[0057] In some embodiments of this application, ensuring that each gate driving unit 1001 can accurately control the output of continuous gate driving signals according to its corresponding second clock signal CK, so as to guarantee the accuracy of the signals and the synchronization of timing, is a problem that needs to be solved. If the output control of the gate driving unit 1001 is inaccurate, it may lead to distortion of the output signal waveform or timing deviation, thereby affecting the normal scanning and display quality of the display panel 100.

[0058] Based on this, in one embodiment, each gate driving unit 1001 includes an output subunit configured to control the signal transmission between the signal output terminal G of the gate driving unit 1001 and the corresponding second clock line.

[0059] Specifically, the output sub-unit is a functional module within the gate drive unit 1001. Its function is to precisely manage the signal flow from the internal drive mechanism of the gate drive unit 1001 to the external signal output terminal G, particularly the signal transmission with the corresponding second clock line. This output sub-unit can be designed in various forms. For example, it can be a controlled switch that, upon receiving a control signal, allows the signal on the second clock line to pass through and be transmitted to the signal output terminal G of the gate drive unit 1001. Alternatively, it can include a buffer or amplifier to shape or amplify the signal from the second clock line to ensure the quality and driving capability of the output signal. Furthermore, the output sub-unit can also be a logic gate circuit that, in conjunction with the internal state signal of the gate drive unit 1001 and the second clock signal CK, jointly determines the timing and waveform of the continuous gate drive signal output. This ensures that the signal output terminal G of the gate drive unit 1001 receives and outputs the signal from the second clock line only within a predetermined valid time period and with the correct waveform.

[0060] In this application, the gate driving unit 1001 can precisely control the signal transmission between its signal output terminal G and the corresponding second clock line through the output subunit. This allows the gate driving unit 1001 to accurately generate and output continuous gate driving signals according to the effective pulse period of the second clock signal CK, thereby effectively avoiding signal output distortion or timing deviation. This precise control ensures that the waveform and timing of the continuous gate driving signals are highly synchronized with system requirements, providing high-quality input for the subsequent demultiplexing unit 1002 to perform segmented signal processing, thus guaranteeing accurate scanning and stable display effects of the 100 pixel rows 1011 of the display panel. Furthermore, through effective management of signal transmission, unnecessary power consumption and potential signal interference are reduced, improving the overall performance and reliability of the gate driving circuit 1000.

[0061] In some embodiments of this application, if the key internal nodes (e.g., pull-up control node Q) of the control output subunit lack fine and stable potential control, the turn-on or turn-off of the output subunit may not be fast or thorough enough, or potential drift may occur during non-working periods, thereby affecting the waveform quality and timing accuracy of the continuous gate drive signal. Especially in application scenarios that drive multiple rows of pixels and require a wide pulse, instability may lead to display abnormalities.

[0062] In one embodiment, Figure 7This is a circuit diagram showing the connection between the gate driving unit and the demultiplexing unit provided in an embodiment of this application, as shown below. Figure 7 As shown, each gate driving unit 1001 further includes: a pull-up control unit electrically connected to the pull-up control node Q of the gate driving unit 1001, configured to perform pull-up driving on the pull-up control node Q; a pull-down unit electrically connected to the pull-up control node Q of the gate driving unit 1001, configured to perform pull-down discharging on the pull-up control node Q; and a pull-down sustaining unit electrically connected to the pull-up control node Q and the signal output terminal G of the gate driving unit 1001, configured to maintain the pull-down potential of the pull-up control node Q and the signal output terminal G; wherein, the output sub-unit is electrically connected to the pull-up control node Q of the gate driving unit 1001, and the output sub-unit is configured to control the signal transmission between the signal output terminal G and the corresponding second clock line according to the signal of the pull-up control node Q.

[0063] The pull-up control unit is used to actively raise the potential of the pull-up control node Q to a high level. During the operating cycle of the gate drive unit 1001, in order to turn on the output sub-unit and transmit the signal on the second clock line to the signal output terminal G, the pull-up control node Q needs to be driven quickly and stably to a sufficiently high potential. This pull-up control unit can be composed of one or more transistors. Its control terminal receives the output signal from the previous stage gate drive unit 1001 or a specific clock signal. When activated, it connects the pull-up control node Q to a high-level power supply, thereby achieving effective pull-up drive of the pull-up control node Q.

[0064] The pull-down unit is used to actively lower the potential of the pull-up control node Q to a low level. After the effective pulse of the continuous gate drive signal ends, in order to quickly turn off the output sub-unit and terminate the signal output, the pull-up control node Q needs to be quickly and completely discharged to a low level. This pull-down unit can be composed of one or more transistors, whose control terminal receives the output signal from the subsequent gate drive unit 1001 or a specific clock signal. When activated, it connects the pull-up control node Q to a low-level power supply, thereby achieving effective pull-down discharge of the pull-up control node Q.

[0065] The pull-down sustaining unit is used to continuously maintain the potential of the pull-up control node Q and the signal output terminal G at a low level during non-operational periods or when a low-level state is required. Throughout the entire operating cycle of the gate drive unit 1001, except during the active pulse period, the pull-up control node Q and the signal output terminal G typically need to be kept at a low level to prevent potential drift caused by parasitic capacitive coupling or noise interference, thereby avoiding mis-energization of the output sub-unit. This pull-down sustaining unit can be composed of one or more transistors, whose control terminal can be connected to a normally low-level signal or a specific clock signal, and whose source and drain terminals are connected to the pull-up control node Q, the signal output terminal G, and the low-level power supply, respectively, to ensure that the node is stably clamped at a low level when needed.

[0066] The output subunit has a direct electrical connection with the pull-up control node Q, and its operating state is entirely determined by the potential of the pull-up control node Q. When the pull-up control node Q is driven high by the pull-up control unit, the output subunit is activated, allowing the signal on the corresponding second clock line to be transmitted to the signal output terminal G, forming a valid pulse of continuous gate drive signal. When the pull-up control node Q is discharged low by the pull-down unit and held low by the pull-down sustaining unit, the output subunit is turned off, thereby preventing signal transmission and terminating the valid pulse.

[0067] This application achieves comprehensive and precise potential control of the pull-up control node Q of the control output subunit through the coordinated operation of the pull-up control unit, pull-down unit, and pull-down sustaining unit within the gate drive unit 1001. The pull-up control unit ensures that the pull-up control node Q can be driven to a high level quickly and forcefully, thereby ensuring that the output subunit can be turned on quickly when needed, resulting in steep and timely rising edges of continuous gate drive signals. The pull-down unit is responsible for quickly and effectively discharging the pull-up control node Q to a low level, ensuring that the output subunit can be turned off in a timely manner, thereby ensuring that the falling edges of continuous gate drive signals are rapid and accurate. In addition, the pull-down sustaining unit continuously maintains the pull-up control node Q and the signal output terminal G at a stable low level during non-operation periods, effectively suppressing potential drift caused by parasitic effects or noise, avoiding mis-turn-on or incomplete turn-off of the output subunit, thereby significantly improving the stability, waveform quality, and timing accuracy of the output signal of the gate drive unit 1001. The sophisticated internal node control mechanism enables the gate drive unit 1001 to reliably generate high-quality continuous gate drive signals, providing a solid foundation for the subsequent demultiplexing unit 1002 to accurately segment and output gate drive signals. This effectively solves the problems of signal instability and timing inaccuracy that may occur in multi-line driving and wide pulse applications, ensuring the stable display performance of the display panel 100.

[0068] In some embodiments of this application, the gate drive unit 1001 needs to ensure that its pull-up control node Q and signal output terminal G can be quickly and thoroughly pulled low and stably maintained during ineffective pulse periods to avoid signal crosstalk or unnecessary power consumption. However, existing technologies still face challenges in achieving efficient and reliable pull-down discharge and potential maintenance, which may lead to a decrease in the stability of the gate drive signal.

[0069] Based on this, in one embodiment, such as Figure 7 As shown, the pull-down sustaining unit includes a first inverter and a first sustaining sub-unit. The first inverter includes a first transistor T51, a second transistor T53, a third transistor T52, and a fourth transistor T54. The control terminal of the first transistor T51, the first source-drain terminal of the first transistor T51, and the first source-drain terminal of the second transistor T53 are configured to receive a third clock signal. The second source-drain terminal of the first transistor T51, the control terminal of the second transistor T53, and the second source-drain terminal of the third transistor T52 are electrically connected. The control terminals of the third transistor T52 and the fourth transistor T54 are electrically connected to the pull-up control node Q. The second source-drain terminals of the second transistor T53 and the second source-drain terminals of the fourth transistor T54 are electrically connected to the gate drive of this stage. The first node of unit 1001, the first source-drain terminal of the third transistor T52 and the first source-drain terminal of the fourth transistor T54 are electrically connected to the first power supply terminal; the first sustaining sub-unit includes the fifth transistor T42 and the sixth transistor T32, the control terminals of the fifth transistor T52 and the sixth transistor T54 are electrically connected to the first node of the gate driving unit 1001 of this stage, the first source-drain terminal of the fifth transistor T42 is electrically connected to the first power supply terminal, the second source-drain terminal of the fifth transistor T42 is electrically connected to the pull-up control node Q of the gate driving unit 1001 of this stage, and the second source-drain terminal of the sixth transistor T54 is electrically connected to the signal output terminal G of the gate driving unit 1001 of this stage.

[0070] Specifically, the first inverter is the core component of the pull-down unit. Its main function is to generate an inverted control signal based on the received third clock signal and transmit it to the first node of the gate drive unit 1001. The first transistor T51, second transistor T53, third transistor T52, and fourth transistor T54 work together to form a complex logic gate circuit. When the third clock signal is in a specific state, the conduction state of the first transistor T51 and the second transistor T53 is controlled, thereby affecting the gate potentials of the third transistor T52 and the fourth transistor T54, i.e., the potential of the pull-up control node Q. Through configuration, the first inverter can effectively pull the first node low or high, providing a drive signal for subsequent sustaining operations. For example, when the pull-up control node is high, the first inverter may be designed to pull the first node low, thereby activating the pull-down sustaining function.

[0071] The first sustaining subunit consists of a fifth transistor T42 and a sixth transistor T32. Its function is to perform pull-down sustaining operations on the pull-up control node Q and the signal output terminal G of the gate drive unit 1001 at this stage, based on the potential of the first node. When the first node is pulled low by the first inverter, the control terminals of the fifth transistor T42 and the sixth transistor T54 receive a low-potential signal, which may enable or disable them to pull the potential of the pull-up control node Q and the signal output terminal G to the first power supply terminal (usually a low potential or ground potential). The fifth transistor T42 is responsible for maintaining the low potential of the pull-up control node Q, while the sixth transistor T54 is responsible for maintaining the low potential of the signal output terminal G. This ensures that during the ineffective pulse period of the gate drive signal, the pull-up control node Q and the signal output terminal G can be stably maintained at a low potential, preventing charge accumulation or signal drift.

[0072] In this application, the pull-down function of the gate drive unit 1001 has been significantly enhanced and optimized. Specifically, the first inverter uses a third clock signal as input to precisely control the potential of the first node. When a pull-down operation is required, the first inverter drives the first node to a low potential, thereby activating the fifth transistor T42 and the sixth transistor T54 in the first sustaining sub-unit. The conduction of the fifth transistor T42 effectively pulls down the potential of the pull-up control node Q and maintains it at the first power supply terminal potential, ensuring that the pull-up control node Q is completely discharged during ineffective pulse periods, avoiding false triggering or signal distortion caused by residual charge. At the same time, the conduction of the sixth transistor T54 pulls down the potential of the signal output terminal G and maintains it at the first power supply terminal potential, thereby ensuring accurate turn-off of the output signal and preventing signal crosstalk and unnecessary power consumption. The collaborative working mechanism enables the gate driving unit 1001 to efficiently, stably, and reliably pull down and maintain the potential of the pull-up control node Q and the signal output terminal G when outputting continuous gate driving signals, thereby improving the performance and stability of the entire display panel 100 gate driving circuit 1000.

[0073] In some embodiments of this application, in the multi-stage cascaded gate drive circuit 1000, the potential of the pull-up control node Q may not be pulled down quickly and thoroughly due to various interferences or leakage currents, which may lead to unstable output of the gate drive signal or even false triggering, thereby affecting the display performance of the display panel 100.

[0074] Based on this, in one embodiment, the pull-down unit further includes: a first auxiliary subunit, the first auxiliary subunit including a first auxiliary transistor T55 and a second auxiliary transistor T56, the first source-drain terminal of the first auxiliary transistor T55 being electrically connected to the control terminal of the second transistor T53, the first source-drain terminal of the second auxiliary transistor T56 being electrically connected to the first node of the gate driving unit 1001 of this stage, and the second source-drain terminal of the first auxiliary transistor T55 and the second source-drain terminal of the second auxiliary transistor T56 being electrically connected to the first power supply terminal; wherein, the control terminal of the first auxiliary transistor T55 and the control terminal of the second auxiliary transistor T56 in the Kth stage gate driving unit 1001 are electrically connected to the pull-up control node Q of the KAth stage gate driving unit 1001, K is an integer, and KA>0, A≥1.

[0075] Specifically, the first auxiliary sub-unit is an auxiliary circuit whose main function is to enhance the pull-down capability of the pull-down unit. It consists of a first auxiliary transistor T55 and a second auxiliary transistor T56. The first source-drain terminal of the first auxiliary transistor T55 is electrically connected to the control terminal of the second transistor T53 of the first inverter in the pull-down unit, while the first source-drain terminal of the second auxiliary transistor T56 is electrically connected to the first node of the gate drive unit 1001 of this stage. The second source-drain terminals of both auxiliary transistors are electrically connected to the first power supply terminal, which is usually at a low potential (e.g., VSS). When the transistors are turned on, they can pull the connection point down to the potential of the first power supply terminal. This allows the first auxiliary sub-unit to be connected to the key nodes in the pull-down unit (the control terminal of the second transistor T53 and the first node) and activated under specific timing, enabling the pull-down unit to more effectively pull down the pull-up control node Q.

[0076] Meanwhile, taking A=2 as an example, the control terminals of the first auxiliary transistor T55 and the second auxiliary transistor T56 in the K-th stage gate driving unit 1001 are not directly controlled by this stage or adjacent stages, but are electrically connected to the pull-up control node Q of the (K-2)-th stage gate driving unit 1001. K is an integer, and K-2>0, indicating that the control signal originates from the gate driving units 1001 of the previous two stages. This cross-stage control connection method allows the state of the pull-up control node Q of the previous stage gate driving unit 1001 (K-2 stage) to serve as a trigger signal, controlling the pull-down operation of the current stage gate driving unit 1001 (K-th stage) in advance or in coordination.

[0077] In this application, when the pull-up control node Q potential of the (K-2)th stage gate driving unit 1001 goes high, it triggers the first auxiliary transistor T55 and the second auxiliary transistor T56 in the Kth stage gate driving unit 1001 to conduct. The conduction of the first auxiliary transistor T55 pulls the control terminal of the second transistor T53 low, thereby affecting the state of the first inverter and accelerating the pull-down process of the pull-up control node Q. At the same time, the conduction of the second auxiliary transistor T56 pulls the first node low, further enhancing the pull-down capability of the pull-down unit and assisting the pull-down function of the first sustaining sub-unit. This effectively solves the problem of incomplete or slow pull-down of the pull-up control node Q potential, ensuring a more stable and reliable output of the gate driving signal, avoiding display abnormalities caused by potential residue or false triggering, and thus significantly improving the display quality and operational stability of the display panel 100.

[0078] In some embodiments of this application, ensuring that the gate driving unit 1001 can efficiently and accurately generate its output signal, while simultaneously and effectively transmitting the control signal to the next-stage gate driving unit 1001 to maintain the stability and timing accuracy of the entire cascaded system, is a technical problem that needs further resolution. If the generation and transmission mechanisms of the output signal and cascaded signal are not clearly defined or are coupled, it may lead to signal distortion, timing errors, or increased power consumption, thereby affecting display performance.

[0079] Based on this, in one embodiment, such as Figure 7 As shown, each gate driving unit 1001 further includes a stage transmission sub-unit, which includes a stage transmission transistor T22. The stage transmission transistor T22 includes a control terminal electrically connected to the pull-up control node Q of the gate driving unit 1001, a first source-drain terminal electrically connected to the corresponding second clock line, and a second source-drain terminal electrically connected to the stage transmission output terminal of the gate driving unit 1001. The output sub-unit includes an output transistor T21, which includes a control terminal electrically connected to the pull-up control node Q of the gate driving unit 1001, a first source-drain terminal electrically connected to the corresponding second clock line, and a second source-drain terminal electrically connected to the signal output terminal G of the gate driving unit 1001. The first source-drain terminals of the output transistor T21 and the first source-drain terminals of the stage transmission transistor T22 of the same gate driving unit 1001 are electrically connected to the same second clock line.

[0080] Specifically, the cascading sub-unit is a key part of the gate driving unit 1001 responsible for transmitting the internal state or clock signal of the current gate driving unit 1001 to the next stage gate driving unit 1001. Its core component is the cascading transistor T22. The control terminal of the cascading transistor T22 is connected to the pull-up control node Q of the current gate driving unit 1001, and the conduction and turn-off of the cascading transistor T22 are controlled by the potential state of the pull-up control node Q. When the pull-up control node Q is at a high level (active state), the cascading transistor T22 conducts, transmitting the signal on the second clock line connected to its first source-drain terminal to its second source-drain terminal, i.e., the stage output terminal of the current gate driving unit 1001. This stage output terminal is usually connected to the input terminal of the next stage gate driving unit 1001, thereby realizing the cascading transmission of signals. This ensures that the next stage gate driving unit 1001 receives the start or control signal at the correct time, maintaining the cascading timing of the entire gate driving circuit 1000.

[0081] The output sub-unit is a key part of the gate drive unit 1001 responsible for generating and outputting continuous gate drive signals to the demultiplexing unit 1002. Its core component is the output transistor T21. Similar to the cascade transistor T22, the control terminal of the output transistor T21 is also electrically connected to the pull-up control node Q of the gate drive unit 1001, so its on / off state is also controlled by the potential state of the pull-up control node Q. When the pull-up control node Q is active, the output transistor T21 is turned on, transmitting the signal on the second clock line connected to its first source-drain terminal to its second source-drain terminal, i.e., the signal output terminal G of the gate drive unit 1001. This signal output terminal G then sends the continuous gate drive signals to the corresponding demultiplexing unit 1002. This ensures that the output signal of the gate drive unit 1001 is synchronized with the internal control state, thereby providing a stable and timing-accurate gate drive signal.

[0082] Furthermore, the first source-drain terminals of the output transistor T21 and the first source-drain terminals of the cascade transistor T22 in the same gate drive unit 1001 are electrically connected to the same second clock line. The output signal and cascaded signal of this stage gate drive unit 1001 both originate from the same second clock line. This shared clock source design simplifies circuit layout and timing control, as the effective pulses of both the output signal and the cascaded signal are driven directly or indirectly by the same clock signal. When the pull-up control node Q is active, the output transistor T21 and the cascade transistor T22 are simultaneously turned on, transmitting the signal on the second clock line to the signal output terminal G and the stage output terminal, respectively. This ensures that the output of the gate drive signal in this stage is highly synchronized with the start signal of the next stage gate drive unit 1001, thereby improving the timing accuracy and operational stability of the entire gate drive circuit 1000.

[0083] In this application, the output sub-unit and cascading sub-unit within the gate drive unit 1001 are explicitly defined as including output transistor T21 and cascading transistor T22. The control of these transistors is uniformly managed by the pull-up control node Q of the gate drive unit 1001, and their signal sources all originate from the same second clock line. This allows the gate drive unit 1001 to precisely control the output of its continuous gate drive signals and synchronously transmit cascaded signals to the next-stage gate drive unit 1001. Since both the output signal and the cascaded signal originate from the same second clock line and are controlled by the same pull-up control node Q, timing design is greatly simplified, ensuring a high degree of synchronization between signal output and cascading transmission, effectively avoiding display abnormalities or cascading failures caused by timing mismatches. Furthermore, this structure helps optimize circuit layout, reduces wiring complexity, and improves the overall integration and reliability of the gate drive circuit 1000.

[0084] In one embodiment, as shown in FIG7, each gate driving unit 1001 further includes: a pull-up control unit electrically connected to the pull-up control node Q of the gate driving unit 1001, configured to perform pull-up driving on the pull-up control node Q; a pull-down unit electrically connected to the pull-up control node Q of the gate driving unit 1001, configured to perform pull-down discharging on the pull-up control node Q; and a pull-down sustaining unit electrically connected to the pull-up control node Q and the signal output terminal G of the gate driving unit 1001, configured to maintain the pull-down potential of the pull-up control node Q and the signal output terminal G; wherein, the output sub-unit is electrically connected to the pull-up control node Q of the gate driving unit 1001, and the output sub-unit is configured to control the signal transmission between the signal output terminal G and the corresponding second clock line according to the signal of the pull-up control node Q.

[0085] The gate drive unit further includes a twelfth transistor T42, a thirteenth transistor T73, and a bootstrap capacitor Cbt.

[0086] The control terminal of the twelfth transistor T42 is electrically connected to the first node (pull-down control node) of the gate drive unit of this stage. The first source-drain terminal of the twelfth transistor T42 is electrically connected to the first power supply terminal (low-level power supply terminal). The second source-drain terminal of the twelfth transistor T42 is electrically connected to the signal output terminal G of the gate drive unit of this stage. The twelfth transistor T42 is used to perform a pull-down sustaining operation on the signal output terminal G under the potential control of the first node.

[0087] The control terminal of the thirteenth transistor T73 is electrically connected to the second node (pull-down control node) of the gate drive unit of this stage. The first source-drain terminal of the thirteenth transistor T73 is electrically connected to the first power supply terminal. The second source-drain terminal of the thirteenth transistor T73 is electrically connected to the pull-up control node Q of the gate drive unit of this stage. The thirteenth transistor T73 is used to perform a pull-down maintenance operation on the pull-up control node Q under the potential control of the second node.

[0088] One end of the bootstrap capacitor Cbt is electrically connected to the pull-up control node Q of the gate drive unit of this stage, and the other end of the bootstrap capacitor Cbt is electrically connected to the signal output terminal G of the gate drive unit of this stage. The bootstrap capacitor Cbt is used to realize the potential bootstrap between the pull-up control node Q and the signal output terminal G, so as to improve the output driving capability and signal stability of the signal output terminal G.

[0089] In some embodiments of this application, to ensure the stability and reliability of the gate drive signal, precise and strong control of the pull-up control node Q is required to resist various interferences and ensure rapid signal establishment and decay. Simply relying on control at the same or adjacent stages may not provide sufficient drive strength or flexible control timing, thus affecting the quality of the gate drive signal.

[0090] Based on this, in one embodiment, such as Figure 7 As shown, the pull-up control unit includes a first switching transistor T11, which includes a control terminal, a first source-drain terminal, and a second source-drain terminal electrically connected to the pull-up control node Q; the pull-down unit includes a second switching transistor T41, which includes a control terminal, a first source-drain terminal electrically connected to the first power supply terminal, and a second source-drain terminal electrically connected to the pull-up control node Q; wherein, in the K-th level gate drive unit 1001, the control terminal of the first switching transistor T11 is electrically connected to the stage output terminal of the KB-th level gate drive unit 1001, and the control terminal of the second switching transistor T41 is electrically connected to the stage output terminal of the K+C-th level gate drive unit 1001, where K is an integer, and KB>0, B≥1, and C≥1.

[0091] Specifically, the pull-up control unit's function is to pull the potential of the pull-up control node Q high, making it reach an effective drive level, thereby enabling the output sub-unit to conduct and transmit the second clock signal CK to the signal output terminal G. The first switching transistor T11 is the key component for implementing pull-up control. Its second source-drain terminal is electrically connected to the pull-up control node Q. When the first switching transistor T11 is turned on, it can transfer the potential from the first source-drain terminal to the first source-drain terminal, realizing the pull-up operation. The first switching transistor T11 can be implemented using an N-type or P-type thin-film transistor, and its conduction state is controlled by the signal received at its control terminal. For example, if it is an N-type transistor, the transistor conducts when the control terminal receives a high-level signal.

[0092] Simultaneously, the pull-down unit's function is to pull the potential of the pull-up control node Q low, causing it to discharge rapidly to a low level, thereby enabling the output sub-unit to turn off and stop transmitting the second clock signal CK to the signal output terminal G. The second switching transistor T41 is the key component for implementing the pull-down operation. Its second source-drain terminal is electrically connected to the pull-up control node Q, and its first source-drain terminal is electrically connected to the first power supply terminal (usually low level or ground). When the second switching transistor T41 is turned on, it discharges the charge of the pull-up control node Q to the first power supply terminal, realizing the pull-down operation. The second switching transistor T41 can also be implemented using an N-type or P-type thin-film transistor, and its conduction state is controlled by the signal received at its control terminal. For example, if it is an N-type transistor, the transistor turns on when the control terminal receives a high-level signal.

[0093] Based on this, taking B=6 and C=8 as an example, the control terminal of the first switching transistor T11 of the Kth stage gate drive unit 1001 receives a signal from the stage output terminal of the preceding (K-6)th stage gate drive unit 1001. The pull-up operation is initiated by the cascaded output of an earlier gate drive unit 1001, thus achieving early pre-charging or an earlier start-up timing. Simultaneously, the control terminal of the second switching transistor T41 of the Kth stage gate drive unit 1001 receives a signal from the stage output terminal of the following (K+8)th stage gate drive unit 1001. The pull-down operation is initiated by the cascaded output of a later gate drive unit 1001, thus achieving delayed pull-down or a longer effective pulse duration. This cross-stage control connection method makes the control timing of the gate drive unit 1001 more flexible and precise, effectively avoiding timing conflicts between adjacent stages and providing more stable control for the generation of continuous gate drive signals. Here, K is an integer, and the condition K-6>0 ensures that the source of the control signal is a valid and existing stage.

[0094] This application achieves precise and powerful control of the pull-up control node Q potential by electrically connecting the control terminal of the first switching transistor T11 in the pull-up control unit of the Kth stage gate drive unit 1001 to the stage output terminal of the (K-6)th stage gate drive unit 1001, and electrically connecting the control terminal of the second switching transistor T41 in the pull-down unit to the stage output terminal of the (K+8)th stage gate drive unit 1001. The introduction of control signals across multiple stages allows the pull-up control node Q to receive an effective drive signal earlier when pull-up is required, ensuring the timeliness and sufficiency of the pull-up operation and effectively improving the rise time speed and high-level stability of the gate drive signal. Simultaneously, the pull-down operation control signal comes from a more distant subsequent stage, providing a longer sustaining time for the effective pulse of the current stage gate drive unit 1001 and ensuring the thoroughness of the pull-down operation, thereby accelerating the fall time speed of the gate drive signal and effectively suppressing crosstalk and fluctuation at the signal output terminal G. This not only enhances the anti-interference capability of the gate driving unit 1001, but also optimizes the waveform quality of the continuous gate driving signal, enabling it to drive multiple rows of pixels more stably, thereby improving the display performance and reliability of the display panel 100.

[0095] In some embodiments of this application, in the pull-down unit of the gate driving unit 1001, when a fast and stable pull-down operation is required, a single pull-down path may not be sufficient to cope with complex noise interference or rapidly changing signal requirements, resulting in an incomplete pull-down effect or insufficient response speed, thereby affecting the stability of the gate driving signal and the display quality.

[0096] Based on this, in one embodiment, such as Figure 7As shown, the pull-down sustaining unit further includes a second inverter, a second sustaining sub-unit, and a second auxiliary sub-unit. The second inverter includes a seventh transistor T61, an eighth transistor T63, a ninth transistor T43, and a tenth transistor T74. The control terminal of the seventh transistor T61, the first source-drain terminal of the seventh transistor T61, and the first source-drain terminal of the eighth transistor T63 are configured to receive a fourth clock signal. The second source-drain terminal of the seventh transistor T61, the control terminal of the eighth transistor T63, and the second source-drain terminal of the ninth transistor T43 are electrically connected. The control terminals of the ninth transistor T43 and the tenth transistor T74 are electrically connected to the pull-up control node Q. The second source-drain terminals of the eighth transistor T63 and the tenth transistor T74 are electrically connected to the second node of the gate drive unit 1001 of this stage. The first source-drain terminals of the ninth transistor T43 and the tenth transistor T74 are electrically connected to the first power supply terminal. The second sustaining sub-unit includes an eleventh transistor T64. The control terminals of the twelfth transistor T62, the eleventh transistor T64, and the twelfth transistor T62 are electrically connected to the second node of the gate drive unit 1001 of this stage. The first source-drain terminal of the eleventh transistor T64 is electrically connected to the first power supply terminal. The second source-drain terminal of the eleventh transistor T64 is electrically connected to the pull-up control node Q of the gate drive unit 1001 of this stage. The second source-drain terminal of the twelfth transistor T62 is electrically connected to the signal output terminal G of the gate drive unit 1001 of this stage. The second auxiliary sub-unit includes the third auxiliary transistor T65 and the third auxiliary transistor T66. The first source-drain terminal of the third auxiliary transistor T65 is electrically connected to the control terminal of the eighth transistor T63. The first source-drain terminal of the third auxiliary transistor T66 is electrically connected to the second node of the gate drive unit 1001 of this stage. The second source-drain terminals of the third auxiliary transistor T65 and the third auxiliary transistor T66 are electrically connected to the first power supply terminal. The third clock signal and the fourth clock signal are inverted.

[0097] Specifically, the second inverter is an additional inverter circuit composed of the seventh transistor T61, the eighth transistor T63, the ninth transistor T43, and the tenth transistor T74. Its main function is to receive the fourth clock signal and, based on the state of this signal, coordinate with the potential of the pull-up control node Q to jointly control the potential of the second node. By introducing a second inverter, an independent pull-down control path can be provided, enhancing the control capability and anti-interference ability of the pull-down unit. For example, the seventh transistor T61 and the eighth transistor T63 can form an input stage to receive the fourth clock signal, while the ninth transistor T43 and the tenth transistor T74 switch according to the potential of the pull-up control node Q, thereby generating a corresponding control signal at the second node. The second sustaining subunit consists of the eleventh transistor T64 and the twelfth transistor T62, and its control terminal is electrically connected to the second node. When the second node is at a specific potential, the second sustaining subunit can conduct, thereby pulling the potential of the pull-up control node Q and the signal output terminal G to the first power supply potential. An additional mechanism for maintaining the pull-down state is provided, working in conjunction with the first sustaining subunit to further ensure that the pull-up control node Q and the signal output G can be stably maintained at a low potential when pull-down is required. For example, the eleventh transistor T64 can be used to pull down the pull-up control node Q, and the twelfth transistor T62 can be used to pull down the signal output G. The second auxiliary subunit consists of the third auxiliary transistors T65 and T66, which assist in the normal operation of the second inverter and the second sustaining subunit. The first source-drain terminal of the third auxiliary transistor T65 is electrically connected to the control terminal of the eighth transistor T63, and the first source-drain terminal of the third auxiliary transistor T66 is electrically connected to the second node, both of which are electrically connected to the first power supply terminal. Additional current paths or potential clamps can be provided to ensure the stability and reliability of the second inverter and the second sustaining subunit during specific operating phases. For example, under certain timing conditions, the auxiliary transistors can help quickly pull down the potential of the relevant nodes to prevent floating or false triggering. The third clock signal and the fourth clock signal are inverted; when one signal is high, the other signal is low, and vice versa. The inverting relationship allows the first and second inverters to operate alternately or complementaryly, providing pull-down control at different times or enhanced pull-down capability within the same time period. For example, when the third clock signal is valid, the first inverter may primarily handle the pull-down; when the fourth clock signal is valid, the second inverter takes over or assists in the pull-down, forming a dual or redundant pull-down mechanism.

[0098] This application introduces a second inverter, a second sustaining subunit, and a second auxiliary subunit into the pull-down unit, and inverts the third and fourth clock signals. This enables the gate drive circuit 1000 to provide dual or complementary pull-down paths. When the gate drive unit 1001 needs to perform a pull-down operation, the inverted third and fourth clock signals ensure that at least one pull-down path is in an effective working state, or that both paths work together, thereby significantly enhancing the pull-down capability of the pull-up control node Q and the signal output terminal G. This effectively solves the problems of incomplete pull-down, slow response speed, or susceptibility to noise interference that may exist with a single pull-down path. Especially under high-frequency or complex timing requirements, it ensures fast, stable, and complete pull-down of the gate drive signal, thereby improving the scanning accuracy and image quality of the display panel 100. Furthermore, the dual pull-down mechanism also improves the robustness of the circuit and reduces the risk of display abnormalities due to single-path failure. In some embodiments of this application, when the circuit is started or experiences power fluctuations, the pull-up control node Q may be at an unstable potential due to residual charge or uncertain initial state, which may cause the gate drive unit 1001 to output abnormal signals, affecting the normal operation of the display panel 100 and even increasing unnecessary power consumption.

[0099] Based on this, in one embodiment, such as Figure 7 As shown, 1001 also includes a reset transistor T44; the gate of the reset transistor T44 is connected to the reset signal Reset terminal of the gate driving unit 1001, the source is connected to the first power supply terminal, and the drain is connected to the pull-up control node Q of the gate driving unit 1001; the reset transistor T44 is used to pull the potential of the pull-up control node Q to the potential of the first power supply terminal when it is turned on.

[0100] Specifically, the reset transistor T44 is a switching device, such as a thin-film transistor (TFT), whose main function is to force the potential of a node in the circuit to a preset value under specific conditions. In this embodiment, it is used to reset the potential of the pull-up control node Q. This transistor can be an N-type or P-type transistor, depending on the potential of the power supply terminal it is connected to and the polarity of the reset signal Reset. The reset signal Reset terminal of the gate drive unit 1001 is an input port of the gate drive unit 1001, used to receive the externally provided reset signal Reset. When the reset signal Reset is in an active state, it controls the reset transistor T44 to turn on, thereby performing a reset operation. The active state of the reset signal Reset can be high or low, matching the type of the reset transistor T44. The first power supply terminal usually refers to a reference potential in the circuit, such as ground potential (VSS) or negative power supply potential. In the gate drive circuit 1000, it is often used to provide a low level or as a reference for pull-down operation. The pull-up control node Q of the gate drive unit 1001 is a critical node inside the gate drive unit 1001. Its potential state directly affects the turn-on and turn-off of the output sub-unit, thereby controlling the output of the gate drive signal. By pulling its potential to the potential of the first power supply terminal through the reset transistor T44, it can be ensured that the node is in a known and stable low-level state at a specific time, providing a reliable starting condition for subsequent drive operations.

[0101] This application introduces a reset transistor T44, with its gate connected to the reset signal Reset terminal, its source connected to the first power supply terminal, and its drain connected to the pull-up control node Q. This effectively solves the problem of potential uncertainty in the pull-up control node Q during circuit startup or abnormal conditions. When the reset signal Reset is valid, the reset transistor T44 is turned on, forcibly pulling the potential of the pull-up control node Q to the potential of the first power supply terminal, thereby ensuring that the pull-up control node Q is always in a definite low-level state. This not only provides stable initial conditions for the subsequent operation of the gate drive unit 1001, avoiding malfunctions caused by node potential drift or residual charge, but also significantly improves the accuracy and reliability of the gate drive signal output. Given that the pull-up control node Q is the key to controlling the output subunit, a reliable reset mechanism is crucial for the stable operation of the entire gate drive circuit 1000, effectively preventing scanning abnormalities or display defects in the display panel 100, and helping to reduce system power consumption.

[0102] In some embodiments of this application, if the timing relationship between the reset operation and the startup stage operation of the gate driving unit 1001 is not precisely defined, the gate driving unit 1001 may start working in the case of incomplete reset, which may lead to unstable startup or abnormal output signal, affecting the display quality of the display panel 100.

[0103] Based on this, in one embodiment, the gate drive circuit further includes a frame start signal terminal, used to control the gate drive circuit to start the stage transmission after the reset transistor T44 completes the charge discharge of the pull-up control node Q; wherein, the time when the reset signal Reset terminal enters the valid state is earlier than the time when the frame start signal of the frame start signal terminal enters the valid state.

[0104] Specifically, the frame start signal terminal is a dedicated input port used to receive an externally generated frame start signal. In some embodiments, the first-stage gate drive unit in the gate drive circuit synchronizes its internal operations by transmitting the frame start signal through this terminal. The frame start signal terminal can be a physical pin or a logic input interface, and the received frame start signal is typically a pulse signal used to indicate the start of a new frame scan cycle. It can be provided by an external timing controller or generated internally by the system.

[0105] The frame start signal is configured to control the gate drive circuit to initiate cascading after the reset transistor T44 completes the charge discharge of the pull-up control node Q. Before the gate drive circuit begins its normal cascading operation, it must be ensured that its internal critical nodes, especially the pull-up control node Q, have been completely discharged to the potential of the first power supply terminal through the reset transistor T44. This ensures that the gate drive unit 1001 is in a clean and defined initial state each time it starts, avoiding the influence of residual charge from the previous frame on the operation of the current frame. Starting cascading means that the gate drive unit 1001 will transition from a static or reset state to an operating state, and begin generating and outputting gate drive signals according to a preset timing sequence. This can be achieved by activating the corresponding timing control module after the internal logic circuit detects a valid edge (e.g., rising or falling edge) of the frame start signal.

[0106] To achieve the precise timing control described above, the reset signal at the Reset input is set to become active earlier than the frame start signal at the frame start signal input. For example, if both the reset signal (Reset) and the frame start signal (Frame Start signal) are active high, the high-level pulse of the reset signal (Reset) must end before the high-level pulse of the frame start signal (Frame Start signal) arrives. This timing arrangement ensures the integrity of the reset operation; that is, all reset actions are completed before the gate drive circuit is officially activated to initiate stage transmission.

[0107] As an example, Figure 8 This is a schematic diagram of the timing waveforms of the reset signal and the frame start signal provided in the embodiments of this application, as shown below. Figure 8As shown, RESET is the reset signal, corresponding to the signal at the Reset terminal of reset transistor T44. During its effective high level, reset transistor T44 is turned on, pulling the potential of pull-up control node Q to the low level of the first power supply terminal, completing charge discharge. STV is the frame start signal, corresponding to the signal at the frame start signal terminal. The start time of its effective high level is later than the end time of the effective high level of the RESET signal. This timing strictly follows the order in which the reset signal Reset is effective before the frame start signal, ensuring that before each gate drive unit 1001 is transmitted to the startup stage, the pull-up control node Q has completed charge discharge, and the initial state is clean and without residue, avoiding signal interference.

[0108] Figure 9 This is a schematic diagram of the timing waveform of the clock signal corresponding to the gate driving unit provided in the embodiments of this application, as shown below. Figure 9 As shown, CK1~CK12 are the second clock signals CK, with waveforms that are effective sequentially in a stepped manner. The effective pulse periods do not overlap, providing the driving clock for each level of the gate drive unit 1001. Reset is the reset signal, and STV is the frame start signal. The effective time of RESET is earlier than that of STV, completing the charge discharge of the pull-up control node Q before starting the stage transmission. The continuous gate drive signals output by each level of the gate drive unit 1001 have effective pulse periods that do not overlap. VSSQ and VSSG are the first power supply terminals, providing low-level potentials for the pull-down unit and the pull-down sustaining unit. The third clock signal LC1 and the fourth clock signal LC2 are sustaining control signals, providing control signals for the pull-down sustaining unit, realizing the stable pull-down of the pull-up control node Q and the output terminal.

[0109] Figure 10 This is a timing diagram illustrating the coordination between the gate drive signal and the data signal provided in an embodiment of the present invention, as shown below. Figure 10 As shown, GN1 is a continuous gate drive signal output by the gate drive unit 1001. During its high-level active period, the data signal sequentially outputs the grayscale data of each pixel row 1011. That is, within the effective period of a long-pulse gate signal, data writing of multiple rows of pixels is completed. CN1 and CN2 are control signals that work synchronously with GN1 and the data signal. They are used to coordinate the timing of the data drive circuit and the gate drive circuit 1000, ensuring that the data signal can be stably written to the corresponding pixel row 1011 during the effective period of the gate signal, thus realizing the normal scanning drive of the high pixel density display panel 100. The timing coordination of a single long-pulse gate signal and multiple rows of data signals can complete the driving of multiple rows of pixels. The CN1, CN2, and data signals work synchronously with the gate drive signal to realize the normal scanning drive of the pixel array 101.

[0110] This application establishes a clear and strict timing relationship between the reset operation and the startup cascade operation of the gate driving unit 1001. The reset signal Reset first places the gate driving unit 1001 into a stable initial state, and then the frame start signal triggers the gate driving unit 1001 to start generating and cascading the output gate driving signal. This step-by-step and orderly startup process effectively avoids problems such as unstable operation or abnormal output pulses of the gate driving unit 1001 caused by incomplete reset or conflict between reset and startup timing. This not only ensures that the gate driving circuit 1000 can operate stably and reliably at the beginning of each frame, but also significantly improves the display quality and operational stability of the display panel 100, effectively suppressing potential problems such as screen flicker, abnormal starting line scanning, or incomplete display of the first line of image, thereby providing users with a better visual experience.

[0111] In some embodiments of this application, if the correspondence between the duration of the continuous gate drive signal and the number of driven pixel rows 1011 is not clear enough, or if the demultiplexing unit 1002 lacks a unified standard for the signal segmentation method, the output gate drive signal may have uncertainties in timing and pulse width, thereby affecting the stable scanning of pixel rows 1011 and the uniformity of display effect.

[0112] Based on this, in one embodiment, the high-level duration of the continuous gate drive signal is equal to the sum of the scan times of L pixel rows 1011, where L is an integer greater than or equal to 2; the demultiplexing unit 1002 is further configured to divide the continuous gate drive signal into L gate drive signals by time, and the high-level duration of each gate drive signal is equal to the scan time of one row of pixels.

[0113] Specifically, the high-level duration of the continuous gate drive signal is precisely defined as the sum of the scan times of L pixel rows 1011. For example, when L is set to 3, the high level of the signal will last precisely for 3 pixel rows 1011 scan times. This quantized duration setting provides a clear and predictable input timing reference for the subsequent operations of the demultiplexing unit 1002, ensuring the stability of the signal source. Based on this, after receiving this continuous gate drive signal with a precise duration, the demultiplexing unit 1002 performs fine time division on it. This division process is uniform, that is, the entire high-level duration is evenly distributed among the L output channels. Therefore, each gate drive signal will have a standardized high-level duration that precisely corresponds to the scan time of a single pixel row 1011. For example, if the continuous signal lasts for 3 row scan times, the demultiplexing unit 1002 will sequentially output 3 independent gate drive signals, each with a high-level duration of 1 row scan time.

[0114] This application establishes a precise quantization relationship between the duration of the continuous gate drive signal and the number of driven pixel rows 1011, and the segmentation method of the demultiplexing unit 1002 is also standardized. This ensures that the gate drive signal received by each pixel row 1011 is highly consistent and accurate in pulse width and timing, effectively avoiding timing deviations and pulse width unevenness caused by inaccurate signal segmentation. Ultimately, this helps to achieve stable and uniform scanning of the 100 pixel rows 1011 of the display panel, significantly improving the quality and consistency of the displayed image. In some embodiments of this application, since the gate lines of the pixel array 101 of the display panel 100 typically have large parasitic capacitance, directly outputting the segmented gate drive signal to the pixel row 1011 through a simple switching element may cause problems such as signal attenuation, slowed rising or falling edges during signal transmission, thereby affecting the waveform quality of the gate drive signal and the normal scanning of the pixel row 1011, and thus affecting the display effect.

[0115] Based on this, in one embodiment, the demultiplexing unit 1002 includes multiple output branches. Each output branch is connected between the gate drive signal output terminal G of the demultiplexing unit 1002 and the corresponding pixel row 1011. Each output branch includes a buffered enhanced switching stage, which includes: an input buffer connected to the clock signal terminal of the demultiplexing unit 1002 for amplifying the demultiplexed clock signal; a switching transistor array whose input terminal is connected to the gate drive signal output terminal G of the demultiplexing unit 1002 and whose control terminal is connected to the output terminal of the input buffer; and an output drive buffer connected to the output terminal of the switching transistor array for outputting the enhanced gate drive signal to the corresponding pixel row 1011.

[0116] Specifically, the multiple output branches are parallel signal paths within the demultiplexing unit 1002, with each path specifically responsible for transmitting the time-segmented gate drive signal to a specific pixel row 1011. This enables the demultiplexing unit 1002 to efficiently process and output multiple independent gate drive signals in parallel to meet the driving requirements of multiple rows of pixels.

[0117] The buffered enhanced switching stage is not a simple switching element, but a circuit stage that integrates signal buffering and enhancement functions. Its main function is to effectively amplify and shape the signal while switching signals, thereby ensuring that the gate drive signal output to pixel row 1011 has sufficient driving capability and excellent waveform quality.

[0118] The input buffer is connected to the clock signal terminal of the demultiplexing unit 1002, and its function is to amplify the demultiplexed clock signal. The demultiplexed clock signal, such as the first clock signal mentioned in the above embodiment, is typically used to precisely control the conduction timing of switching elements. If the driving capability of this clock signal is insufficient, it may lead to slow switching speed or incomplete conduction of the switching elements, thereby affecting the accuracy of signal segmentation. Amplifying the clock signal through the input buffer ensures that it has sufficient current driving capability, enabling the switching transistor array to achieve fast and accurate switching. For example, the input buffer can be composed of one or more inverters, or a non-inverting buffer can be used to improve the signal fan-out capability and driving strength.

[0119] The input terminal of the switching transistor array is connected to the gate drive signal output terminal G of the demultiplexing unit 1002 (i.e., the continuous gate drive signal from the gate drive unit 1001), and its control terminal is connected to the output terminal of the input buffer. This array is a key component for realizing time-segmented switching of the signal. It is typically composed of multiple transistors connected in parallel or series, and its on / off state is precisely controlled by the clock signal amplified by the input buffer. When the control signal is active, the switching transistor array is turned on, transmitting a specific period of the continuous gate drive signal to the output drive buffer. The array design provides a larger current path according to actual needs, effectively reducing on-resistance and ensuring signal transmission efficiency.

[0120] The output drive buffer is connected to the output of the switching transistor array to output the enhanced gate drive signal to the corresponding pixel row 1011. Finally, the processed signal is sent to the portion of pixel row 1011. Even though the switching transistor array has completed the signal switching, considering that the gate lines of pixel row 1011 typically have large parasitic capacitances, a powerful driver is still needed to quickly charge and discharge the capacitors. The output drive buffer can provide a large current output, ensuring steep rising and falling edges of the gate drive signal and stable voltage swing, thereby guaranteeing the scanning timing and display quality of pixel row 1011. For example, this output drive buffer can be a push-pull output stage composed of PMOS and NMOS transistors, or a buffer composed of multiple inverters to provide strong driving capability.

[0121] As an example, Figures 6 to 10As shown, assuming the multiplexing unit includes multiple switches, such as TFT1, TFT2, and TFT3, controlled by the first clock signals CK1, CK2, and CK3 respectively. Taking a 1-to-3 conversion as an example: At time T0: the GOA unit outputs a continuous gate drive signal GN1, high for 6 hours; at time T1: CK1 is active, TFT1 is on, outputting G1 for 2 hours; at time T2: CK2 is active, TFT2 is on, outputting G2 for 2 hours; at time T3: CK3 is active, TFT3 is on, outputting G3 for 2 hours. Thus, one gate drive unit drives three rows of pixels, which can be generalized to a 1-to-N structure. In this embodiment, the timing parameters can be VGH=30V, VGL=-14V, VSSQ=-14V, VSSG=-10V; 541 action cycles are set per frame, and 6480 action cycles are set for data; the LC1 and LC2 signals flip once every 100 frames within the blanking interval to prevent image retention and improve the long-term reliability of the panel. To suppress timing offsets caused by TFT process deviations under high PPI, each output branch of the demultiplexing unit is equipped with a buffered enhanced switching stage, including: an input buffer: shaping and amplifying the first clock signal with steep edges; a switching transistor array: multiple TFTs connected in parallel to average process deviations; and an output drive buffer: strongly driving and reshaping the waveform to ensure accurate gate drive signal amplitude, pulse width, and edges, improving brightness unevenness and image retention. This embodiment achieves one GOA driving multiple rows of pixels through long-pulse GOA and demultiplexing, reducing the number of GOA stages and shrinking the bezel; it improves driving stability through inverters, early reset, and asymmetric pull-down; and it enhances resistance to process deviations through buffered enhanced switching stages, making it suitable for high pixel density narrow bezel display products such as mobile phones, VR / AR, and automotive displays.

[0122] This application effectively solves the problems of gate drive signal attenuation and waveform distortion when driving pixel rows 1011 with large parasitic capacitance by introducing a buffer-enhanced switching stage in each output branch of the demultiplexing unit 1002. Specifically, the input buffer amplifies the demultiplexed clock signal, ensuring that the switching transistor array can be turned on and off quickly and accurately, thereby achieving precise signal segmentation. Subsequently, the output drive buffer enhances the segmented gate drive signal, providing sufficient current drive capability to quickly charge and discharge the gate lines of pixel rows 1011, ensuring steep rising and falling edges of the gate drive signal and stable voltage swing. This results in the gate drive signal output to pixel rows 1011 having excellent waveform quality and driving capability, thereby ensuring accurate scanning timing of pixel rows 1011 and significantly improving the display effect and reliability of the display panel 100.

[0123] As an example, consider a high pixel density (PPI) display panel 100, whose pixel array 101 comprises multiple rows of pixels. In a conventional display panel 100 design, each pixel row 1011 typically requires a separate gate drive unit 1001 to provide the gate drive signal. However, with the increase in PPI and the reduction in pixel size, the height of the pixel row 1011 is limited. Simultaneously, strict requirements on bezel dimensions make it difficult for conventional GOA circuits, which configure one gate drive unit 1001 for each pixel row 1011, to meet layout space requirements, potentially leading to increased bezels or layout difficulties.

[0124] To address this technical problem, an improved gate drive circuit 1000 is employed in the example. The gate drive circuit 1000 includes a plurality of cascaded gate drive units 1001 and a plurality of demultiplexing units 1002 corresponding to the gate drive units 1001.

[0125] Specifically, suppose the pixel array 101 of the display panel 100 needs to drive multiple rows of pixels, for example, from the first row to the Nth row. A conventional GOA circuit might require N gate driving units 1001. In this example, the gate driving circuit 1000 is designed to significantly reduce the number of gate driving units 1001.

[0126] For example, the first gate driving unit 1001 is configured to output a continuous gate driving signal. The effective pulse duration of the continuous gate driving signal is set to be equal to the sum of the scan times of L pixel rows 1011, where L is an integer greater than or equal to 2, for example, L=3. The width of the effective pulse is 3 times the scan time of a single pixel row 1011.

[0127] A first demultiplexing unit 1002 is connected to the first gate driving unit 1001. The first demultiplexing unit 1002 includes M switching elements, where M equals L, i.e., M=3. The three switching elements are electrically connected between the signal output terminal G of the first gate driving unit 1001 and the first pixel row 1011, the second pixel row 1011, and the third pixel row 1011, respectively.

[0128] During the effective pulse period of the continuous gate drive signal output by the first gate drive unit 1001, the M switching elements in the first demultiplexing unit 1002 are configured to be turned on sequentially. Specifically, the M switching elements are controlled to be turned on and off by different first clock signals. For example, the first clock signal generates an effective pulse during the first period of the effective pulse of the continuous gate drive signal, turning on the first switching element and outputting that period of the continuous gate drive signal to the first pixel row 1011. Then, the second clock signal CK generates an effective pulse during the second period of the effective pulse of the continuous gate drive signal, turning on the second switching element and outputting that period of the continuous gate drive signal to the second pixel row 1011. Subsequently, the third clock signal generates an effective pulse during the third period of the effective pulse of the continuous gate drive signal, turning on the third switching element and outputting that period of the continuous gate drive signal to the third pixel row 1011.

[0129] In this manner, the first demultiplexing unit 1002 segments the effective pulses of the continuous gate drive signal output by the first gate drive unit 1001 according to time, thereby forming effective pulses of the gate drive signal corresponding to different pixel rows 1011. The duration of the effective pulse of each segmented gate drive signal is equal to the scanning time of one row of pixels. Therefore, one gate drive unit 1001 (e.g., the first gate drive unit 1001) can drive multiple different pixel rows 1011 (e.g., the first, second, and third pixel rows 1011).

[0130] To ensure sequential scanning of the entire pixel array 101, the effective pulse periods of the continuous gate drive signals output by adjacent gate drive units 1001 (e.g., the first gate drive unit 1001 and the second gate drive unit 1001) do not overlap. Furthermore, the plurality of gate drive units 1001 are electrically connected to N second clock lines, each second clock line transmitting a second clock signal CK, and the effective pulse periods of the N second clock signals CK do not overlap. Each gate drive unit 1001 outputs its continuous gate drive signal according to the corresponding second clock signal CK.

[0131] Compared to existing technologies where each pixel row 1011 requires a separate gate driving unit 1001, this example introduces a demultiplexing unit 1002, enabling one gate driving unit 1001 to drive multiple rows of pixels. For example, if L=3, the number of gate driving units 1001 can be reduced to one-third of the original. This significantly reduces the physical layout space required for the gate driving circuit 1000, effectively reducing the bezel size of high-PPI display products, improving layout feasibility, and simplifying the manufacturing process. For instance, in the bezel area of ​​the display panel 100, the space that previously required three levels of GOA circuitry now only needs to accommodate one level of GOA circuitry and one demultiplexing unit 1002, making bezel design more flexible and facilitating narrower bezels.

[0132] This application embodiment also provides a display panel 100, including the gate driving circuit 1000 described above.

[0133] Display panel 100 is a device for displaying images, including a pixel array 101 composed of multiple pixel rows 1011 and pixel columns. Each pixel typically includes one or more thin-film transistors (TFTs) and storage capacitors. Display panels 100 come in various types, such as liquid crystal display panels (LCDs), organic light-emitting diode display panels (OLEDs), or micro-LED display panels. In practical implementations, display panel 100 is typically supported by a glass substrate or flexible substrate, and key components such as the pixel array 101, gate driving circuit 1000, data driving circuit, and timing controller are integrated on it. The display panel 100 includes the aforementioned gate driving circuit 1000. The gate driving circuit 1000 plays a crucial role in the display panel 100; its main function is to provide on or off gate driving signals (i.e., gate driving signals) to each row of pixels in the pixel array 101 according to timing requirements, thereby controlling the conduction state of the pixels and enabling the data driving circuit to write image data into the corresponding pixels. By integrating the gate drive circuit 1000 with the innovative driving method into the display panel 100, it can be ensured that the display panel 100 can make full use of the continuous gate drive signal and demultiplexing technology provided by the gate drive circuit 1000 to achieve efficient and accurate scanning and driving of the pixel array 101.

[0134] This application integrates the gate driving circuit 1000 into the display panel 100, enabling the display panel 100 to directly utilize the unique driving mechanism provided by the gate driving circuit 1000. Specifically, the display panel 100 can use the continuous gate driving signals output by the gate driving circuit 1000, and then demultiplex it in segments by time via the demultiplexing unit 1002 to form effective pulses of gate driving signals corresponding to different pixel rows 1011. This allows one gate driving unit 1001 to effectively drive multiple different pixel rows 1011, thereby significantly improving the driving efficiency and integration of the display panel 100. This not only simplifies the overall driving architecture of the display panel 100 but also helps reduce power consumption and may reduce the bezel width of the display panel 100. Ultimately, this display panel 100 can achieve stable and efficient image display, improving display performance and user experience. This application embodiment also provides a display device 10, including the display panel 100 described above.

[0135] The display device 10 can be a device capable of receiving, processing, and displaying image or video information. It typically consists of multiple components, including a display panel 100, a driving circuit, a control circuit, a power module, a housing, and a user interface. Display devices 10 come in various types, such as smartphones, tablets, televisions, monitors, and automotive displays. In implementation, the display device 10 needs to effectively integrate the display panel 100 with the corresponding control system, power management system, and user interface to ensure stable and efficient operation of the display panel 100 and to provide display effects that meet user needs. For example, in a smartphone, the display panel 100 is integrated with the main control chip, battery, touchscreen controller, etc., to form a complete display module, which is then packaged into the phone's housing.

[0136] This application integrates the display panel 100 with the specific gate drive circuit 1000 into the display device 10, thereby providing a complete terminal product that can be directly used by the user. This integration not only allows the technical advantages of the display panel 100—segmented output of continuous gate drive signals and driving multiple rows of pixels 1011—to be fully utilized in practical applications, but also ensures optimization of the entire display device 10 in terms of power consumption, display quality, and user experience. The overall design of the display device 10 can fully utilize the efficient scanning characteristics of the display panel 100, thereby achieving smoother image display, lower system power consumption, and a more compact product structure, ultimately enhancing the product's market competitiveness.

[0137] The gate driving circuit 1000, the display panel 100, and the display device 10 provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A gate driving circuit for a display panel, characterized in that, The display panel includes a pixel array, and the pixel array includes multiple pixel rows; The gate driving circuit includes: A cascaded plurality of gate driving units, each of the gate driving units being used to output a continuous gate driving signal, wherein the pulse width of the effective pulse of the continuous gate driving signal is greater than or equal to the scan time of at least two pixel rows; Multiple demultiplexing units are provided, each of which is connected to a gate driving unit. Each demultiplexing unit is configured to output the effective pulses of the continuous gate driving signals output by the corresponding gate driving unit in time segments to form effective pulses of the gate driving signals corresponding to different pixel rows, so that one gate driving unit drives multiple different pixel rows.

2. The gate driving circuit according to claim 1, characterized in that, Each of the demultiplexing units includes M switching elements, and each of the switching elements is electrically connected between the signal output terminal of the corresponding gate driving unit and a pixel row; Where M ≥ 2; the M switching elements in the same demultiplexing unit are configured to be turned on sequentially during the period when the continuous gate drive signal output by the corresponding gate drive unit has a valid pulse, so as to output the valid pulse of the corresponding continuous gate drive signal in time segments.

3. The gate driving circuit according to claim 2, characterized in that, The M switching elements located in the same demultiplexing unit are each controlled to be turned on and off by different first clock signals; Among them, the M first clock signals corresponding to the same demultiplexing unit are configured to generate valid pulses sequentially during the period when the continuous gate drive signal output by the gate drive unit corresponding to the demultiplexing unit has valid pulses.

4. The gate driving circuit according to claim 3, characterized in that, Multiple demultiplexing units are electrically connected to M first clock lines, each of which is configured to transmit a first clock signal; The effective pulse periods of the continuous gate drive signals output by two adjacent gate drive units do not overlap.

5. The gate driving circuit according to claim 4, characterized in that, The plurality of gate driving units are electrically connected to N second clock lines, each of the second clock lines being configured to transmit a second clock signal; Each of the gate driving units outputs the continuous gate driving signal according to the corresponding second clock signal, and the effective pulse periods of the N second clock signals do not overlap.

6. The gate driving circuit according to claim 5, characterized in that, Each of the gate driving units includes: The output subunit is configured to control the signal transmission between the signal output terminal of the gate drive unit and the corresponding second clock line.

7. The gate driving circuit according to claim 6, characterized in that, Each of the gate driving units further includes: The pull-up control unit is electrically connected to the pull-up control node of the gate drive unit at this level and is configured to perform a pull-up drive on the pull-up control node. The pull-down unit is electrically connected to the pull-up control node of the gate drive unit at this level and is configured to perform pull-down discharge on the pull-up control node; The pull-down sustaining unit is electrically connected to the pull-up control node and the signal output terminal of the gate drive unit of this stage, and is configured to maintain the pull-down potential of the pull-up control node and the signal output terminal; The output sub-unit is electrically connected to the pull-up control node of the gate drive unit of this stage, and the output sub-unit is configured to control the signal transmission between the signal output terminal and the corresponding second clock line according to the signal of the pull-up control node.

8. The gate driving circuit according to claim 7, characterized in that, The pull-down sustaining unit includes: The first inverter includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The control terminal of the first transistor, the first source-drain terminal of the first transistor, and the first source-drain terminal of the second transistor are configured to receive a third clock signal. The second source-drain terminal of the first transistor, the control terminal of the second transistor, and the second source-drain terminal of the third transistor are electrically connected. The control terminals of the third transistor and the fourth transistor are electrically connected to the pull-up control node. The second source-drain terminal of the second transistor and the second source-drain terminal of the fourth transistor are electrically connected to the first node of the gate drive unit of this stage. The first source-drain terminal of the third transistor and the first source-drain terminal of the fourth transistor are electrically connected to a first power supply terminal. The first sustaining sub-unit includes a fifth transistor and a sixth transistor. The control terminals of the fifth transistor and the sixth transistor are electrically connected to the first node of the gate driving unit of this stage. The first source-drain terminal of the fifth transistor is electrically connected to the first power supply terminal. The second source-drain terminal of the fifth transistor is electrically connected to the pull-up control node of the gate driving unit of this stage. The second source-drain terminal of the sixth transistor is electrically connected to the signal output terminal of the gate driving unit of this stage.

9. The gate driving circuit according to claim 8, characterized in that, The pull-down sustaining unit also includes: The first auxiliary sub-unit includes a first auxiliary transistor and a second auxiliary transistor. The first source-drain terminal of the first auxiliary transistor is electrically connected to the control terminal of the second transistor. The first source-drain terminal of the second auxiliary transistor is electrically connected to the first node of the gate driving unit of this level. The second source-drain terminals of the first auxiliary transistor and the second source-drain terminal of the second auxiliary transistor are electrically connected to the first power supply terminal. In this context, the control terminals of the first auxiliary transistor and the second auxiliary transistor in the K-th gate driving unit are electrically connected to the pull-up control node of the KA-th gate driving unit, where K is an integer, KA>0, and A≥1.

10. The gate driving circuit according to claim 8, characterized in that, Each of the gate driving units further includes a stage transmission sub-unit, the stage transmission sub-unit including a stage transmission transistor, the stage transmission transistor including a control terminal electrically connected to the pull-up control node of the gate driving unit of the same stage, a first source-drain terminal electrically connected to the corresponding second clock line, and a second source-drain terminal electrically connected to the stage transmission output terminal of the gate driving unit of the same stage. The output subunit includes an output transistor, which includes a control terminal electrically connected to the pull-up control node of the gate driving unit of this level, a first source-drain terminal electrically connected to the corresponding second clock line, and a second source-drain terminal electrically connected to the signal output terminal of the gate driving unit of this level. The first source-drain terminals of the output transistor and the first source-drain terminals of the cascade transistor of the same gate driving unit are electrically connected to the same second clock line.

11. The gate driving circuit according to claim 10, characterized in that, The pull-up control unit includes a first switching transistor, which includes a control terminal, a first source-drain terminal, and a second source-drain terminal electrically connected to the pull-up control node. The pull-down unit includes a second switching transistor, which includes a control terminal, a first source-drain terminal electrically connected to the first power supply terminal, and a second source-drain terminal electrically connected to the pull-up control node. In the Kth level gate driving unit, the control terminal of the first switching transistor is electrically connected to the stage output terminal of the KBth level gate driving unit, and the control terminal of the second switching transistor is electrically connected to the stage output terminal of the K+Cth level gate driving unit. K is an integer, and KB>0, B≥1, C≥1.

12. The gate driving circuit according to claim 9, characterized in that, The pull-down sustaining unit also includes: The second inverter includes a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor. The control terminal of the seventh transistor, the first source-drain terminal of the seventh transistor, and the first source-drain terminal of the eighth transistor are configured to receive a fourth clock signal. The second source-drain terminal of the seventh transistor, the control terminal of the eighth transistor, and the second source-drain terminal of the ninth transistor are electrically connected. The control terminals of the ninth transistor and the tenth transistor are electrically connected to the pull-up control node. The second source-drain terminal of the eighth transistor and the second source-drain terminal of the tenth transistor are electrically connected to the second node of the gate drive unit of this stage. The first source-drain terminal of the ninth transistor and the first source-drain terminal of the tenth transistor are electrically connected to the first power supply terminal. The second sustaining sub-unit includes an eleventh transistor and a twelfth transistor. The control terminals of the eleventh transistor and the twelfth transistor are electrically connected to the second node of the gate driving unit of this stage. The first source-drain terminal of the eleventh transistor is electrically connected to the first power supply terminal. The second source-drain terminal of the eleventh transistor is electrically connected to the pull-up control node of the gate driving unit of this stage. The second source-drain terminal of the twelfth transistor is electrically connected to the signal output terminal of the gate driving unit of this stage. The second auxiliary subunit includes a third auxiliary transistor and a fourth auxiliary transistor. The first source-drain terminal of the third auxiliary transistor is electrically connected to the control terminal of the eighth transistor. The first source-drain terminal of the fourth auxiliary transistor is electrically connected to the second node of the gate driving unit of this stage. The second source-drain terminals of the third and fourth auxiliary transistors are electrically connected to the first power supply terminal. The third clock signal and the fourth clock signal are out of phase.

13. The gate driving circuit according to claim 8, characterized in that, The gate driving unit further includes a reset transistor; the control terminal of the reset transistor is connected to the reset signal terminal of the gate driving unit, the first source-drain terminal is connected to the first power supply terminal, and the second source-drain terminal is connected to the pull-up control node of the gate driving unit. The reset transistor is used to pull the potential of the pull-up control node to the potential of the first power supply terminal when it is turned on.

14. The gate driving circuit according to claim 13, characterized in that, The gate drive circuit further includes a frame start signal terminal, used to control the gate drive circuit to start the stage transmission after the reset transistor completes the charge discharge of the pull-up control node; wherein, the time when the reset signal of the reset signal terminal enters the valid state is earlier than the time when the frame start signal of the frame start signal terminal enters the valid state.

15. The gate driving circuit according to claim 1, characterized in that, The high-level duration of the continuous gate drive signal is equal to the sum of the scan times of L pixel rows, where L is an integer greater than or equal to 2; The demultiplexing unit is further configured to divide the continuous gate drive signals into L gate drive signals by time, wherein the high-level duration of each gate drive signal is equal to the scanning time of one row of pixels.

16. The gate driving circuit according to any one of claims 1-15, characterized in that, The demultiplexing unit includes multiple output branches, each output branch being connected between the gate drive signal output terminal of the demultiplexing unit and the corresponding pixel row. Each output branch includes a buffered enhanced switching stage, the buffered enhanced switching stage comprising: An input buffer, connected to the clock signal terminal of the demultiplexing unit, is used to amplify the demultiplexing clock signal; A switching transistor array, wherein the input terminal of the switching transistor array is connected to the gate drive signal output terminal of the demultiplexing unit, and the control terminal is connected to the output terminal of the input buffer; An output drive buffer is connected to the output terminal of the switching transistor array and is used to output an enhanced gate drive signal to the corresponding pixel row.

17. A display panel, characterized in that, Includes the gate drive circuit according to any one of claims 1-16.

18. A display device, characterized in that, Includes the display panel as described in claim 17.

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