Display device

Abstract

The present application provides a display device. A timing control circuit provides m control signals, where m is a positive integer greater than or equal to 2. A multiplexer circuit provides source driving signals to corresponding m data lines in time division according to the m control signals, where the interval period of fixed edges of at least two control signals among the m control signals is 1 / k of the period of a horizontal synchronization signal in a horizontal synchronization signal period, k is a positive integer, and 2≤k≤m.

Description

Technical Field

[0001] This invention relates to an electronic device, and more particularly to a display device. Background Technology

[0002] In display panels, to avoid data mischarging caused by overlap between the gate selection signals generated by the gate drive circuit and the preceding and following stages, the multiplexer control signal is usually concentrated in the central interval of the row display period of the same row of sub-pixels. While this prevents data mischarging, it also concentrates the charging time of each sub-pixel in a narrow interval, which can easily lead to uneven charging rates and thus cause visual unevenness in the image (such as vertical lines or color shifts). Summary of the Invention

[0003] The present invention provides a display device that can effectively improve the uniformity of visual effects.

[0004] The display device of the present invention includes multiple gate lines, multiple data lines, a gate driving circuit, a timing control circuit, and multiple multiplexer circuits. The gate driving circuit is coupled to the multiple gate lines and drives them sequentially. The timing control circuit provides m control signals, where m is a positive integer greater than or equal to 2. Each control signal includes at least one write interval, the size of which is an integer fraction of the period of the horizontal synchronization signal. The multiple multiplexer circuits are coupled to the timing control circuit and the multiple data lines. Each multiplexer circuit is coupled to a corresponding m data lines. Each multiplexer circuit provides source driving signals to the corresponding m data lines in a time-division multiplexing manner according to the m control signals. The interval period of a fixed edge of the m control signals is 1 / k of the period of the horizontal synchronization signal, and at least two of the m control signals have the same interval period within one horizontal synchronization signal period. The fixed edge is either a rising edge or a falling edge, k is a positive integer, and 2 ≤ k ≤ m.

[0005] In one embodiment of the present invention, each control signal includes at least one write interval. Each write interval is defined by the time corresponding to the start voltage of the rising edge and the end voltage of the falling edge when the start voltage of the rising edge of the corresponding control signal is the same, or by the time corresponding to the end voltage of the rising edge and the start voltage of the falling edge when the end voltage of the rising edge of the corresponding control signal is the same.

[0006] In one embodiment of the present invention, the writing intervals of m control signals are different within the same horizontal synchronization signal period.

[0007] In one embodiment of the present invention, the same control signal has different write intervals in adjacent horizontal synchronization signal periods.

[0008] In one embodiment of the present invention, the size order of the writing intervals of the above-mentioned m control signals changes with the periodic update of the horizontal synchronization signal.

[0009] In one embodiment of the present invention, the writing intervals of m control signals are written in reverse order during two adjacent horizontal synchronization signal cycles.

[0010] In one embodiment of the present invention, in the same horizontal synchronization signal cycle, at least two of the m control signals have the same write interval, and the write intervals of the m control signals are not completely the same.

[0011] In one embodiment of the invention, the voltage variation amplitude of the fixed edge is greater than or equal to 2 volts.

[0012] In one embodiment of the present invention, within the same display frame, the timing control circuit treats only the rising edge as a fixed edge or only the falling edge as a fixed edge.

[0013] In one embodiment of the present invention, the fixed edges of m control signals have the same interval period within at least two consecutive horizontal synchronization signal cycles.

[0014] Based on the above, the multiplexer circuit of this embodiment can provide source drive signals to the corresponding m data lines in a time-division manner according to m control signals, wherein the fixed edge interval of the m control signals is 1 / k of the horizontal synchronization signal period within at least two consecutive horizontal synchronization signal periods, where k is a positive integer and 2≤k≤m. This allows the charging time of each sub-pixel to be evenly distributed during the line display period, effectively improving the uniformity of the visual effect.

[0015] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a display device according to an embodiment of the present invention;

[0017] Figures 2 to 9 This is a waveform diagram of the control signal according to an embodiment of the present invention. Detailed Implementation

[0018] To make the contents of this invention more readily apparent, the following specific embodiments are provided as examples on which this invention can indeed be practiced. Furthermore, wherever possible, components / members referred to by the same reference numerals in the drawings and embodiments represent the same or similar parts.

[0019] Figure 1 This is a schematic diagram of a display device according to an embodiment of the present invention. Please refer to... Figure 1The display device 100 includes a gate driving circuit 102, a timing control circuit 104, multiplexer circuits MUX1 and MUX2, multiple gate lines (for simplicity, only one gate line GL1 is shown in this embodiment), multiple data lines SL1-SL6, multiple sub-pixels P1-P6, and multiple selection transistors MS1-MS6. The selection transistors MS1-MS6 are respectively coupled to their corresponding sub-pixels P1-P6. The gate driving circuit 102 is coupled to the gate line GL1 and, through the gate line GL1, is coupled to the gate of the selection transistors MS1-MS6. The control and output terminals of the multiplexer circuits MUX1 and MUX2 are respectively coupled to the timing control circuit 104 and the data lines SL1-SL6. The signal input terminals of the multiplexer circuits MUX1 and MUX2 receive source driving signals S1 and S2 respectively and are coupled to the sources of the selection transistors MS1-MS6 through the data lines SL1-SL6. Furthermore, the multiplexer circuit MUX1 may include transistors M1, M3, and M5, and the multiplexer circuit MUX2 may include transistors M2, M4, and M6. The gates of transistors M1 to M6 are coupled to the timing control circuit 104, and transistors M1 to M6 are coupled between the corresponding data lines SL1 to SL6 and the corresponding signal input terminals.

[0020] Gate driving circuit 102 generates gate selection signals to sequentially drive multiple gate lines to turn on the corresponding selection transistors during the row display of each row of sub-pixels, for example in... Figure 1 In this circuit, the gate drive circuit 102 generates a gate selection signal CKV1 to turn on selection transistors MS1-MS6 during the display period of sub-pixels P1-P6. The source drive signals S1 and S2 output by the source drive circuit enter the multiplexer circuits MUX1 and MUX2 after fan-out routing. Further, as... Figure 1As shown, the source drive signal S1 can be provided to one end of transistors M1, M3, and M5 in multiplexer circuit MUX1, and the source drive signal S2 can be provided to one end of transistors M2, M4, and M6 in multiplexer circuit MUX2. Timing control circuit 104 generates control signals CKH1~CKH3 to multiplexer circuits MUX1 and MUX2, thereby sequentially controlling the on / off states of transistors M1~M6 through CKH1, CKH2, and CKH3, enabling multiplexer circuits MUX1 and MUX2 to charge sub-pixels P1~P6 in a time-division multiplexing manner. In this embodiment, the 1-to-3 multiplexer circuits MUX1 and MUX2 are used as an example for explanation. However, in other embodiments, the multiplexer circuits MUX1 and MUX2 may also be 1-to-2, 1-to-4, or 1-to-higher-value multiplexer circuits, and coupled to different numbers of data lines. In addition, the timing control circuit 104 will also generate the corresponding number of control signals according to the implementation of the multiplexer circuits MUX1 and MUX2, for example, generating m control signals CKH1~CKHm, where m is a positive integer greater than or equal to 2.

[0021] The timing control circuit 104 can adjust the waveforms of control signals CKH1~CKH3 to ensure that the charging time of each sub-pixel P1~P6 is evenly distributed during the horizontal display period, thereby effectively improving charging uniformity. Furthermore, the timing control circuit 104 can select either the rising edge or the falling edge of the control signal as the fixed edge according to actual needs, and control the fixed edge to maintain the same interval period relationship within at least two consecutive horizontal synchronization signal cycles. The interval period of the fixed edge is 1 / k of the horizontal synchronization signal period, where k is a positive integer, and 2≤k≤m, where m is the number of control signals generated by the timing control circuit 104, and m is a positive integer greater than or equal to 2. This ensures that the charging time is evenly distributed during the horizontal display period, avoiding uneven charging rates and thus improving the visual uniformity of the displayed image.

[0022] For example, such as Figure 2As shown, the interval period of the falling edge Egf (in this embodiment, the fixed edge is the falling edge Egf) of CKH1, CKH2, and CKH3 is 1 / 3 of the horizontal synchronization signal period H (i.e., H / 3), and the falling edge Egf maintains the same interval period relationship within at least two consecutive horizontal synchronization signal periods H (e.g., within two horizontal synchronization signal periods H defined by horizontal synchronization signals Hsync1, Hsync2, and Hsync3). For example, if the horizontal synchronization signal period H is 9µs, then the interval period of the falling edge Egf is 3µs. In other embodiments, the rising edge Egr can also be used as the fixed edge, and is not limited to this embodiment. The voltage change amplitude of the rising edge Egr or falling edge Egf selected as the fixed edge is greater than or equal to 2 volts (V), for example, from 0V to 2V, or from 10V to 7V, or from -16V to -12V. The reference for calculating the interval period of the fixed edge is the same voltage change range, such as two rising edges that both change from 0V to 3V, or two falling edges that both change from -6V to -10V. Furthermore, within the same display frame, the timing control circuit 104 selects only one of the rising edge Egr or the falling edge Egf as the fixed edge. Control signals CKH1, CKH2, and CKH3 respectively include write intervals TD1, TD2, and TD3. The write interval is defined by the time corresponding to the start voltage of the rising edge and the end voltage of the falling edge in the same control signal, or by the time corresponding to the end voltage of the rising edge and the start voltage of the falling edge in the same control signal. For example, in... Figure 3 In this embodiment, the fixed edge is the falling edge Egf, and the interval period of the falling edge Egf is 1 / 2 of the horizontal synchronization signal period H (i.e., H / 2). For example, if the horizontal synchronization signal period H is 9µs, then the interval period of the falling edge Egf is 4.5µs.

[0023] It is worth noting that, since the actual waveform of the control signal may not be a perfect square wave, in some embodiments, the interval period can be determined, for example, based on a portion of the control signal's waveform. For example, such as... Figure 4A and Figure 4B The control signals CKH1 and CKH2 shown can be determined based on the time interval between band AB of control signal CKH1 and band A'-B' of control signal CKH2. Band AB and band A'-B' can, for example, be the first 1% to 10% of the rising edge of control signals CKH1 and CKH2 (1% to 10% of the amplitude value), respectively. In some embodiments, the time interval between control signals CKH1 and CKH2 can be determined, for example, based on the time difference between points A and A' or the time difference between points B and B'.

[0024] Similarly, the time interval between control signals CKH1 and CKH2 can be determined based on the time interval between band CD of control signal CKH1 and bands C'-D' of control signal CKH2, where bands CD and C'-D' can be, for example, the first 1% to 10% of the falling edge of control signals CKH1 and CKH2 (99% to 90% of the amplitude value), respectively. In some embodiments, the time interval between control signals CKH1 and CKH2 can also be determined, for example, based on the time difference between points C and C' or the time difference between points D and D'.

[0025] In some embodiments, within the same horizontal synchronization signal cycle, the sizes of the write intervals of the m control signals generated by the timing control circuit 104 may be different from each other; alternatively, at least two of the m control signals may have the same size write interval, and the sizes of the write intervals of the m control signals may not be completely identical. For example, such as... Figure 5 As shown, in Figure 5 In this embodiment, the fixed edge is the falling edge Egf. Within the same horizontal synchronization signal period H, the write intervals TD1, TD2, and TD3 are written in descending order of size as TD1, TD2, and TD3. In other embodiments, the size of the write intervals can be adjusted according to actual needs. Figure 5 This is a limited embodiment; for example, it can be optimized to address differences in fan-out impedance or sub-pixel load across different panels, further ensuring that each sub-pixel receives an appropriate charging time. The size of each write interval TD1, TD2, and TD3 is an integer fraction of the horizontal synchronization signal period H.

[0026] Furthermore, in some embodiments, the size of the write intervals TD1, TD2, and TD3 can be, for example, greater than H / m. For example... Figure 6 As shown, in Figure 6 In this embodiment, the order of size of the write intervals TD1, TD2, and TD3 is TD1, TD2, TD3, and the size of each write interval TD1, TD2, and TD3 is greater than H / 3 (m=3). This ensures that each sub-pixel has sufficient charging time while maintaining a fixed edge interval period.

[0027] In some embodiments, the size of the write interval for the same control signal in adjacent horizontal synchronization signal cycles may be different. For example, such as Figure 7 As shown, in Figure 7In this embodiment, the order of the write intervals TD1, TD2, and TD3 changes with the update of the horizontal synchronization signal period H. That is, in two adjacent horizontal synchronization signal periods H (the horizontal synchronization signal period H between horizontal synchronization signals Hsync1 and Hsync2, and the horizontal synchronization signal period H between horizontal synchronization signals Hsync2 and Hsync3), the order of the write intervals TD1, TD2, and TD3 of the control signals CKH1, CKH2, and CKH3 is reversed (from TD1>TD2>TD3 to TD3>TD2>TD1). This further improves the overall uniformity of the charging time of multiple consecutive rows of sub-pixels and reduces the charging difference between pixels in adjacent rows. In other embodiments, the change in the size of the write intervals TD1, TD2, and TD3 between two adjacent horizontal synchronization signal periods H is not based on... Figure 7 As limited to this embodiment, in other embodiments, the size of at least one of the write intervals TD1, TD2, and TD3 may be changed, for example, without being limited to the order of the sizes of the write intervals TD1, TD2, and TD3 of two adjacent horizontal synchronization signal periods H being reversed.

[0028] In some embodiments, the control signal may also include multiple write ranges. For example, such as Figure 8 As shown, control signals CKH1~CKH3 can have multiple edge levels. The same control signal may contain multiple rising edges (Egr1, Egr2) or falling edges (Egf1, Egf2). Even if the waveform exhibits multiple rising or falling edges, the fixed edges and write intervals (TD1A, TD1B, TD2A, TD2B, TD3A, TD3B) of this invention are still defined as intervals with voltage changes greater than or equal to 2 volts. This implementation effectively covers signal distortion caused by actual panel wiring and is suitable for display products with long-distance fan-out or high loads.

[0029] Taking control signal CKH1 as an example, such as Figure 9 As shown, the control signal CKH1 has rising edges Egr1 and Egr2 and falling edges Egf1 and Egf2. Rising edge Egr1 starts at voltage V1 and ends at voltage V2, rising edge Egr2 starts at voltage V2 and ends at voltage V4, falling edge Egf1 starts at voltage V4 and ends at voltage V3, and falling edge Egf2 starts at voltage V3 and ends at voltage V1. The write interval is defined by the time corresponding to the start voltage of the rising edge and the end voltage of the falling edge when the start voltage of the corresponding control signal's rising edge is the same as the end voltage of the falling edge, or by the time corresponding to the end voltage of the rising edge and the start voltage of the falling edge when the end voltage of the corresponding control signal's rising edge is the same as the start voltage of the falling edge. Therefore, in Figure 9In this embodiment, the time interval corresponding to the start voltage V1 of the rising edge Egr1 and the end voltage V1 of the falling edge Egf2 is defined as the write interval TD1A, and the time interval corresponding to the end voltage V4 of the rising edge Egr2 and the start voltage V4 of the falling edge Egf1 is defined as the write interval TD1B. The write intervals of the control signals CKH2 and CKH3 are also defined according to the same principle, and will not be described again here.

[0030] return Figure 8 In the embodiments, in Figure 8 In this embodiment, the timing control circuit 104 uses the rising edge Egr2 as the fixed edge. Similar to the above embodiment, the rising edge Egr2 of the control signals CKH1~CKH3 maintains the same interval period relationship within at least two consecutive horizontal synchronization signal periods H, and the interval period of the fixed edge is 1 / k of the horizontal synchronization signal period H. In other embodiments, the timing control circuit 104 may also use the rising edge Egr1, the falling edge Egf1, or the falling edge Egf2 as the fixed edge, for example, and is not limited to this embodiment. In addition, the write intervals TD1A~TD3A and TD1B~TD3B may also use the above-described... Figure 2 , Figure 3 as well as Figures 5-9 The implementation method for writing intervals TD1 to TD3 will not be described in detail here.

[0031] It is worth noting that, in the above Figures 2-3 , Figures 5-9 Even when the waveform of the control signal is not a perfect square wave, it can still be used as follows: Figure 4A , Figure 4B The implementation method determines the time interval between different control signals, and the determination method can be derived from... Figure 4A , Figure 4B It is inferred that this will not be elaborated upon further. Furthermore, regarding... Figure 8 , Figure 9 The control signal, specifically the first 1% to 10% of the rising and falling edges, can also be used to define the write interval. For example, in... Figure 9 In the embodiment, the write interval TD1A can be defined based on the time corresponding to the first 1% to 10% of the band of the rising edge Egr1 and the first 1% to 10% of the band of the falling edge Egf2, ​​and the write interval TD1B can be defined based on the time corresponding to the first 1% to 10% of the band of the rising edge Egr2 and the first 1% to 10% of the band of the falling edge Egf.

[0032] In summary, the multiplexer circuit of the embodiments of the present invention can provide source drive signals to the corresponding m data lines in a time-division multiplexing manner according to m control signals, wherein the fixed edge interval of the m control signals is 1 / k of the horizontal synchronization signal period within at least two consecutive horizontal synchronization signal periods, k is a positive integer, and 2≤k≤m. This allows the charging time of each sub-pixel to be evenly distributed during the row display period, thereby effectively improving the problem of uneven charging rate, significantly improving the visual uniformity of the displayed image, and thus optimizing the overall display quality of the display device.

[0033] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A display device, characterized in that, include: Multiple gate lines; Multiple data cables; A gate driving circuit is coupled to the plurality of gate lines and drives the plurality of gate lines sequentially. A timing control circuit provides m control signals, where m is a positive integer greater than or equal to 2. Each control signal includes at least one write interval, the size of which is an integer fraction of the period of the horizontal synchronization signal. as well as Multiple multiplexer circuits are coupled to the timing control circuit and the multiple data lines. Each multiplexer circuit is coupled to the corresponding m data lines. Each multiplexer circuit provides source drive signals to the corresponding m data lines in a time-division multiplexing manner according to m control signals. The fixed edge interval of the m control signals is 1 / k of the period of the horizontal synchronization signal, and at least two consecutive fixed edges of the m control signals have the same interval period within the period of the horizontal synchronization signal. The fixed edge is a rising edge or a falling edge, k is a positive integer, and 2≤k≤m.

2. The display device according to claim 1, characterized in that, Each control signal includes at least one write interval. Each write interval is defined by the time corresponding to the start voltage of the rising edge and the end voltage of the falling edge when the start voltage of the rising edge of the corresponding control signal is the same, or by the time corresponding to the end voltage of the rising edge and the start voltage of the falling edge when the end voltage of the rising edge of the corresponding control signal is the same.

3. The display device according to claim 2, characterized in that, The writing intervals of the m control signals are different within the same horizontal synchronization signal cycle.

4. The display device according to claim 2, characterized in that, The same control signal has different write intervals in adjacent horizontal synchronization signal cycles.

5. The display device according to claim 2, characterized in that, The order of the size of the writing intervals of the m control signals changes with the periodic update of the horizontal synchronization signal.

6. The display device according to claim 2, characterized in that, In two adjacent horizontal synchronization signal cycles, the writing intervals of the m control signals are written in reverse order.

7. The display device according to claim 2, characterized in that, In the same horizontal synchronization signal cycle, at least two of the m control signals have the same write interval, and the write intervals of the m control signals are not completely the same.

8. The display device according to claim 1, characterized in that, The voltage variation amplitude of the fixed edge is greater than or equal to 2 volts.

9. The display device according to claim 1, characterized in that, Within the same display frame, the timing control circuit may use either the rising edge or the falling edge as the fixed edge.

10. The display device according to claim 1, characterized in that, Within at least two consecutive horizontal synchronization signal cycles, the fixed edges of the m control signals have the same interval period.

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