Display panel driving circuit and display device

Abstract

The application discloses a display panel driving circuit and a display device, wherein the display panel driving circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor forming a double-gate structure, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor and a first capacitor, and is matched with a pulse signal, a first clock signal and a second clock signal. The application can output a waveform row by row, realize a timing circuit with simple circuit and saved space, reduce a frame size and stabilize output.

Description

Technical Field

[0001] This invention relates to the field of OLED devices, and particularly to display panel driving circuits and display devices. Background Technology

[0002] AMOLED (Active Matrix / Organic Light Emitting Diode) display circuits typically include multiple TFT (Thin Film Transistor) driving switches and an OLED (Organic Light-Emitting Diode) pixel compensation circuit (comprising 7 TFT transistors and 1 capacitor) as well as driving circuits to illuminate each display device unit. The 7T1C driver circuit input signals include: EM (Emition, OLED light emission control signal), Scan[n], Scan[n-1], Vini (initial reset signal), Vdata (data signal), and Vdd (high bit signal). The driver circuit typically includes Scan GOA (Gate Driver On Array, array substrate row drive scanning circuit) and EM GOA (Emit Gate Driver On Array, EM array substrate row drive circuit). The Scan GOA and EM GOA (EOA) circuits use input signals such as CK (clock signal), XCK (external clock signal), VGL (low potential), VGH (high potential), and STV (initial signal). After passing through the timing circuit MOS switching unit (composed of multiple TFTs and multiple capacitors), the output stage transmits the driving timing of each row to the pixel circuit of the display area. In particular, with the increasing reduction in bezel size in the AMOLED industry, and the timing circuits of AMOLED products typically placed on the left and right bezels, a simple yet highly stable timing circuit is usually required to ensure a more stable output waveform.

[0003] However, the existing timing circuits are relatively complex and occupy a large amount of space, making it impossible to further reduce the bezel size; in addition, the output waveform is not stable enough, especially the waveform of the falling edge part requires a long timing period and cannot be pulled low in time.

[0004] In view of the above-mentioned deficiencies, the present invention provides a display panel driving circuit and a display device.

[0005] The information disclosed in this background section is only intended to enhance the understanding of the background technology of this invention, and therefore may contain information that is unknown to those skilled in the art and does not constitute prior art. Summary of the Invention

[0006] In view of the problems in the prior art, the purpose of the present invention is to provide a display panel driving circuit and a display device, which overcomes the difficulties of the prior art, can output waveforms line by line, realize a simple and space-saving timing circuit to reduce the bezel size and stabilize the output.

[0007] An embodiment of the present invention provides a display panel driving circuit, comprising:

[0008] The first transistor is used to switch the current path between the pulse signal and the seventh node in response to the voltage signal of the first clock signal.

[0009] The second transistor is used to switch the current path between the seventh node and the eighth node in response to the voltage signal of the second clock signal.

[0010] The third transistor is used to switch the current path between the eighth node and the positive voltage signal in response to the voltage signal of the third node.

[0011] The fourth and fifth transistors form a dual-gate structure to switch the current path between the first clock signal and the ninth node in response to the voltage signal of the seventh node.

[0012] The sixth transistor is used to switch the current path between the negative voltage signal and the ninth node in response to the voltage signal of the first clock signal.

[0013] The seventh transistor is used to switch the current path between the second node and the first node in response to the voltage signal of the fifth node, wherein the first node is connected to the positive voltage signal;

[0014] The eighth transistor is used to switch the current path between the second and tenth nodes in response to the voltage signal of the sixth node;

[0015] The ninth transistor is used to switch the current path between the fourth and tenth nodes in response to the voltage signal of the eleventh node.

[0016] The tenth transistor is used to switch the current path between the first node and the output voltage signal in response to the voltage signal of the second node;

[0017] The eleventh transistor is used to switch the current path between the output voltage signal and the sixth node in response to the voltage signal of the fifth node, wherein the sixth node is connected to the negative voltage signal;

[0018] The twelfth transistor is used to switch the current path between the third and eleventh nodes in response to the voltage signal of the sixth node.

[0019] The thirteenth transistor is used to switch the current path between the fifth and seventh nodes in response to the voltage signal of the sixth node.

[0020] The fourteenth transistor is used to switch the current path between the fifth and sixth nodes in response to the voltage signal from the fourth node; and

[0021] The first capacitor is coupled between the first node and the second node.

[0022] Preferably, it further includes a second capacitor coupled between the eleventh node and the tenth node.

[0023] Preferably, it further includes: a third capacitor coupled between the sixth node and the collector of the fourteenth transistor.

[0024] Preferably, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, and the fourteenth transistor are all P-type thin-film transistors.

[0025] Preferably, the first clock signal and the second clock signal have the same waveform, and the first clock signal is 1 / 2 clock signal cycle ahead of the second clock signal in phase.

[0026] Preferably, the duration of the high level in one cycle of the pulse signal is twice the period of the first clock signal.

[0027] Preferably, the rising edge of the high level within one cycle of the pulse signal is aligned with the falling edge of the first clock signal.

[0028] Preferably, the capacitor further comprises: the first capacitor is 0.2pF, the second capacitor is 0.2pF, and the third capacitor is 0.5pF.

[0029] Embodiments of the present invention also provide a display device, including: a display panel driving circuit as described above.

[0030] This invention can output waveforms line by line, achieving a simple and space-saving sequential circuit with reduced bezel size and stable output. Based on common knowledge in the field, the above-mentioned preferred conditions can be arbitrarily combined to obtain various preferred embodiments of this invention.

[0031] To further understand the features and technical content of this application, please refer to the following detailed description and drawings. However, the detailed description and drawings are only for illustrating this application and are not intended to limit the scope of the claims in any way. Attached Figure Description

[0032] The above and other features and advantages of this application will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0033] Figure 1 This is a circuit diagram of the display panel driving circuit of the present invention.

[0034] Figure 2 This is a schematic diagram of the conduction state of the display panel driving circuit under the first timing of the present invention.

[0035] Figure 3 This is a timing diagram of the first timing sequence of the display panel driving circuit of the present invention.

[0036] Figure 4 This is a schematic diagram of the conduction state of the display panel driving circuit under the second timing of the present invention.

[0037] Figure 5 This is a timing diagram of the second timing of the display panel driving circuit of the present invention.

[0038] Figure 6 This is a schematic diagram of the conduction state of the display panel driving circuit under the third timing of the present invention.

[0039] Figure 7 This is a timing diagram of the third timing sequence of the display panel driving circuit of the present invention.

[0040] Figure 8 This is a schematic diagram of the conduction state of the display panel driving circuit under the fourth timing of the present invention.

[0041] Figure 9 This is a timing diagram of the fourth timing sequence of the display panel driving circuit of the present invention.

[0042] Figure 10 This is a schematic diagram of the conduction state of the display panel driving circuit of the present invention under the fifth timing sequence.

[0043] Figure 11 This is a timing diagram of the fifth timing sequence of the display panel driving circuit of the present invention.

[0044] Figure 12 This is a schematic diagram of the conduction state of the display panel driving circuit under the sixth timing of the present invention.

[0045] Figure 13 This is a timing diagram of the sixth timing sequence of the display panel driving circuit of the present invention. Detailed Implementation

[0046] The following specific examples illustrate the implementation methods of this application. Those skilled in the art can easily understand the other advantages and effects of this application from the content disclosed herein. This application can also be implemented or applied through other different specific embodiments, and various details in this application can be modified or changed according to different viewpoints and application systems without departing from the spirit of this application. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0047] The embodiments of this application will now be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily implement the application. This application may be embodied in many different forms and is not limited to the embodiments described herein.

[0048] In this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics represented in connection with that embodiment or example, which are included in at least one embodiment or example of this application. Furthermore, the specific features, structures, materials, or characteristics represented may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate different embodiments or examples represented in this application, as well as features of different embodiments or examples.

[0049] Furthermore, the terms "first" and "second" are used for illustrative purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the representation of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0050] For the purpose of clearly describing this application, devices that are not relevant to the description are omitted, and the same or similar components throughout the specification are given the same reference numerals.

[0051] Throughout this specification, when it is said that a device is "connected" to another device, this includes not only "direct connection" but also "indirect connection" by placing other components in between. Furthermore, when it is said that a device "comprises" a certain constituent element, unless otherwise stated otherwise, this does not exclude other constituent elements, but rather implies that other constituent elements may be included.

[0052] When we say that a device is "above" another device, this can mean that it is directly above the other device, or it can mean that other devices are present in between. Conversely, when we say that a device is "directly" "above" another device, there are no other devices present in between.

[0053] While the terms first, second, etc., are used in some instances herein to refer to various components, these components should not be limited by these terms. These terms are used only to distinguish one component from another. For example, first interface and second interface, etc., are used. Furthermore, as used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context indicates otherwise. It should be further understood that the terms “comprising,” “including,” indicate the presence of a feature, step, operation, component, element, item, kind, and / or group, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, components, elements, kinds, and / or groups. The terms “or” and “and / or” as used herein are interpreted as inclusive, or mean any one or any combination thereof. Thus, “A, B, or C” or “A, B, and / or C” means “any one of: A; B; C; A and B; A and C; B and C; A, B, and C.” Exceptions to this definition occur only when combinations of components, functions, steps, or operations are inherently mutually exclusive in some way.

[0054] The technical terms used herein are for reference only to specific embodiments and are not intended to limit the scope of this application. The singular form used herein includes the plural form unless the statement explicitly indicates otherwise. The word "comprising" as used in the specification means to specify a particular characteristic, region, integer, step, operation, element, and / or component, and does not exclude the presence or addition of other characteristics, regions, integers, steps, operations, elements, and / or components.

[0055] Although not explicitly defined, all terms, including technical and scientific terms used herein, shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. Terms defined in commonly used dictionaries shall be further interpreted as having a meaning consistent with the relevant technical literature and the content of this present application, and shall not be over-interpreted as having an ideal or overly formulaic meaning unless otherwise defined.

[0056] Figure 1 This is a circuit diagram of the display panel driving circuit of the present invention. Figure 1As shown, the display panel driving circuit of the present invention provides a 14T3C driving circuit, including: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a first capacitor C1, a second capacitor C2, and a third capacitor C3. The first transistor T1 is used to switch the current path between the pulse signal STE and the seventh node N7 in response to the voltage signal of the first clock signal CKE1. The second transistor T2 is used to switch the current path between the seventh node N7 and the eighth node N8 in response to the voltage signal of the second clock signal CKE2. The third transistor T3 is used to switch the current path between the eighth node N8 and the positive voltage signal VDD in response to the voltage signal of the third node N3. The fourth transistor T4 and the fifth transistor T5 form a dual-gate structure to switch the current path between the first clock signal CKE1 and the ninth node N9 in response to the voltage signal of the seventh node N7. The sixth transistor T6 switches the current path between the negative voltage signal VEE and the ninth node N9 in response to the voltage signal of the first clock signal CKE1. The seventh transistor T7 switches the current path between the second node N2 and the first node N1 in response to the voltage signal of the fifth node N5, with the first node N1 connected to the positive voltage signal VDD. The eighth transistor T8 switches the current path between the second node N2 and the tenth node N10 in response to the voltage signal of the sixth node N6. The ninth transistor T9 switches the current path between the fourth node N4 and the tenth node N10 in response to the voltage signal of the eleventh node N11. The tenth transistor T10 switches the current path between the first node N1 and the output voltage signal Eout in response to the voltage signal of the second node N2. The eleventh transistor T11, in response to the voltage signal at the fifth node N5, switches the current path between the output voltage signal Eout and the sixth node N6, which is connected to the negative voltage signal VEE. The twelfth transistor T12, in response to the voltage signal at the sixth node N6, switches the current path between the third node N3 and the eleventh node N11. The thirteenth transistor T13, in response to the voltage signal at the sixth node N6, switches the current path between the fifth node N5 and the seventh node N7. The fourteenth transistor T14, in response to the voltage signal at the fourth node N4, switches the current path between the fifth node N5 and the sixth node N6. A first capacitor C1 is coupled between the first node N1 and the second node N2.

[0057] In a preferred embodiment, it further includes a second capacitor C2, coupled between the eleventh node N11 and the tenth node N10, but is not limited thereto.

[0058] In a preferred embodiment, it further includes a third capacitor C3, coupled between the sixth node N6 and the collector of the fourteenth transistor T14, but is not limited thereto.

[0059] In a preferred embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14 are all P-type thin-film transistors, but are not limited thereto.

[0060] In a preferred embodiment, the waveforms of the first clock signal CKE1 and the second clock signal CKE2 are the same, and the first clock signal CKE1 is 1 / 2 clock signal cycle ahead of the second clock signal CKE2 in phase, but this is not a limitation.

[0061] In a preferred embodiment, the duration of the high level of one cycle within the pulse signal STE is twice the duration of the first clock signal CKE1, but is not limited thereto.

[0062] In a preferred embodiment, the rising edge of the high level within one cycle of the pulse signal STE is aligned with the falling edge of the first clock signal CKE1, but this is not a limitation.

[0063] In a preferred embodiment, the first capacitor C1 is 0.2pF, the second capacitor C2 is 0.2pF, and the third capacitor C3 is 0.5pF, but this is not a limitation.

[0064] The display panel driving circuit of the present invention can output waveforms line by line, realize a simple and space-saving timing circuit, reduce the bezel size, and stabilize the output.

[0065] The following is through the appendix Figures 2 to 13 This paper will specifically introduce the working principle of the display panel driving circuit of the present invention under various timing conditions.

[0066] Figure 2 This is a schematic diagram of the conduction state of the display panel driving circuit under the first timing of the present invention. Figure 3 This is a timing diagram of the first timing sequence of the display panel driving circuit of the present invention. Figure 2 and 3As shown, when the display panel driving circuit of the present invention is in the first timing sequence S1, the pulse signal STE is at a high potential, the first clock signal CKE1 is at a low potential, and the second clock signal CKE2 is at a high potential. The states of each transistor are as follows: the first transistor T1, the third transistor T3, the sixth transistor T6, the ninth transistor T9, the twelfth transistor T12, and the thirteenth transistor T13 are all turned on; the second transistor T2, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8, the tenth transistor T10, the eleventh transistor T11, and the fourteenth transistor T14 are all turned off; so that the final output voltage signal Eout is at a low potential.

[0067] Figure 4 This is a schematic diagram of the conduction state of the display panel driving circuit under the second timing of the present invention. Figure 5 This is a timing diagram of the second timing sequence of the display panel driving circuit of the present invention. Figure 4 and 5 As shown, when the display panel driving circuit of the present invention is in the second timing sequence S2, the pulse signal STE is at a high potential, the first clock signal CKE1 is at a high potential, and the second clock signal CKE2 is at a low potential. The states of each transistor are as follows: the second transistor T2, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14 are all turned on; the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eleventh transistor T11 are all turned off, so that the final output voltage signal Eout is at a high potential.

[0068] Figure 6 This is a schematic diagram of the conduction state of the display panel driving circuit under the third timing of the present invention. Figure 7 This is a timing diagram of the third timing sequence of the display panel driving circuit of the present invention. Figure 6 and 7 As shown, when the display panel driving circuit of the present invention is in the third timing sequence S3, the pulse signal STE is at a high potential, the first clock signal CKE1 is at a low potential, and the second clock signal CKE2 is at a high potential. The states of each transistor are as follows: the first transistor T1, the third transistor T3, the sixth transistor T6, the ninth transistor T9, the tenth transistor T10, the twelfth transistor T12, and the thirteenth transistor T13 are all turned on; the second transistor T2, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8, the eleventh transistor T11, and the fourteenth transistor T14 are all turned off; making the final output voltage signal Eout at a high potential.

[0069] Figure 8 This is a schematic diagram of the conduction state of the display panel driving circuit under the fourth timing of the present invention. Figure 9 This is a timing diagram of the fourth timing sequence of the display panel driving circuit of the present invention. Figure 8 and 9 As shown, when the display panel driving circuit of the present invention is in the fourth timing sequence S4, the pulse signal STE is at a high potential, the first clock signal CKE1 is at a high potential, and the second clock signal CKE2 is at a low potential. The states of each transistor are as follows: the second transistor T2, the third transistor T3, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14 are all turned on; the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eleventh transistor T11 are all turned off; making the final output voltage signal Eout at a high potential.

[0070] Figure 10 This is a schematic diagram of the conduction state of the display panel driving circuit of the present invention under the fifth timing sequence. Figure 11 This is a timing diagram of the fifth timing sequence of the display panel driving circuit of the present invention. Figure 10 and 11 As shown, when the display panel driving circuit of the present invention is in the fifth timing sequence S5, the pulse signal STE is at a low potential, the first clock signal CKE1 is at a low potential, and the second clock signal CKE2 is at a high potential. The states of each transistor are as follows: the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the ninth transistor T9, the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 are all turned on; the second transistor T2, the eighth transistor T8, the tenth transistor T10, and the fourteenth transistor T14 are all turned off; so that the final output voltage signal Eout is at a low potential.

[0071] Figure 12 This is a schematic diagram of the conduction state of the display panel driving circuit under the sixth timing of the present invention. Figure 13 This is a timing diagram of the sixth timing sequence of the display panel driving circuit of the present invention. Figure 12 and 13 As shown, when the display panel driving circuit of the present invention is in the sixth timing sequence S6, the pulse signal STE is at a low potential, the first clock signal CKE1 is at a high potential, and the second clock signal CKE2 is at a low potential. The states of each transistor are as follows: the second transistor T2, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14 are all turned on; the first transistor T1, the third transistor T3, the sixth transistor T6, the ninth transistor T9, and the tenth transistor T10 are all turned off; making the final output voltage signal Eout low.

[0072] This embodiment also provides a display device, such as an OLED panel, including the display driving circuit described above. The display device of the present invention incorporates the structural features, techniques, and effects of the aforementioned display driving circuit, which will not be repeated here.

[0073] In summary, the display panel driving circuit and display device of the present invention can output waveforms line by line, and realize a simple and space-saving timing circuit that reduces the bezel size and stabilizes the output.

[0074] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A display panel driving circuit, characterized in that, include: The first transistor (T1) is used to switch the current path between the pulse signal (STE) and the seventh node (N7) in response to the voltage signal of the first clock signal (CKE1). The second transistor (T2) is used to switch the current path between the seventh node (N7) and the eighth node (N8) in response to the voltage signal of the second clock signal (CKE2); The third transistor (T3) is used to switch the current path between the eighth node (N8) and the positive voltage signal (VDD) in response to the voltage signal of the third node (N3); The fourth transistor (T4) and the fifth transistor (T5) form a dual-gate structure to switch the current path between the first clock signal (CKE1) and the ninth node (N9) in response to the voltage signal of the seventh node (N7). The sixth transistor (T6) is used to switch the current path between the negative voltage signal (VEE) and the ninth node (N9) in response to the voltage signal of the first clock signal (CKE1); The seventh transistor (T7) is used to switch the current path between the second node (N2) and the first node (N1) in response to the voltage signal of the fifth node (N5), the first node (N1) being connected to the positive voltage signal (VDD); The eighth transistor (T8) is used to switch the current path between the second node (N2) and the tenth node (N10) in response to the voltage signal of the sixth node (N6); The ninth transistor (T9) is used to switch the current path between the fourth node (N4) and the tenth node (N10) in response to the voltage signal of the eleventh node (N11). The tenth transistor (T10) is used to switch the current path between the first node (N1) and the output voltage signal (Eout) in response to the voltage signal of the second node (N2); The eleventh transistor (T11) is used to switch the current path between the output voltage signal (Eout) and the sixth node (N6) in response to the voltage signal of the fifth node (N5), the sixth node (N6) being connected to the negative voltage signal (VEE); The twelfth transistor (T12) is used to switch the current path between the third node (N3) and the eleventh node (N11) in response to the voltage signal of the sixth node (N6). The thirteenth transistor (T13) is used to switch the current path between the fifth node (N5) and the seventh node (N7) in response to the voltage signal of the sixth node (N6); The fourteenth transistor (T14) is used to switch the current path between the fifth node (N5) and the sixth node (N6) in response to the voltage signal of the fourth node (N4); as well as A first capacitor (C1) is coupled between the first node (N1) and the second node (N2).

2. The display panel driving circuit as described in claim 1, characterized in that, Also includes: The second capacitor (C2) is coupled between the eleventh node (N11) and the tenth node (N10).

3. The display panel driving circuit as described in claim 2, characterized in that, Also includes: The third capacitor (C3) is coupled between the sixth node (N6) and the collector of the fourteenth transistor (T14).

4. The display panel driving circuit as described in claim 1, characterized in that, The first transistor (T1), the second transistor (T2), the third transistor (T3), the fourth transistor (T4), the fifth transistor (T5), the sixth transistor (T6), the seventh transistor (T7), the eighth transistor (T8), the ninth transistor (T9), the tenth transistor (T10), the eleventh transistor (T11), the twelfth transistor (T12), the thirteenth transistor (T13), and the fourteenth transistor (T14) are all P-type thin-film transistors.

5. The display panel driving circuit as described in claim 1, characterized in that, The first clock signal (CKE1) and the second clock signal (CKE2) have the same waveform, and the first clock signal (CKE1) is 1 / 2 clock signal cycle ahead of the second clock signal (CKE2) in phase.

6. The display panel driving circuit as described in claim 5, characterized in that, The duration of the high level in one cycle of the pulse signal (STE) is twice the cycle of the first clock signal (CKE1).

7. The display panel driving circuit as described in claim 5, characterized in that, The rising edge of the high level within one cycle of the pulse signal (STE) is aligned with the falling edge of the first clock signal (CKE1).

8. The display panel driving circuit as described in claim 3, characterized in that, Also includes: The first capacitor (C1) has a capacitance of 0.2pF, the second capacitor (C2) has a capacitance of 0.2pF, and the third capacitor (C3) has a capacitance of 0.5pF.

9. A display device, characterized in that, include: The display panel driving circuit as described in claim 1.

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