Pixel circuit, display panel and driving method

Abstract

This application discloses a pixel circuit, a display panel, and a driving method. The pixel circuit includes: a driving module, a first switch module, a second switch module, a first storage module, a second storage module, and a voltage transmission module. A first terminal of the first switch module is electrically connected to a first terminal of the driving module. The first storage module is connected between the control terminal of the driving module and a second terminal of the first switch module. The first terminal of the second storage module is electrically connected to the second terminal of the first switch module. The second switch module is connected between the second terminal of the first switch module and a first terminal of a light-emitting element. The voltage transmission module is electrically connected to the control terminal of the driving module. During the data writing phase, the first switch module is turned off, the second switch module is turned off, and the voltage transmission module is turned on, receiving the data voltage. This application embodiment can improve the display effect.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a pixel circuit, a display panel, and a driving method. Background Technology

[0002] Organic light-emitting diode (OLED) and flat panel display devices based on light-emitting diode (LED) technologies are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body and wide range of applications, becoming the mainstream of display devices.

[0003] However, the performance of current OLED display panels needs improvement. Summary of the Invention

[0004] In order to overcome the technical problems mentioned in the background, this application provides a pixel circuit, a display panel, and a driving method, which aim to improve the performance of the display panel.

[0005] This application provides a pixel circuit, including: a driving module, a first switching module, a second switching module, a first storage module, a second storage module, and a voltage transmission module;

[0006] The first terminal of the first switch module is electrically connected to the first terminal of the drive module; the first storage module is connected between the control terminal of the drive module and the second terminal of the first switch module; the first terminal of the second storage module is electrically connected to the second terminal of the first switch module; the second switch module is connected between the second terminal of the first switch module and the first terminal of the light-emitting element; the voltage transmission module is electrically connected to the control terminal of the drive module. During the data writing phase, the first switch module is turned off, the second switch module is turned off, the voltage transmission module is turned on, and the voltage transmission module is connected to the data voltage.

[0007] This application embodiment also provides a pixel circuit, including: a driving module, a first switching module, a second switching module, a first storage module, a second storage module, and a voltage transmission module; The first terminal of the first switch module is electrically connected to the first power line, the second terminal of the first switch module is electrically connected to the second terminal of the drive module, the first storage module is connected between the control terminal and the first terminal of the drive module, the first terminal of the second storage module is electrically connected to the first terminal of the drive module, the second switch module is connected between the first terminal of the drive module and the first terminal of the light-emitting element; the voltage transmission module is electrically connected to the control terminal of the drive module. During the data writing phase, the first switch module is turned off, the second switch module is turned off, the voltage transmission module is turned on, and the voltage transmission module is connected to the data voltage.

[0008] This application also provides a display panel, including the pixel circuit provided in any embodiment of this application.

[0009] This application embodiment also provides a driving method, applied to the pixel circuit or the display panel provided in this application embodiment, the driving method including: During the data writing phase, the first switch module is turned off, the second switch module is turned off, the voltage transmission module is turned on, and the voltage transmission module is connected to the data voltage.

[0010] In this embodiment, the first terminal of the first switch module is electrically connected to the first terminal of the drive module. The first storage module is connected between the control terminal of the drive module and the second terminal of the first switch module. The first terminal of the second storage module is electrically connected to the second terminal of the first switch module. The second switch module is connected between the second terminal of the first switch module and the first terminal of the light-emitting element. The voltage transmission module is electrically connected to the control terminal of the drive module. During the data writing phase, the first switch module is turned off, the second switch module is turned off, and the voltage transmission module is turned on. The voltage transmission module receives the data voltage, which reduces or eliminates the correlation between the voltage at the second terminal of the first storage module and the parasitic capacitance at the first terminal of the light-emitting element, or makes it unaffected by the parasitic capacitance at the first terminal of the light-emitting element. This is beneficial for improving display uniformity, avoiding or mitigating voltage leakage from the first power line to the first node after the data writing phase and / or threshold compensation phase, reducing the risk of brightness differences between the first and last row pixels, and improving the display effect. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of this application.

[0013] Figure 2 This is a schematic diagram of another pixel circuit provided in an embodiment of this application.

[0014] Figure 3 This is a timing waveform diagram of a display frame provided in an embodiment of this application.

[0015] Figure 4This is a top view of a display panel provided in an embodiment of this application.

[0016] Figure 5 This is a top view of another display panel provided in an embodiment of this application.

[0017] Figure 6 This is a schematic diagram of another pixel circuit provided in an embodiment of this application.

[0018] Figure 7a This is a timing waveform diagram of another display frame provided in an embodiment of this application.

[0019] Figure 7b This is a timing waveform diagram of another display frame provided in an embodiment of this application.

[0020] Figure 8 This is a top view of another display panel provided in an embodiment of this application.

[0021] Figure 9 This is a schematic diagram of another pixel circuit provided in an embodiment of this application.

[0022] Figure 10 This is a schematic diagram of another pixel circuit provided in an embodiment of this application.

[0023] Figure 11 This is a top view of another display panel provided in an embodiment of this application.

[0024] Figure 12 This is a timing waveform diagram of another display frame provided in an embodiment of this application.

[0025] Figure 13 This is a schematic diagram of another pixel circuit provided in an embodiment of this application.

[0026] Figure 14 This is a timing waveform diagram of another display frame provided in an embodiment of this application.

[0027] Figure 15 This is a schematic diagram of another pixel circuit provided in an embodiment of this application.

[0028] Figure 16 This is a schematic diagram of another pixel circuit provided in an embodiment of this application.

[0029] Figure 17 This is a schematic diagram of another pixel circuit provided in an embodiment of this application.

[0030] Figure 18 This is a schematic diagram of another pixel circuit provided in an embodiment of this application.

[0031] Figure 19 This is a timing waveform diagram of another display frame provided in an embodiment of this application.

[0032] Figure 20 This is a schematic diagram of another pixel circuit provided in an embodiment of this application.

[0033] Figure 21 This is a timing waveform diagram of another display frame provided in an embodiment of this application.

[0034] Figure 22 This is a schematic diagram of another pixel circuit provided in an embodiment of this application.

[0035] Figure 23 This is a schematic diagram of another pixel circuit provided in an embodiment of this application.

[0036] Figure 24 This is a cross-sectional structural diagram of another display panel provided in an embodiment of this application.

[0037] Figure 25 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0039] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0040] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. It should be noted that, unless otherwise specified, different features in the embodiments of this application can be combined with each other.

[0041] For ease of understanding, the accompanying diagram shows the mutually orthogonal X-axis, Y-axis, and Z-axis. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is the normal direction relative to the plane containing the X and Y directions. Furthermore, a view where various elements are observed parallel to the plane containing the X and Y directions is called a top view. Alternatively, the planes in the X and Y directions can be planes parallel to the display surface of the display panel, and the Z-direction can be a direction parallel to the thickness direction of the display panel.

[0042] For certain elements, terms such as "above" or "over" are sometimes used when describing the position of an element located in the Z direction, and "below" or "under" are used when describing the position of an element located in the opposite direction. Furthermore, when using terms such as "above," "over," "below," "under," and "relative" to define the positional relationship between two elements, this includes not only the state where the two elements are directly connected, but also the state where the two elements are separated by a gap or other elements. Additionally, the terms "first," "second," and "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance or order. At least one may include one or more. At least one may include one or more. At least part may include part or all. The first direction and the second direction intersect, for example, they may be perpendicular. At least one may include one or more. Connections may include direct connections or indirect connections. Equal or identical means equal or identical within a reasonable range of errors such as manufacturing errors, process errors, and measurement errors. The transistor may be a P-type transistor or an N-type transistor. A P-type transistor is turned on when its gate is connected to a low level and turned off when its gate is connected to a high level. An N-type transistor conducts when its gate is connected to a high level and turns off when its gate is connected to a low level. One of the first and second terminals of the same transistor can be the source, and the other can be the drain. P-type transistors can include polysilicon transistors. N-type transistors can include metal-oxide transistors, such as IGZO (indium gallium zinc oxide) transistors. For example, all transistors in a pixel circuit may have the same channel type. For example, the active layer of each (or all) transistor in a pixel circuit may be made of the same material, thus simplifying the manufacturing process.

[0043] This application provides a pixel circuit. Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of this application. See also... Figure 1 The pixel circuit 200 includes: a driving module 10, a first switching module 40, a second switching module 50, a first storage module 20, a second storage module 30, and a voltage transmission module 60.

[0044] The first terminal of the first switch module 40 is electrically connected to the first terminal S of the drive module 10. The first storage module 20 is connected between the control terminal G of the drive module 10 and the second terminal of the first switch module 40. The first terminal of the second storage module 30 is electrically connected to the second terminal of the first switch module 40 (e.g., electrically connected to the first node N1). The second switch module 50 is connected between the second terminal of the first switch module 40 and the first terminal of the light-emitting element 100. The voltage transmission module 60 is electrically connected to the control terminal G of the drive module 10.

[0045] For example, the first end of the first storage module 20 is electrically connected to the control terminal G of the drive module 10, and the second end of the first storage module 20 is electrically connected to the second end of the first switch module 40. For example, the first end of the second switch module 50 is electrically connected to the second end of the first switch module 40, and the second end of the second switch module 50 is electrically connected to the first end of the light-emitting element 100. For example, the second end of the second storage module 30 can be connected to a DC voltage or a power supply voltage.

[0046] For example, the electrical connection between the voltage transmission module 60 and the control terminal G of the drive module 10 may include a direct electrical connection between the voltage transmission module 60 and the control terminal G of the drive module 10, or an indirect electrical connection between the voltage transmission module 60 and the control terminal G of the drive module 10. For example, the voltage transmission module 60 is electrically connected to the second terminal of the second storage module 30, and the voltage transmission module 60 is electrically connected to the control terminal G of the drive module 10 via the second storage module 30 and the first storage module 20.

[0047] During the data writing phase (e.g., t31), the first switch module 40 is turned off, the second switch module 50 is turned off, the voltage transmission module 60 is turned on, and the voltage transmission module 60 is connected to the data voltage Vdata.

[0048] For example, during the data writing stage (e.g., t31), the voltage transmission module 60 transmits the data voltage Vdata to the control terminal G of the drive module 10 and the first terminal of the first storage module 20. In this way, the first storage module 20 can store the voltage related to the data voltage Vdata. The voltage of the first node N1 (or the second terminal of the first storage module 20 or the first terminal of the second storage module 30) is related to the capacitance of the first storage module 20 and the second storage module 30 and the parasitic capacitance of the first node N1.

[0049] In the display panel, besides the capacitors in the first storage module 20 and the second storage module 30, there are other parasitic capacitances, such as the parasitic capacitance of the first node N1 and the parasitic capacitance of the first end (e.g., the anode) of the light-emitting element 100. For example, the parasitic capacitance of the first node N1 in the pixel circuit at each location is related to at least one factor, such as the size of the plates of the capacitor in the first storage module 20 and its positional relationship with surrounding devices. The plates of the capacitors in the first storage module 20 in the pixel circuit at each location are of consistent size with small differences, making them relatively uniform. Their positional relationship with surrounding devices is also consistent. Therefore, the parasitic capacitance of the first node N1 in the pixel circuit at each location is consistent in size with small differences, making it relatively uniform.

[0050] For example, the parasitic capacitance of the first end (e.g., anode) of the light-emitting element 100 connected to the pixel circuit at each location is related to at least one factor such as anode size, shape, and pixel arrangement. The first end (e.g., anode) of the light-emitting element 100 connected to at least some pixel circuits has different sizes, shapes, and positional relationships with surrounding devices. Therefore, the parasitic capacitance of the first end (e.g., anode) of the light-emitting element 100 connected to at least some pixel circuits varies greatly. This results in a large voltage difference at the second end of the first storage module 20 when the second end of the first storage module 20 and the first end of the second storage module 30 are electrically connected to the first end of the light-emitting element 100.

[0051] Compared to the scheme of electrically connecting the second end of the first storage module 20 and the first end of the second storage module 30 to the first end of the light-emitting element 100, for example, the scheme of removing the second switch module 50, this embodiment sets up the second switch module 50, and in the data writing stage (e.g., t31), the second switch module 50 is turned off, so that the correlation between the voltage of the second end of the first storage module 20 and the parasitic capacitance of the first end of the light-emitting element 100 is reduced, or becomes unrelated, or is not affected by the parasitic capacitance of the first end of the light-emitting element 100. The voltage of the second end of the first storage module 20 in the pixel circuit of each position is consistent with the parasitic capacitance of the first node N1, which is beneficial to improving the display uniformity of the pixel circuit at each position and improving the display effect.

[0052] For example, the drive module 10, the first switch module 40, the second switch module 50 and the light-emitting element 100 are connected in series between the first power line and the second power line.

[0053] For example, the second terminal D of the driving module 10 can be electrically connected to the first power line. During the data writing phase (e.g., t31), and / or after the threshold compensation phase and before the light emission phase, the first switching module 40 is turned off. This helps to avoid or improve the phenomenon of voltage leakage from the first power line to the first node N1 after the data writing phase and / or the threshold compensation phase, and reduces the risk of brightness differences between the first and last row pixels.

[0054] For example, during the light-emitting phase, the driving module 10 can generate a driving current to drive the light-emitting element 100 to emit light. The light-emitting element 100 may include a light-emitting diode, such as an organic light-emitting diode. A first power line can be used to transmit a first power supply voltage VDD. A second power line can be used to transmit a second power supply voltage VSS. For example, during the light-emitting phase, one of the first power supply voltage and the second power supply voltage is a high voltage, and the other is a low voltage. For example, during the light-emitting phase, the first power supply voltage VDD is a high voltage, such as the second voltage VDDH, which is a positive voltage, and the second power supply voltage VSS is a low voltage, such as the fourth voltage VSSL, which is a negative voltage.

[0055] For example, the light-emitting element 100 may include a light-emitting diode, such as an organic light-emitting diode. For example, one of the first and second ends of the light-emitting element 100 may be an anode, and the other may be a cathode. For example, the first end of the light-emitting element 100 may be an anode, and the second end of the light-emitting element 100 may be a cathode. The second end of the light-emitting element 100 may be connected to a second power supply voltage and / or electrically connected to a second power supply line VSS.

[0056] In this embodiment, the first terminal of the first switch module 40 is electrically connected to the first terminal S of the drive module 10; the first storage module 20 is connected between the control terminal G of the drive module 10 and the second terminal of the first switch module 40; the first terminal of the second storage module 30 is electrically connected to the second terminal of the first switch module 40; the second switch module 50 is connected between the second terminal of the first switch module 40 and the first terminal of the light-emitting element 100; and the voltage transmission module 60 is electrically connected to the control terminal G of the drive module 10. During the data writing stage (e.g., t31), the first switch module 40 is turned off, the second switch module 50 is turned off, and the voltage transmission module 60 is turned on. The voltage transmission module 60 receives the data voltage Vdata, which reduces or eliminates the correlation between the voltage at the second terminal of the first storage module 20 and the parasitic capacitance at the first terminal of the light-emitting element 100, or makes it unaffected by the parasitic capacitance at the first terminal of the light-emitting element 100. This is beneficial for improving display uniformity, avoiding or mitigating the leakage of voltage from the first power line to the first node N1 after the data writing stage and / or threshold compensation stage, reducing the risk of brightness differences between the first and last rows of pixels, and improving the display effect.

[0057] Figure 2 This is a schematic diagram of another pixel circuit structure provided in an embodiment of this application. For example, see... Figure 2 The driving module 10 may include a driving transistor T1. The driving module 10 or the driving transistor T1 may include an N-type transistor (see [reference needed]). Figure 2The driving transistor T1 can be a P-type transistor or a P-type transistor. The gate of the driving transistor T1 can be the control terminal G of the driving module 10, the first terminal (e.g., the source) of the driving transistor T1 can be the first terminal S of the driving module 10, and the second terminal (e.g., the drain) of the driving transistor T1 can be the second terminal D of the driving module 10. During the light-emitting phase, the driving module 10 can generate a driving current based on the voltage between the control terminal G and the first terminal S of the driving module 10. The driving transistor T1 can include a metal-oxide-semiconductor transistor or a polysilicon transistor. The driving transistor T1 can also include an N-type polysilicon transistor.

[0058] For example, see Figure 2 The first storage module 20 may include a first capacitor C1. For example, the first terminal of the first capacitor C1 may be the first end of the first storage module 20, and the second terminal of the first capacitor C1 may be the second end of the first storage module 20.

[0059] For example, see Figure 2 The second storage module 30 may include a second capacitor C2. For example, the first terminal of the second capacitor C2 may be the first terminal of the second storage module 30, and the second terminal of the second capacitor C2 may be the second terminal of the second storage module 30.

[0060] For example, the capacitance of the second capacitor C2 is greater than or equal to the capacitance of the first capacitor C1.

[0061] For example, see Figure 2 The voltage transmission module 60 may include a first transistor T2. The voltage transmission module 60 or the first transistor T2 may include an N-type transistor (see [reference needed]). Figure 2 The first transistor T2 can be a P-type transistor or a P-type transistor. The gate of the first transistor T2 can be the control terminal of the voltage transmission module 60, the first terminal of the first transistor T2 can be the first terminal of the voltage transmission module 60, and the second terminal of the first transistor T2 can be the second terminal of the voltage transmission module 60. The voltage transmission module 60 or the first transistor T2 can include a metal-oxide-semiconductor transistor or a polysilicon transistor.

[0062] For example, see Figure 2 The first switching module 40 may include a second transistor T3_1. The first switching module 40 or the second transistor T3_1 may include an N-type transistor (see [reference needed]). Figure 2 The first transistor T3_1 can be a P-type transistor or a P-type transistor. The gate of the second transistor T3_1 can be the control terminal of the first switching module 40, the first terminal of the second transistor T3_1 can be the first terminal of the first switching module 40, and the second terminal of the second transistor T3_1 can be the second terminal of the first switching module 40. The first switching module 40 or the second transistor T3_1 can include a metal-oxide-semiconductor transistor or a polysilicon transistor.

[0063] For example, see Figure 2The second switching module 50 may include a third transistor T3_2. The second switching module 50 or the third transistor T3_2 may include an N-type transistor (see [reference needed]). Figure 2 The third transistor T3_2 can be a P-type transistor or a P-type transistor. The gate of the third transistor T3_2 can be the control terminal of the second switching module 50, the first terminal of the third transistor T3_2 can be the first terminal of the second switching module 50, and the second terminal of the third transistor T3_2 can be the second terminal of the second switching module 50. The second switching module 50 or the third transistor T3_2 can include a metal-oxide-semiconductor transistor or a polysilicon transistor.

[0064] For example, the channel regions of the active portions of at least two transistors in the pixel circuit are stacked along the thickness direction of the display panel, which can improve pixel resolution. For example, the channel regions of the active portions of at least one of the first transistor T2, the second transistor T3_1, and the third transistor T3_2 are stacked with the channel region of the active portion of the driving transistor T1 along the thickness direction of the display panel.

[0065] For example, see Figure 2 The control terminals of the first switch module 40 and the second switch module 50 are connected to the same gate signal and / or electrically connected to the same gate line. This configuration reduces the number of signal lines, which is beneficial for improving pixel resolution (PPI). Alternatively, the control terminals of the first switch module 40 and the second switch module 50 can share the same gate drive circuit to reduce the number of gate drive circuits, which is beneficial for lowering the bezel of the display panel and achieving a narrow bezel.

[0066] For example, the transistors in the first switching module 40 (e.g., the second transistor T3_1) and the transistors in the second switching module 50 (e.g., the third transistor T3_2) have the same channel type, such as N-type (see [reference]). Figure 2 ( ) or P-type. For example, the first switch module 40 and the second switch module 50 have the same switching state, such as being simultaneously on and simultaneously off.

[0067] For example, in the threshold compensation stage t2, the first switch module 40 is turned on, the voltage transmission module 60 is turned on, and the voltage transmission module 60 is connected to a first reference voltage, such as the first initialization voltage Vini. In the threshold compensation stage t2, the voltage transmission module 60 can transmit the first reference voltage or the first initialization voltage Vini to the control terminal G of the drive module 10. The first power supply voltage VDD (which can be the second voltage VDDH) on the first power line charges the first terminal S of the drive module 10, the second terminal of the first storage module 20, the first terminal of the second storage module 30, and the first node N1 via the turned-on drive module 10 and the first switch module 40, until the voltage of the first terminal S of the drive module 10, the second terminal of the first storage module 20, the first terminal of the second storage module 30, and the first node N1 is Vini-Vth, where Vth can be the threshold voltage of the drive module 10, thus achieving threshold voltage compensation. In the threshold compensation stage t2, the voltage related to the first initialization voltage Vini and the threshold voltage Vth of the drive module 10 can be transmitted to the first terminal S of the drive module 10. Therefore, the voltage difference between the control terminal G and the first terminal S of the drive module 10 is Vth, and the voltage difference between the first terminal and the second terminal of the first storage module 20 is Vth, that is, Vth is stored in the first storage module 20.

[0068] Threshold compensation ensures that during the light-emitting stage, the magnitude of the driving current generated by the driving module 10 is independent of or less correlated with the threshold voltage Vth of the driving module 10. Instead, the magnitude of the driving current generated by the driving module 10 is correlated with the data voltage Vdata. This improves display uniformity and avoids or mitigates display unevenness caused by differences in the threshold voltage Vth of the driving modules 10 in different pixel circuits. For example, Vth can be the threshold voltage of the driving transistor T1.

[0069] The duration of the threshold compensation stage t2 is adjustable, meaning the compensation time is adjustable and can be set as needed. For example, the duration of the threshold compensation stage t2 can be greater than or equal to M times the row scan time of a single-row pixel circuit, where M is greater than or equal to 2. The row scan time can be the interval between the start times of the data writing stages t3 corresponding to adjacent row pixel circuits, thereby improving the compensation effect. The threshold compensation stages t2 corresponding to multiple row pixel circuits can overlap, thus achieving multi-row compensation, which is beneficial for achieving high-frequency driving.

[0070] For example, during the threshold compensation stage t2, the second switch module 50 is turned on, and the first power supply voltage VDD (which may be the second voltage VDDH) on the first power supply line charges the first terminal of the light-emitting element 100 through the turned-on drive module 10, the first switch module 40, and the second switch module 50 until the voltage at the first terminal of the light-emitting element 100 is Vini-Vth.

[0071] Figure 3This is a timing waveform diagram of a display frame provided in an embodiment of this application. Figure 3 Applicable to Figure 1 and Figure 2 The pixel circuitry. For example, see [link to example]. Figure 3 In the same display frame, the threshold compensation phase t2 precedes the data writing phase (e.g., t31).

[0072] For example, during the data writing phase t3, the voltage transmission module 60 is turned on, transmitting the data voltage Vdata on the data line Data to the voltage at the control terminal G of the drive module 10. That is, the voltage at the control terminal G of the drive module 10 changes from Vini to Vdata. Therefore, the voltage of the first node N1 is VN1 = Vini - Vth + (Vdata - Vini). (C1 / (C1+C2)), the voltage VS of the first terminal S of the driving module 10 is Vdata-Vth, and the voltage Vanode of the first terminal of the light-emitting element 100 is Vini-Vth. For example, the voltages of the second terminal of the first storage module 20, the first terminal of the second storage module 30, and the first node N1 are the same.

[0073] For example, in the first initialization phase t1, the voltage transmission module 60 is turned on and connected to a second reference voltage, which may be the first initialization voltage Vini. With this configuration, in the first initialization phase t1, the voltage transmission module 60 can transmit either the second reference voltage or the first initialization voltage Vini to the control terminal G of the drive module 10 to initialize the control terminal G of the drive module 10. For example, the first reference voltage and the second reference voltage may be the same or different.

[0074] For example, in the same display frame, the threshold compensation phase t2 and / or the data writing phase t3 follow the first initialization phase t1.

[0075] For example, the voltage transmission module 60 is electrically connected to the data line Data, which is used for time-division multiplexing of the data voltage Vdata and the first initialization voltage Vini. For example, during the threshold compensation phase t2 and / or the first initialization phase t1, the data line Data can be used to transmit the first initialization voltage Vini. For example, during the data writing phase t3, the data line Data can be used to transmit the data voltage Vdata. For example, the first terminal of the voltage transmission module 60 is electrically connected to the data line Data, and the second terminal of the voltage transmission module 60 is electrically connected to the control terminal G of the drive module 10.

[0076] For example, the second terminal D of the drive module 10 is electrically connected to the first power line.

[0077] For example, in the same display frame, the voltage on the first power line is a variable voltage.

[0078] For example, in the same display frame, the voltage on the first power line (e.g., the second voltage VDDH) in at least one of the threshold compensation phase t2, data writing phase t3, and light emission phase t4 is different from the voltage on the first power line in the first initialization phase t1 (e.g., the first voltage VDDL).

[0079] For example, in the same display frame, the voltage on the first power line (e.g., the second voltage VDDH) is higher than the voltage on the first power line (e.g., the first voltage VDDL) in at least one of the threshold compensation phase t2, data writing phase t3, and light emission phase t4. For example, in the same display frame, the voltage on the first power line (e.g., the second voltage VDDH) is higher than the voltage on the first power line (e.g., the first voltage VDDL) in the first initialization phase t1. With this configuration, at least one of the first terminal S of the driving module 10, the second terminal of the first storage module 20, the first terminal of the second storage module 30, the first node N1, and the first terminal of the light-emitting element 100 can be initialized in the first initialization phase t1 by the voltage on the first power line.

[0080] For example, in the same display frame, the voltage on the first power line is the same during the threshold compensation phase t2, the data writing phase t3, and the light emission phase t4.

[0081] For example, in the first initialization phase t1, the first switch module 40 is turned on, and the voltage on the first power line (e.g., the first voltage VDDL) is transmitted to the first terminal S of the drive module 10 via the turned-on drive module 10 to initialize the first terminal S of the drive module 10. The voltage on the first power line (e.g., the first voltage VDDL) is transmitted to the second terminal of the first storage module 20, the first terminal of the second storage module 30, and the first node N1 via the turned-on drive module 10 and the first switch module 40 to initialize the second terminal of the first storage module 20, the first terminal of the second storage module 30, and the first node N1.

[0082] For example, in the first initialization phase t1, the first switch module 40 and the second switch module 50 are turned on, and the voltage on the first power line (e.g., the first voltage VDDL) is transmitted to the first end of the light-emitting element 100 through the turned-on drive module 10 to initialize the first end of the light-emitting element 100.

[0083] For example, during the data writing phase t3, the first switch module 40 and the second switch module 50 are turned off.

[0084] For example, the second terminal of the second storage module 30 is connected to a DC voltage or a power supply voltage.

[0085] For example, the second terminal of the light-emitting element 100 is electrically connected to the second power line. For example, in the same display frame, the voltage on the second power line (e.g., a third voltage VSSH) in at least one of the first initialization phase t1, the threshold compensation phase t2, and the data writing phase t3 is different from the voltage on the second power line in the light-emitting phase t4 (e.g., a fourth voltage VSSL). For example, in the same display frame, the voltage on the second power line in the data writing phase t3 (e.g., a third voltage VSSH) is different from the voltage on the second power line in the light-emitting phase t4 (e.g., a fourth voltage VSSL). This configuration prevents the light-emitting element 100 from emitting light during the threshold compensation phase.

[0086] For example, in the same display frame, the absolute value of the difference between the voltage on the first power line and the voltage on the second power line (e.g., a third voltage VSSH) in at least one of the threshold compensation phase t2 and the data writing phase t3 is less than the absolute value of the difference between the voltage on the first power line and the voltage on the second power line (e.g., a fourth voltage VSSL) in the light emission phase t4. This setting prevents the light-emitting element 100 from emitting light during the threshold compensation phase.

[0087] For example, in the same display frame, the voltage on the second power line (e.g., a third voltage VSSH) in at least one of the first initialization phase t1, threshold compensation phase t2, and data writing phase t3 is higher than the voltage on the second power line in the light emission phase t4 (e.g., a fourth voltage VSSL). Similarly, in the same display frame, the voltage on the second power line in the data writing phase t3 (e.g., a third voltage VSSH) is higher than the voltage on the second power line in the light emission phase t4 (e.g., a fourth voltage VSSL). This configuration prevents the light-emitting element 100 from emitting light in the first initialization phase t1, threshold compensation phase t2, and data writing phase t3.

[0088] For example, in the same display frame, the voltage on the second power line is the same during the first initialization phase t1, the threshold compensation phase t2, and the data writing phase t3.

[0089] For example, in the same display frame, during at least one of the threshold compensation phase t2 and the data writing phase t3, the voltage on the first power line (which may be the second voltage VDDH) is greater than or equal to the voltage on the second power line (which may be VSSH).

[0090] For example, in the same display frame, the voltage on the first power line (which may be the first voltage VDDL) in the first initialization phase t1 is less than or equal to the voltage on the second power line (which may be the fourth voltage VSSL) in the light-emitting phase t4.

[0091] For example, the second voltage VDDH is greater than or equal to the third voltage VSSH. For example, the first voltage VDDL is less than or equal to the fourth voltage VSSL.

[0092] This application provides a display panel. Figure 4 This is a top view schematic diagram of a display panel provided in an embodiment of this application. The display panel 300 includes the pixel circuit 200 provided in any of the above embodiments, and has the beneficial effects of the pixel circuit in any of the embodiments of this application, which will not be described again here. The display panel 300 may include a display area 301 and a non-display area 302. The pixel circuit 200 may be located in the display area 301. The display panel may include a light-emitting element 100. The light-emitting element 100 may be located in the display area 301.

[0093] For example, combining Figure 2 and Figure 4 As shown, the display panel 300 also includes a selection circuit 303, which includes a third switch module 70 and a fourth switch module 80. The first terminal of the third switch module 70 is connected to the data voltage Vdata, and the first terminal of the fourth switch module 80 is connected to the first initialization voltage Vini. The second terminals of the third switch module 70 and the fourth switch module 80 are electrically connected and are electrically connected to the first terminal of the voltage transmission module 60 via the data line Data. The second terminal of the voltage transmission module 60 is electrically connected to the control terminal G of the drive module 10.

[0094] The third switch module 70 and the fourth switch module 80 are turned on in a time-division manner. The data line Data can be used to transmit the data voltage Vdata and the first initialization voltage Vini in a time-division manner. The third switch module 70 and the fourth switch module 80 are not turned on simultaneously.

[0095] For example, during the data writing phase t3, the third switch module 70 is turned on, and the fourth switch module 80 is turned off. For example, during the data writing phase t3, the data line Data can be used to transmit the data voltage Vdata. With this configuration, the data voltage Vdata can be transmitted to the data line Data via the turned-on third switch module 70, and then transmitted to the control terminal G of the drive module 10 and the first terminal of the first storage module 20 via the turned-on voltage transmission module 60.

[0096] For example, during the threshold compensation phase t2 and / or the first initialization phase t1, the third switch module 70 is turned off, and the fourth switch module 80 is turned on. For example, during the threshold compensation phase t2 and / or the first initialization phase t1, the data line Data can be used to transmit the first initialization voltage Vini. With this configuration, the first initialization voltage Vini can be transmitted via the turned-on fourth switch module 80 to the data line Data, and then via the turned-on voltage transmission module 60 to the control terminal G of the drive module 10 and the first terminal of the first storage module 20.

[0097] For example, at least two pixel circuits 200 share the same selection circuit 303. This configuration simplifies the structure of the pixel circuits 200, reduces the number of transistors in the pixel circuits 200 of the display area 301, and helps to improve the pixel resolution (PPI) and achieve a high pixel resolution (PPI).

[0098] For example, the selection circuit 303 is located in the non-display area 302.

[0099] For example, the display panel includes a plurality of pixel circuits 200 arranged in an array. For example, the same column of pixel circuits 200 may share the same selection circuit 303. For example, each column of pixel circuits 200 includes a plurality of pixel circuits 200 arranged along a second direction Y.

[0100] For example, multiple data lines (Data) correspond to different selection circuits 303. For example, the control terminals of the third switch modules 70 in multiple selection circuits 303 are connected to the same gate signal (e.g., the second control signal MUX2) and / or electrically connected to the same control signal line (e.g., the second control signal line L6). For example, the control terminals of the fourth switch modules 80 in multiple selection circuits 303 are connected to the same gate signal (e.g., the first control signal MUX1) and / or electrically connected to the same control signal line (e.g., the first control signal line L5).

[0101] For example, the multiple rows of pixel circuits 200 are arranged along the second direction Y. For example, each row of pixel circuits 200 includes a plurality of pixel circuits 200 arranged along the first direction X.

[0102] Optionally, the display panel 300 includes gate lines (e.g., L1, L2), and the pixel circuit 200 is electrically connected to the gate lines (e.g., gate lines L1, L2, etc.), which extend along a first direction X. For example, multiple gate lines are arranged along a second direction Y. The first direction X and the second direction Y intersect, for example, perpendicularly. For example, multiple data lines (Data) may extend along the second direction Y and be arranged along the first direction X.

[0103] For example, in the same display frame, the first initialization phase t1 of the multi-row pixel circuit 200 starts and ends simultaneously.

[0104] For example, in the same display frame, the threshold compensation phase t2 of the multi-row pixel circuit 200 starts and ends simultaneously.

[0105] For example, in the same display frame, the data writing phase t3 of the multi-line pixel circuit 200 does not overlap. That is, in the same display frame, data is written to the pixel circuit 200 line by line.

[0106] For example, in the same display frame, the light-emitting phase t4 of the multi-row pixel circuit 200 starts and ends simultaneously.

[0107] For example, in the first initialization phase t1, the control terminal G of the driving module 10 in the multi-row pixel circuit 200 (which may be all pixel circuits 200, or include the first row pixel circuit 200 and the last row pixel circuit 200) is initialized simultaneously.

[0108] For example, during the threshold compensation stage t2, the first switch module 40 in the multi-row pixel circuit (which can be all pixel circuits 200, or include the first row pixel circuit 200 and the last row pixel circuit 200) is simultaneously turned on. This configuration allows multiple rows of pixel circuits to perform threshold voltage compensation simultaneously.

[0109] For example, the control terminal of the first switch module 40 in the multi-row pixel circuit 200 (which may be all pixel circuits 200, or include the first row pixel circuit 200 and the last row pixel circuit 200) is electrically connected. For example, the first switch modules 40 in the multi-row pixel circuit 200 (which may be all pixel circuits 200, or include the first row pixel circuit 200 and the last row pixel circuit 200) have the same switching state, for example, simultaneously on and simultaneously off. This configuration reduces the number of gate drive circuits, which is beneficial for reducing the width of the display panel and achieving a narrow bezel.

[0110] For example, the control terminal of the second switch module 50 in the multi-row pixel circuit 200 (which may be all pixel circuits 200, or include the first row pixel circuit 200 and the last row pixel circuit 200) is electrically connected. For example, the switching states of the second switch modules 50 in the multi-row pixel circuit 200 (which may be all pixel circuits 200, or include the first row pixel circuit 200 and the last row pixel circuit 200) are the same; for example, they are simultaneously on and simultaneously off. This configuration reduces the number of gate drive circuits, which is beneficial for reducing the width of the display panel and achieving a narrow bezel.

[0111] For example, in the same display frame, the time interval between the data writing phase and the light emission phase t4 corresponding to at least two rows of pixel circuits 200 is different. For example, in the same display frame, the time interval between the data writing phase and the light emission phase t4 corresponding to the first row of pixel circuits 200 is greater than the time interval between the data writing phase and the light emission phase t4 corresponding to the second row of pixel circuits 200.

[0112] For example, in the same display frame, the time interval between the data writing phase and the light emission phase t4 corresponding to the first row pixel circuit 200 is greater than the time interval between the data writing phase and the light emission phase t4 corresponding to the last row pixel circuit 200. If the first switch module 40 is not turned off after the data writing phase, the voltage on the first power line will leak to the first node N1, resulting in different leakage times between the first and last row pixel circuits, leading to differences in brightness between the first and last row pixels. Therefore, by turning off the first switch module 40 after the data writing phase, brightness uniformity can be improved.

[0113] Figure 5 This is a top view schematic diagram of another display panel provided in an embodiment of this application. For example, see... Figure 5 The display panel also includes a gate drive circuit 400, which includes multiple cascaded shift registers 401. The control terminal of the voltage transmission module 60 in the multi-row pixel circuit is electrically connected to the gate drive circuit 400.

[0114] For example, the control terminal of the voltage transmission module 60 is electrically connected to the first gate line L1. The first gate line L1 can transmit the second gate signal S2. For example, during the data writing stage t3, the control terminal of the voltage transmission module 60 in the multi-row pixel circuit provides the corresponding first gate signal S2 through different shift registers 401.

[0115] For example, see Figure 5 The control terminal of the first switch module 40 is electrically connected to the second gate line L2, for example, and receives the same gate signal. The second gate line L2 can transmit the second gate signal EM. For example, multiple second gate lines L2 that are electrically connected to the multi-row pixel circuit 200 (or overlap with the multi-row pixel circuit 200 along the thickness direction of the display panel) are electrically connected, for example, and receive the same gate signal. For example, the thickness direction of the display panel is perpendicular to the first direction X. For example, the thickness direction of the display panel is perpendicular to the second direction Y.

[0116] For example, see Figure 2 The third switching module 70 may include a fifth transistor T5. The third switching module 70 or the fifth transistor T5 may include an N-type transistor (see [reference needed]). Figure 2 The fifth transistor T5 can be a P-type transistor or a P-type transistor. The gate of the fifth transistor T5 can be the control terminal of the third switching module 70, the first terminal of the fifth transistor T5 can be the first terminal of the third switching module 70, and the second terminal of the fifth transistor T5 can be the second terminal of the third switching module 70. The third switching module 70 or the fifth transistor T5 can include a metal-oxide-semiconductor transistor or a polysilicon transistor.

[0117] For example, see Figure 2The fourth switching module 80 may include a sixth transistor T6. The fourth switching module 80 or the sixth transistor T6 may include an N-type transistor (see [reference needed]). Figure 2 The sixth transistor T6 can be a P-type transistor or a P-type transistor. The gate of the sixth transistor T6 can be the control terminal of the fourth switching module 80, the first terminal of the sixth transistor T6 can be the first terminal of the fourth switching module 80, and the second terminal of the sixth transistor T6 can be the second terminal of the fourth switching module 80. The fourth switching module 80 or the sixth transistor T6 can include a metal-oxide-semiconductor transistor or a polysilicon transistor.

[0118] See Figure 2 The control terminal of the voltage transmission module 60 (which may be the gate of the first transistor T2) can be connected to the first gate signal S2; the control terminal of the first switch module 40 (which may be the gate of the second transistor T3_1) can be connected to the second gate signal EM; the control terminal of the second switch module 50 (which may be the gate of the third transistor T3_2) can be connected to the second gate signal EM; the control terminal of the third switch module 70 (which may be the gate of the fifth transistor T5) can be connected to the first control signal MUX1; and the control terminal of the fourth switch module 80 (which may be the gate of the sixth transistor T6) can be connected to the second control signal MUX2.

[0119] See Figure 2 and Figure 4 The first terminal of the fifth transistor T5 is connected to the data voltage Vdata and / or electrically connected to the driver chip. The second terminal of the fifth transistor T5 is electrically connected to the first terminal of the first transistor T2 via the data line Data. The first terminal of the sixth transistor T6 is connected to the first initialization voltage Vini. The second terminal of the sixth transistor T6 is electrically connected to the first terminal of the first transistor T2 via the data line Data. The second terminal of the first transistor T2 is electrically connected to the gate of the driver transistor T1. The first terminal of the second transistor T3_1 is electrically connected to the first terminal of the driver transistor T1. The first capacitor C1 is connected between the gate of the driver transistor T1 and the second terminal of the second transistor T3_1. The first terminal of the second capacitor C1 is electrically connected to the second terminal of the second transistor T3_1. The second terminal of the second capacitor C1 is connected to the DC voltage VEH. The third transistor T3_2 is connected between the second terminal of the second transistor T3_1 and the first terminal of the light-emitting element 100. The second terminal of the driver transistor T1 is electrically connected to the first power line. The second terminal of the light-emitting element 100 is electrically connected to the second power line.

[0120] See Figure 2 In the pixel circuit, each transistor (or all transistors) is an N-type transistor.

[0121] See Figures 2 to 4 The working process of the pixel circuit is described below. The display frame may include a first initialization stage t1, a threshold compensation stage t2, a data writing stage t31, and a first light emission stage t5.

[0122] In the first initialization phase t1, the first gate signal S2 is at an on level, for example, a high level; the second gate signal EM is at an on level, for example, a high level; the first control signal MUX1 is at an on level, for example, a high level; the second control signal MUX2 is at an off level, for example, a low level; the voltage on the first power line is the first voltage VDDL; and the voltage on the second power line is the third voltage VSSH. The fourth switch module 80 (which may be the sixth transistor T6) is turned on, which can transmit the first initialization voltage Vini to the data line Data, and the voltage on the data line Data is the first initialization voltage Vini. The fourth switch module 80 (which may be the sixth transistor T6) and the voltage transmission module 60 (which may be the first transistor T2) are turned on, which can transmit the first initialization voltage Vini to the control terminal of the drive module 10 (which may be the gate of the drive transistor T1) and the first terminal of the first storage module 20 (which may be the first electrode of the first capacitor C1) to initialize the control terminal of the drive module 10 (which may be the gate of the drive transistor T1) and the first terminal of the first storage module 20 (which may be the first electrode of the first capacitor C1). The first switching module 40 (which can be the second transistor T3_1) and the second switching module 50 (which can be the third transistor T3_2) are turned on, allowing the voltage on the first power line (which can be the first voltage VDDL) to be transmitted through the turned-on driving module 10 (which can be the driving transistor T1) to the first terminal S (which can be the first electrode of the driving transistor T1) of the driving module 10. The voltage on the first power line (which can be the first voltage VDDL) can also be transmitted through the turned-on driving module 10 (which can be the driving transistor T1) and the first switching module 40 (which can be the second transistor T3_1) to the second terminal (which can be the second electrode of the first capacitor C1) of the first storage module 20. The first terminal of module 30 (which may be the first electrode of the second capacitor C2) and the first node N1 initialize the second terminal of the first storage module 20 (which may be the second electrode of the first capacitor C1), the first terminal of the second storage module 30 (which may be the first electrode of the second capacitor C2), and the first node N1. The voltage on the first power line (which may be the first voltage VDDL) can be transmitted to the first terminal of the light-emitting element 100 through the conducting drive module 10 (which may be the drive transistor T1), the first switch module 40 (which may be the second transistor T3_1), and the second switch module 50 (which may be the third transistor T3_2) to initialize the first terminal of the light-emitting element 100. The third switch module 70 (which may be the fifth transistor T5) is turned off.

[0123] During the threshold compensation stage t2, the first gate signal S2 is at an on level, for example, a high level; the second gate signal EM is at an on level, for example, a high level; the first control signal MUX1 is at an on level, for example, a high level; the second control signal MUX2 is at an off level, for example, a low level; the voltage on the first power line is the second voltage VDDH; and the voltage on the second power line is the third voltage VSSH. The fourth switch module 80 (which may be the sixth transistor T6) is turned on, which can transmit the first initialization voltage Vini to the data line Data, and the voltage on the data line Data is the first initialization voltage Vini. The fourth switch module 80 (which may be the sixth transistor T6) and the voltage transmission module 60 (which may be the first transistor T2) are turned on, which can transmit the first initialization voltage Vini to the control terminal of the drive module 10 (which may be the gate of the drive transistor T1) and the first terminal of the first storage module 20 (which may be the first electrode of the first capacitor C1). The first switching module 40 (which can be the second transistor T3_1) and the second switching module 50 (which can be the third transistor T3_2) are turned on. The voltage on the first power line (which can be the second voltage VDDH) charges the first terminal S (which can be the first electrode of the driving transistor T1) of the driven module 10 (which can be the driving transistor T1) through the turned-on driving module 10 (which can be the driving transistor T1). The second voltage VDDH charges the second terminal (which can be the second electrode of the first capacitor C1) of the first storage module 20, the first terminal (which can be the first electrode of the second capacitor C2) of the second storage module 30, and the first node N1 through the turned-on driving module 10 (which can be the driving transistor T1) and the first switching module 40 (which can be the second transistor T3_1). The voltage on the first power line... (This could be a second voltage VDDH) The first terminal of the light-emitting element 100 is charged through the conducting drive module 10 (which could be a drive transistor T1), the first switch module 40 (which could be a second transistor T3_1), and the second switch module 50 (which could be a third transistor T3_2) until the voltage at the first terminal S of the drive module 10 (which could be the first electrode of the drive transistor T1), the second terminal of the first storage module 20 (which could be the second electrode of the first capacitor C1), the first terminal of the second storage module 30 (which could be the first electrode of the second capacitor C2), the first node N1, and the first terminal of the light-emitting element 100 is Vini-Vth. This is equivalent to storing Vth in the first storage module 20 (which could be the first capacitor C1) to achieve threshold voltage compensation. This is equivalent to transmitting the voltage related to the threshold voltage Vth of the drive module 10 (which could be a drive transistor T1) to the first terminal S of the drive module 10 (which could be the first electrode of the drive transistor T1), the second terminal of the first storage module 20 (which could be the second electrode of the first capacitor C1), and the first terminal of the second storage module 30 (which could be the first electrode of the second capacitor C2). The third switch module 70 (which may be the fifth transistor T5) is turned off.

[0124] During the data writing phase t31, the first gate signal S2 is at an on level, for example, a high level; the second gate signal EM is at an off level, for example, a low level; the first control signal MUX1 is at an off level, for example, a low level; the second control signal MUX2 is at an on level, for example, a high level; the voltage on the first power line is the second voltage VDDH; and the voltage on the second power line is the third voltage VSSH. The third switch module 70 (which can be the fifth transistor T5) is turned on, which can transmit the data voltage Vdata to the data line Data, and the voltage on the data line Data is the data voltage Vdata. The third switch module 70 (which can be the fifth transistor T5) and the voltage transmission module 60 (which can be the first transistor T2) are turned on, transmitting the data voltage Vdata to the control terminal of the drive module 10 (which can be the gate of the drive transistor T1) and the first terminal of the first storage module 20 (which can be the first electrode of the first capacitor C1). Through the coupling effect of the first storage module 20 (which can be the first capacitor C1), the voltage of the second terminal of the first storage module 20 (which can be the second electrode of the first capacitor C1), the first terminal of the second storage module 30 (which can be the first electrode of the second capacitor C2), and the first node N1 is Vini - Vth + (Vdata - Vini). (C1 / (C1+C2)). The voltage VS = Vdata - Vth at the first terminal S of the driving module 10 (which can be the first terminal of the driving transistor T1), and the voltage Vanode = Vini - Vth at the first terminal of the light-emitting element 100. The fourth switch module 80 (which can be the sixth transistor T6), the first switch module 40 (which can be the second transistor T3_1), and the second switch module 50 (which can be the third transistor T3_2) are turned off.

[0125] During the light-emitting stage t4, the first gate signal S2 is at a turn-off level, for example, low; the second gate signal EM is at a turn-on level, for example, high; the first control signal MUX1 is at a turn-off level, for example, low; the second control signal MUX2 is at a turn-off level, for example, low; the voltage on the first power line is the second voltage VDDH; and the voltage on the second power line is the fourth voltage VSSL. The first switching module 40 (which may be the second transistor T3_1) and the second switching module 50 (which may be the third transistor T3_2) are turned on, and the driving module 10 (for example, the driving transistor T1) generates a driving current, driving the light-emitting element 100 to emit light. The driving current generated by the driving module 10... k = C2 / (C1+C2), where μ is the carrier mobility of driving transistor T1, Cox is the channel capacitance per unit area of ​​driving transistor T1, and W / L is the channel width-to-length ratio of driving transistor T1. For example, if driving transistor T1 is an N-type transistor, μ is the electron mobility of driving transistor T1. For example, if driving transistor T1 is a P-type transistor, μ is the hole mobility of driving transistor T1. The third switching module 70 (which can be the fifth transistor T5), the voltage transmission module 60 (which can be the first transistor T2), and the fourth switching module 80 (which can be the sixth transistor T6) are turned off.

[0126] For example, see Figure 3 Within the same display frame, the total data writing stage t3 corresponding to the multi-row pixel circuit 200 may include the data writing stage corresponding to each row of pixel circuits. For example, the data writing stage corresponding to the nth row of pixel circuits is before the data writing stage corresponding to the (n+1)th row of pixel circuits, where n is an integer greater than or equal to 1. For example, the data writing stage corresponding to the first row of pixel circuits may be t31, the data writing stage corresponding to the second row of pixel circuits may be t32, the gate signal connected to the control terminal of the voltage transmission module 60 in the first row of pixel circuits may be S2 (1), and the gate signal connected to the control terminal of the voltage transmission module 60 in the second row of pixel circuits may be S2 (2). The multi-row pixel circuit 200 may include the nth row of pixel circuits and the (n+1)th row of pixel circuits.

[0127] For example, see Figure 3 Within the same display frame, the first initialization phase t1 corresponding to the nth and (n+1)th row pixel circuits starts and ends simultaneously; the threshold compensation phase t2 corresponding to the nth and (n+1)th row pixel circuits starts and ends simultaneously; and the light emission phase t4 corresponding to the nth and (n+1)th row pixel circuits starts and ends simultaneously. That is, the pixel circuits across the entire screen initialize each node simultaneously in the first initialization phase t1, perform threshold voltage compensation simultaneously in the threshold compensation phase t2, then write data row by row in the data writing phase t3, and finally, the entire screen emits the same light.

[0128] For example, see Figure 3 Within the same display frame, the first turn-on pulse of the gate signal connected to the control terminal of the voltage transmission module 60 in the nth row pixel circuit overlaps with the first turn-on pulse of the gate signal connected to the control terminal of the voltage transmission module 60 in the (n+1)th row pixel circuit. For example, they coincide, meaning they have the same start time and the same end time, such as the start time of the first initialization stage t1 and the end time of the threshold compensation stage t2.

[0129] For example, see Figure 3Within the same display frame, the second turn-on pulse of the gate signal connected to the control terminal of the voltage transmission module 60 in the nth row pixel circuit does not overlap with the second turn-on pulse of the gate signal connected to the control terminal of the voltage transmission module 60 in the (n+1)th row pixel circuit, for example, corresponding to stages t31 and t32 respectively.

[0130] Figure 6 This is a schematic diagram of another pixel circuit structure provided in an embodiment of this application. For example, see... Figure 6 The pixel circuit 200 also includes a first initialization module 90, which (e.g., the second end of the first initialization module 90) is electrically connected to the first end of the light-emitting element 100, and the first initialization module 90 (e.g., the first end of the first initialization module 90) is connected to a second initialization voltage Vref.

[0131] For example, during the first initialization phase t1, the voltage on the first power line (which may be the first voltage VDDL) is less than or equal to the second initialization voltage Vref.

[0132] For example, the second initialization voltage Vref is less than or equal to the voltage on the second power line during the light-emitting phase t4 (which may be the fourth voltage VSSL).

[0133] For example, the first initialization voltage Vini is greater than the second initialization voltage Vref.

[0134] For example, in the first initialization phase t1, the first initialization module 90 is turned on or off.

[0135] For example, in the first initialization phase t1, the first initialization module 90 is turned on, which can transmit the second initialization voltage Vref to the first terminal of the light-emitting element 100 to initialize the first terminal of the light-emitting element 100.

[0136] Figure 7a This is a timing waveform diagram of another display frame provided in an embodiment of this application. Figure 7a Applicable to Figure 6 Pixel circuit.

[0137] For example, see Figure 6 and Figure 7a In the second initialization stage t5, the first initialization module 90 is turned on, which can transmit the second initialization voltage Vref to the first terminal of the light-emitting element 100 to initialize the first terminal of the light-emitting element 100.

[0138] For example, in the same display frame, the second initialization phase t5 follows the data writing phase t3. For example, in the same display frame, the second initialization phase t5 precedes the light emission phase t4.

[0139] By setting the first initialization module 90, a second initialization stage t5 is added after the data writing stage t3 and before the light emission stage to initialize the first end of the light-emitting element 100. The duration of the second initialization stage t5 and / or the magnitude of the second initialization voltage Vref can be adjusted as needed to achieve better uniformity of low grayscale brightness and brightness effect of the first frame.

[0140] For example, the second initialization voltage Vref can be a DC voltage or a power supply voltage.

[0141] For example, in the second initialization phase t5, the first switch module 40 is turned off. For example, in the second initialization phase t5, the second switch module 50 is turned off. For example, in the second initialization phase t5, the voltage transmission module 60 is turned off.

[0142] For example, in the first initialization phase t1, the second switch module 50 and the first initialization module 90 are turned on, and the second initialization voltage Vref can be transmitted through the turned-on first initialization module 90 and second switch module 50 to the second end of the first storage module 20, the first end of the second storage module 30, and the first node N1 to initialize the second end of the first storage module 20, the first end of the second storage module 30, and the first node N1.

[0143] For example, in the first initialization phase t1, the first switch module 40, the second switch module 50, and the first initialization module 90 are turned on, and the second initialization voltage Vref can be transmitted to the first terminal S of the drive module 10 through the turned-on first initialization module 90, second switch module 50, and first switch module 40 to initialize the first terminal S of the drive module 10.

[0144] For example, within the same display frame, the voltage on the first power line is a variable voltage. For instance, the second initialization voltage Vref can be equal to the voltage on the first power line during the first initialization phase t1. This configuration avoids micro-short circuits between the second initialization voltage Vref input terminal and the first power line, thereby reducing power consumption. For example, during the first initialization phase t1, the first switch module 40, the second switch module 50, and the first initialization module 90 are turned on.

[0145] For example, see Figure 6 The first terminal of the first initialization module 90 is insulated from the first terminal of the voltage transmission module 60, meaning they are not electrically connected. For example, during the first initialization phase t1, the first initialization module 90 is turned on.

[0146] In some embodiments, during the first initialization phase t1, the first initialization module 90 is turned off. For example, the gate signal connected to the control terminal of the first initialization module 90 is not given a turn-on pulse during the first initialization phase t1, which is equivalent to... Figure 7aThe first turn-on pulse of the third gate signal S1 (corresponding to the first initialization phase t1) is removed.

[0147] For example, the control terminal of the first initialization module 90 and the control terminal of the first switching module 40 are connected to different gate signals and / or electrically connected to different gate lines.

[0148] For example, the transistors in the first initialization module 90 and the transistors in the first switching module 40 have the same channel type, for example, both are N-type (see...). Figure 6 () or P type.

[0149] Figure 7b This is a timing waveform diagram of another display frame provided in an embodiment of this application. Figure 7b Applicable to Figure 6 Pixel circuit.

[0150] For example, within the same display frame, the voltage on the first power line is a fixed voltage (e.g., the second voltage VDDH), i.e., a constant voltage or DC voltage. This reduces the design complexity of the power supply corresponding to the first power line and helps reduce interference between the first power line and other signal lines, thereby improving the display effect. For example, within the same display frame, the voltage on the first power line is the same during the first initialization phase t1, the threshold compensation phase t2, the data writing phase t3, and the light emission phase t4. For example, during the first initialization phase t1, the first switch module 40, the second switch module 50, and the first initialization module 90 are turned on. Figure 7b , Figure 6 Corresponding technical solutions and Figure 7a , Figure 6 The working principles of the corresponding technical solutions are similar, and will not be elaborated here. The difference lies in... Figure 7b , Figure 6 In the corresponding technical solution, the voltage on the first power line during the first initialization phase t1 is the second voltage VDDH. Compared to Figure 7b , Figure 6 The corresponding technical solution, Figure 7a , Figure 6 The corresponding technical solution can improve or avoid the problem of micro-short circuit between the second initialization voltage Vref access terminal and the first power supply line in the first initialization stage t1, thereby reducing power consumption.

[0151] Figure 8 This is a top view schematic diagram of another display panel provided in an embodiment of this application. For example, see... Figure 6 and Figure 8 The first terminal of the first initialization module 90 is electrically connected to the over-initialization signal line L4, which can transmit the second initialization voltage Vref. At least a portion of the initialization signal line L4 is located in the display area 301.

[0152] For example, see Figure 6 and Figure 8 The control terminal of the first initialization module 90 is electrically connected to the third gate line L3, and the third gate line L3 can transmit the third gate signal S1.

[0153] For example, see Figure 6 and Figure 8 The control terminals of the first initialization module 90 in the multi-row pixel circuit 200 (which may be all pixel circuits 200, or include the first row pixel circuit 200 and the last row pixel circuit 200) are electrically connected and connected to the same gate signal. For example, the switching states of the first initialization module 90 in the multi-row pixel circuit 200 (which may be all pixel circuits 200, or include the first row pixel circuit 200 and the last row pixel circuit 200) are the same, for example, simultaneously turned on and simultaneously turned off. This configuration reduces the number of gate driving circuits, which is beneficial for reducing the width of the display panel and achieving a narrow bezel. For example, multiple third gate lines L3 that are electrically connected to the multi-row pixel circuit 200 (or overlap with the multi-row pixel circuit 200 along the thickness direction of the display panel) are electrically connected and connected to the same gate signal.

[0154] For example, in the same display frame, the second initialization phase t5 of the multi-row pixel circuit 200 starts and ends simultaneously.

[0155] For example, see Figure 6 The first initialization module 90 may include a fourth transistor T4. The first initialization module 90 or the fourth transistor T4 may include an N-type transistor (see [reference needed]). Figure 6 The fourth transistor T4 can be a P-type transistor or a P-type transistor. The gate of the fourth transistor T4 can be the control terminal of the first initialization module 90, the first terminal of the fourth transistor T4 can be the first terminal of the first initialization module 90, and the second terminal of the fourth transistor T4 can be the second terminal of the first initialization module 90. The first initialization module 90 or the fourth transistor T4 can include a metal-oxide-semiconductor transistor or a polysilicon transistor.

[0156] Figures 6 to 8 , Figure 4 , Figure 5 Corresponding technical solutions and Figures 2 to 5 The working principle and process of the corresponding technical solutions are similar, and will not be repeated here. The difference lies in... Figures 6 to 8 , Figure 4 , Figure 5 In the corresponding technical solution, during the first initialization phase t1, the third gate signal S1 is at a conducting level, for example, a high level, and the first initialization module 90 (which may be the fourth transistor T4) is turned on. During the threshold compensation phase t2 and / or the data writing phase t3, the third gate signal S1 is at a turning-off level, for example, a low level, and the first initialization module 90 (which may be the fourth transistor T4) is turned off.

[0157] During the second initialization phase t5, the first gate signal S2 is at a turn-off level, for example, a low level; the second gate signal EM is at a turn-off level, for example, a low level; the first control signal MUX1 is at a turn-off level, for example, a low level; the second control signal MUX2 is at a turn-off level, for example, a low level; the third gate signal S1 is at a turn-on level, for example, a high level; the voltage on the first power line is the second voltage VDDH; the voltage on the second power line is the third voltage VSSH; the first initialization module 90 (which can be the fourth transistor T4) is turned on, transmitting the second initialization voltage Vref to the first terminal of the light-emitting element 100 to initialize the first terminal of the light-emitting element 100. The third switch module 70 (which can be the fifth transistor T5), the voltage transmission module 60 (which can be the first transistor T2), the fourth switch module 80 (which can be the sixth transistor T6), the first switch module 40 (which can be the second transistor T3_1), and the second switch module 50 (which can be the third transistor T3_2) are turned off.

[0158] Figure 9 A schematic diagram of another pixel circuit structure provided in an embodiment of this application. For example, see... Figure 9 The control terminal of the first initialization module 90 and the control terminal of the second switching module 50 are connected to the same gate signal and / or electrically connected to the same gate line.

[0159] For example, the control terminal of the first switch module 40 and the control terminal of the second switch module 50 are connected to different gate signals and / or electrically connected to different gate lines.

[0160] For example, the transistors in the first initialization module 90 and the transistors in the second switching module 50 have the same channel type, such as N-type (see [reference]). Figure 9 ( ) or P-type. For example, the first initialization module 90 and the second switch module 50 have the same switching state, such as being simultaneously on and simultaneously off.

[0161] For example, Figure 7a , Figure 7b Applicable to Figure 9 Pixel circuit.

[0162] For example, during the threshold compensation stage t2, the first switch module 40 is turned on, the second switch module 50 is turned off, the voltage transmission module 60 is turned on, and the voltage transmission module 60 is connected to the first initialization voltage Vini.

[0163] For example, in the first initialization phase t1, the voltage transmission module 60 is turned on and connected to the first initialization voltage Vini.

[0164] For example, in the same display frame, the threshold compensation phase t2 is after the first initialization phase t1.

[0165] For example, in the same display frame, the threshold compensation phase t2 precedes the data writing phase t3.

[0166] For example, in the second initialization phase t5, the first initialization module 90 is turned on, and in the same display frame, the second initialization phase t5 is after the data writing phase t3.

[0167] Figure 7a and Figure 9 Corresponding technical solutions and Figure 6 , Figure 7a The working principle and process of the corresponding technical solutions are similar, and will not be elaborated here. Figure 7b and Figure 9 Corresponding technical solutions and Figure 6 , Figure 7b The working principle and process of the corresponding technical solutions are similar, and will not be repeated here. The difference lies in... Figure 7a and Figure 9 Corresponding technical solutions Figure 7b and Figure 9 In the corresponding technical solution, during the threshold compensation stage t2, the second switch module 50 (which may be the third transistor T3_2) is turned off; during the second initialization stage t5, the first initialization module 90 (which may be the fourth transistor T4) and the second switch module 50 (which may be the third transistor T3_2) are turned on, which can transmit the second initialization voltage Vref to the second terminal of the first storage module 20, the first terminal of the second storage module 30, and the first node N1.

[0168] Figure 10 A schematic diagram of another pixel circuit structure provided in an embodiment of this application. For example, see... Figure 10 The second end of the voltage transmission module 60 is electrically connected to the control terminal G of the drive module 10; the first end of the first initialization module 90 is electrically connected to the first end of the voltage transmission module 60, and the second end of the first initialization module 90 is electrically connected to the first end of the light-emitting element 100.

[0169] Figure 11 This is a top view of another display panel provided in an embodiment of this application. For example, in conjunction with... Figure 10 and Figure 11 As shown, the first terminal of the first initialization module 90 and the first terminal of the voltage transmission module 60 are electrically connected to the data line Data. The data line Data can be used for time-division multiplexing of the data voltage Vdata, the second initialization voltage Vref, and the first initialization voltage Vini. This configuration eliminates the need for an initialization signal line for transmitting the second initialization voltage Vref, which is beneficial for improving pixel resolution (PPI). For example, in the second initialization phase t5, the data line Data can be used to transmit the second initialization voltage Vref.

[0170] For example, combining Figure 10 and Figure 11 As shown, the selection circuit 303 also includes a fifth switch module 91. The first terminal of the fifth switch module 91 is connected to the second initialization voltage Vref, and the second terminal of the fifth switch module 91 is electrically connected to the first terminal of the first initialization module 90 via the data line Data.

[0171] The third switch module 70, the fourth switch module 80, and the fifth switch module 91 are time-divisionally activated. At least two of the third switch module 70, the fourth switch module 80, and the fifth switch module 91 are not activated simultaneously. The third switch module 70, the fourth switch module 80, and the fifth switch module 91 are not activated simultaneously.

[0172] For example, in the second initialization stage t5, the fifth switch module 91 and the first initialization module 90 are turned on, and the second initialization voltage Vref can be transmitted to the data line Data through the turned-on fifth switch module 91, and then transmitted to the first end of the light-emitting element 100 through the turned-on first initialization module 90 to initialize the first end of the light-emitting element 100.

[0173] For example, in the first initialization phase t1, the first initialization module 90 is turned off. This is configured so that the first initialization voltage Vini transmitted by the data line Data in the first initialization phase t1 is not transmitted to the first terminal of the light-emitting element 100, etc.

[0174] For example, in the first initialization phase t1, the fifth switch module 91 is turned off. For example, in the threshold compensation phase t2, the fifth switch module 91 is turned off. For example, in the data writing phase t3, the fifth switch module 91 is turned off.

[0175] For example, the second terminal of the fifth switch module 91, the second terminal of the third switch module 70, and the second terminal of the fourth switch module 80 are electrically connected. For example, the first terminal of the voltage transmission module 60 and the first terminal of the first initialization module 90 are electrically connected.

[0176] For example, the second end of the fifth switch module 91, the second end of the third switch module 70, and the second end of the fourth switch module 80 are electrically connected, and are electrically connected to the first end of the voltage transmission module 60 and the first end of the first initialization module 90 via the data line Data.

[0177] For example, see Figure 10 The fifth switching module 91 may include a seventh transistor T7. The fifth switching module 91 or the seventh transistor T7 may include an N-type transistor (see [reference needed]). Figure 10The seventh transistor T7 can be a P-type transistor or a P-type transistor. The gate of the seventh transistor T7 can be the control terminal of the fifth switching module 91, the first terminal of the seventh transistor T7 can be the first terminal of the fifth switching module 91, and the second terminal of the seventh transistor T7 can be the second terminal of the fifth switching module 91. The fifth switching module 91 or the seventh transistor T7 can include a metal-oxide-semiconductor transistor or a polysilicon transistor.

[0178] For example, the control terminal of the fifth switch module 91 in multiple selection circuits 303 is connected to the same gate signal (e.g., the third control signal MUX3) and / or electrically connected to the same control signal line (e.g., the third control signal line).

[0179] For example, the control terminal of the fifth switch module 91 is electrically connected to the control terminal of the first initialization module 90, and / or receives the same gate signal. This configuration reduces the number of signal sources required.

[0180] For example, the fifth switch module 91 and the first initialization module 90 have the same switch state, such as being simultaneously turned on and simultaneously turned off.

[0181] For example, the transistors in the fifth switching module 91 and the transistors in the first initialization module 90 have the same channel type, such as N-type (see [reference]). Figure 10 () or P type.

[0182] Figure 12 This is a timing waveform diagram of another display frame provided in an embodiment of this application. Figure 12 Applicable to Figure 10 Pixel circuitry. For example, see... Figure 12 In the first initialization phase t1, the first initialization module 90 is shut down. Figure 10 The control terminal of the second switch module 50 in the pixel circuit is connected to the same gate signal (e.g., the second gate signal EM) and / or electrically connected to the same gate line as the control terminal of the first switch module 40. Figure 10 , Figure 12 Corresponding technical solutions and Figure 6 , Figure 7a The working principle and process of the corresponding technical solutions are similar, and will not be repeated here. The difference lies in... Figure 10 and Figure 12 In the corresponding technical solution, during the second initialization stage t5, the fifth switch module 91 and the first initialization module 90 are turned on, and the second initialization voltage Vref can be transmitted to the data line Data through the turned-on fifth switch module 91, and then transmitted to the first end of the light-emitting element 100 through the turned-on first initialization module 90, so as to initialize the first end of the light-emitting element 100.

[0183] Figure 13 This is a schematic diagram of another pixel circuit provided in an embodiment of this application. Figure 14 This is a timing waveform diagram of another display frame provided in an embodiment of this application. Figure 14 Applicable to Figure 13 Pixel circuit. Figure 13 The control terminal of the second switching module 50 in the pixel circuit is connected to the same gate signal (e.g., the third gate signal S1) and / or electrically connected to the same gate line as the control terminal of the first initialization module 90. Figure 13 , Figure 14 Corresponding technical solutions and Figure 10 , Figure 12 The working principle and process of the corresponding technical solutions are similar. Figure 13 , Figure 14 Corresponding technical solutions and Figure 7a , Figure 9 The working principle and process of the corresponding technical solutions are similar, and will not be repeated here. The difference lies in... Figure 13 and Figure 14 In the corresponding technical solution, the display frame also includes a third initialization phase t6. In the same display frame, the third initialization phase t6 is before the first initialization phase t1. In the third initialization phase t6, the first gate signal S2 is at a turn-off level, for example, a low level; the second gate signal EM is at a turn-on level, for example, a high level; the first control signal MUX1 is at a turn-off level, for example, a low level; the second control signal MUX2 is at a turn-off level, for example, a low level; the third control signal MUX3 is at a turn-on level, for example, a high level; the voltage on the first power line is the first voltage VDDL; the voltage on the second power line is the third voltage VSSH; the voltage on the data line Data is the second initialization voltage Vref; the fifth switch module 91 (which can be the seventh transistor T7) and the first initialization module 90 (which can be the fourth transistor T7) are also included. 4) When the second switch module 50 (which may be the third transistor T3_2) and the first switch module 40 (which may be the second transistor T3_1) are turned on, the second initialization voltage Vref can be transmitted to the first terminal of the light-emitting element 100, the second terminal of the first storage module 20 (which may be the second terminal of the first capacitor C1), the first terminal of the second storage module 30 (which may be the first terminal of the second capacitor C2), the first node N1, and the first terminal S of the driving module 10 (which may be the first terminal of the driving transistor T1) to initialize the first terminal of the light-emitting element 100, the second terminal of the first storage module 20 (which may be the second terminal of the first capacitor C1), the first terminal of the second storage module 30 (which may be the first terminal of the second capacitor C2), the first node N1, and the first terminal S of the driving module 10 (which may be the first terminal of the driving transistor T1). The voltage transmission module 60 (which may be the first transistor T2), the third switch module 70 (which may be the fifth transistor T5), and the fourth switch module 80 (which may be the sixth transistor T6) are turned off.

[0184] Figure 12 Applicable to Figure 13 Pixel circuit. Figure 12 and Figure 13 Corresponding technical solutions and Figure 10 and Figure 12 The corresponding technical solutions work on similar principles, and will not be elaborated upon here. Compared to Figure 12 and Figure 13 The corresponding technical solution, Figure 10 and Figure 12 The corresponding technical solution increases the number of initialization steps for the first end of the light-emitting element 100. For example, Figure 10 and Figure 12 The corresponding technical solution initializes the first end of the light-emitting element 100 in both the first initialization stage t1 and the second initialization stage t5. Figure 12 and Figure 13 The corresponding technical solution initializes the first end of the light-emitting element 100 in the second initialization stage t5, but does not initialize the first end of the light-emitting element 100 in the first initialization stage t1.

[0185] Figure 14 Applicable to Figure 10 Pixel circuit. Figure 10 and Figure 14 Corresponding technical solutions and Figure 13 and Figure 14 The working principles of the corresponding technical solutions are similar, and will not be elaborated here.

[0186] Based on the same inventive concept, this application provides another pixel circuit. Figure 15 A schematic diagram of another pixel circuit structure provided in an embodiment of this application. For example, see... Figure 15 The pixel circuit 200 includes: a driving module 10, a first switching module 40, a second switching module 50, a first storage module 20, a second storage module 30, and a voltage transmission module 60.

[0187] The first end of the first switch module 40 is electrically connected to the first power line, the second end of the first switch module 40 is electrically connected to the second end D of the drive module 10, the first storage module 20 is connected between the control end G and the first end S of the drive module 10, the first end of the second storage module 30 is electrically connected to the first end of the drive module 10, the second switch module 50 is connected between the first end S of the drive module 10 and the first end of the light-emitting element 100, and the voltage transmission module 60 is electrically connected to the control end G of the drive module 10.

[0188] During the data writing phase t2, the first switch module 40 is turned off, the second switch module 50 is turned off, the voltage transmission module 60 is turned on, and the voltage transmission module 60 is connected to the data voltage Vdata.

[0189] Figure 15The corresponding pixel circuit and Figure 1 The corresponding pixel circuits have similar structures and principles, and have the same or similar beneficial effects, which will not be elaborated here. The difference lies in the connection position of the first switch module 40.

[0190] In this embodiment, the first end of the first switch module 40 is electrically connected to the first power line, the second end of the first switch module 40 is electrically connected to the second end D of the drive module 10, the first storage module 20 is connected between the control end G and the first end S of the drive module 10, the first end of the second storage module 30 is electrically connected to the first end of the drive module 10, the second switch module 50 is connected between the first end S of the drive module 10 and the first end of the light-emitting element 100, and the voltage transmission module 60 is electrically connected to the control end G of the drive module 10. During the data writing phase (e.g., t31), the first switch module 40 is turned off, the second switch module 50 is turned off, and the voltage transmission module 60 is turned on. The voltage transmission module 60 is connected to the data voltage Vdata, which reduces or eliminates the correlation between the voltage at the second terminal of the first storage module 20 and the parasitic capacitance at the first terminal of the light-emitting element 100, or makes it unaffected by the parasitic capacitance at the first terminal of the light-emitting element 100. This is beneficial for improving display uniformity, avoiding or mitigating the leakage of voltage from the first power line to the first node N1 after the data writing phase and / or threshold compensation phase, reducing the risk of brightness differences between the first and last row pixels, and improving the display effect.

[0191] This embodiment can be combined with some or all of the features in the above embodiments, which will not be repeated here.

[0192] Figure 16 This is a schematic diagram of another pixel circuit provided in an embodiment of this application. Figure 3 , Figure 4 , Figure 5 Can be with Figure 16 and Figure 15 Combine. Figure 3 , Figure 4 , Figure 5 , Figure 16 Corresponding technical solutions and Figures 2 to 5 The working principles of the corresponding technical solutions are similar, and will not be elaborated here. The difference lies in... Figure 3 , Figure 4 , Figure 5 , Figure 16In the corresponding technical solution, during the first initialization stage t1, the first switch module 40 (which can be the second transistor T3_1) is turned on, and the first voltage VDDL can be transmitted through the turned-on first switch module 40 (which can be the second transistor T3_1) and drive module 10 (which can be the drive transistor T1) to the first terminal S of drive module 10 (which can be the first electrode of drive transistor T1), the second terminal of first storage module 20 (which can be the second electrode of first capacitor C1), the first terminal of second storage module 30 (which can be the first electrode of second capacitor C2), and the first node N1, so as to initialize the first terminal S of drive module 10 (which can be the first electrode of drive transistor T1), the second terminal of first storage module 20 (which can be the second electrode of first capacitor C1), the first terminal of second storage module 30 (which can be the first electrode of second capacitor C2), and the first node N1.

[0193] For example, see Figure 16 The control terminal of the first switch module 40 and the control terminal of the second switch module 50 are connected to the same gate signal (e.g., the second gate signal EM) and / or electrically connected to the same gate line.

[0194] For example, the transistors in the first switching module 40 and the transistors in the second switching module 50 have the same channel type, such as N-type (see [reference]). Figure 16 () or P type.

[0195] For example, during the threshold compensation stage t2, the first switch module 40 is turned on, the voltage transmission module 60 is turned on, and the voltage transmission module 60 is connected to the first initialization voltage Vini.

[0196] For example, in the same display frame, the threshold compensation phase t2 precedes the data writing phase t3.

[0197] For example, in the first initialization phase t1, the voltage transmission module 60 is turned on and connected to the first initialization voltage.

[0198] Within the same display frame, threshold compensation phase t2 and / or data writing phase t3 follow the first initialization phase t1.

[0199] For example, voltage transmission module 60 is electrically connected to data line Data, which is used for time-division transmission of data voltage Vata and first initialization voltage Vini.

[0200] For example, in the same display frame, the voltage on the first power line is a variable voltage. For example, in the same display frame, the voltage on the first power line during the threshold compensation phase t2 is different from the voltage on the first power line during the first initialization phase t1.

[0201] For example, in the same display frame, the voltage on the first power line during the threshold compensation phase t2 is higher than the voltage on the first power line during the first initialization phase t1.

[0202] For example, in the same display frame, the voltage on the first power line is the same during the threshold compensation phase t2, the data writing phase t3, and the light emission phase t4.

[0203] Figure 17 This is a schematic diagram of another pixel circuit provided in an embodiment of this application. Figure 7a , Figure 7b , Figure 8 Can be with Figure 17 Combine. Figure 7a , Figure 7b , Figure 8 , Figure 17 Corresponding technical solutions and Figure 7a , Figure 7b , Figure 8 , Figure 6 , Figure 9 The working principles of the corresponding technical solutions are similar, and will not be elaborated here.

[0204] For example, see Figure 17 The pixel circuit also includes a first initialization module 90, which is electrically connected to the first end of the light-emitting element 100, and the first initialization module 90 is connected to a second initialization voltage Vref.

[0205] For example, in the second initialization phase, the first initialization module 90 is turned on, and in the same display frame, the second initialization phase t5 is after the data writing phase t3.

[0206] For example, see Figure 17 The first terminal of the first initialization module 90 is insulated from the first terminal of the voltage transmission module 60. For example, during the first initialization phase t1, the first initialization module 90 is turned on or off. See, for example, [link to documentation]. Figure 17 , Figure 7a In the same display frame, the voltage on the first power line is a variable voltage, and the second initialization voltage Vref is equal to the voltage on the first power line during the first initialization phase t1 (which can be the first voltage VDDL). During the first initialization phase t1, the first switch module 40, the second switch module 50, and the first initialization module 90 are turned on. Alternatively, see [link to other documentation]. Figure 17 , Figure 7b In the same display frame, the voltage on the first power line is a fixed voltage. During the first initialization phase, the first switch module 40, the second switch module 50, and the first initialization module 90 are turned on.

[0207] Figure 18 This is a schematic diagram of another pixel circuit provided in an embodiment of this application. Figure 7a , Figure 7b , Figure 8 Can be with Figure 18 Combine. Figure 7a , Figure 7b , Figure 8 , Figure 18 Corresponding technical solutions and Figure 7a , Figure 7b , Figure 8 , Figure 6 , Figure 9 The working principles of the corresponding technical solutions are similar, and will not be elaborated here.

[0208] For example, see Figure 18 The control terminal of the first initialization module 90 and the control terminal of the second switching module 50 are connected to the same gate signal (e.g., the third gate signal S1) and / or electrically connected to the same gate line.

[0209] For example, the transistors in the first initialization module 90 and the transistors in the second switching module 50 have the same channel type.

[0210] For example, during the threshold compensation stage t2, the first switch module 40 is turned on, the second switch module 50 is turned off, the voltage transmission module 60 is turned on, and the voltage transmission module 60 is connected to the first initialization voltage Vini.

[0211] For example, in the first initialization phase t1, the voltage transmission module 60 is turned on and connected to the first initialization voltage Vini.

[0212] For example, in the same display frame, threshold compensation phase t2 is after the first initialization phase t1; threshold compensation phase t2 is before the data writing phase t3.

[0213] For example, in the second initialization phase t5, the first initialization module 90 is turned on, and in the same display frame, the second initialization phase t5 is after the data writing phase t3.

[0214] For example, voltage transmission module 60 is electrically connected to data line Data, which is used for time-division transmission of data voltage Vdata and first initialization voltage Vini.

[0215] For example, in the second initialization phase t4, the second switch module 50 is turned on and the first switch module 40 is turned off.

[0216] For example, see Figure 18 The first terminal of the first initialization module 90 is insulated from the first terminal of the voltage transmission module 60. For example, during the first initialization phase t1, the first initialization module 90 is turned on or off. See, for example. Figure 18 , Figure 7aIn the same display frame, the voltage on the first power line is a variable voltage, and the second initialization voltage Vref is equal to the voltage on the first power line during the first initialization phase t1. During the first initialization phase, the first switch module 40, the second switch module 50, and the first initialization module 90 are turned on; or, see [link to relevant documentation]. Figure 18 , Figure 7b In the same display frame, the voltage on the first power line is a fixed voltage. During the first initialization phase, the second switch module 50 and the first initialization module 90 are turned on, and the first switch module 40 is turned on.

[0217] Figure 19 This is a timing waveform diagram of another display frame provided in an embodiment of this application. Figure 19 Applicable to Figure 18 Pixel circuit. Figure 18 and Figure 19 Corresponding technical solutions and Figure 18 , Figure 7b The corresponding technical solutions are based on similar principles, and will not be elaborated upon here. The difference lies in... Figure 18 and Figure 19 In the corresponding technical solution, in the same display frame, the voltage on the first power line is a fixed voltage (for example, it can be the second voltage VDDH). In the first initialization phase t1, the second switch module 50 and the first initialization module are turned on 90, and the first switch module is turned off 40. Figure 18 and Figure 19 The corresponding technical solution helps to avoid micro-short circuits between the second initialization voltage Vref input terminal and the first power supply line, thereby reducing power consumption.

[0218] Figure 20 This is a schematic diagram of another pixel circuit provided in an embodiment of this application. Figure 11 , Figure 12 , Figure 14 Can be with Figure 20 Combine. Figure 7a , Figure 7b , Figure 8 Can be with Figure 18 Combine. Figure 11 , Figure 12 , Figure 14 , Figure 20 Corresponding technical solutions and Figures 10 to 14 The working principles of the corresponding technical solutions are similar, and will not be elaborated here.

[0219] For example, see Figure 20 The second end of the voltage transmission module 60 is electrically connected to the control terminal G of the drive module 10; the first end of the first initialization module 90 is electrically connected to the first end of the voltage transmission module 60, and the second end of the first initialization module 90 is electrically connected to the first end of the light-emitting element 100.

[0220] For example, the first terminal of the first initialization module 90 and the first terminal of the voltage transmission module 60 are electrically connected to the data line Data. The data line Data is used for time-division transmission of data voltage Vdata, first initialization voltage Vini, and second initialization voltage Vref. For example, in the first initialization phase t1, the first initialization module 90 is turned off.

[0221] Figure 21 This is a timing waveform diagram of another display frame provided in an embodiment of this application. Figure 21 Applicable to Figure 20 Pixel circuit. Figure 20 and Figure 21 Corresponding technical solutions and Figure 20 , Figure 14 The corresponding technical solutions are based on similar principles, and will not be elaborated upon here. The difference lies in... Figure 20 and Figure 21 In the corresponding technical solution, during the third initialization phase t6, the second gate signal EM is at a shutdown level, for example, a low level; the first switch module 40 (which may be the second transistor T3_1) is turned off, and in the same display frame, the voltage on the first power line is a fixed voltage (for example, the second voltage VDDH). During the third initialization phase t6, the fifth switch module 91 (which may be the seventh transistor T7), the first initialization module 90 (which may be the fourth transistor T4), and the second switch module 50 (which may be the third transistor T3_2) are turned on, which can transmit the second initialization voltage Vref to the light-emitting element 100. The first terminal, the second terminal of the first storage module 20 (which may be the second terminal of the first capacitor C1), the first terminal of the second storage module 30 (which may be the first terminal of the second capacitor C2), the first node N1, and the first terminal S of the driving module 10 (which may be the first terminal of the driving transistor T1) are used to initialize the first terminal of the light-emitting element 100, the second terminal of the first storage module 20 (which may be the second terminal of the first capacitor C1), the first terminal of the second storage module 30 (which may be the first terminal of the second capacitor C2), the first node N1, and the first terminal S of the driving module 10 (which may be the first terminal of the driving transistor T1).

[0222] For example, the second terminal of the second storage module 30 is connected to a DC voltage or a power supply voltage.

[0223] For example, the second end of the light-emitting element 100 is electrically connected to the second power line. In the same display frame, the voltage on the second power line during the data writing phase t3 is different from the voltage on the second power line during the light-emitting phase t4.

[0224] For example, in the same display frame, the voltage on the second power line during the data writing phase t3 is higher than the voltage on the second power line during the light emission phase.

[0225] For example, in the same display frame, the voltage on the second power line is the same during the first initialization phase t1, the threshold compensation phase t2, and the data writing phase t3.

[0226] This embodiment has the same or similar effects as the above embodiments, and will not be repeated here. This embodiment can be combined with some or all of the features of the above embodiments, and will not be repeated here.

[0227] Figure 22 This is a schematic diagram of another pixel circuit structure provided in an embodiment of this application. For example, see... Figure 21 The voltage transmission module 60 may include a fifth transistor T5 and a sixth transistor T6. The first terminal of the fifth transistor T5 is connected to the data voltage Vdata and / or electrically connected to the data line Data. The first terminal of the sixth transistor T6 is connected to the first initialization voltage Vini. The second terminals of the fifth transistor T5 and the sixth transistor T6 are electrically connected to the control terminal G of the drive module 10. The signal timing of the gates of each transistor can be set as needed, which will not be described in detail here. Figure 22 pixel circuit and Figure 2 The working principle of the pixel circuit is similar, and will not be elaborated here. It is equivalent to... Figure 2 The third switch module 70 and the fourth switch module 80 are located in the display area. Each pixel circuit has its own third switch module 70 and fourth switch module 80, which can be removed as needed. Figure 2 The first transistor T2 in the process is used to obtain Figure 22 The pixel circuit. In this embodiment, during the data writing stage, the first switch module 40 is turned off, the second switch module 50 is turned off, and the voltage transmission module 60 is turned on. The voltage transmission module 60 is connected to the data voltage Vdata, which reduces or eliminates the correlation between the voltage at the second terminal of the first storage module 20 and the parasitic capacitance at the first terminal of the light-emitting element 100, or makes it unaffected by the parasitic capacitance at the first terminal of the light-emitting element 100. This is beneficial for improving display uniformity, avoiding or improving the leakage of voltage from the first power line to the first node N1 after the data writing stage and / or threshold compensation stage, reducing the risk of brightness differences between the first and last rows of pixels, and improving the display effect.

[0228] Figure 23 This is a schematic diagram of another pixel circuit structure provided in an embodiment of this application. For example, see... Figure 23 The voltage transmission module 60 may include a fifth transistor T5, a sixth transistor T6 and a first transistor T2. The first terminal of the fifth transistor T5 is connected to the data voltage Vdata and / or electrically connected to the data line Data. The first terminal of the sixth transistor T6 is connected to the first initialization voltage Vini. The second terminals of the fifth transistor T5 and the sixth transistor T6 are electrically connected to the control terminal G of the drive module 10 via the first transistor T2. Figure 23pixel circuit and Figure 2 The working principle of the pixel circuit is similar, and will not be elaborated here. It is equivalent to... Figure 2 The third switch module 70 and the fourth switch module 80 are located in the display area, and each pixel circuit has its own third switch module 70 and fourth switch module 80 to achieve the desired result. Figure 23 The pixel circuit. In this embodiment, during the data writing stage, the first switch module 40 is turned off, the second switch module 50 is turned off, and the voltage transmission module 60 is turned on. The voltage transmission module 60 is connected to the data voltage Vdata, which reduces or eliminates the correlation between the voltage at the second terminal of the first storage module 20 and the parasitic capacitance at the first terminal of the light-emitting element 100, or makes it unaffected by the parasitic capacitance at the first terminal of the light-emitting element 100. This is beneficial for improving display uniformity, avoiding or improving the leakage of voltage from the first power line to the first node N1 after the data writing stage and / or threshold compensation stage, reducing the risk of brightness differences between the first and last rows of pixels, and improving the display effect. For example, the second terminal of the fifth transistor T5, the second terminal of the sixth transistor T6, and the first terminal of the first transistor T2 are electrically connected to the second node N2. The second terminal of the first transistor T2 is electrically connected to the control terminal G of the driving module 10.

[0229] For example, within the same display frame, the voltage on the first power line can be a DC voltage or a variable voltage. Similarly, within the same display frame, the voltage on the second power line can be a DC voltage or a variable voltage.

[0230] Compared to Figure 15 , Figure 16 pixel circuit, Figure 1 , Figure 2 The closer proximity of the first switch module 40 and the second switch module 50 in the pixel circuit makes it easier to design the layout, simplifies the layout, reduces the number of vias, and helps improve pixel resolution. Figure 24 This is a cross-sectional structural diagram of a display panel provided in an embodiment of this application. For example, see... Figure 24 The display panel includes a substrate 103 and a first active layer 101 and a second active layer 102 stacked on the substrate along the thickness direction Z of the substrate (e.g., parallel to the thickness direction of the display panel). The first active layer includes an active portion 101a of a driving transistor T1, and the second active layer includes an active portion 102a of a second transistor T3_1 and an active portion 102b of a third transistor T3_2. For example, the orthographic projection of the active portion of the driving transistor T1 on the substrate overlaps with the orthographic projection of the active portion of the second transistor T3_1 on the substrate, and / or, the orthographic projection of the active portion of the driving transistor T1 on the substrate overlaps with the orthographic projection of the active portion of the third transistor T3_2 on the substrate. An insulating layer may be provided between the first active layer 101 and the second active layer 102.

[0231] For example, the first active layer 101 and the second active layer 102 may be made of the same or different materials. For example, the material of the first active layer 101 may include polysilicon or metal oxide. For example, the material of the second active layer 102 may include polysilicon or metal oxide.

[0232] In some embodiments, the voltage transmission module 60 is electrically connected to the control terminal G of the driving module 10 via the second storage module 30 and the first storage module 20. The pixel circuit also includes a second initialization module, which is electrically connected to the control terminal G of the driving module 10. The second initialization module can be used to initialize the control terminal G of the driving module 10. The voltage transmission module 60 can be used to initialize the second terminal of the second storage module 30.

[0233] This application provides a driving method. The driving method includes: during the data writing stage t3, the first switch module 40 is turned off, the second switch module 50 is turned off, the voltage transmission module 60 is turned on, and the voltage transmission module 60 is connected to the data voltage Vdata.

[0234] The driving method of this application embodiment can be applied to the pixel circuit 200 of any embodiment of this application or to the display panel 300 of any embodiment of this application, and has the beneficial effects of the pixel circuit of any embodiment of this application, which will not be described again here. This embodiment can be combined with some or all of the features in the above embodiments, which will not be described again here.

[0235] Figure 25 This is a schematic diagram of a display device provided in an embodiment of this application. This application also provides a display device 1, including the display panel 300 provided in any embodiment of this application.

[0236] For example, the display device includes a photosensitive element and a display panel provided in any embodiment of this application. The photosensitive element is used to receive light transmitted through the light-transmitting area. The photosensitive element may include one or more of a camera, a fingerprint recognition module, an ambient light sensor, an infrared sensor, etc.

[0237] Display devices include, but are not limited to, mobile phones, personal digital assistants (PDAs), tablets, e-books, televisions, access control systems, smart landlines, consoles, laptops, wearable devices, in-vehicle displays, virtual reality (VR) and augmented reality (AR) and other near-eye display devices with display functions.

[0238] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0239] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A pixel circuit, characterized in that, The pixel circuit includes: a driving module, a first switching module, a second switching module, a first storage module, a second storage module, and a voltage transmission module; The first terminal of the first switch module is electrically connected to the first terminal of the drive module; the first storage module is connected between the control terminal of the drive module and the second terminal of the first switch module; the first terminal of the second storage module is electrically connected to the second terminal of the first switch module; and the second switch module is connected between the second terminal of the first switch module and the first terminal of the light-emitting element; the voltage transmission module is electrically connected to the control terminal of the drive module. During the data writing phase, the first switch module is turned off, the second switch module is turned off, the voltage transmission module is turned on, and the voltage transmission module is connected to the data voltage.

2. The pixel circuit according to claim 1, characterized in that, The control terminal of the first switch module and the control terminal of the second switch module are connected to the same gate signal and / or electrically connected to the same gate line; Preferably, the transistors in the first switching module and the transistors in the second switching module have the same channel type; Preferably, during the threshold compensation stage, the first switch module is turned on, the voltage transmission module is turned on, and the voltage transmission module is connected to the first initialization voltage. Preferably, in the same display frame, the threshold compensation stage precedes the data writing stage; Preferably, during the first initialization phase, the voltage transmission module is turned on and connected to the first initialization voltage. In the same display frame, the threshold compensation phase and / or the data writing phase follow the first initialization phase; Preferably, the voltage transmission module is electrically connected to the data line, and the data line is used for time-division multiplexing of the data voltage and the first initialization voltage; Preferably, the second end of the drive module is electrically connected to the first power line. In the same display frame, the voltage on the first power line is a variable voltage; in the same display frame, the voltage on the first power line during the threshold compensation phase is different from the voltage on the first power line during the first initialization phase; preferably, in the same display frame, the voltage on the first power line during the threshold compensation phase is higher than the voltage on the first power line during the first initialization phase; preferably, in the same display frame, the voltage on the first power line is the same during the threshold compensation phase, the data writing phase, and the light emission phase. Preferably, the pixel circuit further includes a first initialization module, which is electrically connected to a first terminal of the light-emitting element, and the first initialization module is connected to a second initialization voltage. During the first initialization phase, the first initialization module is either turned on or off. Preferably, in the second initialization phase, the first initialization module is turned on, and in the same display frame, the second initialization phase follows the data writing phase; Preferably, in the same display frame, the voltage on the first power line is a variable voltage, the second initialization voltage is equal to the voltage on the first power line during the first initialization phase, and during the first initialization phase, the first switch module, the second switch module, and the first initialization module are turned on. Alternatively, in the same display frame, the voltage on the first power line is a fixed voltage, and during the first initialization phase, the first switch module, the second switch module, and the first initialization module are turned on.

3. The pixel circuit according to claim 1, characterized in that, The pixel circuit further includes a first initialization module, which is electrically connected to a first terminal of the light-emitting element, and the first initialization module is connected to a second initialization voltage. Preferably, the control terminal of the first initialization module and the control terminal of the second switching module are connected to the same gate signal and / or electrically connected to the same gate line; Preferably, the transistors in the first initialization module and the transistors in the second switching module have the same channel type; Preferably, during the threshold compensation stage, the first switch module is turned on, the second switch module is turned off, the voltage transmission module is turned on, and the voltage transmission module is connected to the first initialization voltage. During the first initialization phase, the voltage transmission module is turned on and connected to the first initialization voltage. In the same display frame, the threshold compensation phase occurs after the first initialization phase; the threshold compensation phase occurs before the data writing phase. Preferably, in the second initialization phase, the first initialization module is turned on, and in the same display frame, the second initialization phase follows the data writing phase; Preferably, during the second initialization phase, the first switch module is turned off; Preferably, the voltage transmission module is electrically connected to the data line, and the data line is used for time-division multiplexing of the data voltage and the first initialization voltage; Preferably, the control terminal of the first switch module and the control terminal of the second switch module are connected to different gate signals and / or electrically connected to different gate lines; Preferably, the transistors in the first switching module and the transistors in the second switching module have the same channel type.

4. The pixel circuit according to claim 2 or 3, characterized in that, The first terminal of the first initialization module is insulated from the first terminal of the voltage transmission module. Preferably, during the first initialization phase, the first initialization module is turned on or off. Preferably, the second terminal of the drive module is electrically connected to the first power line. In the same display frame, the voltage on the first power line is a variable voltage, and the second initialization voltage is equal to the voltage on the first power line during the first initialization phase. During the first initialization phase, the first switch module, the second switch module, and the first initialization module are turned on. Alternatively, in the same display frame, the voltage on the first power line is a fixed voltage, and during the first initialization phase, the first switch module, the second switch module, and the first initialization module are turned on. Alternatively, the second terminal of the voltage transmission module is electrically connected to the control terminal of the drive module; the first terminal of the first initialization module is electrically connected to the first terminal of the voltage transmission module, and the second terminal of the first initialization module is electrically connected to the first terminal of the light-emitting element; preferably, the first terminal of the first initialization module and the first terminal of the voltage transmission module are electrically connected to a data line, and the data line is used for time-division transmission of the data voltage, the first initialization voltage, and the second initialization voltage; preferably, during the first initialization phase, the first initialization module is turned off. Preferably, during the first initialization phase and / or the threshold compensation phase, the data line is used to transmit the first initialization voltage; during the data writing phase, the data line is used to transmit the data voltage; and during the second initialization phase, the data line is used to transmit the second initialization voltage. Preferably, the second terminal of the second storage module is connected to a DC voltage or a power supply voltage; Preferably, the second end of the light-emitting element is electrically connected to the second power line, and in the same display frame, the voltage on the second power line during the data writing phase is different from the voltage on the second power line during the light-emitting phase; Preferably, in the same display frame, the voltage on the second power line during the data writing phase is higher than the voltage on the second power line during the light emission phase; Preferably, in the same display frame, during the first initialization phase, the threshold compensation phase, and the data writing phase, the voltage on the second power line is the same; Preferably, the first initialization voltage is greater than the second initialization voltage; Preferably, the second end of the driving module is electrically connected to the first power line, and in the same display frame, during at least one of the threshold compensation stage and the data writing stage, the voltage on the first power line is greater than or equal to the voltage on the second power line. Preferably, during the first initialization phase, the voltage on the first power line is less than or equal to the second initialization voltage; the second initialization voltage is less than or equal to the voltage on the second power line during the light emission phase.

5. A pixel circuit, characterized in that, The pixel circuit includes: a driving module, a first switching module, a second switching module, a first storage module, a second storage module, and a voltage transmission module; The first terminal of the first switch module is electrically connected to the first power line, the second terminal of the first switch module is electrically connected to the second terminal of the drive module, the first storage module is connected between the control terminal and the first terminal of the drive module, the first terminal of the second storage module is electrically connected to the first terminal of the drive module, and the second switch module is connected between the first terminal of the drive module and the first terminal of the light-emitting element; the voltage transmission module is electrically connected to the control terminal of the drive module. During the data writing phase, the first switch module is turned off, the second switch module is turned off, the voltage transmission module is turned on, and the voltage transmission module is connected to the data voltage.

6. The pixel circuit according to claim 5, characterized in that, The control terminal of the first switch module and the control terminal of the second switch module are connected to the same gate signal and / or electrically connected to the same gate line; Preferably, the transistors in the first switching module and the transistors in the second switching module have the same channel type; Preferably, during the threshold compensation stage, the first switch module is turned on, the voltage transmission module is turned on, and the voltage transmission module is connected to the first initialization voltage. Preferably, in the same display frame, the threshold compensation stage precedes the data writing stage; Preferably, during the first initialization phase, the voltage transmission module is turned on and connected to the first initialization voltage. In the same display frame, the threshold compensation phase and / or the data writing phase follow the first initialization phase; Preferably, the voltage transmission module is electrically connected to the data line, and the data line is used for time-division multiplexing of the data voltage and the first initialization voltage; Preferably, in the same display frame, the voltage on the first power line is a variable voltage; in the same display frame, the voltage on the first power line during the threshold compensation phase is different from the voltage on the first power line during the first initialization phase; preferably, in the same display frame, the voltage on the first power line during the threshold compensation phase is higher than the voltage on the first power line during the first initialization phase; preferably, in the same display frame, the voltage on the first power line is the same during the threshold compensation phase, the data writing phase, and the light emission phase. Preferably, the pixel circuit further includes a first initialization module, which is electrically connected to a first terminal of the light-emitting element, and the first initialization module is connected to a second initialization voltage. Preferably, in the second initialization phase, the first initialization module is turned on, and in the same display frame, the second initialization phase follows the data writing phase; Preferably, the first terminal of the first initialization module is insulated from the first terminal of the voltage transmission module; preferably, during the first initialization phase, the first initialization module is turned on or off; preferably, in the same display frame, the voltage on the first power line is a variable voltage, the second initialization voltage is equal to the voltage on the first power line during the first initialization phase, and during the first initialization phase, the first switch module, the second switch module, and the first initialization module are turned on; or, in the same display frame, the voltage on the first power line is a fixed voltage, and during the first initialization phase, the first switch module, the second switch module, and the first initialization module are turned on. Alternatively, the second terminal of the voltage transmission module is electrically connected to the control terminal of the drive module; the first terminal of the first initialization module is electrically connected to the first terminal of the voltage transmission module, and the second terminal of the first initialization module is electrically connected to the first terminal of the light-emitting element; preferably, the first terminal of the first initialization module and the first terminal of the voltage transmission module are electrically connected to a data line, and the data line is used for time-division transmission of the data voltage, the first initialization voltage, and the second initialization voltage; preferably, during the first initialization phase, the first initialization module is turned off. Preferably, the second terminal of the second storage module is connected to a DC voltage or a power supply voltage; Preferably, the second end of the light-emitting element is electrically connected to the second power line, and in the same display frame, the voltage on the second power line during the data writing phase is different from the voltage on the second power line during the light-emitting phase; Preferably, in the same display frame, the voltage on the second power line during the data writing phase is higher than the voltage on the second power line during the light emission phase; Preferably, in the same display frame, during the first initialization phase, the threshold compensation phase, and the data writing phase, the voltage on the second power line is the same.

7. The pixel circuit according to claim 5, characterized in that, The pixel circuit further includes a first initialization module, which is electrically connected to a first terminal of the light-emitting element, and the first initialization module is connected to a second initialization voltage. Preferably, the control terminal of the first initialization module and the control terminal of the second switching module are connected to the same gate signal and / or electrically connected to the same gate line; Preferably, the transistors in the first initialization module and the transistors in the second switching module have the same channel type; Preferably, during the threshold compensation stage, the first switch module is turned on, the second switch module is turned off, the voltage transmission module is turned on, and the voltage transmission module is connected to the first initialization voltage. During the first initialization phase, the voltage transmission module is turned on and connected to the first initialization voltage. In the same display frame, the threshold compensation phase occurs after the first initialization phase; the threshold compensation phase occurs before the data writing phase. Preferably, in the second initialization phase, the first initialization module is turned on, and in the same display frame, the second initialization phase follows the data writing phase; Preferably, the voltage transmission module is electrically connected to the data line, and the data line is used for time-division multiplexing of the data voltage and the first initialization voltage; Preferably, during the second initialization phase, the second switch module is turned on and the first switch module is turned off; preferably, the control terminal of the first switch module and the control terminal of the second switch module are connected to different gate signals and / or electrically connected to different gate lines. Preferably, the transistors in the first switching module and the transistors in the second switching module have the same channel type; Preferably, the first terminal of the first initialization module is insulated from the first terminal of the voltage transmission module. Preferably, during the first initialization phase, the first initialization module is turned on or off. Preferably, in the same display frame, the voltage on the first power line is a variable voltage, the second initialization voltage is equal to the voltage on the first power line during the first initialization phase, and during the first initialization phase, the first switch module, the second switch module, and the first initialization module are turned on. Alternatively, in the same display frame, the voltage on the first power line is a fixed voltage, and during the first initialization phase, the second switch module and the first initialization module are turned on, and the first switch module is turned off. Alternatively, the first terminal of the first initialization module is electrically connected to the first terminal of the voltage transmission module, and the second terminal of the voltage transmission module is electrically connected to the control terminal of the drive module; the second terminal of the first initialization module is electrically connected to the first terminal of the light-emitting element; preferably, the first terminal of the first initialization module and the first terminal of the voltage transmission module are electrically connected to a data line, and the data line is used for time-division transmission of the data voltage, the first initialization voltage, and the second initialization voltage; preferably, during the first initialization phase, the first initialization module is turned off. Preferably, the second terminal of the second storage module is connected to a DC voltage or a power supply voltage; Preferably, the second end of the light-emitting element is electrically connected to the second power line, and in the same display frame, the voltage on the second power line during the data writing phase is different from the voltage on the second power line during the light-emitting phase; Preferably, in the same display frame, the voltage on the second power line during the data writing phase is higher than the voltage on the second power line during the light emission phase; Preferably, in the same display frame, during the first initialization phase, the threshold compensation phase, and the data writing phase, the voltage on the second power line is the same.

8. A display panel, characterized in that, Includes the pixel circuit as described in any one of claims 1-7.

9. The display panel according to claim 8, characterized in that, The display panel further includes a selection circuit, which includes a third switch module and a fourth switch module. The first terminal of the third switch module is connected to a data voltage, and the first terminal of the fourth switch module is connected to a first initialization voltage. The second terminals of the third switch module and the fourth switch module are electrically connected and connected to the first terminal of the voltage transmission module via a data line. The second terminal of the voltage transmission module is electrically connected to the control terminal of the drive module. The third switch module and the fourth switch module are turned on in a time-division manner; the data line is used to transmit the data voltage and the first initialization voltage in a time-division manner. Preferably, during the data writing phase, the third switch module is turned on, the fourth switch module is turned off, and the data line is used to transmit the data voltage. During the threshold compensation phase and / or the first initialization phase, the third switch module is turned off, the fourth switch module is turned on, and the data line is used to transmit the first initialization voltage. Preferably, at least two of the pixel circuits share the same selection circuit; Preferably, the display panel includes a display area and a non-display area, the pixel circuit is located in the display area, and the selection circuit is located in the non-display area; Preferably, when the pixel circuit further includes a first initialization module, the selection circuit further includes a fifth switch module, the first terminal of the fifth switch module is connected to a second initialization voltage, and the second terminal of the fifth switch module is electrically connected to the first terminal of the first initialization module via the data line; The third switch module, the fourth switch module, and the fifth switch module are turned on in a time-division manner, and the data line is used to transmit the data voltage, the first initialization voltage, and the second initialization voltage in a time-division manner. Preferably, during the second initialization phase, the fifth switch module is turned on, the third switch module and the fourth switch module are turned off, and the data line is used to transmit the second initialization voltage; Preferably, the second terminal of the third switch module is electrically connected to the second terminal of the fourth switch module and the second terminal of the fifth switch module, and the first terminal of the first initialization module and the first terminal of the voltage transmission module are electrically connected. Preferably, the display panel includes a plurality of pixel circuits arranged in an array, within the same display frame. The first initialization phase of the pixel circuit described in multiple rows starts and ends simultaneously. The threshold compensation phase of the pixel circuits in the multiple rows starts and ends simultaneously. The data writing stages of the pixel circuits in the multiple rows do not overlap; The light-emitting phases of the pixel circuits described in multiple rows begin and end simultaneously; Preferably, the second initialization phase of the multiple rows of pixel circuits starts and ends simultaneously; Preferably, during the first initialization phase, the control terminals of the driving modules in the multiple rows of pixel circuits are initialized simultaneously. During the threshold compensation phase, the first switch module in the multiple rows of pixel circuits is simultaneously turned on. Preferably, the control terminal of the first switch module in the multiple rows of pixel circuits is electrically connected; the control terminal of the second switch module in the multiple rows of pixel circuits is electrically connected; Preferably, the display panel further includes a gate driving circuit, which includes multiple cascaded shift registers, and the control terminal of the voltage transmission module in the multiple rows of pixel circuits is electrically connected to the gate driving circuit. Preferably, the control terminal of the first initialization module in the multiple rows of pixel circuits is electrically connected; Preferably, the control terminal of the fifth switch module and the control terminal of the first initialization module are electrically connected and / or connected to the same gate signal; Preferably, the transistors in the fifth switching module and the transistors in the first initialization module have the same channel type.

10. A driving method, characterized in that, Applied to a pixel circuit as described in any one of claims 1-7 or a display panel as described in claim 8 or 9, the driving method includes: During the data writing phase, the first switch module is turned off, the second switch module is turned off, the voltage transmission module is turned on, and the voltage transmission module is connected to the data voltage.

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