Control device, disk device, control method, and program

Abstract

Embodiments of the present application provide a control device, a disc device, a control method, and a program that can inhibit a time required for an operation process other than a predetermined operation process from becoming longer. The control device of the embodiments can execute a first determination process. The processor of the control device can execute a first operation process performed in order to control a position of a head of the disc device, a second operation process, and a replacement process performed in order to maintain the position of the head at a predetermined position with a lower operation load than the first operation process. The first determination process includes obtaining a first execution time and a second execution time. The first determination process includes, in a case where the second execution time is shorter than the first execution time, selecting a second execution method that is different from a first execution method in which the first operation process is executed while the second operation process is executed. In the second execution method, the second operation process is executed after the replacement process is started in place of the first operation process.

Description

[0001] This application enjoys priority based on Japanese Patent Application No. 2025-023987 (filed on February 18, 2025). This application incorporates the entire contents of the basic application by reference to that basic application. Technical Field

[0002] Embodiments of the present invention relate to a control device, a control panel, a control method, and a program (program product). Background Technology

[0003] A processing device that performs a predetermined arithmetic operation sometimes executes that operation along with other arithmetic operations via a processor. In this case, a portion of the processor's processing power is used for the predetermined arithmetic operation, thus increasing the time required to complete the other arithmetic operations. For example, in a disk drive, sometimes the processor executes a predetermined arithmetic operation to control the position of the disk head, as well as other arithmetic operations to improve the processing performance of the disk drive. In this case, sometimes the time required for the other arithmetic operations to improve the processing performance of the disk drive increases, and the time required to achieve the desired improvement in the disk drive's processing performance also increases. Summary of the Invention

[0004] Embodiments of the present invention provide a control device, disk device, control method, and program capable of suppressing the increase in time required for other computational processes besides the predetermined computational processes.

[0005] The control device in this embodiment is a control device for a control disk device. The control device includes a processor. The control device is configured to execute a first determination process. The processor is configured to execute a first arithmetic process for controlling the position of the head of the disk device. The processor is configured to execute a second arithmetic process that can be executed simultaneously with the first arithmetic process. The processor is configured to execute a substitution process for maintaining the head position at a predetermined position with a lower computational load than the first arithmetic process. The first determination process is a process executed based on information stored in a predetermined storage medium when it is determined that the second arithmetic process will be executed. The information stored in the storage medium includes a first processing time required until the second arithmetic process is completed when the processor only executes the second arithmetic process. The information stored in the storage medium includes a second processing time required until the head position is maintained at the predetermined position by the substitution process, replacing the first arithmetic process. The information stored in the storage medium includes a third processing time required to restart the first arithmetic process, which was interrupted by the execution of the substitution process. The information stored in the storage medium includes a first processing occupancy of the processor required to perform the first arithmetic operation. The information stored in the storage medium also includes a second processing occupancy of the processor required to maintain the position of the head through the substitution process. The first determination process includes: when the first processing time is set to TA, the second processing time to TB, the third processing time to TC, the first processing occupancy to k1, and the second processing occupancy to k2, obtaining a first execution time expressed as TA / (1-k1) and a second execution time expressed as {TA / (1-k2)}+TB+TC based on the information stored in the storage medium. The first determination process includes: when the second execution time is shorter than the first execution time, selecting a second execution method different from the first execution method that executes the first arithmetic operation while simultaneously executing the second arithmetic operation. The second execution method is a method that starts executing the substitution process after replacing the first arithmetic operation and then executes the second arithmetic operation. Attached Figure Description

[0006] Figure 1 This is a perspective view of the disk device according to the embodiment.

[0007] Figure 2 This is a block diagram illustrating the configuration of the disk device in the embodiment.

[0008] Figure 3 This is a diagram showing a portion of the disk device in an embodiment.

[0009] Figure 4 This diagram shows the state in which the position of the head is fixed by the locking mechanism of the implementation method.

[0010] Figure 5 This is a diagram showing the state of contact between the head assembly and the stop in the embodiment.

[0011] Figure 6 This is a block diagram illustrating an example of the configuration of a read / write channel in an implementation method.

[0012] Figure 7 This is a block diagram illustrating an example of the configuration of a driver IC in an implementation method.

[0013] Figure 8 This is a block diagram illustrating the voice coil motor control process and micro-actuator control process of the implementation method.

[0014] Figure 9 This is a block diagram illustrating the voice coil motor control process and microactuator control process when the first MA filter generation process of the embodiment is executed.

[0015] Figure 10 This is a block diagram illustrating the voice coil motor control process and microactuator control process when the second VCM filter generation process and the second MA filter generation process of the embodiment are executed.

[0016] Figure 11 This is a coordinate graph showing an example of the relationship between the first execution time of the implementation method and the second execution time of each alternative process, and the first processing time.

[0017] Figure 12 This is a flowchart illustrating a portion of the processing performed by the control device in an embodiment.

[0018] Figure 13 This is a flowchart illustrating another part of the processing performed by the control device in the implementation method.

[0019] Figure 14 This is a coordinate graph illustrating an example of the change in the processing performance of the disk device when the second operation processing is performed by the first execution method and the second execution method of the embodiment, respectively.

[0020] Explanation of reference numerals in the attached figures

[0021] 20… disk, 30… head assembly, 31… head, 40… control device, 41… processor, 53… non-volatile memory (storage medium), 73… actuator, 80… host device, 90… locking mechanism, 91… stop, 100… disk device, AP… alternative processing, APT… actual processing time, CP1… first operation processing, CP2… second operation processing, CTP… control processing, DP1… first decision processing, DP2… second decision processing, EM1… first execution method, EM2… second execution method, k1… first processing occupancy, k2… second processing occupancy, TA… first processing time, TB… second processing time, TC… third processing time, TE1… first execution time, TE2… second execution time, θ… head position. Detailed Implementation

[0022] Hereinafter, with reference to the accompanying drawings, the control device, disk device, control method and procedure of the embodiments will be described.

[0023] Figure 1 This is a perspective view showing the disk device 100 of this embodiment. Figure 2 This is a block diagram showing the configuration of the disk device 100 in this embodiment. Figure 3 This is a diagram showing a portion of the disk device 100 according to this embodiment. Figures 1-3 The disk device 100 shown in this embodiment is a disk drive with a built-in hard disk drive. The disk device 100 is capable of storing information as digital data. The disk device 100 is driven based on instructions from a host device 80. The host device 80 is, for example, a server, a personal computer, etc. The host device 80 is not particularly limited to any device that assigns instructions to the disk device 100. The host device 80 can cause the disk device 100 to record information and can read the data recorded by the disk device 100.

[0024] like Figure 1 As shown, the disk assembly 100 includes a housing 10, a disk 20, a head assembly 30, a control device 40, a power terminal 81, and a connection terminal 82. Figure 2 As shown, the disk assembly 100 includes a spindle motor 72, an actuator 73, and a vibration sensor 76. (As...) Figure 3 As shown, the disc device 100 includes a locking mechanism 90 and a stop 91.

[0025] like Figure 1 As shown, the housing 10 houses the disc 20 and the head assembly 30 internally. The housing 10 has a housing body 11 and a cover 12. Figure 3 As shown, the housing body 11 houses a disc 20, a head assembly 30, a locking mechanism 90, and a stop 91.

[0026] In this embodiment, disk 20 is a magnetic disk. Disk 20 is circular. Disk 20 is rotated about a first rotation axis R1 by a spindle motor 72. Disk 20 has a recording surface for recording digital data. Figure 1 As shown, multiple disks 20 are arranged at intervals along the axial direction of the first rotation axis R1. The number of disks 20 is not particularly limited as long as there is one or more.

[0027] Figure 3 The head assembly 30 shown is electrically connected to the control device 40. The head assembly 30 is controlled by the control device 40 to perform the writing of data to the disk 20 and the reading of data recorded on the disk 20. The head assembly 30 is a head stack assembly included in the disk device 100. The head assembly 30 is rotated about a second rotation axis R2 by a voice coil motor 74 (described later) of the actuator 73. The second rotation axis R2 extends axially along the first rotation axis R1. The second rotation axis R2 is parallel to the first rotation axis R1.

[0028] The head assembly 30 includes a main body 30a, multiple heads 31, and a head amplifier IC 37. Although not shown, the head amplifier IC 37 includes a read amplifier and a write driver. The read amplifier amplifies the signal of data read from the disk 20 by the heads 31 and outputs it to the read / write channel 43 in the controller 44. The write driver outputs a write current corresponding to the data output from the read / write channel 43 to the heads 31. The heads 31 write data to the disk 20 based on the write current output from the write driver. The head amplifier IC 37 is mounted on a flexible substrate (not shown). This flexible substrate electrically connects the heads 31 and the control device 40.

[0029] The main body 30a has a base 33, a plurality of arms 32, and a holding portion 34. A head amplifier IC 37 is mounted on the base 33 via a flexible substrate (not shown). The plurality of arms 32 extend radially from the base 33 about a second rotation axis R2. Figure 1 As shown, multiple arms 32 are arranged at intervals along the axial direction of the first rotation axis R1. A head 31 is fitted onto the front end of each arm 32. Figure 3 As shown, a retaining portion 34 is formed in the base 33. The coil 74a of the voice coil motor 74 is held in the retaining portion 34.

[0030] The head 31 is a magnetic head capable of reading data recorded on the disk 20 and writing data to the disk 20. The head 31 can read data from the recording surface of the disk 20 and write data to the recording surface of the disk 20 at a position opposite to the recording surface of the disk 20. By using the voice coil motor 74 described later to rotate the head assembly 30 about the second rotation axis R2, each head 31 mounted on the front end of each arm 32 is moved to a position opposite to the recording surface of each disk 20 and a position not opposite to the recording surface of the disk 20.

[0031] Actuator 73 is the actuator that moves head 31. For example... Figure 2 As shown, in this embodiment, the actuator 73 includes a voice coil motor 74 and a micro-actuator 75. The circumferential position θ of the head 31 about the second rotation axis R2 is controlled by the voice coil motor 74 and the micro-actuator 75. The voice coil motor 74 rotates the head assembly 30 about the second rotation axis R2. Figure 3 As shown, microactuators 75 are respectively mounted on the front end portions of the plurality of arms 32. Each microactuator 75 causes each head 31 to move slightly in the circumferential direction about the second rotation axis R2. Each microactuator 75 is, for example, an actuator that moves the head 31 by means of two piezoelectric elements. Furthermore, the microactuator 75 can be any actuator as long as it can move the head 31. In this embodiment, the circumferential position θ of the head 31 about the second rotation axis R2 is controlled by the voice coil motor 74 and the microactuator 75. Furthermore, the actuator 73 may not have a microactuator 75. The actuator 73 can be any configuration as long as it can move the head 31.

[0032] The locking mechanism 90 is a mechanism that fixes the position θ of the head 31 at the position where it is away from the disk 20. In this embodiment, the locking mechanism 90 is a ramp mechanism. Figure 4 This diagram shows the state in which the position θ of the head 31 is fixed by the locking mechanism 90. (Example) Figure 4 As shown, the head 31 is held by the locking mechanism 90 at a position where it is not facing the recording surface of the disk 20. The position where the head 31 is held by the locking mechanism 90 is the outermost position of the head 31 radially about the first rotation axis R1. Furthermore, the locking mechanism 90 can be any mechanism with any construction as long as it can fix the position θ of the head 31 at the position away from the disk 20.

[0033] The stop 91 faces the head assembly 30 in the direction of movement of the head assembly 30. The stop 91 can contact the head assembly 30 in the direction of movement of the head assembly 30. In this embodiment, the direction of movement of the head assembly 30 is circumferential about the second rotation axis R2. Figure 5 This diagram shows the state in which the head assembly 30 is in contact with the stop member 91. In this embodiment, the stop member 91 is in contact with the retaining portion 34 in the main body 30a. Furthermore, the stop member 91 can contact any part of the head assembly 30. The position θ of the head 31 when the head assembly 30 is in contact with the stop member 91 is the position where the head 31 is located at its innermost point radially about the first rotation axis R1. The stop member 91 can prevent the head 31 from moving excessively inward radially about the first rotation axis R1.

[0034] Control device 40 is a component of control panel device 100. For example... Figure 1As shown, the control device 40 is, for example, mounted on the outer surface of the housing 10. For example, at least a portion of the control device 40 is exposed to the outside of the housing 10. The control device 40 has a circuit board 40a. The circuit board 40a is a printed circuit board (PCB).

[0035] like Figure 2 As shown, the control device 40 includes a controller 44, a driver IC 45, a first volatile memory 51, a second volatile memory 52, a non-volatile memory 53, and an A / D conversion circuit 46. The controller 44, driver IC 45, first volatile memory 51, second volatile memory 52, non-volatile memory 53, and A / D conversion circuit 46 are mounted on a circuit board 40a, for example.

[0036] Controller 44 is the system controller of the control disk device 100. Controller 44 is, for example, a large-scale integrated circuit (LSI) called a system-on-a-chip (SoC), which integrates multiple components such as a microprocessor onto a single chip. Controller 44 is electrically connected to driver IC 45, first volatile memory 51, second volatile memory 52, non-volatile memory 53, and A / D conversion circuit 46. Controller 44 has a processor 41, a hard disk controller 42, and a read / write channel 43.

[0037] The hard disk controller 42 controls data transfer between the host device 80 and the read / write channel 43 based on instructions from the processor 41. The hard disk controller 42 is electrically connected to the processor 41, the read / write channel 43, the head amplifier IC 37, the driver IC 45, the first volatile memory 51, the second volatile memory 52, and the non-volatile memory 53. The hard disk controller 42 has an interface control unit 42a, a buffer control unit 42b, and a format control unit 42c. The interface control unit 42a controls the interface with the host device 80. The interface control unit 42a reads instructions from the host device 80 and performs data reception and transmission. The buffer control unit 42b temporarily records data input from the host device 80 via the interface control unit 42a and data read from the disk 20 in the first volatile memory 51. The format control unit 42c converts the format of data input from the buffer control unit 42b and data input from the read / write channel 43.

[0038] The read / write channel 43 performs signal processing on data sent from disk 20 to host device 80 and data sent from host device 80 to disk 20, based on instructions from processor 41. The read / write channel 43 may, for example, have a function to measure the signal quality of the data. Figure 6This is a block diagram illustrating an example of the configuration of read / write channel 43. For example... Figure 6 As shown, the read / write channel 43 includes a signal processing circuit 43a and a position detection circuit 43b. The signal processing circuit 43a processes the read signals and write signals corresponding to the servo information read from the read head included in the head 31 and the user data read from the read head included in the head 31. The position detection circuit 43b extracts the servo information from the read signal and generates a position detection signal for detecting the position θ of the head 31.

[0039] The driver IC45 controls the spindle motor 72 and actuator 73 based on instructions from the controller 44. Figure 7 This is a block diagram illustrating an example of the configuration of driver IC45. For example... Figure 7 As shown, the driver IC 45 has a first drive circuit 45a, a second drive circuit 45b, and a third drive circuit 45c. The first drive circuit 45a is a circuit that drives the spindle motor 72. The second drive circuit 45b is a circuit that drives the voice coil motor 74. The third drive circuit 45c is a circuit that drives the microactuator 75.

[0040] like Figure 2 As shown, the A / D conversion circuit 46 converts the analog signal input from the vibration sensor 76 into a digital signal and outputs it to the processor 41. The vibration sensor 76 is a sensor capable of detecting vibrations applied to the disk assembly 100. In this embodiment, the vibration sensor 76 is an acceleration sensor. The vibration sensor 76 can be any sensor as long as it can detect vibrations applied to the disk assembly 100.

[0041] The first volatile memory 51 and the second volatile memory 52 are semiconductor memories whose data is lost when the power supply is cut off. In this embodiment, data is temporarily recorded in the first volatile memory 51 by the buffer control unit 42b. In this embodiment, the first volatile memory 51 is DRAM (Dynamic Random Access Memory). In this embodiment, the first volatile memory 51 is used as a cache for read data read from the disk 20 and write data written to the disk 20. The second volatile memory 52 records data required for processing by various parts of the disk device 100. In this embodiment, the second volatile memory 52 is SRAM (Static Random Access Memory). The first volatile memory 51 and the second volatile memory 52 can be integrated into one volatile memory. The first volatile memory 51 can also be SRAM, SDRAM (Synchronous Dynamic Random Access Memory), FeRAM (Ferroelectric Random Access Memory), MRAM (Magnetoresistive Random Access Memory), etc. The second volatile memory 52 can also be DRAM, SDRAM, FeRAM, MRAM, etc.

[0042] The non-volatile memory 53 is a semiconductor memory that retains recorded data even when the power supply is cut off. In this embodiment, the non-volatile memory 53 is a flash memory. The non-volatile memory 53 is, for example, a NOR or NAND flash memory. At least a portion of the program for driving the disk drive 100, as well as data required before reading and writing data to the disk 20, are recorded in the non-volatile memory 53.

[0043] Figure 2The blank arrows indicate the flow of user data UD. User data UD input from host device 80 to disk device 100 is input to buffer control unit 42b via interface control unit 42a, and temporarily recorded in first volatile memory 51 by buffer control unit 42b. User data UD recorded in first volatile memory 51 is read out by buffer control unit 42b and transformed into a form that can be recorded on disk 20 in format control unit 42c. The transformed user data UD is sent to head amplifier IC 37 via read / write channel 43 and written to disk 20 from head 31. When reading user data UD recorded on disk 20 by host device 80, for example, the user data UD is read out in the reverse order of the steps described above for writing user data UD to disk 20.

[0044] Processor 41 is the CPU (Central Processing Unit) of the control disk assembly 100. Processor 41 controls actuator 73 via driver IC 45 to perform servo control for positioning head 31. Processor 41 controls spindle motor 72 via first drive circuit 45a of driver IC 45, causing disk 20 to rotate. Processor 41 controls the writing operation (write operation) of data to disk 20. Processor 41 selects the destination for saving the data written to disk 20. Processor 41 controls the reading operation (read operation) of data recorded on disk 20. Processor 41 controls the processing of data read from disk 20. Processor 41 is electrically connected to various parts of the disk assembly 100.

[0045] The processor 41 is configured to execute a first arithmetic process CP1, a second arithmetic process CP2, and a replacement process AP. That is, the control method executed by the control device 40 includes the first arithmetic process CP1, the second arithmetic process CP2, and the replacement process AP. The first arithmetic process CP1 is an arithmetic process executed to control the position θ of the head 31. The processor 41 executes servo control as a control for positioning the head 31 by executing the first arithmetic process CP1. The first arithmetic process CP1 includes multiple control processes CTP. In this embodiment, the multiple control processes CTP include a voice coil motor control process, a micro-actuator control process, a postcode control process, and a feedforward control process. The voice coil motor control process is a control process CTP that controls the voice coil motor 74. The micro-actuator control process is a control process CTP that controls the micro-actuator 75. The postcode control process is a control process CTP that corrects the position θ of the head 31 using postcode, which includes correction data such as correction data that corrects errors caused by deformation of the tracks of the disk 20. The feedforward control processing is a control processing CTP that corrects the position θ of the head 31 by feedforward control based on the output value of the vibration sensor 76.

[0046] Figure 8 This is a block diagram representing the control processing of the voice coil motor and the microactuator. For example... Figure 8 As shown, actuator 73 is controlled by feedback control based on a target value θr for the current position θ of head 31. The current position θ of head 31 is detected by position detection circuit 43b. The target value θr is input to the second drive circuit 45b and the third drive circuit 45c. The second drive circuit 45b outputs an output value such as current to the voice coil motor 74 based on the input target value θr. The third drive circuit 45c outputs an output value such as current to the micro-actuator 75 based on the input target value θr. The voice coil motor 74 and the micro-actuator 75 are driven based on the output values ​​such as current input from each drive circuit to position head 31.

[0047] The second arithmetic process CP2 is an arithmetic process that can be executed simultaneously with the first arithmetic process CP1. In this embodiment, the second arithmetic process CP2 is a process executed to improve the processing performance of the disk device 100. In this embodiment, the processor 41 can execute multiple second arithmetic processes CP2. The multiple second arithmetic processes CP2 include a process for generating digital filters used in the control of the actuator 73 that moves the head 31. The multiple second arithmetic processes CP2 include a first VCM filter generation process, a second VCM filter generation process, a first MA filter generation process, and a second MA filter generation process. The first VCM filter generation process is a process for generating one VCM filter 78va that corrects the input value input to the voice coil motor 74. The second VCM filter generation process is a process for generating two VCM filters 78va and 78vb that correct the input value input to the voice coil motor 74. The first MA filter generation process is a process for generating one MA filter 78ma that corrects the input value input to the micro-actuator 75. The second MA filter generation process is the process of generating two MA filters 78ma and 78mb that correct the input value of the opposing microactuator 75.

[0048] Figure 9 This is a block diagram illustrating the voice coil motor control process and microactuator control process during the execution of the first MA filter generation process. (Example) Figure 9 As shown, when the MA filter 78ma is generated through the first MA filter generation process, the output value from the third drive circuit 45c is input to the micro actuator 75 after being corrected by the MA filter 78ma. Figure 10 This is a block diagram illustrating the voice coil motor control process and microactuator control process after the execution of the second VCM filter generation process and the second MA filter generation process. (Example) Figure 10As shown, when two VCM filters 78va and 78vb are generated through the second VCM filter generation process, the output value from the second drive circuit 45b is input to the voice coil motor 74 after being corrected by the two VCM filters 78va and 78vb. When two MA filters 78ma and 78mb are generated through the second MA filter generation process, the output value from the third drive circuit 45c is input to the microactuator 75 after being corrected by the two MA filters 78ma and 78mb.

[0049] Table 1 shows an example of the first processing time TA [ms (microseconds)] required to complete each of the second arithmetic operations CP2 when the processor 41 executes only the second arithmetic operation CP2. The first processing time TA is the time required to complete each of the second arithmetic operations CP2 when the processor 41 can use 100% of its processing power. The first processing time TA shown in Table 1 is the information stored in a predetermined storage medium provided by the disk device 100. In this embodiment, the predetermined storage medium is non-volatile memory 53. The predetermined storage medium may also be disk 20, or it may include both non-volatile memory 53 and disk 20.

[0050] Table 1

[0051]

[0052] As shown in Table 1, the first processing time (TA) of generating the second VCM filter (78va and 78vb) is longer than the first processing time (TA) of generating the first VCM filter (78va). Similarly, the first processing time (TA) of generating the second MA filter (78ma and 78mb) is longer than the first processing time (TA) of generating the first MA filter (78ma). The first processing time (TA) of the first MA filter generation process is longer than the first processing time (TA) of the first VCM filter generation process. Finally, the first processing time (TA) of the second MA filter generation process is longer than the first processing time (TA) of the second VCM filter generation process.

[0053] Furthermore, the multiple second operation processes CP2 may also include processes other than the aforementioned process of generating digital filters. For example, the multiple second operation processes CP2 may also include processes for generating digital filters that correct the signal from the vibration sensor 76. The multiple second operation processes CP2 may also include processes for adjusting parameters used in other controls of the head 31.

[0054] The alternative processing AP is a process performed to maintain the position θ of the head 31 at a predetermined position with a lower computational load than the first processing CP1. This predetermined position can also be a range of positions. This predetermined position is any position θ maintained by the alternative processing AP performed by the processor 41. In this disclosure, "maintaining the position θ of the head 31 at a predetermined position by the alternative processing AP" simply means that the head 31 is in a state determined by the alternative processing AP performed by the processor 41.

[0055] The substitution processing AP is executed in place of the first operation processing CP1. During the execution of the substitution processing AP, the first operation processing CP1 is interrupted. The substitution processing AP only needs to maintain the position θ of the head 31 at a predetermined position. That is, it is also possible to not use the head 31, which is maintained at the predetermined position by the substitution processing AP, to write data to the disk 20 or read data from the disk 20. In this embodiment, when the head 31 is maintained at the predetermined position by the retraction processing AP1 and the pressing processing AP2, it is impossible to write data to the disk 20 or read data from the disk 20 via the head 31. When the head 31 is maintained at the predetermined position by the idle operation processing AP3 and the simplified control processing AP4, "writing data to the disk 20 and reading data from the disk 20 via the head 31" may or may not be possible.

[0056] In this embodiment, the processor 41 is configured to execute multiple alternative processing APs. The multiple alternative processing APs include a backoff processing AP1, a press processing AP2, an idle action processing AP3, and a simple control processing AP4.

[0057] The retraction process AP1 is an alternative process AP performed to fix the position θ of the head 31 by the locking mechanism 90. In the retraction process AP1, the processor 41 rotates the head assembly 30 about the second rotation axis R2 via the actuator 73, as shown. Figure 4 The locking mechanism 90 secures the head 31 as shown. Thus, the position θ of the head 31 is maintained by the locking mechanism 90 at a predetermined position where the head 31 is secured. With the head 31 secured by the locking mechanism 90, the processor 41 does not perform any processing to control the position θ of the head 31, and the position θ of the head 31 is maintained at the predetermined position. That is, the backoff processing AP1 is an alternative processing AP that can maintain the position θ of the head 31 at the predetermined position without incurring computational load in the processor 41. Therefore, by using the backoff processing AP1, the position θ of the head 31 can be maintained at the predetermined position with a lower computational load than the first processing CP1.

[0058] Pressing process AP2 is an alternative process AP performed to control the head assembly 30 to contact the stop member 91. In pressing process AP2, the processor 41 rotates the head assembly 30 about the second rotation axis R2 via the actuator 73, as shown below. Figure 5 The head assembly 30 is brought into contact with the stop member 91 as shown. In the pressing process AP2, the processor 41 controls the head assembly 30 to maintain contact with the stop member 91. Thus, the position θ of the head 31 is maintained at a predetermined position where the head assembly 30 contacts the stop member 91. When controlled in such a way that the head assembly 30 contacts the stop member 91, the computational load on the processor 41 is lower than when the head assembly 30 is controlled at a specific position where it does not contact other components in the circumferential direction about the second rotation axis R2. Therefore, by using the pressing process AP2, the position θ of the head 31 can be maintained at a predetermined position with a lower computational load than the first computational process CP1.

[0059] Idle Action Processing AP3 is a substitute processing AP executed to control the position θ of head 31 with a sampling period longer than that of the first operational processing CP1. In Idle Action Processing AP3, only the voice coil motor 74 in actuator 73 is controlled, and the micro-actuator 75 is not controlled. Idle Action Processing AP3 is the same as the first operational processing CP1 except that the sampling period is longer than that of the first operational processing CP1 and the micro-actuator 75 is not controlled. In Idle Action Processing AP3, since the position θ of head 31 is controlled, head 31 is maintained at a predetermined position. In Idle Action Processing AP3, the position θ of head 31 is maintained at the position of head 31 when switching from the first operational processing CP1 to Idle Action Processing AP3. Compared with the first operational processing CP1, Idle Action Processing AP3 has a longer sampling period and the micro-actuator 75 is not controlled, so the computational load of processor 41 when executing Idle Action Processing AP3 is smaller than that when executing the first operational processing CP1. Therefore, by using the idle operation processing AP3, the position of head 31 can be maintained at the predetermined position with a lower computational load than the first operation processing CP1.

[0060] The simplified control process AP4 is an alternative process AP executed to control the position θ of the head 31 without executing at least one of the multiple control processes CTP. In the simplified control process AP4, at least one of the multiple control processes CTP included in the first arithmetic process CP1 is not executed. The simplified control process AP4 is the same as the first arithmetic process CP1 except that it does not execute at least one control process CTP. In the simplified control process AP4 of this embodiment, the microactuator control process, the postcode control process, and the feedforward control process described above are not executed. Furthermore, in the simplified control process AP4, it is sufficient to not execute at least one of the multiple control processes CTP; more than one of the microactuator control process, the postcode control process, and the feedforward control process may also be executed. In the simplified control process AP4, since the position θ of the head 31 is controlled, the head 31 is maintained at a predetermined position. In the simplified control process AP4, the position θ of the head 31 is maintained at the position where the head 31 was when switching from the first arithmetic process CP1 to the simplified control process AP4. Since at least one control process CTP is not executed, the computational load on processor 41 is smaller when the simplified control process AP4 is executed than when the first operation process CP1 is executed. Therefore, by using the simplified control process AP4, the position θ of head 31 can be maintained at a predetermined position with a lower computational load than the first operation process CP1.

[0061] The time required to maintain the position θ of head 31 at the predetermined position by substitution processing AP, replacing the first operation processing CP1, is the second processing time TB. The time required to restart the first operation processing CP1, which was interrupted by the execution of substitution processing AP, is the third processing time TC.

[0062] Table 2 is an example of the second processing time TB [ms] and the third processing time TC [ms] under each substitution processing AP. Table 2 also shows an example of the first processing occupancy k1 of the processor 41 required to perform the first arithmetic processing CP1 and an example of the second processing occupancy k2 of the processor 41 required to maintain the position θ of the head 31 through the substitution processing AP. The second processing time TB, the third processing time TC, the first processing occupancy k1, and the second processing occupancy k2 shown in Table 2 are information stored in the non-volatile memory 53, which is a predetermined storage medium.

[0063] Table 2

[0064]

[0065] As shown in Table 2, in the backoff process AP1, the second processing time TB is longer than other alternative processing APs because the head 31 needs to be moved to the locking mechanism 90. Furthermore, in order to restart the first operation process CP1, which was interrupted by the backoff process AP1, the head 31 needs to be moved from the locking mechanism 90 to a position opposite to the disk 20, resulting in a longer third processing time TC compared to other alternative processing APs. On the other hand, in the backoff process AP1, after the head 31 is fixed by the locking mechanism 90, it is possible to maintain the head 31 in a predetermined position without performing processor-based operations, thus the second processing occupancy k2 is zero.

[0066] In the pressing process AP2, the head assembly 30 needs to be moved to the position where it contacts the stop 91. Therefore, the second processing time TB is longer than that in the idle operation process AP3 and the simplified control process AP4. On the other hand, the time required to move the head assembly 30 to the position where it contacts the stop 91 is shorter than the time required to move the head 31 to the locking mechanism 90. Therefore, the second processing time TB in the pressing process AP2 is shorter than that in the retraction process AP1. For the same reason, in the pressing process AP2, the third processing time TC is longer than that in the idle operation process AP3 and the simplified control process AP4, and shorter than that in the retraction process AP1. In the pressing process AP2, since the control to make the head assembly 30 contact the stop 91 needs to be executed, the processor 41 needs to perform some degree of computation. Therefore, the second processing occupancy rate k2 in the pressing process AP2 is higher than that in the retraction process AP1. On the other hand, in the pressing process AP2, since it is only necessary to make the head assembly 30 contact the stop 91, the second process has a lower occupancy rate k2 compared with the idle action process AP3 and the simple control process AP4, which control the position θ of the head 31 to some extent.

[0067] In the idle motion processing AP3 and the simplified control processing AP4, since some degree of control over the position θ of head 31 is required, the second processing occupancy rate k2 is higher compared to the retreat processing AP1 and the pressing processing AP2. On the other hand, in the idle motion processing AP3 and the simplified control processing AP4, since it is not necessary to move head 31 from its current position to a different position, the second processing time TB and the third processing time TC are shorter compared to the retreat processing AP1 and the pressing processing AP2. In the examples in Table 2, the second processing occupancy rate k2 under the idle motion processing AP3 is lower than that under the simplified control processing AP4. In the examples in Table 2, the second processing time TB under the idle motion processing AP3 is longer than that under the simplified control processing AP4. In the examples in Table 2, the third processing time TC under the idle motion processing AP3 is longer than that under the simplified control processing AP4.

[0068] The second processing utilization rate k2 of each alternative processing AP is lower than the first processing utilization rate k1 of the first processing CP1. In the example of Table 2, the first processing utilization rate k1 of the first processing CP1 is 0.75. Furthermore, for each processing utilization rate in the examples of Table 2, a value of 1 indicates that the processing utilization rate of processor 41 is 100%. That is, when the first processing utilization rate k1 is 0.75, the processing utilization rate of processor 41 when executing the first processing CP1 is 75%. The first processing utilization rate k1 and the second processing utilization rate k2 are not limited to the examples of Table 2 and are not particularly limited. The first processing utilization rate k1 and the second processing utilization rate k2 are both less than 1.

[0069] The control device 40 is configured to determine whether to execute the second operation processing CP2 if the processing performance (throughput) of the disk drive 100 is lower than a predetermined performance value. In this embodiment, the determination of whether to execute the second operation processing CP2 is performed by the processor 41. That is, the processor 41 is configured to determine whether to execute the second operation processing CP2 if the processing performance of the disk drive 100 is lower than a predetermined performance value. Alternatively, the determination of whether to execute the second operation processing CP2 may be performed by a part other than the processor 41 in the control device 40. The processing performance of the disk drive 100 is represented, for example, by the amount of data that the disk drive 100 can process per unit time. The amount of data that the disk drive 100 can process per unit time is, for example, IOPS (Input / Output Per Second), which is a performance indicator of the disk drive 100. The processor 41 calculates the IOPS of the disk drive 100 based on the amount of data written to the disk 20 per unit time according to the instructions from the host device 80, and the amount of data read from the disk 20 per unit time according to the instructions from the host device 80. Therefore, the processor 41 measures the processing performance of the disk drive 100. If the calculated IOPS is lower than a predetermined threshold, the processor 41 determines that the processing performance of the disk drive 100 is lower than the predetermined performance value, and decides to execute the second operation, CP2. The predetermined threshold is not specifically defined.

[0070] The processing performance of the disc assembly 100 is reduced due to factors such as "increased time required for position control of the head 31 caused by interference such as vibration applied to the disc assembly 100". The processor 41 determines which of a plurality of second operation processes CP2 to execute based on the degree of reduction in the processing performance of the disc assembly 100, the period and magnitude of the vibration applied to the disc assembly 100. For example, when the period of the vibration applied to the disc assembly 100 is short, it is necessary to move the head 31 quickly for adjustment. In this case, the processor 41 determines to execute a second operation process CP2 that corrects the control of the microactuator 75, which can move the head 31 faster than the voice coil motor 74. That is, the processor 41 determines to execute either the first MA filter generation process or the second MA filter generation process.

[0071] The control device 40 is configured to execute the first decision process DP1. That is, the control method executed by the control device 40 includes the first decision process DP1. In this embodiment, the first decision process DP1 is executed by the processor 41. That is, the processor 41 is configured to execute the first decision process DP1. Alternatively, the first decision process DP1 may be executed by a component other than the processor 41 in the control device 40. Alternatively, the control device 40 may have a dedicated arithmetic unit that executes the first decision process DP1. Alternatively, the control device 40 may have a processor independent of the processor 41, and the first decision process DP1 may be executed by this processor independent of the processor 41. This processor independent of the processor 41 may, for example, be a neural network processor.

[0072] The first decision process DP1 is a process executed based on information stored in a predetermined storage medium, namely, information stored in non-volatile memory 53, when it is determined that the second operation process CP2 will be executed. The first decision process DP1 includes obtaining a first execution time TE1, expressed as TA / (1-k1), and a second execution time TE2, expressed as {TA / (1-k2)}+TB+TC, based on the information stored in the non-volatile memory 53, which is the predetermined storage medium. The first execution time TE1 and the second execution time TE2 may also be pre-stored in the non-volatile memory 53. In this case, in the first decision process DP1, the processor 41 obtains the first execution time TE1 and the second execution time TE2 from the non-volatile memory 53. Alternatively, in the first decision process DP1, the processor 41 may calculate the first execution time TE1 and the second execution time TE2 using the information stored in the non-volatile memory 53. The first execution time TE1 is the time obtained by dividing the value obtained by subtracting the first processing occupancy rate k1 from 1 by the first processing time TA. The first execution time TE1 is the time from the start of the second operation CP2 during the execution of the first operation CP1 until the completion of the second operation CP2. The second execution time TE2 is the time obtained by dividing the first processing time TA by the value obtained by subtracting the second processing occupancy k2 from 1, the second processing time TB, and the third processing time TC. The second execution time TE2 is the time from the start of replacing the first operation CP1 with processing AP until the first operation CP1 starts again.

[0073] The first determination process DP1 includes: when the second execution time TE2 is greater than or equal to the first execution time TE1, selecting a first execution method EM1 that executes the first operation process CP1 and the second operation process CP2 simultaneously as the method for executing the second operation process CP2. The first determination process DP1 also includes: when the second execution time TE2 is shorter than the first execution time TE1, selecting a second execution method EM2 that executes the second operation process CP2 after replacing the first operation process CP1 and starting the execution of the replacement process AP. In this embodiment, the second execution method EM2 is a method that replaces the first operation process CP1 by maintaining the position θ of the head 31 at a predetermined position by replacing the process AP before executing the second operation process CP2.

[0074] The first decision process DP1 includes: when multiple second execution times TE2, when multiple alternative processing APs are used respectively, are all greater than or equal to the first execution time TE1, selecting the first execution method EM1. The first decision process DP1 also includes: when at least one of the multiple second execution times TE2, when multiple alternative processing APs are used respectively, is shorter than the first execution time TE1, selecting the second execution method EM2 of the alternative processing AP with the shortest second execution time TE2.

[0075] Figure 11 This is a coordinate graph illustrating an example of the relationship between the first execution time TE1 and the second execution time TE2 for each of the alternative processes AP, and the first processing time TA. Figure 11 In the diagram, the horizontal axis represents the first processing time TA [ms], and the vertical axis represents the first execution time TE1 [ms] or the second execution time TE2 [ms]. Figure 11 The straight line representing the first execution time TE1 is represented by TE1 = TA / (1-k1). Figure 11 The lines representing the second execution time TE2 are represented by TE2={TA / (1-k2)}+TB+TC. Figure 11 The straight lines shown, representing each execution time, are based on the values ​​recorded in Table 2.

[0076] exist Figure 11In the example, when the first processing time TA of the second operation processing CP2 is 100 [ms], the second execution time TE2 of each operation is shorter than the first execution time TE1. Therefore, in the first decision processing DP1, the processor 41 selects a second execution method EM2 that uses a certain alternative processing AP. Furthermore, when the first processing time TA of the second operation processing CP2 is 100 [ms], the second execution time TE2 using the pressing processing AP2 among the multiple alternative processing APs is the shortest. Therefore, in the first decision processing DP1, the processor 41 selects the second execution method EM2 that uses the pressing processing AP2. Figure 11 In the example, when the first processing time TA of the second operation processing CP2 is 30 [ms], the second execution time TE2 of each operation except the second execution time TE2 of the backoff processing AP1 is shorter than the first execution time TE1. Therefore, in the first decision processing DP1, the processor 41 selects the second execution method EM2, which uses the alternative processing AP other than the backoff processing AP1. Furthermore, when the first processing time TA of the second operation processing CP2 is 30 [ms], the second execution time TE2 of the multiple alternative processing APs using the idle action processing AP3 is the shortest. Therefore, in the first decision processing DP1, the processor 41 selects the second execution method EM2, which uses the idle action processing AP3.

[0077] The first determination process DP1 includes sending a signal to the host device 80, which sends instructions to the disk device 100, inquiring whether the second execution method EM2 can be executed, when the second execution method EM2 is selected. In this embodiment, the signal inquiring whether the second execution method EM2 can be executed includes information about the second execution time TE2. For example, if the processor 41 has a first processing time TA of the second operation processing CP2 of 30 [ms] and has selected the second execution method EM2 using idle action processing AP3, it sends information that the second execution time TE2 is 70 [ms] to the host device 80. The first determination process DP1 includes determining whether to execute the second execution method EM2 based on the signal from the host device 80. The host device 80 sends a signal indicating whether the second execution method EM2 can be executed to the control device 40 based on the signal sent from the processor 41. The host device 80 determines whether the second execution method EM2 can be executed, for example, based on the content and number of instructions sent to the disk device 100.

[0078] The processor 41 is configured to execute the second execution method EM2 if, in the first determination process DP1, it is determined based on a signal from the host device 80 that the second execution method EM2 can be executed. That is, the control method executed by the control device 40 includes executing the second execution method EM2 if, in the first determination process DP1, it is determined based on a signal from the host device 80 that the second execution method EM2 can be executed. The processor 41 is also configured to execute the first execution method EM1 if, in the first determination process DP1, it is determined based on a signal from the host device 80 that the second execution method EM2 cannot be executed. That is, the control method executed by the control device 40 includes executing the first execution method EM1 if, in the first determination process DP1, it is determined based on a signal from the host device 80 that the second execution method EM2 cannot be executed.

[0079] The control device 40 is configured to execute the second decision process DP2. That is, the control method executed by the control device 40 includes the second decision process DP2. In this embodiment, the second decision process DP2 is executed by the processor 41. That is, the processor 41 is configured to execute the second decision process DP2. Alternatively, the second decision process DP2 may be executed by a part of the control device 40 other than the processor 41. Alternatively, the control device 40 may have a dedicated arithmetic unit that executes the second decision process DP2. Alternatively, the control device 40 may have a processor independent of the processor 41, and the second decision process DP2 may be executed by this processor independent of the processor 41. This processor independent of the processor 41 may, for example, be a neural network processor.

[0080] The second determination process DP2 is performed while the second execution method EM2 is being executed. The second determination process DP2 includes determining whether the time required for the completion of the second execution method EM2 is longer than the second execution time TE2 notified to the host device 80. In the second determination process DP2, for example, after a predetermined proportion of the second execution time TE2 of the currently executing second execution method EM2 has elapsed, the processor 41 estimates the remaining time until the completion of the second execution method EM2. The processor 41 estimates this remaining time based on the elapsed time and the proportion of processing completed so far. In the second determination process DP2, the processor 41 determines, based on the estimated remaining time, whether the time required for the completion of the second execution method EM2 is longer than the second execution time TE2. This predetermined proportion is, for example, approximately 70% to 90%. The value of this predetermined proportion is not particularly limited.

[0081] The processor 41 is configured to terminate the second execution method EM2 and execute the first execution method EM1 if the second determination process DP2 determines that the time required to complete the second execution method EM2 is longer than the second execution time TE2. That is, the control method executed by the control device 40 includes terminating the second execution method EM2 and executing the first execution method EM1 if the second determination process DP2 determines that the time required to complete the second execution method EM2 is longer than the second execution time TE2. If the second determination process DP2 determines that the time required to complete the second execution method EM2 is longer than the second execution time TE2, the processor 41 notifies the host device 80 of the termination of the second execution method EM2 and the execution of the first execution method EM1. Furthermore, in this case, the processor 41 notifies the host device 80 of the determination that the second operation process CP2 will not complete within the notified second execution time TE2, i.e., that the execution of the second operation process CP2 within the notified second execution time TE2 has failed. The processor 41 is configured to continue executing the second execution method EM2 if, during the second determination process DP2, it is determined that the time required for the completion of the second execution method EM2 is within the second execution time TE2. Upon completion of the second execution method EM2, the processor 41 immediately notifies the host device 80 of the completion of the second execution method EM2, regardless of whether the second execution time TE2 for notification to the host device 80 has elapsed.

[0082] The control device 40 is configured to calculate the actual processing time (APT) as the time required to complete the second operation processing CP2 after it has been completed. This APT is then converted into the time required to complete the second operation processing CP2 if the processor 41 has only executed the second operation processing CP2. In this embodiment, the calculation of the actual processing time APT is performed by the processor 41. That is, the processor 41 is configured to calculate the actual processing time (APT) as the time required to complete the second operation processing CP2 after it has been completed, and this APT is then converted into the time required to complete the second operation processing CP2 if the processor 41 has only executed the second operation processing CP2. Alternatively, the calculation of the actual processing time APT can be performed by a component other than the processor 41 in the control device 40. Alternatively, the control device 40 may have a dedicated arithmetic unit, which performs the calculation of the actual processing time APT. Alternatively, the control device 40 may have a processor independent of the processor 41, through which the actual processing time (APT) is calculated. This processor independent of the processor 41 may be, for example, a neural network processor.

[0083] For example, in the idle action processing AP3 shown in Table 2, the second processing occupancy k2 is 0.5. Therefore, when the second operation processing CP2 is completed using the second execution method EM2 of the idle action processing AP3, the processing time is twice as long as when the processor 41 only executes the second operation processing CP2. Therefore, the processor 41 multiplies the time required to complete the second operation processing CP2 by 0.5 to calculate the actual processing time APT.

[0084] The control device 40 is configured to update the first processing time TA stored in the non-volatile memory 53 to the actual processing time APT when the actual processing time APT is longer than the first processing time TA stored in the non-volatile memory 53. In this embodiment, the determination and update process of whether the first processing time TA has been updated is performed by the processor 41. That is, the processor 41 is configured to update the first processing time TA stored in the non-volatile memory 53 to the actual processing time APT when the actual processing time APT is longer than the first processing time TA stored in the non-volatile memory 53. Alternatively, the determination and update process of whether the first processing time TA has been updated can also be performed by a part other than the processor 41 in the control device 40. Alternatively, the control device 40 may have a dedicated arithmetic unit, which performs the determination and update process of whether the first processing time TA has been updated. Alternatively, the control device 40 may have a processor independent of the processor 41, which performs the determination and update process of whether the first processing time TA has been updated. The processor independent of processor 41 could also be, for example, a neural network processor.

[0085] The control device 40 is configured not to update the first processing time TA stored in the non-volatile memory 53 when the actual processing time APT is less than or equal to the first processing time TA stored in the non-volatile memory 53. That is, the processor 41 is configured not to update the first processing time TA stored in the non-volatile memory 53 when the actual processing time APT is less than or equal to the first processing time TA stored in the non-volatile memory 53.

[0086] The control device 40 is configured such that, upon completion of the second arithmetic operation CP2, when the actual processing time APT is longer than the first processing time TA stored in the non-volatile memory 53, the difference between the actual processing time APT and the first processing time TA is stored in the non-volatile memory 53. In this embodiment, the process of storing the difference in the non-volatile memory 53 is executed by the processor 41. That is, the processor 41 is configured such that, upon completion of the second arithmetic operation CP2, when the actual processing time APT is longer than the first processing time TA stored in the non-volatile memory 53, the difference between the actual processing time APT and the first processing time TA is stored in the non-volatile memory 53. Alternatively, the process of storing this difference in the non-volatile memory 53 can also be executed by a component other than the processor 41 in the control device 40. Alternatively, the control device 40 may have a dedicated arithmetic unit, which executes the process of storing the difference in the non-volatile memory 53. Alternatively, the control device 40 may have a processor independent of the processor 41, through which the process of storing the differential time in the non-volatile memory 53 is executed. This processor independent of the processor 41 may also be, for example, a neural network processor.

[0087] For example, when the first MA filter generation process is executed as the second operation process CP2, the actual processing time APT is set to 120 [ms]. If the first processing time TA of the first MA filter generation process stored in the non-volatile memory 53 is set to 100 [ms] as shown in Table 1, then the actual processing time APT is longer than the first processing time TA. In this case, the processor 41 updates the first processing time TA of the first MA filter generation process stored in the non-volatile memory 53 from 100 [ms] to 120 [ms]. Furthermore, in this case, the processor 41 stores 20 [ms] as the difference between the actual processing time APT and the first processing time TA in the non-volatile memory 53. This difference time is stored in the non-volatile memory 53 for each second operation process CP2. For example, when storing this difference time, if the difference time of the second operation process CP2 has already been stored, the processor 41 updates the difference time if the difference time to be stored is longer than the already stored difference time. Processor 41 can also process CP2 in each second operation, so that multiple differential times are stored in non-volatile memory 53.

[0088] Figure 12 This is a flowchart representing a part of the process performed by the control device 40. Figure 13 This is a flowchart illustrating another part of the processing performed by the control device 40. In this embodiment, the control device 40 executes the processing via the processor 41. Figure 12 and Figure 13The processing is shown. (As shown in the image.) Figure 12 As shown, processor 41 starts the first operation processing CP1 based on instructions from host device 80 (step S110). The position θ of control head 31 is thus determined by the first operation processing CP1. When starting the first operation processing CP1, processor 41 determines whether the processing performance of disk device 100 is lower than a predetermined performance value (step S120). In step S120, processor 41 makes this determination by comparing the IOPS of disk device 100 calculated as described above with a predetermined threshold. If processor 41 determines in step S120 that the processing performance of disk device 100 is above the predetermined performance value (step S120: No), it continues with the first operation processing CP1. If processor 41 determines in step S120 that the processing performance of disk device 100 is lower than the predetermined performance value (step S120: Yes), it decides to execute the second operation processing CP2, selecting the second operation processing CP2 to be executed from among multiple second operation processing CP2s (step S130). In step S130, processor 41 determines the second operation to be executed, CP2, as described above.

[0089] After deciding on the second operation CP2 to be executed, processor 41 determines whether the first execution time TE1 is longer than the second execution time TE2 when executing the decided second operation CP2 (step S140). Processor 41 is based on Figure 11 The processor 41 determines the relationship between the first execution time TE1 and the second execution time TE2 and the first processing time TA as shown in step S140. In step S140, the processor 41 refers to the first execution time TE1 and the second execution time TE2 corresponding to the first processing time TA of the determined second operation processing CP2, and determines whether the first execution time TE1 is longer than the second execution time TE2 in the case of executing each substitute processing AP. If the processor 41 determines in step S140 that the first execution time TE1 is less than or equal to each second execution time TE2 (step S140: No), the processor 41 executes the first execution method EM1 (step S180). That is, if the processor 41 determines in step S140 that the first execution time TE1 is less than or equal to each second execution time TE2, the processor 41 executes the first operation processing CP1 as is while executing the second operation processing CP2. The first execution method EM1 is executed until the second operation processing CP2 is completed. After the second operation CP2 is completed and the first execution method EM1 ends, the processor 41 continues to execute the first operation CP1 as is.

[0090] If, in step S140, the processor 41 determines that the first execution time TE1 is longer than each of the second execution times TE2 (step S140: Yes), it decides to execute the second execution method EM2 and selects to replace the processing AP (step S150). In step S150, the processor 41, based on... Figure 11 The information shown indicates that the alternative process AP with the shortest second execution time TE2 is selected when the selected second operation process CP2 is executed.

[0091] After selecting an alternative processing AP, the processor 41 sends a signal to the host device 80 inquiring whether the second execution method EM2 using the selected alternative processing AP can be executed (step S160). Upon receiving this signal, the host device 80, based on the current data processing status, sends a signal to the disk device 100 indicating whether the processor 41 can execute the second execution method EM2. The processor 41 determines whether the second execution method EM2 can be executed based on the signal sent from the host device 80 (step S170). In step S170, if the signal sent from the host device 80 indicates that the second execution method EM2 can be executed, the processor 41 determines that the second execution method EM2 can be executed (step S170: Yes). In step S170, if the signal sent from the host device 80 indicates that the second execution method EM2 cannot be executed, the processor 41 determines that the second execution method EM2 cannot be executed (step S170: No).

[0092] If processor 41 determines in step S170 that the second execution method EM2 cannot be executed (step S170: No), it does not execute the second execution method EM2, but executes the first execution method EM1 instead (step S180). If processor 41 determines in step S170 that the second execution method EM2 can be executed (step S170: Yes), it starts the second execution method EM2 (step S190). In this embodiment, steps S140 to S170 are an example of the steps of the first determination process DP1 described above.

[0093] like Figure 13As shown, after starting the second execution method EM2, the processor 41 determines whether a predetermined time has elapsed since the start of the second execution method EM2 (step S200). The predetermined time is a predetermined proportion of the second execution time TE2 as described above. For example, if the second execution time TE2 is 200 [ms] and the predetermined proportion is 80%, the predetermined time is 160 [ms]. If the processor 41 determines in step S200 that no predetermined time has elapsed since the start of the second execution method EM2 (step S200: No), the second execution method EM2 continues as is. If the processor 41 determines in step S200 that a predetermined time has elapsed since the start of the second execution method EM2 (step S200: Yes), it determines whether the processing of the second execution method EM2 will be completed within the second execution time TE2 (step S210).

[0094] In step S210, the processor 41 estimates the remaining time until the completion of the second execution method EM2 based on the elapsed time and the proportion of processing completed so far, and makes a determination based on this estimated remaining time. If the processor 41 determines in step S210 that the second execution method EM2 will be completed within the second execution time TE2 (step S210: Yes), it continues to execute the second execution method EM2 (step S220), and determines whether the second operation processing CP2 has been completed (step S230). In this embodiment, steps S200 and S210 are an example of the steps of the second determination processing DP2 described above.

[0095] If processor 41 determines in step S230 that the second operation processing CP2 has not been completed (step S230: No), it continues to execute the second execution method EM2. If processor 41 determines in step S230 that the second operation processing CP2 has been completed (step S230: Yes), it restarts the first operation processing CP1 (step S240). While executing the second execution method EM2, a third processing time TC corresponding to the executed alternative processing AP is spent until the first operation processing CP1 is restarted. By restarting the first operation processing CP1, the second execution method EM2 is completed. When the second execution method EM2 is completed, processor 41 sends a signal indicating "the second execution method EM2 is completed" to the host device 80. The signal indicating "the second execution method EM2 is completed" includes information indicating "the second operation processing CP2 is completed".

[0096] After restarting the first operation processing CP1, the processor 41 calculates the actual processing time APT (step S250). The processor 41 determines whether the calculated actual processing time APT is longer than the first processing time TA stored in the non-volatile memory 53 as the processing time of the executed second operation processing CP2 (step S260). If the actual processing time APT is less than or equal to the first processing time TA (step S260: No), the processor 41 does not save the actual processing time APT and continues to perform the first operation processing CP1 (step S330). If the actual processing time APT is longer than the first processing time TA (step S260: Yes), the processor 41 updates the first processing time TA stored in the non-volatile memory 53 to the actual processing time APT (step S270). In addition, in step S270, the processor 41 stores the difference between the first processing time TA before the update and the actual processing time APT in the non-volatile memory 53. After updating the first processing time TA and saving the differential time, processor 41 continues to perform the first operation processing CP1 (step S330). In addition, processor 41 may also perform the processing of steps S240 to S270 during the period before the first operation processing CP1 starts again, or it may perform the processing of steps S240 to S270 before starting the process of restarting the first operation processing CP1.

[0097] If, in step S210, the processor 41 determines that the second execution method EM2 will not be completed within the second execution time TE2 (step S210: No), it terminates the second execution method EM2 and starts the first execution method EM1 (step S280). In step S280, the processor 41 spends a third processing time TC corresponding to the executed second execution method EM2 to restart the first operation processing CP1, and continues to execute the second operation processing CP2 while executing the first operation processing CP1. In step S280, the processor 41 sends signals indicating that the second execution method EM2 has been terminated and that the second operation processing CP2 cannot be completed within the notified time to the host device 80. The processor 41 executes the first execution method EM1 while determining whether the second operation processing CP2 has been completed (step S290).

[0098] If processor 41 determines in step S290 that the second operation processing CP2 has not been completed (step S290: No), it continues with the first execution method EM1. If processor 41 determines in step S290 that the second operation processing CP2 has been completed (step S290: Yes), it calculates the actual processing time APT (step S300). Since the first operation processing CP1 and the second operation processing CP2 are executed simultaneously in the first execution method EM1, processor 41 resumes the normal processing of the first operation processing CP1 upon completion of the second operation processing CP2.

[0099] When the method for executing the second operation processing CP2 is switched from the second execution method EM2 to the first execution method EM1, the processor 41 calculates the actual processing time APT according to the following steps: The processor 41 converts the time spent executing the second operation processing CP2 in the second execution method EM2 into the time required if the processor 41 only executes the second operation processing CP2. The processor 41 converts the time spent executing the second operation processing CP2 in the first execution method EM1 into the time required if the processor 41 only executes the second operation processing CP2. The processor 41 adds up the converted times for the second operation processing CP2 executed in each execution method to calculate the actual processing time APT.

[0100] Processor 41 determines whether the calculated actual processing time APT is longer than the first processing time TA stored in non-volatile memory 53 as the processing time of the second operation CP2 being performed (step S310). If the actual processing time APT is less than or equal to the first processing time TA (step S310: No), processor 41 does not save the actual processing time APT and continues performing the first operation CP1 (step S330). If the actual processing time APT is longer than the first processing time TA (step S310: Yes), processor 41 updates the first processing time TA stored in non-volatile memory 53 to the actual processing time APT (step S320). In addition, in step S320, processor 41 stores the difference between the first processing time TA before the update and the actual processing time APT in non-volatile memory 53. After updating the first processing time TA and saving the difference, processor 41 also continues performing the first operation CP1 (step S330).

[0101] After step S330, the processor 41 also performs the determination of step S120 above at all times or periodically during the execution of the first operation processing CP1. If it is determined that the second operation processing CP2 needs to be performed, the second operation processing CP2 is executed again in the same manner as the above steps.

[0102] Furthermore, in this embodiment, step S210 determines whether the processing of the second execution method EM2 will end within the second execution time TE2. Therefore, if the second execution method EM2 continues after step S210, there is a high probability that the actual processing time APT is less than or equal to the first processing time TA stored in the non-volatile memory 53. However, by comparing the actual processing time APT with the stored first processing time TA in step S260, the first processing time TA can be updated if the time required for the second operation processing CP2 becomes longer than expected for some reason. In addition, if the second execution method EM2 is switched to the first execution method EM1 after step S210, there is a high probability that the actual processing time APT is longer than the first processing time TA stored in the non-volatile memory 53. However, by comparing the actual processing time APT with the stored first processing time TA in step S310, the first operation processing CP1 can continue without performing unnecessary processing if the time required for the second operation processing CP2 becomes shorter than expected for some reason.

[0103] Figure 14 This is a coordinate graph illustrating an example of the change in processing performance of the disk device 100 when the second operation processing CP2 is executed by the first execution method EM1 and the second execution method EM2, respectively. Figure 14 In the diagram, the horizontal axis represents time t, and the vertical axis represents the IOPS (Input / Output Per Second) of the disk device 100. Figure 14 The double-dotted line in the figure represents the change in IOPS when the second operation CP2 is processed through the first execution method EM1. Figure 14 The solid line in the figure represents the change in IOPS when the second operation CP2 is performed by the second execution method EM2. Figure 14 As an example of the case where the second operation processing CP2 is performed by the second execution method EM2, an example is shown where the second operation processing CP2 is started when it is determined at time t1 that the IOPS of the disk device 100 is lower than the predetermined threshold Ps. Figure 14 The second execution time TE2 under the second execution method EM2 shown is compared to Figure 14 The first execution time TE1 of the first execution method EM1 shown is short.

[0104] exist Figure 14 In the above, the IOPS of disk device 100 at time t1 is a value P1 lower than the threshold Ps. Figure 14In the example, when the second operation CP2 is executed by the first execution method EM1, the second operation CP2 is completed at time t3, which is later than time t1, and the IOPS of the disk device 100 becomes a value P2 that is higher than the threshold Ps. When the second operation CP2 is executed by the first execution method EM1, the IOPS of the disk device 100 remains at the value P1 from time t1 to time t3.

[0105] exist Figure 14 In the example, when the second operation CP2 is executed via the second execution method EM2, since data writing and reading via the head 31 cannot be performed when the second operation CP2 begins, the IOPS of the disk device 100 becomes zero at time t1. In the second execution method EM2, since the computational load for maintaining the position θ of the head 31 at the predetermined position is lower than that of the first operation CP1, the second operation CP2 is processed faster than in the first execution method EM1. Therefore, in Figure 14 In the example, when the second operation processing CP2 is performed by the second execution method EM2, the second operation processing CP2 is completed at time t2, which is later than time t1 and earlier than time t3, and the IOPS of the disk device 100 becomes a value P2 that is higher than the threshold Ps. Figure 14 In the example, when executing the second execution method EM2, although the IOPS of the disk device 100 becomes zero during the execution of the second operation processing CP2, the IOPS of the disk device 100 can be improved to a value P2 higher than the threshold Ps more quickly compared to the case of executing the first execution method EM1. Furthermore, when the IOPS of the disk device 100 is zero, there is no response from the disk device 100 to the host device 80.

[0106] The control method in this embodiment is performed by the control device 40 described above. At least a portion of the function of the control device 40 is implemented, for example, by the processor 41 executing a program, i.e., software, stored on the disk 20 or non-volatile memory 53. This program is a program that causes the control device 40, which functions as a computer, to execute the control method of this embodiment. Furthermore, at least a portion of the function of the control device 40 can be implemented, for example, by hardware including circuitry such as LSI (Large Scale Integration), ASIC (Application Specific Integrated Circuit), FPGA (Field-Programmable Gate Array), and GPU (Graphics Processing Unit), or by a combination of software and hardware. The control device 40 can be composed of multiple devices.

[0107] The medium storing the program that enables the control device 40, which functions as a computer, to execute the control method of this embodiment is not particularly limited, and can be a storage medium other than the disk 20 or the non-volatile memory 53. The storage medium storing the program can be a different storage medium from the predetermined storage medium storing the first processing time TA, the second processing time TB, the third processing time TC, the first processing utilization rate k1, and the second processing utilization rate k2. The storage medium storing the program can also be other storage media provided with the disk drive 100, or it can be a storage medium provided independently of the disk drive 100. Examples of such storage media include floppy disks, optical disks, RAM (Random Access Memory), ROM (Read Only Memory), CD-ROMs, HDDs (hard disk drives), SSDs (Solid State Drives), and flash memory. The program that enables the control device 40, which functions as a computer, to execute the control method of this embodiment can also be sent to the control device 40 via an electrical communication line. The predetermined storage medium for storing the first processing time TA, the second processing time TB, the third processing time TC, the first processing occupancy k1, and the second processing occupancy k2 can also be a storage medium other than disk 20 and non-volatile memory 53. This predetermined storage medium can also be a storage medium disposed externally to disk device 100. In this case, disk device 100 can communicate with the predetermined storage medium via an electrical communication line and obtain various information from the storage medium.

[0108] According to this embodiment, the control device 40 is a control device for the control disk device 100. The control device 40 includes a processor 41. The disk device 100 is configured to execute a first determination process DP1. The processor 41 is configured to execute a first arithmetic process CP1 to control the position θ of the head 31 of the disk device 100. The processor 41 is configured to execute a second arithmetic process CP2 that can be executed simultaneously with the first arithmetic process CP1. The processor 41 is configured to execute a substitution process AP to maintain the position θ of the head 31 at a predetermined position with a lower computational load than the first arithmetic process CP1. The first determination process DP1 is a process executed based on information stored in the non-volatile memory 53 (a predetermined storage medium) when it is determined that the second arithmetic process CP2 will be executed. The information stored in the non-volatile memory 53 includes a first processing time TA required until the second arithmetic process CP2 is completed when the processor 41 only executes the second arithmetic process CP2. The information stored in the non-volatile memory 53 includes a second processing time TB required to maintain the position θ of the head 31 at a predetermined position by the substitution process AP in place of the first arithmetic process CP1. The information stored in the non-volatile memory 53 includes a third processing time TC required to restart the first arithmetic process CP1, which was interrupted by the execution of the substitution process AP. The information stored in the non-volatile memory 53 includes a first processing occupancy k1 of the processor 41 required to execute the first arithmetic process CP1. The information stored in the non-volatile memory 53 includes a second processing occupancy k2 of the processor 41 required to maintain the position θ of the head 31 by the substitution process AP. The first decision process DP1 includes: based on the information stored in the non-volatile memory 53, obtaining a first execution time TE1 expressed as TA / (1-k1) and a second execution time TE2 expressed as {TA / (1-k2)}+TB+TC. The first decision process DP1 includes: if the second execution time TE2 is shorter than the first execution time TE1, selecting a second execution method EM2, which is different from the first execution method EM1 that executes the first operation process CP1 while simultaneously executing the second operation process CP2, as the method for executing the second operation process CP2. The second execution method EM2 is a method that replaces the first operation process CP1 and begins the execution of the process AP before executing the second operation process CP2.

[0109] Therefore, if the execution of the second execution method EM2 can complete the second operation processing CP2 faster than the execution of the first execution method EM1, the control device 40 can select the second execution method EM2 as the method for executing the second operation processing CP2. Thus, by having the processor 41 execute the second execution method EM2, the control device 40 can complete the second operation processing CP2 faster than simultaneously processing the first operation processing CP1 and the second operation processing CP2. Therefore, according to this embodiment, the situation where the time required for the second operation processing CP2 (other operation processing) other than the first operation processing CP1 (the predetermined operation processing) becomes longer can be suppressed. Therefore, the time until the completion of the second operation processing CP2 can be shortened, and the processing performance of the disk device 100 can be rapidly improved.

[0110] According to this embodiment, the first determination process DP1 includes: when the second execution time TE2 is greater than or equal to the first execution time TE1, selecting a first execution method EM1 that executes both the first operation process CP1 and the second operation process CP2 as the method for executing the second operation process CP2. Therefore, the control device 40 can select the first execution method EM1 as the method for executing the second operation process CP2 if the execution of the first execution method EM1 can complete the second operation process CP2 faster than the execution of the second execution method EM2. Furthermore, the control device 40 can select the first execution method EM1 as the method for executing the second operation process CP2 if, even when the second execution method EM2 is executed, the time required to complete the second operation process CP2 remains unchanged compared to the case where the first execution method EM1 is executed. Thus, by having the processor 41 execute the first execution method EM1, the control device 40 can simultaneously process the first operation process CP1 and the second operation process CP2 while suppressing the increase in the time required for the second operation process CP2. In this embodiment, the control device 40 can select from the first execution method EM1 and the second execution method EM2 a method that enables the second operation processing CP2 to be completed faster.

[0111] According to this embodiment, the disk device 100 has a locking mechanism 90 that fixes the position θ of the head 31 at a position away from the disk 20 of the disk device 100. A plurality of alternative processing APs include a backoff processing AP1 as an alternative processing performed to fix the position θ of the head 31 by the locking mechanism 90. When the position θ of the head 31 is fixed by the locking mechanism 90, the processor 41 can maintain the position θ of the head 31 at a predetermined position without performing any computational processing. Therefore, in the second execution method EM2 using the backoff processing AP1, the execution of the second computational processing CP2 can utilize 100% or approximately 100% of the processing power of the processor 41. Therefore, by executing the second execution method EM2 using the backoff processing AP1, the processor 41 can complete the second computational processing CP2 in a shorter time than the first execution method EM1.

[0112] According to this embodiment, the disk device 100 includes a head assembly 30 having a head 31. The disk device 100 also includes a stop 91 that faces the head assembly 30 in its moving direction and is capable of contacting the head assembly 30 in that direction. A plurality of alternative processing APs include a pressing processing AP2, which is executed to control the head assembly 30 so that it contacts the stop 91. When the head 31 is controlled at a position θ such that the head assembly 30 contacts the stop 91, the computational load on the processor 41 is lower than when performing the normal first processing CP1. Therefore, in the second execution method EM2 using the pressing processing AP2, the execution of the second processing CP2 can utilize more of the processor 41's processing power. Thus, by executing the second execution method EM2 using the pressing processing AP2, the processor 41 can complete the second processing CP2 in a shorter time than the first execution method EM1. Furthermore, when the head assembly 30 contacts the stop member 91, the amount of movement of the head assembly 30 is smaller compared to moving the head 31 to the locking mechanism 90. Therefore, when executing the second execution method EM2 using the pressing process AP2, the second processing time TB and the third processing time TC can be shortened compared to the second execution method EM2 using the retraction process AP1.

[0113] According to this embodiment, the multiple alternative processing APs include an idle action processing AP3, which is an alternative processing AP executed to control the position θ of the head 31 with a sampling period longer than that of the first operation processing CP1. In the idle action processing AP3, since the position θ of the head 31 is controlled with a sampling period longer than that of the first operation processing CP1, the computational load on the processor 41 is lower than that of the first operation processing CP1. Therefore, in the second execution method EM2 using the idle action processing AP3, the execution of the second operation processing CP2 can utilize the processing performance of the processor 41 more effectively. Thus, by executing the second execution method EM2 using the idle action processing AP3, the processor 41 can complete the second operation processing CP2 in a shorter time than the first execution method EM1. Furthermore, since the idle action processing AP3 can be performed simply by reducing the sampling period in the first operation processing CP1, the second processing time TB and the third processing time TC can be shortened compared to the backoff processing AP1 and the press processing AP2.

[0114] According to this embodiment, the first arithmetic process CP1 includes multiple control processing CTPs. Multiple alternative processing APs include a simplified control processing AP4, which is executed to control the position θ of the head 31 without executing at least one of the multiple control processing CTPs. In the simplified control processing AP4, since at least one control processing CTP performed in the first arithmetic process CP1 is not executed, the computational load on the processor 41 is lower than that of the first arithmetic process CP1. Therefore, in the second execution method EM2 using the simplified control processing AP4, the execution of the second arithmetic process CP2 can utilize more of the processing power of the processor 41. Therefore, by executing the second execution method EM2 using the simplified control processing AP4, the processor 41 can complete the second arithmetic process CP2 in a shorter time than the first execution method EM1. Furthermore, since the simplified control processing AP4 can be performed if at least one control processing CTP is stopped in the first arithmetic process CP1, the second processing time TB and the third processing time TC can be shorter than the retreat processing AP1 and the press processing AP2.

[0115] According to this embodiment, the processor 41 is configured to execute multiple alternative processing APs. The first determination process DP1 includes selecting the second execution method EM2 that uses the alternative processing AP with the shortest second execution time TE2 when at least one of the multiple second execution times TE2 is shorter than the first execution time TE1 when multiple alternative processing APs are used. Therefore, the processor 41 can adopt the execution method with the shortest processing time for the second operation processing CP2 based on the executed second operation processing CP2. As a result, the situation where the time required for the second operation processing CP2 becomes longer can be further suppressed. Therefore, the time until the second operation processing CP2 is completed can be further shortened, and the processing performance of the disk device 100 can be improved more quickly. In addition, in this embodiment, the first determination process DP1 includes selecting the first execution method EM1 when multiple second execution times TE2 when multiple alternative processing APs are used are all greater than or equal to the first execution time TE1. Therefore, if the control device 40 cannot make the time required for the second operation CP2 shorter than that required by the first execution method EM1 when any second execution method EM2 is used, the control device 40 can select the first execution method EM1. Thus, by having the processor 41 execute the first execution method EM1, the control device 40 can process the first operation CP1 and the second operation CP2 simultaneously while suppressing the increase in the time required for the second operation CP2.

[0116] According to this embodiment, the first determination process DP1 includes: when the second execution method EM2 is selected, sending a signal to the host device 80 that sends the instruction to the disk device 100, inquiring whether the second execution method EM2 can be executed. The first determination process DP1 includes: determining whether to execute the second execution method EM2 based on the signal from the host device 80. The processor 41 is configured to execute the second execution method EM2 if it is determined in the first determination process DP1 that the second execution method EM2 can be executed based on the signal from the host device 80. Therefore, even when the second execution method EM2 is selected, the processor 41 does not execute the second execution method EM2 if no permission is issued from the host device 80. Therefore, the execution of the second execution method EM2 can be suppressed in situations where even a temporary interruption in the response from the disk device 100 to the host device 80 would cause problems. As a result, the unintended deterioration of the response time of the host device 80 can be suppressed. In this embodiment, the processor 41 is configured to execute the first execution method EM1 if, in the first determination process DP1, it is determined from the signal from the host device 80 that the second execution method EM2 cannot be executed. Therefore, in cases where even a temporary interruption in the response from the slave device 100 to the host device 80 would cause problems, the second execution method EM2 is not executed, and the first execution method EM1 is executed instead. As a result, the first arithmetic process CP1 and the second arithmetic process CP2 are executed together, thereby suppressing interruptions in the response from the slave device 100 to the host device 80.

[0117] According to this embodiment, the signal sent to the host device 80 to inquire whether the second execution method EM2 can be executed includes information about the second execution time TE2. Therefore, the host device 80 can determine the time of the response interruption from the disk device 100 due to the execution of the second execution method EM2 based on the information about the second execution time TE2. As a result, the host device 80 can more appropriately determine whether the processor 41 can execute the second execution method EM2 based on the current data processing status, etc.

[0118] According to this embodiment, the control device 40 is configured to execute a second determination process DP2 that is executed when the second execution method EM2 is executed. The second determination process DP2 includes determining whether the time required for the completion of the second execution method EM2 is longer than the second execution time TE2 notified to the host device 80. The processor 41 is configured to suspend the second execution method EM2 if the second determination process DP2 determines that the time required for the completion of the second execution method EM2 is longer than the second execution time TE2. Therefore, when the host device 80 permits the execution of the second execution method EM2, if the time required for the completion of the second operation process CP2 appears to be longer than expected, the control device 40 can suspend the second execution method EM2, thus suppressing situations that may hinder the processing of the host device 80. In this embodiment, the processor 41 is configured to suspend the second execution method EM2 and execute the first execution method EM1 if the second determination process DP2 determines that the time required for the completion of the second execution method EM2 is longer than the second execution time TE2. Since the head 31 is position-controlled as usual in the first execution method EM1, the disk device 100 can write and read data based on instructions from the host device 80. Therefore, when the second execution method EM2 is aborted and the first execution method EM1 is started, the response from the disk device 100 to the host device 80 is restored. Therefore, even when the host device 80 permits the execution of the second execution method EM2, even if the time required to complete the second operation processing CP2 appears to be longer than expected, executing the first execution method EM1 can further suppress the occurrence of unexpected deterioration in the response time of the host device 80.

[0119] According to this embodiment, the control device 40 is configured to, upon completion of the second operation process CP2, calculate the time required until the completion of CP2 as the actual processing time APT, which is converted to the time required to complete the second operation process CP2 if the processor 41 has only executed CP2. The control device 40 is configured to update the first processing time TA stored in the non-volatile memory 53 to the actual processing time APT if the actual processing time APT is longer than the first processing time TA stored in the non-volatile memory 53. Therefore, when the completion of the second operation process CP2 takes longer than expected, the control device 40 can update the first processing time TA based on the actual result. Thus, when the second operation process CP2 is executed again, the control device 40 can more appropriately select the execution method for executing the second operation process CP2. Furthermore, when the second execution method EM2 is selected to be executed when the second operation processing CP2 is executed in the next operation, the control device 40 can more accurately estimate the second execution time TE2 required for the host device 80 to notify the second execution method EM2.

[0120] According to this embodiment, the control device 40 is configured such that, when the second operation processing CP2 is completed, if the actual processing time APT is longer than the first processing time TA stored in the non-volatile memory 53, the difference between the actual processing time APT and the first processing time TA is stored in the non-volatile memory 53. Therefore, the control device 40 can more accurately estimate the second execution time TE2 required for the second execution method EM2 based on the stored difference time.

[0121] According to this embodiment, the control device 40 is configured to determine to execute the second operation process CP2 when the processing performance of the disk drive 100 is lower than a predetermined performance value. Therefore, when the processing performance of the disk drive 100 decreases, the second operation process CP2 is executed. Thus, by setting the second operation process CP2 as a process executed, for example, to improve the processing performance of the disk drive 100, the reduced processing performance of the disk drive 100 can be improved through the execution of the second operation process CP2.

[0122] According to this embodiment, the second arithmetic process CP2 includes a process for generating a digital filter used in controlling the actuator 73 that moves the head 31. Therefore, by generating the digital filter using the second arithmetic process CP2, the accuracy of controlling the actuator 73 can be improved. Thus, the processing performance of the disk device 100 can be appropriately improved through the execution of the second arithmetic process CP2.

[0123] According to at least one embodiment described above, the control device of the embodiment is a control device for a control disk device. The control device includes a processor. The control device is configured to execute a first determination process. The processor is configured to execute a first arithmetic process to control the position of the head of the control disk device. The processor is configured to execute a second arithmetic process that can be executed simultaneously with the first arithmetic process. The processor is configured to execute a substitution process to maintain the head position at a predetermined position with a lower computational load than the first arithmetic process. The first determination process is a process executed based on information stored in a predetermined storage medium when it is determined that the second arithmetic process will be executed. The information stored in the predetermined storage medium includes a first processing time required until the second arithmetic process is completed when the processor only executes the second arithmetic process. The information stored in the predetermined storage medium includes a second processing time required until the head position is maintained at the predetermined position by substitution process in place of the first arithmetic process. The information stored in the predetermined storage medium includes a third processing time required to restart the first arithmetic process that was interrupted by the execution of the substitution process. The information stored in the predetermined storage medium includes a first processing occupancy rate of the processor required to execute the first arithmetic process. The information stored in the predetermined storage medium includes a second processing occupancy rate of the processor required to maintain the position of the processing head by replacing the processing. The first determination process includes: when the first processing time is set to TA, the second processing time to TB, the third processing time to TC, the first processing occupancy rate to k1, and the second processing occupancy rate to k2, based on the information stored in the predetermined storage medium, obtaining a first execution time expressed as TA / (1-k1) and a second execution time expressed as {TA / (1-k2)}+TB+TC. The first determination process includes: if the second execution time is shorter than the first execution time, selecting a second execution method different from the first execution method that executes the first operation processing while simultaneously executing the second operation processing as the method for executing the second operation processing. The second execution method is the method of executing the second operation processing after starting the replacement processing to replace the first operation processing. Therefore, it is possible to suppress the situation where the time required for the second operation processing (other operation processing) other than the first operation processing (predetermined operation processing) becomes longer.

[0124] Furthermore, while the above embodiments illustrate an example of a control device applicable to a disk drive, the embodiments of the control device can also be applied to processing devices other than disk drives. This processing device can be any device capable of performing arbitrary processing. For example, any device can be equipped with a small processor such as a CPU. Examples of devices equipped with a small processor include automobiles, mobile phones, smartwatches, wireless speakers, and noise-canceling headphones. This processing device can be, for example, a semiconductor device or a device installed in a power plant. The control device for controlling this processing device is described as follows: The control device includes a processor. The control device is configured to perform decision processing. The processor is configured to perform a first arithmetic operation. The processor is configured to perform a second arithmetic operation that can be performed simultaneously with the first arithmetic operation. The processor is configured to perform an alternative operation with a lower computational load than the first arithmetic operation. Additionally, the control method for controlling this processing device is described as follows: The control method includes a first arithmetic operation. The control method includes a second arithmetic operation that can be performed simultaneously with the first arithmetic operation. The control method includes an alternative operation with a lower computational load than the first arithmetic operation. The control method includes a decision process performed based on information stored in a predetermined storage medium when it is determined that a second operation will be performed. In the control device and control method of this processing apparatus, the decision process is a process performed based on information stored in a predetermined storage medium when it is determined that a second operation will be performed. The information stored in the predetermined storage medium includes a first processing time required until the second operation is completed when the processor only performs the second operation. The information stored in the predetermined storage medium includes a second processing time required to perform a replacement operation instead of the first operation. The information stored in the predetermined storage medium includes a third processing time required to restart the first operation, which was interrupted by the execution of the replacement operation. The information stored in the predetermined storage medium includes a first processing occupancy of the processor required to perform the first operation. The information stored in the predetermined storage medium includes a second processing occupancy of the processor required to perform the replacement operation. The determination process includes: when the first processing time is set to TA, the second processing time to TB, the third processing time to TC, the first processing occupancy rate to k1, and the second processing occupancy rate to k2, based on the information stored in the predetermined storage medium, obtaining the first execution time represented by TA / (1-k1) and the second execution time represented by {TA / (1-k2)}+TB+TC. The determination process also includes: if the second execution time is shorter than the first execution time, selecting a second execution method different from the first execution method that executes the first and second operations simultaneously as the method for executing the second operation. The second execution method is a method that replaces the first operation and begins execution of the second operation after the replacement process.According to such a control device and control method, similarly to the above-described embodiment, it is possible to suppress the situation where the time required for the second operation (other operation) other than the first operation (predetermined operation) performed by the processing device becomes longer. Furthermore, in such a control device and control method, the determination process may also include: if the second execution time is longer than the first execution time, selecting a first execution method that performs the first operation while simultaneously performing the second operation as the method for performing the second operation.

[0125] Alternatively, if the decision-making process determines that the second execution time is later than the first execution time, a third execution method different from both the first and second execution methods can be selected as the method for performing the second operation. The third execution method can be any method that is different from both the first and second execution methods and capable of performing the second operation. For example, the third execution method could be a method that performs the second operation without performing the first operation or any alternative processing. Alternatively, the third execution method could be a method that performs the third operation, which is different from the first operation, while simultaneously performing the second operation.

[0126] The second operation that can be executed simultaneously with the first operation can be any operation. There is no particular limitation on the number of second operations, as long as there is one or more. In the control device and control method of the disk drive, the alternative operation can be any operation performed to maintain the head position at a predetermined position with a lower computational load than the first operation. There is no particular limitation on the number of alternative operations in the control device and control method of the disk drive.

[0127] The control device, control panel, control method, and program (program product) of the implementation method include the following appended technical solutions.

[0128] (Postscript 1)

[0129] A control device for a control panel device.

[0130] Equipped with a processor

[0131] It is configured to be able to perform the first decision process.

[0132] The processor is configured to execute:

[0133] The first arithmetic operation is performed to control the position of the head of the disk device;

[0134] A second operation that can be executed simultaneously with the first operation; and

[0135] An alternative process performed to maintain the head position at a predetermined position with a lower computational load than the first computational process.

[0136] The first determination process is a process performed based on information stored in a predetermined storage medium, when it is determined that the second operation process will be executed.

[0137] The information stored in the storage medium includes:

[0138] The first processing time required until the second operation is completed when the processor only performs the second operation;

[0139] The second processing time required until the position of the head is maintained at the predetermined position by the replacement processing, replacing the first computational processing;

[0140] The third processing time required to restart the first operation process that was interrupted by the execution of the substitution process;

[0141] The first processing occupancy of the processor required to perform the first arithmetic operation; and

[0142] In order to maintain the position of the head through the alternative processing, the second processing occupancy of the processor is required, and the first determination process includes:

[0143] When the first processing time is set to TA, the second processing time to TB, the third processing time to TC, the first processing occupancy rate to k1, and the second processing occupancy rate to k2, based on the information stored in the storage medium, the first execution time represented by TA / (1-k1) and the second execution time represented by {TA / (1-k2)}+TB+TC are obtained; and

[0144] If the second execution time is shorter than the first execution time, a second execution method, different from the first execution method that executes the first and second operations simultaneously, is selected as the method for performing the second operation.

[0145] The second execution method is a method of starting the second operation process after replacing the first operation process.

[0146] (Postscript 2)

[0147] According to the control device described in Appendix 1

[0148] The first determination process includes: if the second execution time is longer than the first execution time, selecting the first execution method as the method for executing the second operation process.

[0149] (Note 3)

[0150] According to the control device described in Appendix 1 or Appendix 2

[0151] The disc assembly has a locking mechanism that fixes the position of the head in a position where it is disengaged from the disc of the disc assembly.

[0152] The replacement process includes the replacement process performed in order to fix the position of the head by the locking mechanism.

[0153] (Note 4)

[0154] The control device according to any one of Annexes 1 to 3,

[0155] The disk assembly has:

[0156] A head assembly having the head; and

[0157] A stop member that is opposite to the head assembly in the direction of movement of the head assembly and is capable of contacting the head assembly in the direction of movement.

[0158] The alternative process includes: the alternative process performed in order to control the head assembly to make the head assembly contact the stop.

[0159] (Note 5)

[0160] The control device according to any one of Annexes 1 to 4,

[0161] The substitution process includes the substitution process performed to control the position of the head with a sampling period longer than the first operation process.

[0162] (Note 6)

[0163] The control device according to any one of Annexes 1 to 5,

[0164] The first arithmetic process includes multiple control processes.

[0165] The alternative process includes the alternative process performed to control the position of the head in a manner that does not involve performing at least one of the plurality of control processes.

[0166] (Note 7)

[0167] The control device according to any one of Annexes 1 to 6

[0168] The processor is configured to perform multiple of the aforementioned replacement processes.

[0169] The first determination process includes: if at least one of the multiple second execution times when multiple alternative processes are used is shorter than the first execution time, selecting the second execution method that uses the alternative process with the shortest second execution time.

[0170] (Postscript 8)

[0171] The control device according to any one of Annexes 1 to 7

[0172] The first determination process includes:

[0173] When the second execution method is selected, a signal is sent to the host device that sent the instruction to the disk device, inquiring whether the second execution method can be executed; and

[0174] The decision to execute the second execution method is based on the signal from the host device.

[0175] The processor is configured to execute the second execution method if, during the first determination process, a signal from the host device indicates that the second execution method can be executed.

[0176] (Note 9)

[0177] According to the control device described in Appendix 8

[0178] The signal inquiring whether the second execution method can be executed includes information about the second execution time.

[0179] (Postscript 10)

[0180] According to the control device described in Appendix 9

[0181] This is configured to perform a second determination process that is executed while the second execution method is being executed.

[0182] The second determination process includes: determining whether the time required for the second execution method to complete is longer than the second execution time notified to the host device.

[0183] The processor is configured to terminate the second execution method if, during the second determination process, it is determined that the time required for the second execution method to complete is longer than the second execution time.

[0184] (Postscript 11)

[0185] The control device according to any one of Annexes 1 to 10,

[0186] The configuration is such that, when the second operation is completed, the time required until the completion of the second operation is calculated as the actual processing time, which is converted into the time required to complete the second operation if the processor has only executed the second operation. If the actual processing time is longer than the first processing time stored in the storage medium, the first processing time stored in the storage medium is updated to the actual processing time.

[0187] (Postscript 12)

[0188] According to the control device described in Appendix 11

[0189] The configuration is such that, when the second operation is completed, if the actual processing time is longer than the first processing time stored in the storage medium, the difference between the actual processing time and the first processing time is stored in the storage medium.

[0190] (Postscript 13)

[0191] The control device according to any one of Annexes 1 to 12,

[0192] The system is configured to execute the second operation when the processing performance of the disk device is lower than a predetermined performance value.

[0193] (Postscript 14)

[0194] According to the control device described in Appendix 13

[0195] The second computational process includes the process of generating digital filters used in the control of the actuator that moves the head.

[0196] (Postscript 15)

[0197] A control device for a control processing device,

[0198] Equipped with a processor

[0199] It is configured to be capable of performing decision processing.

[0200] The processor is configured to execute:

[0201] First operation processing;

[0202] A second operation that can be executed simultaneously with the first operation; and

[0203] An alternative process with a lower computational load than the first computational process.

[0204] The determination process is a process performed based on the information stored in a predetermined storage medium when it is determined that the second operation process will be executed.

[0205] The information stored in the storage medium includes:

[0206] The first processing time required until the second operation is completed when the processor only performs the second operation;

[0207] The second processing time required to perform the alternative processing in place of the first arithmetic processing;

[0208] The third processing time required to restart the first operation process that was interrupted by the execution of the substitution process;

[0209] The first processing occupancy of the processor required to perform the first arithmetic operation; and

[0210] The second processing occupancy of the processor required to perform the replacement process.

[0211] The determination process includes:

[0212] When the first processing time is set to TA, the second processing time to TB, the third processing time to TC, the first processing occupancy rate to k1, and the second processing occupancy rate to k2, based on the information stored in the storage medium, the first execution time represented by TA / (1-k1) and the second execution time represented by {TA / (1-k2)}+TB+TC are obtained; and

[0213] If the second execution time is shorter than the first execution time, a second execution method, different from the first execution method that executes the first and second operations simultaneously, is selected as the method for performing the second operation.

[0214] The second execution method is a method of starting the second operation process after replacing the first operation process.

[0215] (Postscript 16)

[0216] A disk device comprising:

[0217] plate;

[0218] The head is capable of reading data recorded on the disk and writing data to the disk; and

[0219] The control device as described in any one of Appendix 1 to Appendix 15.

[0220] (Postscript 17)

[0221] A method for controlling a disk device includes:

[0222] The first arithmetic operation is performed to control the position of the head of the disk device;

[0223] A second operation that can be executed simultaneously with the first operation;

[0224] Alternative processing performed to maintain the head position at a predetermined position with a lower computational load than the first computational processing; and

[0225] If the second operation is determined to be performed, the first determination process is performed based on the information stored in the predetermined storage medium.

[0226] The information stored in the storage medium includes:

[0227] The first processing time required until the second operation is completed when the processor capable of performing the first operation, the second operation, and the alternative operation only performs the second operation;

[0228] The second processing time required until the position of the head is maintained at the predetermined position by the replacement processing, replacing the first computational processing;

[0229] The third processing time is required to restart the first operation process that was interrupted due to the execution of the substitution process;

[0230] The first processing occupancy of the processor required to perform the first arithmetic operation; and

[0231] In order to maintain the position of the head through the alternative processing, the second processing occupancy of the processor is required, and the first determination process includes:

[0232] When the first processing time is set to TA, the second processing time to TB, the third processing time to TC, the first processing occupancy rate to k1, and the second processing occupancy rate to k2, based on the information stored in the storage medium, the first execution time represented by TA / (1-k1) and the second execution time represented by {TA / (1-k2)}+TB+TC are obtained; and

[0233] If the second execution time is shorter than the first execution time, a second execution method, different from the first execution method that executes the first and second operations simultaneously, is selected as the method for performing the second operation.

[0234] The second execution method is a method of starting the second operation process after replacing the first operation process.

[0235] (Postscript 18)

[0236] According to the control method described in Appendix 17

[0237] The first determination process includes:

[0238] When the second execution method is selected, a signal is sent to the host device that sent the instruction to the disk device, inquiring whether the second execution method can be executed; and

[0239] The decision to execute the second execution method is based on the signal from the host device.

[0240] The control method includes: in the first determination process, if it is determined from the signal from the host device that the second execution method can be executed, then executing the second execution method.

[0241] (Postscript 19)

[0242] A method for controlling a processing device, comprising:

[0243] First operation processing;

[0244] A second operation that can be executed simultaneously with the first operation;

[0245] Alternative processing with a lower computational load than the first computational processing; and

[0246] The decision-making process performed based on the information stored in the predetermined storage medium when it is determined to execute the second operation.

[0247] The information stored in the storage medium includes:

[0248] The first processing time required until the second operation is completed when the processor capable of performing the first operation, the second operation, and the alternative operation only performs the second operation;

[0249] The second processing time required to perform the alternative processing in place of the first arithmetic processing;

[0250] The third processing time required to restart the first arithmetic process, which was interrupted by the execution of the replacement process; the first processing occupancy of the processor required to execute the first arithmetic process; and

[0251] The second processing occupancy of the processor required to perform the replacement process.

[0252] The determination process includes:

[0253] When the first processing time is set to TA, the second processing time to TB, the third processing time to TC, the first processing occupancy rate to k1, and the second processing occupancy rate to k2, based on the information stored in the storage medium, the first execution time represented by TA / (1-k1) and the second execution time represented by {TA / (1-k2)}+TB+TC are obtained; and

[0254] If the second execution time is shorter than the first execution time, a second execution method, different from the first execution method that executes the first and second operations simultaneously, is selected as the method for performing the second operation.

[0255] The second execution method is a method of starting the second operation process after replacing the first operation process.

[0256] (Postscript 20)

[0257] A program that causes a computer to execute any one of the control methods described in Appendix 17 to Appendix 19.

[0258] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and / or variations thereof are included within the scope and spirit of the invention, as well as within the scope of the claims and their equivalents.

Claims

1. A control device, specifically a control panel device. Equipped with a processor It is configured to be able to perform the first decision process. The processor is configured to execute: The first arithmetic operation is performed to control the position of the head of the disk device; A second operation that can be executed simultaneously with the first operation; and An alternative process performed to maintain the head position at a predetermined position with a lower computational load than the first computational process. The first determination process is a process performed based on information stored in a predetermined storage medium, when it is determined that the second operation process will be executed. The information stored in the storage medium includes: The first processing time required until the second operation is completed when the processor only performs the second operation; The second processing time required until the position of the head is maintained at the predetermined position by the replacement processing, replacing the first computational processing; The third processing time required to restart the first operation process that was interrupted by the execution of the substitution process; The first processing occupancy of the processor required to perform the first arithmetic operation; as well as The second processing occupancy of the processor required to maintain the position of the head through the alternative processing. The first determination process includes: When the first processing time is set to TA, the second processing time is set to TB, the third processing time is set to TC, the first processing occupancy rate is set to k1, and the second processing occupancy rate is set to k2, the first execution time represented by TA / (1-k1) and the second execution time represented by {TA / (1-k2)}+TB+TC are obtained based on the information stored in the storage medium. and If the second execution time is shorter than the first execution time, a second execution method, different from the first execution method that executes the first and second operations simultaneously, is selected as the method for performing the second operation. The second execution method is a method of starting the second operation process after replacing the first operation process.

2. The control device according to claim 1, The first determination process includes: If the second execution time is longer than or equal to the first execution time, the first execution method is selected as the method for performing the second operation.

3. The control device according to claim 1, The disc assembly has a locking mechanism that fixes the position of the head in a position where it is disengaged from the disc of the disc assembly. The replacement process includes the replacement process performed in order to fix the position of the head by the locking mechanism.

4. The control device according to claim 1, The disk assembly has: A head assembly having the head; and A stop member that is opposite to the head assembly in the direction of movement of the head assembly and is capable of contacting the head assembly in the direction of movement. The replacement process includes the replacement process performed in order to control the head assembly to contact the stop.

5. The control device according to claim 1, The substitution process includes the substitution process performed to control the position of the head with a sampling period longer than that of the first operation process.

6. The control device according to claim 1, The first arithmetic process includes multiple control processes. The alternative process includes the alternative process performed to control the position of the head in a manner that does not involve performing at least one of the plurality of control processes.

7. The control device according to claim 1, The processor is configured to perform multiple of the aforementioned replacement processes. The first determination process includes: If at least one of the multiple second execution times is shorter than the first execution time when multiple alternative processes are used, the second execution method that uses the alternative process with the shortest second execution time is selected.

8. The control device according to any one of claims 1 to 7, The first determination process includes: When the second execution method is selected, a signal is sent to the host device that sent the instruction to the disk device, inquiring whether the second execution method can be executed; and The decision to execute the second execution method is based on the signal from the host device. The processor is configured to execute the second execution method if, during the first determination process, a signal from the host device indicates that the second execution method can be executed.

9. The control device according to claim 8, The signal inquiring whether the second execution method can be executed includes information about the second execution time.

10. The control device according to claim 9, This is configured to perform a second determination process that is executed while the second execution method is being executed. The second determination process includes: Determine whether the time required for the completion of the second execution method is longer than the second execution time notified to the host device. The processor is configured to terminate the second execution method if, during the second determination process, it is determined that the time required for the second execution method to complete is longer than the second execution time.

11. The control device according to any one of claims 1 to 7, The control device is configured such that, When the second operation is completed, the time required until the second operation is completed is calculated as the actual processing time. The actual processing time is converted into the time required for the second operation to complete when the processor has only executed the second operation. If the actual processing time is longer than the first processing time stored in the storage medium, the first processing time stored in the storage medium is updated to the actual processing time.

12. The control device according to claim 11, The control device is configured such that, when the second operation is completed, if the actual processing time is longer than the first processing time stored in the storage medium, the difference between the actual processing time and the first processing time is stored in the storage medium.

13. The control device according to any one of claims 1 to 7, The control device is configured to determine to execute the second arithmetic operation when the processing performance of the disk device is lower than a predetermined performance value.

14. The control device according to claim 13, The second computational process includes the process of generating digital filters used in the control of the actuator that moves the head.

15. A control device, which is a control device for a control processing device. Equipped with a processor It is configured to be capable of performing decision processing. The processor is configured to execute: First operation processing; A second operation that can be executed simultaneously with the first operation; and An alternative process with a lower computational load than the first computational process. The determination process is a process performed based on information stored in a predetermined storage medium when it is determined that the second operation process will be executed. The information stored in the storage medium includes: The first processing time required until the second operation is completed when the processor only performs the second operation; The second processing time required to perform the alternative processing in place of the first arithmetic processing; The third processing time required to restart the first operation process that was interrupted by the execution of the substitution process; The first processing occupancy of the processor required to perform the first arithmetic operation; as well as The second processing occupancy of the processor required to perform the replacement process. The determination process includes: When the first processing time is set to TA, the second processing time is set to TB, the third processing time is set to TC, the first processing occupancy rate is set to k1, and the second processing occupancy rate is set to k2, the first execution time represented by TA / (1-k1) and the second execution time represented by {TA / (1-k2)}+TB+TC are obtained based on the information stored in the storage medium. and If the second execution time is shorter than the first execution time, a second execution method, different from the first execution method that executes the first and second operations simultaneously, is selected as the method for performing the second operation. The second execution method is a method of starting the second operation process after replacing the first operation process.

16. A disk device comprising: plate; The head is capable of reading data recorded on the disk and writing data to the disk; and The control device according to any one of claims 1 to 7.

17. A control method, a control method for a disk device, comprising: The first arithmetic operation is performed to control the position of the head of the disk device; A second operation that can be executed simultaneously with the first operation; An alternative process performed to maintain the head position at a predetermined position with a lower computational load than the first operation; as well as If the second operation is determined to be performed, the first determination process is performed based on the information stored in the predetermined storage medium. The information stored in the storage medium includes: The first processing time required until the second operation is completed when the processor capable of performing the first operation, the second operation, and the alternative operation only performs the second operation; The second processing time required until the position of the head is maintained at the predetermined position by the replacement processing, replacing the first computational processing; The third processing time required to restart the first operation process that was interrupted by the execution of the substitution process; The first processing occupancy of the processor required to perform the first arithmetic operation; and The second processing occupancy of the processor required to maintain the position of the head through the alternative processing. The first determination process includes: When the first processing time is set to TA, the second processing time to TB, the third processing time to TC, the first processing occupancy rate to k1, and the second processing occupancy rate to k2, based on the information stored in the storage medium, the first execution time represented by TA / (1-k1) and the second execution time represented by {TA / (1-k2)}+TB+TC are obtained; and If the second execution time is shorter than the first execution time, a second execution method, different from the first execution method that executes the first and second operations simultaneously, is selected as the method for performing the second operation. The second execution method is a method of starting the second operation process after replacing the first operation process.

18. The control method according to claim 17, The first determination process includes: When the second execution method is selected, a signal is sent to the host device that sends the instruction to the disk device to inquire whether the second execution method can be executed; and The decision to execute the second execution method is based on the signal from the host device. The control method includes: in the first determination process, if it is determined from the signal from the host device that the second execution method can be executed, then executing the second execution method.

19. A control method, which is a control method for a processing device, comprising: First operation processing; A second operation that can be executed simultaneously with the first operation; An alternative process with a lower computational load than the first computational process; as well as The decision-making process performed based on the information stored in the predetermined storage medium when it is determined to execute the second operation. The information stored in the storage medium includes: The first processing time required until the second operation is completed when the processor capable of performing the first operation, the second operation, and the alternative operation only performs the second operation; The second processing time required to perform the alternative processing in place of the first arithmetic processing; The third processing time required to restart the first operation process that was interrupted by the execution of the substitution process; The first processing occupancy of the processor required to perform the first arithmetic operation; and The second processing occupancy of the processor required to perform the replacement process. The determination process includes: When the first processing time is set to TA, the second processing time to TB, the third processing time to TC, the first processing occupancy rate to k1, and the second processing occupancy rate to k2, based on the information stored in the storage medium, the first execution time represented by TA / (1-k1) and the second execution time represented by {TA / (1-k2)}+TB+TC are obtained; and If the second execution time is shorter than the first execution time, a second execution method, different from the first execution method that executes the first and second operations simultaneously, is selected as the method for performing the second operation. The second execution method is a method of starting the second operation process after replacing the first operation process.

20. A program that causes a computer to perform the control method according to any one of claims 17 to 19.

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