Three-dimensional memory chip and fault layer detection method and monitoring method thereof

Abstract

The present application relates to a kind of three-dimensional storage chip and its failure layer detection method and monitoring method.The three-dimensional storage chip includes stacked storage unit stacked on substrate die, wherein layer-in power system is formed in each layer of storage die, the storage die is configured as when the stacked storage unit is powered on, corresponding power on-off signal with layer number information is obtained, and the power supply of corresponding layer-in power system is independently controlled according to the power on-off signal, the shielding of storage die can be realized, avoid the influence of faulty storage die on the power system of chip whole, other layers can work normally, it is advantageous to improve the yield of three-dimensional storage chip.The failure layer detection method can screen failure layer when the power system of above-mentioned three-dimensional storage chip has failure.The monitoring method can be powered on monitoring to storage die, avoid the influence of failure layer on the power system of chip whole.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, and in particular to a three-dimensional memory chip, a fault layer detection method for a three-dimensional memory chip, and a monitoring method for a three-dimensional memory chip. Background Technology

[0002] Three-dimensional memory chips vertically stack multiple memory layers, greatly improving storage density compared to traditional two-dimensional chips, and also offering significant advantages in power consumption and memory access bandwidth.

[0003] An existing three-dimensional memory chip includes stacked memory cells, each comprising at least two memory dies (such as DRAM dies) vertically bonded together in sequence. Additionally, a substrate die (such as a logic die) is bonded to the stacked memory cells, enabling power supply and control signals to the memory dies. Each die has devices and circuits fabricated using a monolithic substrate (such as a silicon wafer) process and may have a TSV (Transient Voltage Suppressor) extending through the substrate. Metal pads on adjacent dies can be interconnected, allowing each memory die to share external power supply voltage and on-chip power control signals, and to be powered by an independent in-layer power system.

[0004] However, under the aforementioned shared power supply architecture, existing 3D memory chips cannot be isolated if a power system failure (such as a short circuit or bias anomaly) occurs in a certain layer of the memory die. The fault current may be conducted to other layers through the shared power network, causing the overall power supply system to fail and resulting in a loss of chip yield. Summary of the Invention

[0005] In order to avoid the impact of faulty bare dies on the overall chip power system and improve the yield of three-dimensional memory chips, this invention provides a three-dimensional memory chip, as well as a fault layer detection method and a monitoring method for three-dimensional memory chips.

[0006] On one hand, the present invention provides a three-dimensional memory chip, the three-dimensional memory chip comprising:

[0007] A stacked memory cell stacked on a substrate bare die, the stacked memory cell comprising at least two layers of memory bare dies vertically stacked interconnected and conductive paths connecting the memory bare dies to the substrate bare die; and

[0008] An in-layer power supply system is provided in each of the memory bare cells. The memory bare cells are configured to acquire a power on / off signal with corresponding layer number information when the stacked memory unit is powered on, and independently control the power supply of the in-layer power supply system according to the power on / off signal.

[0009] Optionally, the substrate die is configured to transmit, when the stacked memory cell is powered on, the power channel signal with layer number information and the external sink voltage and on-chip power control signal shared by the at least two layers of memory dies through the conductive path.

[0010] Optionally, the three-dimensional memory chip further includes a power control circuit. The power control circuit is disposed in each layer of the memory die and is configured to receive the on-chip power control signal and the power on / off signal corresponding to the layer and perform logic processing. Based on the result of the logic processing, the power system within the layer is connected to or disconnected from the external power supply voltage. Specifically, when the power on / off signal corresponding to the layer indicates that the memory die is not shielded, the external power supply voltage is allowed to supply power to the power system within the layer; otherwise, the external power supply voltage to the power system within the layer is disconnected.

[0011] Optionally, the substrate bare core is a logic bare core or a buffer bare core.

[0012] Optionally, the in-layer power system includes at least one of a low-dropout linear regulator, a bandgap reference voltage source, and a charge pump.

[0013] Optionally, the substrate die is bonded to a packaging substrate on the side opposite to the stacked memory cell. The three-dimensional memory chip also includes the substrate die, the packaging substrate, and a power management chip bonded to the surface of the packaging substrate for generating external voltage.

[0014] On the other hand, the present invention provides a fault layer detection method for the above-mentioned three-dimensional memory chip, wherein the fault layer isolation method includes the following steps:

[0015] When the power system of the three-dimensional memory chip fails, a set of power on / off signals with layer number information are sent from the substrate bare die to the memory bare dies in the stacked memory cell. In this case, the power system of at least one layer of the memory bare die with the set layer number is de-energized, and the power system of the other memory bare dies is powered on to power up the corresponding memory bare dies. In addition, it is detected whether the power system has returned to normal and the fault layer is determined based on the detection result.

[0016] Optionally, if the power system in one layer of the memory die is powered off and the power system is not restored to normal after each power outage and traversal, the detection is performed again, and the power system in at least two layers of the memory die is powered off each time.

[0017] Optionally, after determining the fault layer, the fault layer detection method further includes:

[0018] The layer number information of the storage bare core corresponding to the fault layer is stored in the electric fuse storage unit on the substrate bare core.

[0019] Furthermore, the present invention provides a monitoring method for the above-mentioned three-dimensional storage chip, the monitoring method comprising the following steps:

[0020] Send a common external sink voltage and a common on-chip power control signal to each of the aforementioned memory dies; and

[0021] By sending the power on / off signal with layer number information, the power supply system in each layer of the multi-layer memory die is powered up layer by layer. The powered in-layer power supply system starts up and powers up the corresponding memory die. During the power-up process, the external sink voltage is monitored. When the external sink voltage is abnormal, the abnormal external sink voltage and the information of the currently monitored memory die are output.

[0022] Optionally, when the external charging voltage is abnormal, the currently monitored bare memory die is determined to be a faulty layer, and the corresponding power on / off signal is adjusted to de-energize the power system within the faulty layer to shield the faulty layer.

[0023] Optionally, the substrate bare die has an electric fuse storage unit, which stores the layer number information of the faulty storage bare die; before powering the in-layer power system of the multiple layers of storage bare dies, the monitoring method further includes: reading the layer number information of the faulty storage bare die and sending a corresponding power on / off signal to the faulty storage bare die to de-energize the in-layer power system of the faulty storage bare die.

[0024] In the three-dimensional memory chip provided by the present invention, when the stacked memory cell is powered on, the memory die can obtain the corresponding power on / off signal with layer number information and independently control the power supply of the power system in the layer according to the power on / off signal. This can achieve precise shielding of the memory die, avoid faulty memory dies from affecting the overall power system of the chip, and enable layers other than the faulty layer to work normally, which is beneficial to improving the yield of the three-dimensional memory chip.

[0025] In the fault layer detection method for a three-dimensional memory chip provided by the present invention, when the power system of the three-dimensional memory chip is faulty, the power supply system in at least one layer of the memory die with the specified layer number is de-energized by sending a power on / off signal with layer number information, while the power supply system in the remaining memory dies is powered on to power on the corresponding memory dies. Then, it is detected whether the power system has returned to normal, which facilitates the screening of faulty memory dies and avoids the faulty memory dies from affecting the overall power system of the chip.

[0026] In the monitoring method for three-dimensional memory chips provided by this invention, the power on / off signal with layer number information is used to power the power system within each layer of the multi-layer memory die, thereby powering on the corresponding memory die. During the power-on process, the external sink voltage is monitored to obtain information on whether the external sink voltage is abnormal. When the external sink voltage is abnormal, the abnormal state of the external sink voltage and the information of the currently monitored memory die are output. This method can realize power-on monitoring of the memory die and avoid the faulty layer from affecting the overall power system of the chip. Attached Figure Description

[0027] Figure 1 and Figure 2 These are schematic diagrams of the structure of the three-dimensional storage chip in the embodiments of the present invention.

[0028] Figure 3 yes Figure 2 The diagram shows the signal transmission of a three-dimensional memory chip.

[0029] Figure 4 This is a schematic diagram of a logic die sending signals to two memory dies in one embodiment of the present invention.

[0030] Figure 5 yes Figure 4 The diagram shows two bare memory chips, one shielded and the other undergoing normal internal power-on.

[0031] Figure 6 This is a flowchart illustrating a fault layer detection method for a three-dimensional memory chip according to another embodiment of the present invention.

[0032] Figure 7 This is a flowchart illustrating a monitoring method for a three-dimensional storage chip according to an embodiment of the present invention. Detailed Implementation

[0033] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, further illustrates the three-dimensional memory chip and its fault layer detection and monitoring method of the present invention. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, used only to facilitate and clarify the illustration of the embodiments of the present invention. The terms "first," "second," etc., used below are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence; it should be understood that these terms can be replaced where appropriate.

[0034] Reference Figure 1 and Figure 2In this embodiment of the invention, the three-dimensional memory chip includes stacked memory cells 110 stacked on a base die BD. The stacked memory cells 110 include at least two layers of memory dies (such as memory dies D0~D3) that are vertically stacked and interconnected, and conductive paths 10 connecting the memory dies and the base die BD.

[0035] In a three-dimensional memory chip, the memory dies and substrate dies (BDs) are stacked along the thickness direction of the chip. To form this three-dimensional memory chip, for example, two or more memory wafers are stacked using bonding technology, and then stacked with a substrate wafer designed according to requirements. Afterwards, a dicing process is used to form individual stacked dies. The memory wafers form the memory dies that primarily provide storage functions, while the substrate wafers form the substrate dies (BDs). Storage elements (such as DRAM or SRAM) and interconnect circuits are formed on the memory dies. The stacked structure of multiple memory dies forms a stacked memory cell 110. Logic elements and MBIST circuits can be formed on the substrate dies (BDs) as needed, providing control and / or data buffering functions.

[0036] In a three-dimensional memory chip, a TSV (Transient Voltage Suppressor) can be formed within the memory die and the substrate die (BD), penetrating the respective wafer. The TSV can lead signals from one side of the die to the other. At the bonding interface, metal pads on adjacent dies can be connected by bump bonding or hybrid bonding, giving the three-dimensional memory chip a conductive path 10 connecting the memory die and the substrate die (BD). The circuits on each memory die and the substrate die (BD) can be interconnected. As an example, each memory die and the substrate die (BD) may have a shared conductive path 10. Figure 1 As an example, one of the conductive paths 10 is identified. A common electrical signal can be sent to each memory die through the common conductive path 10.

[0037] like Figure 1 As shown, in some embodiments, the three-dimensional memory chip may further include a substrate die BD and a packaging substrate 120 (e.g., a PCB board or an interposer substrate) located on the side of the substrate die BD away from the memory die. For example, metal bumps 20 are formed on the side of the substrate die BD away from the memory die. The stacked structure of the substrate die BD and the stacked memory cells 110 can be bonded to the surface of the packaging substrate 120 by bump bonding or other suitable means.

[0038] like Figure 2As shown, in some embodiments, the three-dimensional memory chip may further include a power management chip (PMIC) bonded to the surface of the packaging substrate 120. For example, a metal bump 20 is also formed on the lower surface of the power management chip. The power management chip is used to provide power management functions. It can be electrically connected to the substrate bare die BD through the packaging substrate 120. The external sink voltage (such as VCC, VDD or VPP) can be generated by the power management chip, distributed to the bottom metal bump 20 of the substrate bare die BD through the power distribution network on the packaging substrate 120, and then transported to the substrate bare die BD and each memory bare die through the aforementioned conductive path 10.

[0039] The substrate die BD can be a logic die or a buffer die. In the following embodiments, the substrate die BD is, for example, a logic die, and the three-dimensional memory chip is, for example, a three-dimensional DRAM chip, that is, each memory die (such as memory dies D0~D3) in the stacked memory cell 110 is a DRAM die.

[0040] Figure 3 yes Figure 2 The diagram shows the signal transmission of a three-dimensional memory chip. (Refer to...) Figure 3 In some embodiments, the 3D memory chip may further include a power control circuit 130 and an in-layer power system 140 independently formed in each layer of memory die. The in-layer power system 140 can power the memory cells (such as individual "BANKs") in the memory die of the layer by establishing an internal power supply voltage (such as a reference voltage, bit line voltage, and word line voltage). The in-layer power system 140 includes, for example, at least one of a low-dropout linear regulator (LDO), a bandgap reference voltage source, and a charge pump, but is not limited thereto; the in-layer power system 140 may also include other power supply and voltage reference circuits. The power control circuit 130 can receive externally input signals and perform power-on control.

[0041] When the stacked memory cell 110 is powered on, the external sink voltage generated by the power management chip (PMIC) can be supplied through, for example, as shown in the figure. Figure 3 The shared external voltage path shown is transmitted through the package substrate 120 to the bare substrate BD, and further transmitted to each bare memory die through the conductive path 10 shared by the bare substrate BD and each bare memory die in the stacked memory cell 110; in addition, the bare substrate BD also transmits the voltage through the path shown in the figure. Figure 3 The shared Power_ctrl signal path and Power_Gating signal path shown, as well as the conductive path 10, send the shared on-chip power control signal Power_ctrl and the power on / off signal Power_Gating with layer number information (i.e., non-shared) to each memory die.

[0042] The Power_Gating signal indicates whether a memory die of the corresponding layer number is shielded. A set of Power_Gating signals can be transmitted through a set of conductive paths 10 used for signal transmission and are respectively identified by the memory dies of the corresponding layer number. In this embodiment, the memory die is configured to acquire the corresponding Power_Gating signal with layer number information when the stacked memory cell 110 is powered on, and independently control the power supply of the layer power system 140 according to the Power_Gating signal. For example, when the Power_Gating signal of the layer corresponding to the memory die indicates that the memory die is not shielded, external voltage is allowed to supply power to the layer power system 140 of the layer. When the Power_Gating signal indicates that the memory die is shielded, the external voltage is disconnected from the layer power system 140 of the layer, so that the layer power system 140 cannot start, thereby preventing the establishment of internal power voltage, and thus the corresponding memory die is shielded.

[0043] The on-chip power control signal Power_ctrl and the power on / off signal Power_Gating can be emitted by the substrate bare die (BD) after the external sink voltage is established. As an example, after the external sink voltage is established, the power control circuit 130 receives the on-chip power control signal Power_ctrl and the power on / off signal Power_Gating corresponding to its layer from the substrate bare die (BD), performs logical processing on the received signals, and, based on the result of the logical processing, connects or disconnects the in-layer power system 140 of the layer where the power control circuit 130 is located from the external sink voltage. For example, when the on-chip power control signal Power_ctrl is enabled and the power on / off signal Power_Gating corresponding to the current memory die is disabled, it indicates that the current memory die is powered on normally. Its internal power control circuit 130 connects the in-layer power system 140 of the current memory die to the external sink voltage to supply power to the in-layer power system 140. When the on-chip power control signal Power_ctrl is disabled, none of the memory dies are powered on. When the on-chip power control signal Power_ctrl is enabled but the power on / off signal Power_Gating corresponding to some memory dies is enabled, it indicates that these memory dies are shielded. Their internal power control circuit 130 disconnects the in-layer power system 140 from the external sink voltage and does not supply power (i.e., power off). The in-layer power system 140 is connected to the signal of the external sink voltage, for example, through a switching element. The power control circuit 130 can control the switching element to turn on or off, thus connecting or disconnecting the in-layer power system 140 from the external sink voltage.

[0044] Figure 4 This is a schematic diagram illustrating the transmission of signals from a logic die to two memory dies in one embodiment of the present invention. (Refer to...) Figure 4 As an example, the three-dimensional memory chip includes logic dies, memory dies D0, and memory dies D1 stacked sequentially, wherein the logic die serves as the aforementioned base die BD, and memory dies D0 and D1 are, for example, DRAM dies. When the stacked memory cell 110 including memory dies D0 and D1 is powered on, the logic die sends an external sink voltage and an on-chip power control signal Power_ctrl that are shared by memory dies D0 and D1, and also sends a set of power on / off signals Power_Gating<1:0> with layer number information. Each memory die can obtain the power on / off signal Power_Gating sent to the memory die in that layer according to the layer number information.

[0045] Figure 5 yes Figure 4 The diagram shows two bare memory chips, one shielded and the other undergoing normal internal power-on. (Refer to...) Figure 5 As an example, the power on / off signal obtained from the bare die D0 is a high level 1 (i.e., Power_Gating). <0> =1), indicating that the bare memory chip D0 is shielded, and the power control circuit 130 on the bare memory chip D0 is based on Power_Gating <0> =1, disconnecting the external sink voltage from the internal power supply system 140 of the storage bare die D0, then the internal power supply system 140 ( Figure 5 The example shows that the LDO, bandgap reference voltage source, and charge pump are turned off and in a power-down state, achieving the effect of shielding the memory die D0; the power on / off signal obtained by the memory die D1 is, for example, a low level 0 (i.e., Power_Gating). <1> =0), indicating that internal power-on is allowed for the storage die D1. The power control circuit 130 on the storage die D1 is based on Power_Gating. <1> The on-chip power control signal Power_ctrl, which is set to 0 and enabled, connects the external power supply voltage to the in-layer power system 140 in the memory die D1. The in-layer power system 140 in the memory die D1 then starts up and establishes its internal power supply voltage, enabling the memory die D1 to complete its internal power-on process normally. It should be noted that... Figure 4 and Figure 5 The structure of the stacked memory cell 110 and the power on / off signal shown are merely examples. The concept of using the power on / off signal to power off the in-layer power system 140 in a portion of the memory dies (i.e., shielding a portion of the memory dies) can also be applied to stacked memory cells 110 with more memory dies. It should be noted that in this embodiment, when shielding a portion of the memory dies in the stacked memory cell 110 using the power on / off signal, the other portion of the memory dies can be powered on normally. Depending on the needs, in some embodiments, the power on / off signal can also be used to shield all the memory dies in the stacked memory cell 110.

[0046] When the in-layer power system 140 of one or more memory dies is powered down, thus shielding the corresponding memory die, the substrate die D0 will no longer send read, write, or refresh control signals to the shielded memory die during subsequent operation. For the entire power network of the 3D memory chip, since the external power supply voltage and the on-chip power control signal Power_ctrl are transmitted through the common conductive path of each memory die in the stacked memory cell 110, the in-layer power systems 140 of memory dies in different layers are connected in parallel. Disconnecting the in-layer power system 140 of a portion of the memory dies is equivalent to disconnecting a portion of the parallel branch, which will only result in a loss of some storage capacity. The conductive path between other memory dies and the substrate die D0 is not affected, and the substrate die D0 can send read, write, or refresh control signals to memory dies that have completed their internal power-on normally.

[0047] As can be seen, in the three-dimensional memory chip described in this embodiment of the invention, when the stacked memory cell 110 is powered on, some layers of memory dies can be shielded and disconnected from the external voltage, while other layers of memory dies remain unaffected and can still operate normally. This means that the internal power system 140 of each layer of memory die can be independently controlled, achieving precise shielding of the target layer's memory die. When a memory die in one layer fails, shielding it prevents the faulty layer from affecting the overall chip power system, facilitating the normal operation of layers other than the faulty layer and improving the yield of the three-dimensional memory chip. In some embodiments, the substrate die D0 has an electric fuse memory cell that stores the layer number information of the faulty memory die, so that the faulty layer can be precisely shielded using the power on / off signal Power_Gating when the three-dimensional memory chip is powered on.

[0048] Some embodiments of the present invention relate to a fault layer detection method for a three-dimensional memory chip, which can be used to detect fault layers (i.e., faulty bare dies) in the three-dimensional memory chip described in the above embodiments. The fault layer detection method includes the following steps:

[0049] Step 1: When the power system of the three-dimensional memory chip is faulty (such as a short circuit or bias failure during chip testing), a set of power on / off signals Power_Gating with layer number information is sent to the memory bare cells in the stacked memory cell 110 through the substrate bare cell BD. In this case, the in-layer power system 140 in at least one layer of the memory bare cell with the set layer number is de-energized, and the in-layer power system 140 in the other memory bare cells is powered on to enable the corresponding memory bare cells to be powered on.

[0050] Step 2: Check whether the power system has returned to normal, and make a fault level judgment based on the test results.

[0051] When the power system 140 of at least one layer of storage bare die with a set layer number is de-energized, if the power system returns to normal in step two, it can be further determined whether the power system 140 of only one layer of storage bare die is de-energized, i.e., the storage bare die of that layer is shielded. If so, the shielded storage bare die is the faulty layer, and the detection ends. If more than one layer of storage bare die is shielded, or the power system has not returned to normal, the set layer number is adjusted, the power on / off signal Power_Gating is sent again, and it is detected whether the power system has returned to normal at this time.

[0052] In some embodiments, when sending the power on / off signal Power_Gating to each memory die in step one, one layer of memory dies is shielded each time. (See also...) Figure 6 As an example, initialization is performed first, i.e., preparing for power-on. Then, a shared external sink voltage is sent to each memory die via the substrate die BD. After the external sink voltage is established, a shared on-chip power control signal Power_ctrl and a power on / off signal Power_Gating with layer number information are sent. Using the layer number setting in the Power_Gating signal, for example, the first memory die stacked on the substrate die BD, i.e., memory die D0, is powered off while the other memory dies are powered on normally internally. Then, a self-test is run to check if the chip's power system is working properly. For example, the self-test can be run by detecting the external sink voltage and / or performing read / write tests. Based on the test results, it is determined whether the self-test passes. If the power failure is confirmed, the memory die that was de-energized is the faulty layer, and the test can be terminated. If the failure is confirmed, it indicates that a faulty layer exists among the powered-on memory dies. In this case, the layer number is adjusted, and the power on / off signal Power_Gating is resent. For example, in this test, the second memory die stacked on the logic die, i.e., memory die D1, is de-energized while other memory dies are powered on normally. Then, a self-test is run to determine whether the self-test passes. If the power system is working normally, the self-test passes; otherwise, the self-test fails. Based on the judgment result, if the faulty layer can be identified, the test ends. Otherwise, if the faulty layer cannot be identified, the layer number is adjusted again, and the power on / off signal Power_Gating is resent. This process is repeated. By adjusting the layer number and running the self-test, the faulty layer can be accurately located.

[0053] The above embodiments sequentially shield the corresponding memory bare cells in the stacking order from bottom to top on the substrate bare cells BD to perform fault layer detection. However, the present invention is not limited to this. Since shielding any layer of memory bare cells does not affect the normal power-on of other memory bare cells, the shielding order can be selected as needed.

[0054] Using the fault layer detection method described in the above embodiments, when sending the power on / off signal Power_Gating to each memory die, if one layer of memory die is shielded each time, and the chip power system is still not normal after traversing the shielded memory dies once, it indicates that there may be more than one fault layer. In this case, the detection can be repeated, and at least two layers of memory die are shielded each time. By adjusting the layer number and performing a self-test, the layer number information of the fault layer can be obtained when the chip power system is normal.

[0055] In some embodiments, when sending the power on / off signal Power_Gating to each memory die in step one, at least two layers of memory dies are shielded at once. If the chip power system is normal after running the self-test, then for the shielded at least two layers of memory dies, the layer number information is adjusted so that some of the memory dies are shielded while the other memory dies are powered on normally. The self-test is then run again and it is determined whether the self-test passes. Based on the determination result, if the faulty layer can be identified, the test ends. Otherwise, if the faulty layer is not identified, the layer number is adjusted again and the power on / off signal Power_Gating is resent. This process is repeated. By adjusting the layer number and running the self-test, the faulty layer can be accurately located.

[0056] After identifying the faulty layer using the aforementioned fault layer detection method, the layer number information of the corresponding bare memory die can be stored in the storage module of the 3D memory chip. This allows for subsequent power-on of the stacked storage unit 110, where a power-on / off signal (Power_Gating) containing the layer number information is sent to indicate that the faulty layer is being shielded, thus achieving the purpose of shielding the faulty layer. In some embodiments, the layer number information corresponding to the faulty layer is burned into a fuse storage unit on the substrate bare die BD for storage. After the substrate bare die BD is powered on, the faulty layer information is read from this fuse storage unit, and the corresponding power-on / off signal (Power_Gating) is sent to shield the faulty layer. By identifying the faulty layer and accurately shielding it, other layers can still function normally, which helps improve the yield of the 3D memory chip.

[0057] Some embodiments of the present invention relate to a monitoring method for a three-dimensional memory chip, which can monitor the power system of the three-dimensional memory chip described in the above embodiments and shield abnormal memory dies, i.e., fault layers.

[0058] Reference Figure 7As an example, the monitoring method includes the following steps: First, the system operation of the three-dimensional memory chip is initialized, enabling the three-dimensional memory chip to start working. This involves the substrate die BD sending a shared external power supply voltage and a shared on-chip power control signal Power_ctrl to each memory die. Next, by sending a power on / off signal Power_Gating with layer number information, the in-layer power system 140 in the multi-layer memory die is powered layer by layer. The powered in-layer power system 140 starts up and establishes its internal power supply voltage, thus powering on the corresponding memory die. During the power-on process, the external power supply voltage is monitored. When the external power supply voltage is abnormal, information indicating an abnormal external power supply voltage and the currently powered memory die (i.e., the monitored memory die) is output. When powering on the in-layer power system 140 in the multi-layer memory die layer by layer, for example, the memory dies with set layer numbers are powered on sequentially according to their stacking order on the substrate die BD, while other memory dies are powered off. However, this is not limited to this; the order in which the in-layer power system 140 in the multi-layer memory die is powered on can be set as needed.

[0059] When monitoring the external sink voltage, it is determined whether the monitored external sink voltage is abnormal. If so, it indicates that the currently powered-on memory die has a power-on fault, and therefore, information indicating an abnormal external sink voltage and the memory die information are output. This information can also be recorded and an alarm issued. If not, it indicates that the currently powered-on memory die does not have a power-on fault and can operate normally, and information indicating a normal external sink voltage can be output. Figure 7 As shown, it can then be determined whether there are any undetected memory cells. If so, the layer number is adjusted, and the power supply system 140 of the next layer memory cell is powered on to power on the next layer memory cell. During the power-on process, the external voltage is monitored. If each of the multiple memory cells has gone through the process of establishing the internal power supply voltage and monitoring the external voltage, the monitoring ends.

[0060] like Figure 7 As shown, after detecting an abnormal external voltage, in order to avoid the monitored memory die affecting subsequent detection, the monitored memory die is determined to be a fault layer. Furthermore, by adjusting the power on / off signal Power_Gating for the memory die, the power system 140 in the fault layer is de-energized to shield the fault layer.

[0061] In some embodiments, the substrate bare die BD has an electric fuse storage unit that stores layer number information of known faulty bare dies. Before powering the in-layer power system 140 in the multi-layer bare dies layer by layer, the monitoring method sends a corresponding power on / off signal (Power_Gating) to the faulty bare dies, causing the in-layer power system 140 in the faulty bare dies to be de-energized, thus shielding the known faulty layers. In subsequent monitoring, the power-on of these known faulty layers does not need to be monitored.

[0062] Using the above monitoring method, the Power_Gating signal with layer number information is used to power the in-layer power system 140 in the multi-layer memory die layer by layer, thereby powering on the corresponding memory die. During the power-on process, the external sink voltage is monitored to obtain information on whether the external sink voltage is abnormal. When the external sink voltage is abnormal, the abnormal external sink voltage status and the information of the currently monitored memory die are output. This can realize the power-on monitoring of the memory die and avoid the faulty layer from affecting the overall power system of the chip.

[0063] At least some features of the aforementioned fault layer detection method and monitoring method for three-dimensional storage chips can be implemented by computer programs and / or hardware circuits, for example, by using a computer program in conjunction with a device or equipment. The computer program can be stored in various readable storage media (such as hard disks, random access memory (RAM), or external storage media) for processor execution. When the computer program is executed, the corresponding fault layer detection method or monitoring method can be performed.

[0064] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A three-dimensional memory chip, characterized in that, include: A stacked memory cell stacked on a substrate bare core, the stacked memory cell including at least two layers of memory bare cores vertically stacked interconnected and a conductive path connecting the memory bare cores and the substrate bare core; as well as An in-layer power supply system is provided in each of the memory bare cells. The memory bare cells are configured to acquire a power on / off signal with corresponding layer number information when the stacked memory unit is powered on, and independently control the power supply of the in-layer power supply system according to the power on / off signal.

2. The three-dimensional storage chip as described in claim 1, characterized in that, The substrate die is configured to transmit, when the stacked memory cell is powered on, the power channel signal with layer number information, as well as the external sink voltage and on-chip power control signal shared by the at least two layers of memory dies, through the conductive path.

3. The three-dimensional storage chip as described in claim 2, characterized in that, Also includes: A power control circuit is disposed in each layer of the memory die and is configured to receive the on-chip power control signal and the power on / off signal corresponding to the layer and perform logic processing. Based on the result of the logic processing, the power system within the layer is connected to or disconnected from the external power supply voltage. Specifically, when the power on / off signal corresponding to the layer indicates that the memory die is not shielded, the external power supply voltage is allowed to supply power to the power system within the layer; otherwise, the external power supply voltage to the power system within the layer is disconnected.

4. The three-dimensional memory chip as described in claim 1, characterized in that, The substrate bare core is a logic bare core or a buffer bare core.

5. The three-dimensional memory chip as described in claim 1, characterized in that, The in-layer power system includes at least one of a low-dropout linear regulator, a bandgap reference voltage source, and a charge pump.

6. The three-dimensional memory chip according to any one of claims 1 to 5, characterized in that, The substrate die is bonded to the packaging substrate on the side opposite to the stacked memory cell. The three-dimensional memory chip also includes the substrate die, the packaging substrate, and a power management chip bonded to the surface of the packaging substrate for generating external voltage.

7. A method for fault layer detection of a three-dimensional memory chip as described in any one of claims 1 to 6, characterized in that, Includes the following steps: When the power system of the three-dimensional memory chip fails, a set of power on / off signals with layer number information are sent from the substrate die to the memory dies in the stacked memory cell. Specifically, the power system within the layer of at least one memory die with the specified layer number is de-energized, while the power systems within the layers of the remaining memory dies are powered on, thus powering up the corresponding memory dies. Check whether the power system has returned to normal, and determine the fault level based on the test results.

8. The fault layer detection method as described in claim 7, characterized in that, If the power system in one layer of the memory die is powered off and the process is repeated once, and the power system still does not return to normal, then the test is repeated, and the power system in at least two layers of the memory die is powered off each time.

9. The fault layer detection method as described in claim 7, characterized in that, After determining the fault layer, the method further includes: The layer number information of the storage bare core corresponding to the fault layer is stored in the electric fuse storage unit on the substrate bare core.

10. A monitoring method for a three-dimensional memory chip as described in any one of claims 1 to 6, characterized in that, Includes the following steps: Send a common external sink voltage and a common on-chip power control signal to each of the aforementioned memory bare dies; as well as By sending the power on / off signal with layer number information, the power supply system in each layer of the multi-layer memory die is powered up layer by layer. The powered in-layer power supply system starts up and powers up the corresponding memory die. During the power-up process, the external sink voltage is monitored. When the external sink voltage is abnormal, the abnormal external sink voltage and the information of the currently monitored memory die are output.

11. The monitoring method as described in claim 10, characterized in that, When the external charging voltage is abnormal, the currently monitored bare memory die is determined to be a faulty layer, and the corresponding power on / off signal is adjusted to de-energize the power system within the faulty layer to shield the faulty layer.

12. The monitoring method as described in claim 10, characterized in that, The substrate bare core has an electric fuse storage unit, which stores the layer number information of the storage bare core that has a fault; Before powering the in-layer power systems in the multiple layers of the memory die, the monitoring method further includes: Read the layer number information of the faulty memory die and send the corresponding power on / off signal to the faulty memory die to de-energize the power system within the layer of the faulty memory die.

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