Memory device and method of forming the same

Abstract

A memory device with fly-over bit lines is provided. The memory device includes an array having a plurality of columns. Each of the plurality of columns includes a first read bit line pair connected to a first portion of memory cells in a top region of the column, a second read bit line pair connected to a second portion of memory cells in a bottom region of the column, and a first fly-over read bit line pair. The memory device also includes a connection unit located between the top region and the bottom region. The connection unit includes a vertical interconnect connecting the first read bit line pair to the first fly-over read bit line pair. Embodiments of this application also provide a method of forming the memory device.

Description

Technical Field

[0001] Embodiments of this application relate to memory devices and methods of forming the same. Background Technology

[0002] Semiconductor memory devices are electronic data storage devices implemented on semiconductor-based integrated circuits. Semiconductor memory devices come in various types and offer much faster access times than other data storage technologies. For example, bytes of data can typically be written to or read from a semiconductor memory device within nanoseconds, while the access time for rotating storage such as hard drives is in the millisecond range. For these reasons, semiconductor memory devices are used as the primary storage mechanism in computers to hold data currently being processed and for other purposes. Summary of the Invention

[0003] According to one aspect of the embodiments of this application, a memory device is provided, comprising: an array including a plurality of columns, wherein each of the plurality of columns includes: a first read bit line pair connected to a first portion of a memory cell in a top region of the column; a second read bit line pair connected to a second portion of a memory cell in a bottom region of the column; and a first fly-over read bit line pair; and a connection unit located between the top region and the bottom region, wherein the connection unit includes a vertical interconnect connecting the first read bit line pair to the first fly-over read bit line pair.

[0004] According to another aspect of the embodiments of this application, a memory device is provided, comprising: an array including a first region and a second region, wherein the second region is closer to an input / output (I / O) circuit of the memory device than the first region; a first read bit line pair connected to a first portion of a memory cell in the first region of a column of the array; a second read bit line pair connected to a second portion of a memory cell in the second region of a column; a first fly-over read bit line pair; and a connection unit located between the first region and the second region, wherein the connection unit includes a vertical interconnect connecting the first read bit line pair to the first fly-over read bit line pair.

[0005] According to another aspect of the embodiments of this application, a method for forming a memory device is provided, the method comprising: forming a plurality of memory cells in an array, wherein the array includes a first region and a second region, wherein the second region is closer to an input / output (I / O) circuit of the memory device than the first region; forming write bit line pairs in a first metal layer, wherein the write bit line pairs are connected to a first plurality of memory cells in a column of the array; forming a connection unit located between the first region and the second region; and forming a first fly-through write bit line pair in a second metal layer perpendicularly separated from the write bit line pairs, wherein the connection unit includes a vertical interconnect connecting the write bit line pairs to the first fly-through write bit line pairs. Attached Figure Description

[0006] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various parts are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various parts may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 A schematic diagram of a memory cell according to some embodiments is shown.

[0008] Figure 2 The nth column of an array of memory devices according to an example embodiment is shown.

[0009] Figure 3 A top view of the first wiring layer of the interconnection unit of a memory device according to an example embodiment is shown.

[0010] Figure 4 A top view of the second wiring layer of the connection unit according to an example embodiment is shown.

[0011] Figure 5 A cross-sectional view of the connection unit according to an example embodiment is shown.

[0012] Figure 6 A top view of the fourth wiring layer of the connection unit according to an example embodiment is shown.

[0013] Figure 7 A top view of the first wiring layer of the connection unit according to an example embodiment is shown.

[0014] Figure 8 The nth column of an array of another memory device according to an example embodiment is shown.

[0015] Figure 9 The nth column of an array of yet another memory device according to an example embodiment is shown.

[0016] Figure 10 This is a flowchart illustrating a first method for forming a memory device according to some embodiments.

[0017] Figure 11 This is a flowchart illustrating a second method for forming any memory device according to some embodiments.

[0018] Figure 12 This is a block diagram of a layout system according to some embodiments. Detailed Implementation

[0019] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific embodiments or examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0020] Furthermore, for ease of description, this document may use spacing terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing descriptors used herein may be interpreted accordingly.

[0021] One type of integrated circuit memory is Static Random Access Memory (SRAM) devices. SRAM is a semiconductor memory device that uses bistable circuitry to store data in bits without requiring refresh. An SRAM cell can be called a bit cell because it stores one bit of information. SRAM cells are bistable, meaning they can maintain their state indefinitely as long as sufficient power is supplied. SRAM can operate at higher speeds and lower power consumption, which is why it is used in computer cache memory. Other applications include embedded memory and network device memory. Several types of SRAM cells exist (e.g., 6-transistor (6T) SRAM, dual-port 8-transistor (8T) SRAM, and dual-read-write (2R1W) 10-transistor (10T) SRAM, etc.).

[0022] Memory arrays typically consist of multiple bit cells arranged in rows and columns. Each bit cell in a memory array may include connections to a power supply voltage and a reference voltage. Bit lines (BLs) are used to access bit cells, and word lines (WLs) control the connections to the BLs. A WL can be coupled to a corresponding set of bit cells arranged in a row of the memory array, providing a different WL for each row, and a BL can be coupled to a corresponding set of bit cells arranged in a column of the memory array, providing a different BL for each column. Typically, bit lines extend along a first direction (parallel to a first axis), and word lines extend along a second direction perpendicular to the first direction (parallel to a second axis).

[0023] Each bit in an SRAM cell is stored on four transistors, which form two cross-coupled inverters. These transistors are typically implemented using Complementary Metal-Oxide-Semiconductor (CMOS) technology, where each inverter consists of a p-type CMOS transistor and an N-type CMOS transistor. The gates of the PMOS and NMOS transistors are interconnected to form a feedback loop. This cross-coupled structure allows the cell to store a single data bit (0 or 1) by latching complementary values ​​on the bit line.

[0024] A typical memory cell in an SRAM memory device uses six transistors (6T) connected between an upper reference potential and a lower reference potential (typically ground), allowing one of the two storage nodes to be occupied by the information to be stored, while complementary information is stored in the other storage node. Each bit in the SRAM cell is stored on four transistors, which form two cross-coupled inverters. Two additional transistors of the 6T memory cell are connected to the memory cell's WL to control access to the memory cell during read and write operations (i.e., the "access transistors") by selectively connecting the memory cell to its BL. For example, in a read operation, the BL is precharged to a predefined threshold voltage. When the WL is enabled, a sense amplifier connected to the BL senses and outputs the stored information.

[0025] Another type of SRAM cell is the 2R1W cell, also known as a 10-transistor (10T) cell. For example, a 2R1W 10TSRAM cell includes a pair of read pull-down NMOS transistors and a pair of read transfer gate NMOS transistors. The gates of the read pull-down transistors are connected to the corresponding data nodes. The source / drain (SD) regions of each read transfer gate transistor are connected to the corresponding read BL. The read transfer gate transistors are used for the corresponding read WL. An example 2R1W cell is discussed in more detail in the following sections of this disclosure.

[0026] The 2R1W cell allows two memory accesses to occur simultaneously or nearly simultaneously at two ports. A 2R1W cell memory device comprises one or more memory cell libraries, each containing multiple 10T memory cells arranged in rows and columns. Two WLs correspond to the two ports and extend along each row, electrically coupled to each memory cell in the row. Two pairs of complementary BLs (BBLs) correspond to the two ports, extend along each column, and are electrically coupled to each memory cell in the column. The WL at each port provides access to the memory cell line by line, and the BBL at each port enables the data state of the memory cell to be written to or read from column by column.

[0027] A typical memory cell bank has 128 to 512 rows. However, this results in a long read order block (BL), leading to a high load on the BL. This high load on the BL can, in turn, result in high minimum read and minimum write voltages. Read and write voltages below the minimum read voltage, and the minimum write voltage itself, cause instability when reading from and writing to the memory cells. Furthermore, the low minimum read voltage and high minimum write voltage, in turn, lead to increased dynamic power consumption. One solution to mitigate the effects of a long BL is to use smaller memory cell banks. For example, a large bank with 128 rows of memory cells can be replaced by two smaller banks of 64 rows each. However, increasing the number of banks increases the area used by the memory cells, which can lead to higher costs.

[0028] Furthermore, buffer lines (BLs) are typically parallel to each other and very close together. As technology advances and component sizes shrink, the distance between adjacent BLs will become even smaller. However, this close spacing leads to significant capacitive coupling, especially for long BLs that extend continuously along the entire column of the library. Capacitive coupling, in turn, can slow down read and write times and may further degrade the signal-to-noise ratio.

[0029] In view of the above, this disclosure relates to a bypass bit line and a connection unit for connecting the bit line to the bypass bit line. Figure 1 A schematic diagram of a memory cell 100 is shown, which is implemented, for example, as a 2R1W cell and a 10T SRAM cell. Figure 1 As shown, memory cell 100 includes NMOS transistors N1, N2, N3, N4, N5, N6, N7, N8 and PMOS transistors P1, P2. The gate of each of transistors N3 and N4 is coupled to the write WL (WWL). The drain / source of transistor N3 is coupled to the write BL (WB), and the source / drain of transistor N3 is coupled to node Q. The drain / source of transistor N4 is coupled to the complementary WLB (WBB), and the source / drain of transistor N4 is coupled to node QB. Node QB is complementary to node Q. Transistors N3 and N4 operate as electrical switches, allowing WB to be electrically coupled or decoupled from node Q, and WBB to be electrically coupled or decoupled from node QB, based on the voltage applied to WWL. For example, based on the supply voltage VDD corresponding to the high state (or logic value "1") applied to WWL, transistor N3 is enabled to electrically couple WB to node Q, and transistor N4 is enabled to electrically couple WBB to node QB. In another example, based on the ground voltage VSS corresponding to the low state (or logic value "0") applied to WWL, transistor N3 is disabled to electrically decouple WB from node Q, and transistor N4 is disabled to electrically decouple WBB from node QB.

[0030] Transistor N1 includes a source / drain coupled to a first power supply voltage rail providing ground voltage VSS, a gate coupled to node QB, and a drain / source coupled to node Q. Transistor P1 includes a source / drain coupled to a second power supply voltage rail providing power supply voltage VDD, a gate coupled to node QB, and a drain / source coupled to node Q. Transistor P2 includes a source / drain coupled to a second power supply voltage rail providing power supply voltage VDD, a gate coupled to node Q, and a drain / source coupled to node QB. Transistors N1 and P1 operate as first inverters, and transistors N2 and P2 operate as second inverters, with the first and second inverters cross-coupled to each other. The cross-coupled inverters can sense and amplify the voltage difference at nodes Q and QB. When writing data, the cross-coupled inverters can sense the voltage at nodes Q and QB provided by transistors N3 and N4, and amplify the voltage difference at WB and WBB. For example, a cross-coupled inverter senses a voltage of 0.5V at node Q and a voltage of 0.4V at node QB, and amplifies the voltage difference between nodes Q and QB through positive feedback (or regenerative feedback), so that the voltage at node Q becomes the power supply voltage VDD (e.g., 1V), and the voltage at node QB becomes the ground voltage VSS (e.g., 0V). The amplified voltages at nodes Q and QB can be supplied to WB and WBB respectively through transistors N3 and N4 for reading.

[0031] Transistor N5 includes a source / drain coupled to a first power supply voltage rail providing ground voltage VSS, a gate coupled to node QB, and a drain / source coupled to the source / drain of transistor N7. The drain / source of transistor N7 is coupled to the first read BL (RBL_P0), and the gate of transistor N7 is connected to the first read WL (RWL_P0). Transistors N5 and N7 together form the first read port of the 2R1W cell.

[0032] Transistor N6 includes a source / drain coupled to a first power supply voltage rail providing ground voltage VSS, a gate coupled to node Q, and a drain / source coupled to the source / drain of transistor N8. The drain / source of transistor N8 is coupled to the second read BL (RBL_P1), and the gate of transistor N8 is connected to the second read WL (RWL_P1). Transistors N6 and N8 together form the first read port of the 2R1W cell.

[0033] Transistors N7 and N8 operate as electrical switches, allowing RBL_P1 to be electrically coupled or decoupled from node QB, and RBL_P0 to be electrically coupled or decoupled from node QB, respectively, based on the voltages applied to RWL_P1 and RWL_P0, respectively. For example, transistor N7 is enabled to electrically couple RBL_P0 to node QB based on the supply voltage VDD corresponding to a high state (or logic value "1") applied to RWL_P0. Similarly, transistor N8 is enabled to electrically couple RBL_P1 to node Q based on the supply voltage VDD corresponding to a high state applied to RWL_P1. In another example, transistor N7 is disabled to electrically decouple RBL_P0 from node QB based on the ground voltage VSS corresponding to a low state (or logic value "0") applied to RWL_P0. Similarly, transistor N8 is disabled to electrically decouple RBL_P1 from node Q based on the ground voltage VSS corresponding to a low state applied to RWL_P1.

[0034] Figure 2 The nth column of an array of memory devices 200 according to an example embodiment is shown. The array of memory devices 200 includes multiple columns and multiple rows. Each of the multiple columns may include a first plurality of memory cells, for example, as referenced above. Figure 1 The first plurality of 2R1W units. Each row in the plurality of rows may include a second plurality of memory units, for example, as referred to above. Figure 1 The second plurality of 2R1W cells are described. The memory device 200 may also include WL driver circuitry and input / output (I / O) circuitry. I / O circuitry may include local I / O circuitry and global I / O circuitry.

[0035] The memory device 200 also includes a connection unit 210. As described in the following sections of this disclosure, the connection unit 210 includes a plurality of vertical interconnects for routing BL signals in the vertical direction. The connection unit 210 may be located between a top region 202 (or a first region 202) and a bottom region 204 (or a second region 204) of the array. In some examples, the top region 202 is also referred to as the top array, and the bottom region 204 is also referred to as the bottom array. The connection unit 210 may be approximately equal to two cell heights (i.e., 2H, where H is the cell height).

[0036] In some examples, the connection unit 210 is created by modifying the memory cell. For example, the connection unit 210 is modified from a 2R1W SRAM cell. In the method of forming the connection unit 210 from the 2R1W SRAM cell, the front-end layer pattern of the 2R1W SRAM cell remains unchanged. The back-end layer pattern is modified. For example, the via connections and metal layers of the 2R1W SRAM cell are modified to form the connection unit 210. The following sections will refer to the present disclosure. Figures 3-7The layout of the connection unit 210 is discussed.

[0037] The nth column may include a first plurality of memory cells, for example, as mentioned above. Figure 1 The first plurality of 2R1W10T SRAM cells. The top region 202 of the nth column may include a first portion of the memory cells of the first plurality of memory cells, and the bottom region 204 of the nth column may include a second portion of the memory cells of the first plurality of memory cells. In some embodiments, the number of the first portion of memory cells is the same as the number of the second portion of memory cells. In some other embodiments, the number of the first portion of memory cells is different from the number of the second portion of memory cells. For example, the number of the first portion of memory cells is greater than the number of the second portion of memory cells. In some other examples, the number of the first portion of memory cells is less than the number of the second portion of memory cells.

[0038] like Figure 2 As shown, the nth column includes read BLs, such as the first read BL215 at the top of the nth column (i.e., RBL_P0_Top[n]215) and the second read BL220 at the top of the nth column (i.e., RBL_P1_Top[n]220). Each of RBL_P0_Top[n]215 and RBL_P1_Top[n]220 is connected to a first portion of memory cells in the top region 202 of the nth column. In one example, RBL_P0_Top[n]215 is connected to a first port and is used to perform a read operation on one or more first portion memory cells through the first port. Similarly, RBL_P1_Top[n]220 is connected to a second port and can be used to perform a read operation on one or more first portion memory cells through the second port. In some examples, RBL_P0_Top[n]215 and RBL_P1_Top[n]220 are also referred to as first segment or top segment read BLs.

[0039] The nth column also includes a first read BL225 (i.e., RBL_P0_Bot[n]225) at the bottom of the nth column and a second read BL230 (i.e., RBL_P1_Bot[n]230) at the bottom of the nth column. Each of RBL_P0_Bot[n]225 and RBL_P1_Bot[n]230 is connected to a second portion of memory cells in the bottom region 204 of the nth column. In one example, RBL_P0_Bot[n]225 is connected to a first port and used to perform read operations on one or more second portion memory cells through the first port. Similarly, RBL_P1_Bot[n]230 is connected to a second port and used to perform read operations on one or more second portion memory cells through the second port. In some examples, RBL_P0_Bot[n]225 and RBL_P1_Bot[n]230 are also referred to as second segment or bottom segment read BLs.

[0040] The top segment reads (i.e., RBL_P0_Top[n]215 and RBL_P1_Top[n]220) extend from the top of the nth column to the connection unit 210 in the first direction. Therefore, RBL_P0_Top[n]215 and RBL_P1_Top[n]220 do not extend to the bottom region 204 of the nth column. The bottom segment reads (i.e., RBL_P0_Bot[n]225 and RBL_P1_Bot[n]230) extend from the connection unit 210 to the IO circuit in the first direction. Therefore, RBL_P0_Bot[n]225 and RBL_P1_Bot[n]230 do not extend to the top region 202 of the nth column. In this example, the top segment reads and bottom segment reads are formed by segmenting the reads BL of the nth column around the connection unit 210. In some examples, the top segment reads may be longer than the bottom segment reads. Therefore, the top segment read BL can connect to more memory cells than the bottom segment read BL.

[0041] The nth column also includes fly-through reads BL, such as the first fly-through read BL 235 (i.e., FRBL_P0_Top[n]235) and the second fly-through read BL 240 (i.e., FRBL_P1_Top[n]240) of the nth column. FRBL_P0_Top[n]235 is connected to RBL_P0_Top[n]215 at connection unit 210, and FRBL_P1_Top[n]240 is connected to RBL_P1_Top[n]220 at connection unit 210. In some examples, RBL_P0_Top[n]215 is connected to FRBL_P0_Top[n]235 so that RBL_P0_Top[n]215 bypasses the bottom region 204 of the nth column. Similarly, RBL_P1_Top[n]220 is connected to FRBL_P1_Top[n]240 so that RBL_P1_Top[n]220 bypasses the bottom region 204 of the nth column. By bypassing the bottom region 204 of the nth column, each of RBL_P0_Top[n]215 and RBL_P1_Top[n]220 can avoid the load caused by the second part of the memory cells from the bottom region 204 and minimize the interference between the top region 202 and the bottom region 204.

[0042] In one example, each of RBL_P0_Bot[n]225 and RBL_P1_Bot[n]230 is directly connected to the I / O circuit. On the other hand, each of RBL_P0_Top[n]215 and RBL_P1_Top[n]220 is connected to the I / O circuit via a corresponding fly-through read BL (i.e., via FRBL_P0_Top[n]235 and FRBL_P1_Top[n]240, respectively). In this example, the fly-through read BL extends from the connection unit 210 to the I / O circuit along a first direction, but not to the top region 202 of the nth column.

[0043] The read BL is separated from the fly-through read BL in the vertical direction. That is, the read BLs (i.e., RBL_P0_Top[n]215, RBL_P1_Top[n]220, RBL_P0_Bot[n]225, and RBL_P1_Bot[n]230) are formed in a different metal layer than the fly-through read BLs (i.e., FRBL_P0_Top[n]235 and FRBL_P1_Top[n]240). For example, the read BL is formed in metal layer zero (i.e., layer M0), while the fly-through read BL is formed in metal layer four (i.e., layer M4). In some examples, the fly-through read BL may be formed in metal layer two (i.e., layer M2) or higher (e.g., metal layer six (i.e., layer M6)).

[0044] The nth column also includes write BLs. For example, the nth column includes an nth write BL 245 (i.e., WB[n]245) and an nth complementary write BL 250 (i.e., WBB[n]250). Each of WB[n]245 and WBB[n]250 extends from the top to the bottom of the array in a first direction. Thus, the write BLs are connected to the first portion of the memory cells in the top region 202 and the second portion of the memory cells in the bottom region 204 of the nth column.

[0045] In addition, the nth column includes fly-through writes (BLs). For example, the nth row includes the nth fly-through write BL 255 (i.e., FWB[n]255) and the nth fly-through complementary write BL 260 (i.e., FWBB[n]260). Similar to the write bit lines, the fly-through write bit lines (i.e., FWB[n]255 and FWBB[n]260) extend from the top to the bottom of the array in the first direction.

[0046] In the example, the fly-through write BL is formed in a different metal layer than the write BL. For example, each of WB[n]245 and WBB[n]250 is formed in metal layer zero (i.e., layer M0), while each of FWB[n]255 and FWBB[n]260 is formed in metal layer two (i.e., layer M2). In some implementations, the fly-through write BL may be formed in metal layer four (i.e., layer M4) or metal layer six (i.e., layer M6).

[0047] The write BL is connected to the fly-over write BL, for example, at connection unit 210. In some examples, the write BL is connected to the fly-over write BL at multiple locations, such as at top region 202, bottom region 204, and connection unit 210. Therefore, the write signal is propagated by the write BL and the fly-over write BL. This increases the current-carrying capacity of the write operation, thereby reducing signal impedance, minimizing voltage drop, and improving drive strength, especially for long-distance wiring in high-density memory arrays.

[0048] To connect the read BL to the flyaway read BL, the RBL_P0_Top[n]215 and RBL_P1_Top[n]220 signals are first routed on layer M0. These signals are then vertically connected to layer M4 (or a higher / lower metal layer) via connection unit 210. Once routed to layer M4, the read BL from top region 202 does not share any connection with the read BL from bottom region 204. The signals from top region 202 (i.e., RBL_P0_Top[n]215 and RBL_P1_Top[n]220 signals) extend along layer M4 all the way to the IO circuitry. This routing helps reduce BL load and minimizes interference between top region 202 and bottom region 204.

[0049] The RBL_P0_Bot[n]225 and RBL_P1_Bot[n]230 signals are routed entirely on the M0 layer. Unlike the top region 202, the RBL_P0_Bot[n]225 and RBL_P1_Bot[n]230 signals remain on the M0 layer and extend directly to the IO circuitry without going through the connection unit 210 or being raised to a higher metal layer.

[0050] The write BL 245 (i.e., WB[n]245) and complementary write BL 250 (i.e., WBB[n]250) signals are transmitted through layers M0 and M2, allowing the signals to be vertically distributed across different regions (i.e., top region 202, bottom region 204, and connection unit 210). The WB[n]245 and WBB[n]250 signals begin at layer M0, typically within the array. They are then vertically routed through via 0 (Via0) → layer M1 → via 1 (Via1) → layer M2. This vertical interconnect can be implemented in various locations, such as within the top region 202 of the array, within the bottom region 204 of the array, or within connection unit 210. By using layers M0 (i.e., the lower metal layer) and M2 (i.e., the higher metal layer) for BL signal propagation, the current carrying capacity is increased, which effectively reduces signal impedance, minimizes voltage drop, and improves drive strength, especially for long-distance wiring in high-density memory arrays.

[0051] Figure 3 A top view of the first wiring layer 300 of the connection unit 210 is shown. The first wiring layer 300 shows four example columns (i.e., column 0, column 1, column 2, and column 3) of the array of memory devices 200. It is clear that the memory device 200 may include more than four columns of memory cells. For example, Figure 2 The memory device 200 may include 32, 64, 128 columns, etc.

[0052] The first wiring layer 300 includes metal strips of layers M0 and M1. For example, as... Figure 3 As shown, the M0 layer includes metal strips for reading BLs in the top region 202 and the bottom region 204. In one example, the M0 layer includes metal strips for reading BL 302 (i.e., RBL_P0_Top[0]302) at the top first port of column 0, reading BL 304 (i.e., RBL_P1_Top[0]304) at the top second port of column 0, and reading BL 306 (i.e., RBL_P1_Bot[0]306) at the bottom second port of column 0. Furthermore, as... Figure 3As shown, the read BLs (i.e., RBL_P0_Top[0]302 and RBL_P1_Top[0]304) of the top region 202 of column 0 are connected to the metal strip of layer M1 through through-hole 310, while the read BLs of the bottom region 204 of column 0 are not. By connecting the read BLs of the top region 202 of column 0 to the metal strip of layer M1, the signal from the read BLs is routed to layer M1.

[0053] Column 0 also includes a metal strip for writing BL, for example, column 0 writes BL 312 (i.e., WB[0]312) and column 0 complementary writes BL 314 (i.e., WBB[0]314). Figure 3 As shown, the write BLs in column 0 (i.e., WB[0]312 and WBB[0]314) are connected to the metal strip of layer M1. Therefore, the signal from the write BL is also routed to layer M1.

[0054] The M0 layer of the first wiring layer 300 also includes metal strips for reading the first port of the first column top (i.e., RBL_P0_Top[1]322), the second port of the first column top (i.e., RBL_P1_Top[1]324), and the second port of the first column bottom (i.e., RBL_P1_Bot[1]326). Figure 3 As shown, the read BLs (i.e., RBL_P0_Top[1]322 and RBL_P1_Top[0]324) of the top region 202 of the first column are connected to the metal strip of the M1 layer. Therefore, the signal from the read BL of the first column is propagated to the connecting metal strip of the M1 layer.

[0055] The first column also includes writing BL, for example, writing BL 328 (i.e., WB[1]328) to the first column and writing BL 330 (i.e., WBB[1]330) to the first column complement. Figure 3 As shown, the write BLs of the first column (i.e., WB[1]328 and WBB[1]330) are connected to the metal strip of the M1 layer. Therefore, the signal from the write BL of the first column is propagated to the connected metal strip of the M1 layer.

[0056] The M0 layer of the first wiring layer 300 also includes a second column top first port read BL 332 (i.e., RBL_P0_Top[2]332), a second column top second port read BL 334 (i.e., RBL_P1_Top[2]334), and a second column bottom second port read BL 336 (i.e., RBL_P1_Bot[2]336) for the second column. Figure 3As shown, the read BLs (i.e., RBL_P0_Top[0]332 and RBL_P1_Top[0]334) of the top region 202 of the second column are connected to the metal strip of the M1 layer. Therefore, the signal from the read BL of the second column is propagated to the connected metal strip of the M1 layer.

[0057] The second column also includes writing BL, for example, writing BL 338 (i.e., WB[2]338) in the second column and writing BL 340 (i.e., WBB[2]340) in the complementary second column. Figure 3 As shown, the write BLs of the second column (i.e., WB[2]328 and WBB[2]340) are connected to the metal strip of the M1 layer. Therefore, the signal from the write BL of the second column is propagated to the connected metal strip of the M1 layer.

[0058] The M0 layer of the first wiring layer 300 also includes BL 342 (i.e., RBL_P0_Top[3]342), BL 344 (i.e., RBL_P1_Top[3]344), and BL 346 (i.e., RBL_P1_Bot[3]346), which are used for the first port read of the third column top, the second port read of the third column top, and the second port read of the third column bottom. Figure 3 As shown, the read BLs (i.e., RBL_P0_Top[3]342 and RBL_P1_Top[3]344) of the top region 202 of the third column are connected to the metal strip of the M1 layer. Therefore, the signal from the read BL of the third column is propagated to the connected metal strip of the M1 layer.

[0059] The third column also includes writing BL, for example, writing BL 348 (i.e., WB[3]348) in the third column and writing BL 350 (i.e., WBB[3]350) in the third column complement. Figure 3 As shown, the write BLs in the third column (i.e., WB[3]348 and WBB[3]350) are connected to the metal strip of the M1 layer. Therefore, the signal from the write BL in the third column is propagated to the connected metal strip of the M1 layer.

[0060] Figure 4 A top view of the second wiring layer 360 of the connection unit 210 is shown. In one example, the second wiring layer 360 connects a metal strip from layer M1 to layer M2. For example, as... Figure 4 As shown, the metal strip is connected to the metal strip of layer M2 via via 1 (Via1) 362 for the read BL signal and write BL signal of each of columns 0, 1, 2 and 3. This causes the read BL signal and write BL signal of each of columns 0, 1, 2 and 3 to be routed vertically from layer M1 to layer M2.

[0061] Figure 5A top view of the third wiring layer 370 of the connection unit 210 is shown. In one example, the third wiring layer 370 connects the metal strip of layer M2 to the metal strip of layer M3. For example, as... Figure 5 As shown, the metal strip and the read BL signal of each of columns 0, 1, 2 and 3 are connected to the metal strip of layer M3 through via 2 (Via2) 372. This causes the read BL signal of each of columns 0, 1, 2 and 3 to be routed vertically from the metal strip of layer M2 to the metal strip of layer M3.

[0062] Figure 6 A top view of the fourth wiring layer 380 of the connection unit 210 is shown. In one example, the fourth wiring layer 380 connects the metal strip of the M3 layer to the metal strip of the M4 layer. For example, as Figure 6 As shown, the metal strip and the read BL signal of each of columns 0, 1, 2 and 3 are connected to the metal strip of layer M4 through via 3 (Via3) 382. This causes the read BL signal of each of columns 0, 1, 2 and 3 to be routed vertically from the metal strip of layer M3 to the metal strip of layer M4. Figure 7 A cross-sectional view of the connecting unit 210 is shown. (As shown) Figure 7 As shown, the signal is vertically routed from the lower metal layer (e.g., the M0 layer) to the higher metal layer (e.g., the M2 layer for writing the BL signal and the M4 layer for reading the BL signal).

[0063] In some examples, the column write BL can also be segmented into two or more sections. Figure 8 The nth column of an array of memory devices 400 with segmented write BLs according to an example embodiment is shown. For example, the memory device 400 includes, for example, a top write BL415 (i.e., WB[n]_T 415) and a top complementary write BL420 (i.e., WBB[n]_T 420) for the nth column. Each of WB[n]_T 415 and WBB[n]_T 420 is connected to a first portion of memory cells located in the top region 202 of the nth column. In one example, WB[n]_T 415 and WBB[n]_T 420 are used to perform a write operation in one or more first portion memory cells.

[0064] The nth column also includes a bottom write BL425 (i.e., WB[n]_B 425) and a bottom complementary write BL430 (i.e., WBB[n]_B 430). Each of WB[n]_B 425 and WBB[n]_B 430 is connected to a second portion of memory cells in the bottom region 204 of the nth column. In one example, WB[n]_B 425 and WBB[n]_B 430 are used to perform a write operation on one or more second portion memory cells.

[0065] The top segment write BL (i.e., WB[n]_T 415 and WBB[n]_T 420) extends from the top of the nth column to the connection unit 210 in the first direction. Therefore, WB[n]_T 415 and WBB[n]_T 420 do not extend to the bottom region 204 of the nth column. The bottom segment write BL (i.e., WB[n]_B 425 and WBB[n]_B 430) extends from the connection unit 210 to the IO circuit in the first direction. Therefore, WB[n]_B 425 and WBB[n]_B 430 do not extend to the top region 202 of the nth column. In the example, the top segment write BL and the bottom segment write BL are formed by segmenting the write BL of the nth column around the connection unit 210. In some examples, the top segment write BL may be longer than the bottom segment write BL.

[0066] The nth column also includes a fly-through write BL, for example, a fly-through read BL 435 (i.e., FWB[n]_T 435) and a complementary fly-through BL 440 (i.e., FWBB[n]_T 440). FWB[n]_T 435 is connected to WB[n]_T 415 at connection unit 210, and FWBB[n]_T 440 is connected to WB[n]_T 420 at connection unit 210. In some examples, WB[n]_T 415 is connected to FWB[n]_T 435 such that WB[n]_T 415 bypasses the bottom region 204 of the nth column. Similarly, WBB[n]_T 420 is connected to FWBB[n]_T 440 such that WBB[n]_T 420 bypasses the bottom region 204 of the nth column. By bypassing the bottom region 204 of the column, each of WB[n]_T 415 and WBB[n]_T 420 can avoid the load caused by the second part of the memory cell from the bottom region 204 of the nth column and minimize the interference between the top region 202 and the bottom region 204.

[0067] In one example, each of WB[n]_B 425 and WBB[n]_B 430 is directly connected to the I / O circuit. On the other hand, each of WB[n]_T 415 and WBB[n]_T 420 is connected to the I / O circuit via a corresponding fly-through write BL (i.e., FWB[n]_T435 and FWBB[n]_T 440, respectively). In some examples, the write BLs (i.e., WB[n]_T 415, WBB[n]_T420, WB[n]_B 425, and WBB[n]_B 430) are formed in a different metal layer than the fly-through write BLs (i.e., FWB[n]_T435 and FWBB[n]_T440). For example, the write BL is formed in metal layer zero (i.e., layer M0), while the fly-through write BL is formed in metal layer four (i.e., layer M4). In some examples, fly-through writes to the BL can be formed in metal layer two (i.e., M2 layer) or higher metal layers (e.g., M6 layer).

[0068] As mentioned above Figures 3-7 The fly-over write BL can be connected to the write BL in the same way that the read BL is connected to the fly-over read BL, and therefore will be described again for the sake of brevity in this disclosure. Figure 8 The nth column also includes RBL_P0_Top[n]215, RBL_P1_Top[n]220, RBL_P0_Bot[n]225, RBL_P1-Bot[n]230, FRBL_P0_Top[n]235 and FRBL_P1_Top[n]240.

[0069] In some examples, each write BL can be associated with multiple fly-through write BLs. Figure 9 The nth column of an array of memory devices 500 according to an example embodiment is shown, wherein each write BL has multiple fly-over read BLs. Figure 9 As shown, the memory device 500 includes the nth column read BL, namely RBL_P0_Top[n]215, RBL_P1_Top[n]220, RBL_P0_Bot[n]225, RBL_P1_Bot[n]230, FRBL_P0_Top[n]235, and FRBL_P1_Top[n]240. Furthermore, the memory device 500 includes write BLs, namely WB[n]245 and WBB[n]250.

[0070] WB[n]245 is associated with or connected to multiple fly-through writes (BLs), such as a first fly-through write BL 255 (i.e., FWB[n]_1 255) and a second fly-through write BL 510 (i.e., FWB[n]_2 510). FWB[n]_1 255 extends parallel to WB[n]245 from the top region 202 into the I / O circuitry of the memory device 500. FWB[n]_1 255 is vertically separated from WB[n]245 and is formed in a different metal layer than WB[n]245. For example, FWB[n]_1 255 is formed in layer M2 and connected to WB[n]245 via via 0 (Via 0) 310 and via 1 (Via 1) 362. Therefore, write BL signals propagate vertically from WB[n]245 to FWB[n]_1 255.

[0071] FWB[n]_2 510 also extends parallel to WB[n]245 and FWB[n]_1 255 from the top region 202 to the I / O circuitry of the memory device 500. Furthermore, FWB[n]_2 510 is vertically separated from WB[n]245 and FWB[n]_1 255. FWB[n]_2 510 is formed in a different metal layer than WB[n]245 and FWB[n]_1 255. For example, FWB[n]_2 510 is formed in layer M4 and connected to FWB[n]_1 255 via via 2 (Via 2) 372 and via 3 (Via 3) 382. Therefore, the write BL signal propagates vertically from WB[n]245 through FWB[n]_1 255 to FWB[n]_2 510.

[0072] Similarly, WWB[n]250 is associated with or connected to multiple complementary fly-through writes (BLs), such as a first complementary fly-through write BL 260 (i.e., FWBB[n]_1 260) and a second complementary fly-through write BL 520 (i.e., FWBB[n]_2 520). FWBB[n]_1 260 extends parallel to WBB[n]250 from the top region 202 to the I / O circuitry of the memory device 500. FWBB[n]_1 260 is vertically separated from WBB[n]250 and is formed in a different metal layer than WBB[n]250. For example, FWBB[n]_1 260 is formed in layer M2 and connected to WBB[n]250 via vias 0 310 and 1 362. Therefore, complementary write BL signals propagate vertically from WBB[n]250 to FWBB[n]_1 260.

[0073] FWBB[n]_2 520 also extends from the top region 202 parallel to WBB[n]250 and FWBB[n]_1 260 to the I / O circuitry of the memory device 500. Furthermore, FWBB[n]_2 520 is vertically separated from WBB[n]250 and FWBB[n]_1 260. FWBB[n]_2 520 is formed in a different metal layer than WBB[n]250 and FWBB[n]_1 260. For example, FWBB[n]_2520 is formed in layer M4 and connected to FWBB[n]_1 515 via vias 2 372 and 3 382. Therefore, the complementary write BL signal propagates vertically from WBB[n]250 through FWBB[n]_1 260 to FWBB[n]_2 520.

[0074] Figure 10 This is a flowchart illustrating a first method 600 for forming a memory device 200, memory device 400, or memory device 500 according to some embodiments. Method 600 may be derived from methods such as those described with reference to this disclosure. Figure 12 The layout system 800 discussed is executed. In some examples, method 600 can be stored as an instruction on a memory device, which can then execute method 600 when the processor is executed. The implementation of each stage of method 600 will be described in more detail below.

[0075] At stage 610 of method 600, memory cells of an array of memory devices 200 are formed. For example, they can be formed as described above. Figure 1 The array of the 10T 2R1W memory cells. The memory array includes a first region and a second region, the second region being closer to the input / output (I / O) circuitry of the memory device than the first region. For example, memory cells can be formed in a top region 202 and a bottom region 204.

[0076] At stage 620 of method 600, a metal strip of the M0 layer is deposited and patterned to form a first read bit line pair and a second read bit line pair in the first metal layer. As described above, the first read bit line pair is connected to a first portion of the memory cell in a first region of a column of the array, and the second read bit line pair is connected to a second portion of the memory cell in a second region of a column of the array. The metal strip of the M0 layer is deposited and patterned to route the initial BL signal from the top region 202 and the bottom region 204. For example, signals from RBL_P0_Top[n]215, RBL_P1_Top[n]220, RBL_P0_Bot[n]225, RBL_P1-Bot[n]230, WB[n]245, and WBB[n]250 are routed to the metal strip of the M0 layer.

[0077] At stage 630 of method 600, via 0 310 is formed. A first end of via 0 310 is connected to a first read bit line pair. At step 640 of method 600, a metal strip of layer M1 is deposited and patterned. As described above, the metal strip of layer M1 is separated from layer M0 in the vertical direction. A second end of via 0 310 is connected to the metal strip of layer M1, thereby connecting the metal strip of layer M1 to the first read bit line pair.

[0078] The metal strip of layer M1 is connected to the metal strip of layer M0 through via 0310. For example, the metal strip of layer M0 is connected to the metal strip of layer M1 to propagate the BL signal from layer M0 to layer M1 in the vertical direction.

[0079] At stage 650 of method 600, a via 1362 is formed. The first end of the via 1362 is connected to a metal strip in layer M1. At stage 660 of method 600, a metal strip in layer M2 is deposited and patterned. As described above, the metal strip in layer M2 is separated from layer M1 in the vertical direction.

[0080] The metal strip of layer M2 is connected to the metal strip of layer M1 through via 1362, thereby connecting the first read bit line pair to the first fly-through read bit line pair. For example, the metal strip of layer M1 is connected to the metal strip of layer M2 to propagate the BL signal from layer M1 to layer M2 in the vertical direction. In this example, higher layers (e.g., layer M3, layer M4, etc.) are formed by repeating stages 650 and 660 of method 600.

[0081] Figure 11 This is a flowchart illustrating a second method 700 for forming any one of memory device 200, memory device 400, or memory device 500 according to some embodiments. Method 700 can be performed by a layout system 800, as referenced in this disclosure. Figure 12 The above discussion focuses on how, in some examples, method 700 can be stored as an instruction on a memory device, allowing the processor to execute method 700 when it is run. The implementation of each stage of method 700 will be described in more detail below.

[0082] At stage 710 of method 700, an array having multiple memory cells is formed. This array includes a first region 202 and a second region 204. The second region 204 is closer to the I / O circuitry of the memory device 200 than the first region 202. For example, it can be formed as described above. Figure 1 The array of the 10T 2R1W memory cells.

[0083] At stage 720 of method 700, write BL pairs are formed in the first metal layer. The write BL pairs are connected to the first plurality of memory cells of the array column. For example, write BL 245 (i.e., WB[n]245) and complementary write BL 250 (i.e., WBB[n]250) are formed in the M0 layer.

[0084] At stage 730 of method 700, a connection unit 210 is formed between the first region 202 and the second region 204. The connection unit 210 includes vertical interconnects that can connect write BL pairs to fly-through write BL pairs.

[0085] At step 740 of method 700, a fly-through write BL pair is formed in a second metal layer perpendicular to the write BL pair. For example, a fly-through write BL 255 (i.e., FWB[n]255) and a complementary fly-through write BL 260 (i.e., FWBB[n]260) are formed in layer M2. The fly-through write BL is connected to the write BL via connection unit 210. In some examples, as described above, the write BL is connected to the fly-through write BL at multiple locations, such as at top region 202, bottom region 204, and connection unit 210. Therefore, the write signal propagates through the write BL and the fly-through write BL.

[0086] The process disclosed herein accelerates array read access time and reduces power consumption during read operations. Furthermore, as described above, connecting the BL to a fly-through BL helps reduce BL load and minimizes interference between the top and bottom regions of the array. Layered metal wiring for the fly-through BL (e.g., M2 or M4 layer wiring) provides greater wiring flexibility, especially in large memory macros with severe signal congestion.

[0087] Figure 12 This is a block diagram of a layout system 800 according to some embodiments. For example, the layout system 800 can be used to implement the methods described herein for memory device 200, memory device 400, or memory device 500 according to one or more embodiments. In some embodiments, the layout system 800 is a general-purpose computing device including a hardware processor 802 and a non-transitory computer-readable storage medium (also referred to as memory) 804. The storage medium 804, among others, is encoded with computer program code 806, i.e., a set of executable instructions. The execution of the instructions 806 by the hardware processor 802 represents (at least partially) an EDA tool that implements respectively... Figure 10 and Figure 11 Some or all of the methods 600 and 700 described for forming memory device 200.

[0088] Processor 802 is electrically coupled to computer-readable storage medium 804 via bus 808. Processor 802 is also electrically coupled to I / O interface 810 via bus 808. Network interface 812 is also electrically connected to processor 802 via bus 808. Network interface 812 is connected to network 814, enabling processor 802 and computer-readable storage medium 804 to be connected to external components via network 814. Processor 802 is configured to execute computer program code 806 encoded in computer-readable storage medium 804 to make layout system 800 available for performing part or all of the process and / or method. In one or more embodiments, processor 802 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0089] In one or more embodiments, the computer-readable storage medium 804 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 804 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 804 includes optical disc read-only memory (CD-ROM), optical disc read / write (CD-R / W), and / or digital video disc (DVD).

[0090] In one or more embodiments, computer-readable storage medium 804 stores computer program code 806 configured to enable layout system 800 (where such execution representation (at least partially) EDA tools) to perform some or all of the said processes and / or methods. In one or more embodiments, computer-readable storage medium 804 also stores information that facilitates the execution of some or all of the said processes and / or methods. In one or more embodiments, computer-readable storage medium 804 stores a cell library 807 of memory cells, including those described herein. Figure 1 Publicly available memory cells.

[0091] The layout system 800 includes an I / O interface 810. The I / O interface 810 is coupled to external circuitry. The I / O interface 810 may include a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to the processor 802.

[0092] The layout system 800 also includes a network interface 812 coupled to the processor 802. The network interface 812 allows the layout system 800 to communicate with a network 814 to which one or more other computer systems are connected. The network interface 812 may include a wireless network interface or a wired network interface.

[0093] The layout generation system 800 is configured to receive information via I / O interface 810. The information received via I / O interface 810 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 802. This information is transmitted to processor 802 via bus 808. The layout system 800 is also configured to receive UI-related information via I / O interface 810. This information is stored as a user interface (UI) 842 in computer-readable medium 804.

[0094] According to some embodiments, a memory device includes: an array comprising a plurality of columns, wherein each of the plurality of columns includes: a first read bit line pair connected to a first portion of a memory cell in a top region of the column; a second read bit line pair connected to a second portion of a memory cell in a bottom region of the column; and a first fly-over read bit line pair; and a connection unit located between the top region and the bottom region, wherein the connection unit includes a vertical interconnect connecting the first read bit line pair to the first fly-over read bit line pair.

[0095] In some embodiments, each of the first read bit line pair and the second read bit line pair is formed in the first metal layer.

[0096] In some embodiments, a first fly-through read bit line pair is formed in a second metal layer, wherein the second metal layer is different from the first metal layer.

[0097] In some embodiments, a first fly-through read bit line pair is formed in metal layer four, and each of the first read bit line pair and the second read bit line pair is formed in metal layer zero.

[0098] In some embodiments, the connection unit is formed by a dual read-write (2R1W) 10-transistor (10T) static random access memory (SRAM) cell.

[0099] In some embodiments, the first portion and the second portion of the memory cell include a dual read-write (2R1W) 10-transistor (10T) static random access memory (SRAM) cell.

[0100] In some embodiments, the memory device further includes a pair of write bit lines connected to a first portion of the memory cell in the column and a second portion of the memory cell.

[0101] In some embodiments, the memory device further includes a fly-over write bit line pair, wherein the fly-over write bit line pair is connected to the write bit line pair via a vertical interconnect of the connection unit.

[0102] According to some embodiments, a memory device includes: an array including a first region and a second region, wherein the second region is closer to an input / output (I / O) circuitry of the memory device than the first region; a first read bit line pair connected to a first portion of a memory cell in the first region of a column of the array; a second read bit line pair connected to a second portion of a memory cell in the second region of a column; a first fly-over read bit line pair; and a connection unit located between the first region and the second region, wherein the connection unit includes a vertical interconnect connecting the first read bit line pair to the first fly-over read bit line pair.

[0103] In some embodiments, the connection unit is formed by a dual read-write (2R1W) 10-transistor (10T) static random access memory (SRAM) cell.

[0104] In some embodiments, the connection unit includes a first wiring layer, wherein the first wiring layer vertically connects a first read bit line pair from metal layer zero to metal layer one via via zero.

[0105] In some embodiments, the connection unit further includes a second wiring layer, wherein the second wiring layer vertically connects the first metal layer to the second metal layer through a through-hole.

[0106] In some embodiments, the first read bit line pair does not extend into the second region.

[0107] In some embodiments, a first read bit line pair is formed in a first metal layer, wherein a first fly-through read bit line pair is formed in a second metal layer, and wherein the second metal layer is separated from the first metal layer in a vertical direction.

[0108] In some embodiments, a first read bit line pair is formed in metal layer zero, and a first fly-through read bit line pair is formed in metal layer four.

[0109] In some embodiments, the memory device further includes a pair of write bit lines connected to a first portion of the memory cell in the column and a second portion of the memory cell.

[0110] In some embodiments, the memory device further includes a fly-over write bit line pair, wherein the fly-over write bit line pair is connected to the write bit line pair via a vertical interconnect of the connection unit.

[0111] According to an example embodiment, a method of forming a memory device includes: forming a plurality of memory cells in an array, wherein the array includes a first region and a second region, wherein the second region is closer to an input / output (IO) circuit of the memory device than the first region; forming write bit line pairs in a first metal layer, wherein the write bit line pairs are connected to a first plurality of memory cells in a column of the array; forming a connection unit located between the first region and the second region; and forming a first fly-through write bit line pair in a second metal layer perpendicularly separated from the write bit line pairs, wherein the connection unit includes a vertical interconnect connecting the write bit line pairs to the first fly-through write bit line pairs.

[0112] In some embodiments, the method further includes forming a second fly-through write bit pair in a second metal layer that is perpendicularly separated from the first fly-through write bit pair.

[0113] In some embodiments, a first fly-through write bit line pair is formed in metal layer two, and a second fly-through write bit line pair is formed in metal layer four.

[0114] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to them within this disclosure without departing from its spirit and scope.

Claims

1. A memory device, comprising: An array comprising multiple columns, wherein each of the multiple columns includes: a first read bit line pair connected to a first portion of a memory cell in the top region of the column; a second read bit line pair connected to a second portion of a memory cell in the bottom region of the column; and a first fly-over read bit line pair; and A connection unit is located between the top region and the bottom region, wherein the connection unit includes a vertical interconnect that connects the first read bit line pair to the first fly-over read bit line pair.

2. The memory device according to claim 1, wherein, Each of the first read bit line pair and the second read bit line pair is formed in the first metal layer.

3. The memory device according to claim 2, wherein, The first fly-through read bit line pair is formed in the second metal layer, wherein the second metal layer is different from the first metal layer.

4. The memory device according to claim 2, wherein, The first fly-through read bit line pair is formed in metal layer four, and each of the first read bit line pair and the second read bit line pair is formed in metal layer zero.

5. The memory device according to claim 1, wherein, The connection unit is formed by a dual-read-write 10-transistor static random access memory unit.

6. The memory device of claim 1, further comprising a pair of write bit lines connected to the first portion of the memory cell and the second portion of the memory cell in the column.

7. A memory device, comprising: The array includes a first region and a second region, wherein the second region is closer to the input / output circuitry of the memory device than the first region; The first read bit line pair is connected to a first portion of the memory cell in the first region of the column of the array; The second read bit line pair is connected to the second portion of the memory cell in the second region of the column; First flyby read bit pair; and A connection unit is located between the first region and the second region, wherein the connection unit includes a vertical interconnect that connects the first read bit line pair to the first fly-over read bit line pair.

8. The memory device according to claim 7, wherein, The connection unit includes a first wiring layer, wherein the first wiring layer connects the first read bit line pair vertically from metal layer zero to metal layer one via via zero.

9. The memory device according to claim 7, wherein, The first read bit line pair is formed in a first metal layer, wherein the first fly-through read bit line pair is formed in a second metal layer, and wherein the second metal layer is separated from the first metal layer in a vertical direction.

10. A method of forming a memory device, the method comprising: A plurality of memory cells forming an array, wherein the array includes a first region and a second region, wherein the second region is closer to the input / output circuitry of the memory device than the first region; Write bit line pairs are formed in a first metal layer, wherein the write bit line pairs are connected to a first plurality of memory cells in a column of the array; Forming a connection unit located between the first region and the second region; and A first fly-through write bit line pair is formed in a second metal layer perpendicularly separated from the write bit line pair, wherein the connection unit includes a vertical interconnect that connects the write bit line pair to the first fly-through write bit line pair.

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