A low power enhanced read type 11t cnfet sram cell circuit

Abstract

The application belongs to the field of integrated circuits, and specifically provides a low-power consumption enhanced reading type 11T CNFET SRAM cell circuit to solve the problems of slow speed, low stability, high power consumption and the like in the prior art; the application comprises N-type carbon nanometer field effect transistors MN1-MN9 and P-type carbon nanometer field effect transistors MP1-2, on the basis of a conventional 6T SRAM cell circuit, a dynamic load structure composed of transistors MN7, MN8 and MN9, and a high-resistance differential readout circuit composed of transistors MN3, MN4, MN5 and MN6; the adoption of P-type transistors realizes a bistable latch structure to reduce holding and writing power consumption, eliminate path competition phenomena caused by data flipping during writing, and improve writing speed; during reading, a resistive load tube is turned on to eliminate charge accumulation and ensure data storage stability; the high-resistance differential readout circuit reduces voltage disturbance of a storage node caused by bit line load; meanwhile, the differential writing / reading circuit can suppress common-mode noise and external interference on the bit line, reduce the probability of error sampling, and enhance overall anti-interference capability.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuits and relates to SRAM cell circuits, specifically providing a low-power enhanced read-type 11T CNFET SRAM cell circuit. Background Technology

[0002] In system-on-chip and high-speed signal processing circuits, static random access memory (SRAM) is often used for high-speed data temporary storage and caching, which is then handed over to the processor or digital signal processing module for calculation and control. Static noise margin, read / write speed and power consumption are the core indicators for measuring the performance of SRAM cells. Static noise margin determines the stability of data retention, read / write speed determines the system response efficiency, and power consumption determines the battery life of portable devices and IoT terminals.

[0003] Currently, commonly used traditional 6T SRAM cell structures, such as Figure 1 As shown, for this type of SRAM cell, there is an inherent mutual constraint between its read / write performance and power consumption: at low power supply voltage, in order to ensure sufficient driving capability and noise margin, it is usually necessary to increase the device size or increase the operating current, which leads to a significant increase in power consumption; while reducing power consumption and shrinking device size will reduce static noise margin, worsen read / write reliability, and significantly aggravate short-channel effect, drain-induced barrier reduction effect and subthreshold leakage current.

[0004] During the data retention phase, the cross-coupled inverters of traditional 6T SRAM cells always have a static discharge path. Even when not selected for access, a continuous subthreshold leakage current flows through the memory node, resulting in high static power consumption. With advanced nanotechnology, device size continues to shrink, and source-drain tunneling current and gate leakage current further increase, causing array-level static power consumption to account for most of the total power consumption, severely limiting low-power applications.

[0005] During the write operation phase, traditional 6T SRAM relies on bit lines to forcefully pull and flip memory nodes. The write path and hold path directly compete. When the power supply voltage drops, the write drive capability is insufficient, which can easily lead to write failures and slow write speeds. At the same time, write interference can be transmitted to adjacent cells, causing half-select interference and data flipping, which affects the overall stability of the array.

[0006] During the read operation phase, the storage nodes of a traditional 6T SRAM are directly connected to the bit lines. The parasitic capacitance of the bit lines and the read current will cause significant disturbances to the storage node voltage, resulting in the storage "0" potential being raised and the storage "1" potential being pulled down. This can reduce the read noise margin or even directly cause the storage data to flip, resulting in read errors. Under low voltage conditions, this disturbance is further amplified, causing a sharp drop in read reliability.

[0007] It is evident that traditional 6T SRAM cells cannot simultaneously achieve low voltage, low power consumption, and high stability. To meet noise margin and read / write speed requirements, a significant power consumption cost is often required; while in pursuing low power consumption, stability and speed must be sacrificed. Summary of the Invention

[0008] The purpose of this invention is to provide a low-power enhanced read-mode 11T CNFET SRAM cell circuit to solve the problems of slow speed, low stability, and high power consumption in existing SRAM cell circuits. This invention is based on a carbon nanotube field-effect transistor design, using only P-type transistors to achieve a bistable latch structure, reducing hold and write power consumption, eliminating path contention that causes data flipping during writes, and improving write speed. During reads, a resistive load transistor is turned on to eliminate charge accumulation, ensuring data storage stability. A high-impedance differential readout circuit is used to reduce voltage disturbances to the storage node caused by bit line load charging and discharging. The circuit uses differential input and output, which can suppress common-mode noise and external interference on the bit lines, reduce the probability of incorrect sampling, and enhance overall anti-interference capability.

[0009] To achieve the above objectives, the technical solution adopted by this invention is as follows: a low-power enhanced read-type 11T CNFETSRAM cell circuit, comprising: transistors MN1~MN9 and transistors MP1~MP2. Specifically: the source of transistor MN1 and the drain of transistor MN3 are both connected to bit line BL; the source of transistor MN2 and the drain of transistor MN5 are both connected to complementary bit line BLB; the gates of transistors MN1 and MN2 are both connected to write word line WWL; and the gates of transistors MN3, MN5, and MN9 are all connected to read word line RWL. The source of transistor MN3 and the drain of transistor MN4 are connected; the source of transistor MN5 and the drain of transistor MN6 are connected; and the drains of transistors MN1 and MN7 and the gates of transistor MN6 are connected. The drain of transistor MP1 and the gate of transistor MP2 are connected. The drain of transistor MN2, the drain of transistor MN8, the gate of transistor MN4, the gate of transistor MP1, and the drain of transistor MP2 are connected. The gate of transistor MN7, the gate of transistor MN8, and the source of transistor MN9 are connected. The drain of transistor MN9 is connected to the reference voltage VB. The sources of transistor MP1 and transistor MP2 are both connected to the power supply. The sources of transistor MN4, transistor MN6, transistor MN7, and transistor MN8 are all connected to ground.

[0010] Furthermore, transistors MP1 and MP2 constitute a bistable latch structure.

[0011] Furthermore, transistors MN1 and MN2 constitute a differential write circuit.

[0012] Furthermore, during the read operation, transistor MN9 turns on to bias transistors MN7 and MN8, making transistors MN7 and MN8 the resistive load of the bistable latch during the read operation.

[0013] Furthermore, transistors MN3, MN4, MN5, and MN6 constitute a high-impedance differential readout circuit.

[0014] Furthermore, transistors MN1~MN9 and transistors MP1~MP2 all employ carbon nanotube field-effect transistors.

[0015] Based on the above technical solution, the beneficial effects of the present invention are as follows: The present invention provides a low-power enhanced read-type 11T CNFET SRAM cell circuit. Based on the traditional 6T SRAM structure, it introduces a dynamic load structure composed of transistors MN7, MN8, and MN9, and a high-impedance differential readout circuit composed of transistors MN3, MN4, MN5, and MN6. It employs a P-type transistor bistable latch structure to reduce holding and writing power consumption, eliminates path contention during data flipping in complementary CMOS bistable latch structures, and improves writing speed. The dynamic load structure conducts the load transistors during reading to discharge accumulated charge, strengthening bistable latching and ensuring data storage stability. The high-impedance differential readout circuit reduces voltage disturbances to the storage node caused by bit line load, enhancing read reliability. Simultaneously, the differential write / read circuit suppresses common-mode noise and external interference on the bit lines, reducing the probability of incorrect sampling and enhancing overall anti-interference capability.

[0016] Attached image description: Figure 1 This is a schematic diagram of the circuit structure of a traditional 6T SRAM cell circuit. Figure 2 This is a schematic diagram of the circuit structure of the low-power enhanced read-type 11T CNFET SRAM cell circuit in this invention. Figure 3 This is a comparison diagram of the storage node voltage during a read operation of the SRAM cell circuit in the embodiments and comparative examples of the present invention. To make the objectives, technical solutions, and beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0017] This embodiment provides a low-power enhanced read-type 11T CNFET SRAM cell circuit, the circuit structure of which is as follows: Figure 2 As shown, BL is the bit line of the 11T CNFET SRAM circuit, BLB is the complementary bit line of the 11T CNFET SRAM circuit, WWL is the write word line of the 11T CNFET SRAM circuit, RWL is the read word line of the 11T CNFET SRAM circuit, VDD is the power supply, and GND is the analog ground.

[0018] Specifically, the 11T CNFET SRAM cell circuit includes: carbon nanotube field-effect transistor MN1, carbon nanotube field-effect transistor MN2, carbon nanotube field-effect transistor MN3, carbon nanotube field-effect transistor MN4, carbon nanotube field-effect transistor MN5, carbon nanotube field-effect transistor MN6, carbon nanotube field-effect transistor MN7, carbon nanotube field-effect transistor MN8, carbon nanotube field-effect transistor MN9, carbon nanotube field-effect transistor MP1, and carbon nanotube field-effect transistor MP2. Specifically: the source of carbon nanotube field-effect transistor MN1 and the drain of carbon nanotube field-effect transistor MN3 are both connected to bit line BL; the source of carbon nanotube field-effect transistor MN2 and the drain of carbon nanotube field-effect transistor MN5 are both connected to complementary bit line BLB; the gates of carbon nanotube field-effect transistors MN1 and MN2 are both connected to write word line WWL; the gates of carbon nanotube field-effect transistors MN3, MN5, and MN9 are all connected to read word line RWL; the source of carbon nanotube field-effect transistor MN3 and the drain of carbon nanotube field-effect transistor MN4 are connected; the source of carbon nanotube field-effect transistor MN5 and the drain of carbon nanotube field-effect transistor MN6 are connected; the drain of carbon nanotube field-effect transistor MN1, the drain of carbon nanotube field-effect transistor MN7, the gate of carbon nanotube field-effect transistor MN6, and the gate of carbon nanotube field-effect transistor M... The drain of P1 and the gate of MP2 are connected (connection point Q); the drain of MN2, the drain of MN8, the gate of MN4, the gate of MP1, and the drain of MP2 are connected (connection point Q_b); the gate of MN7, the gate of MN8, and the source of MN9 are connected, and the drain of MN9 is connected to the reference voltage VB; the sources of MP1 and MP2 are connected to the power supply, and the sources of MN4, MN6, MN7, and MN8 are connected to ground.

[0019] Furthermore, the carbon nanotube field-effect transistors MP1 and MP2 constitute a bistable latch structure.

[0020] Furthermore, the carbon nanotube field-effect transistor MN1 constitutes a differential writing circuit.

[0021] Furthermore, during the read operation, the carbon nanotube field-effect transistor MN9 is turned on to bias the carbon nanotube field-effect transistors MN7 and MN8, making the carbon nanotube field-effect transistors MN7 and MN8 the resistive load of the bistable latch during the read operation.

[0022] Furthermore, the carbon nanotube field-effect transistors MN3, MN4, MN5, and MN6 constitute a high-impedance differential readout circuit.

[0023] In terms of working principle: such as Figure 2 As shown, in the 11T CNFET SRAM cell circuit proposed in this invention, carbon nanotube field-effect transistors MP1 and MP2 constitute a bistable latch structure; carbon nanotube field-effect transistors MN7, MN8, and MN9 constitute a dynamic load structure; and carbon nanotube field-effect transistors MN3, MN4, MN5, and MN6 constitute a high-impedance differential readout circuit. The use of P-type transistors to implement the bistable latch structure reduces holding and writing power consumption; the dynamic load structure conducts the load transistors during reading to discharge accumulated charge, enhancing bistable latching and ensuring data storage stability; and the high-impedance differential readout circuit reduces voltage disturbances to the storage node caused by bit line load.

[0024] During the write operation, carbon nanotube field-effect transistors MN1 and MN2 are turned on, and data is loaded into data storage nodes Q and Q_b via complementary bit lines BL and BLB. The data within the cell is then latched by carbon nanotube field-effect transistors MP1 and MP2. Because carbon nanotube field-effect transistor MN9 is turned off during writing, the storage node lacks the pull-down path of a traditional 6T SRAM cell circuit. This eliminates the path contention phenomenon caused by data flipping during writing in traditional 6T SRAM cell circuits, thereby improving write speed and reducing write power consumption.

[0025] During hold operations, the carbon nanotube field-effect transistor MN9 is in the off state, and the data within the cell is latched by carbon nanotube field-effect transistors MP1 and MP2. The pull-down path currents at memory nodes Q and Q_b are extremely weak and negligible, thus significantly reducing hold and write power consumption.

[0026] During the read operation, on one hand, the carbon nanotube field-effect transistor MN9 is turned on, and VB is loaded onto the gates of pull-down load transistors MN7 and MN8, putting them in a subthreshold conducting state to discharge the accumulated charge of the storage node and stabilize the storage node voltages Q and Q_b, enhancing bistable latching. On the other hand, the differential read carbon nanotube field-effect transistors MN3 and MN5 are turned on. The storage node voltages Q and Q_b determine the switching states of carbon nanotube field-effect transistors MN4 and MN6. When Q stores "1" and Q_b stores "0", carbon nanotube field-effect transistors MN6 and MN5 form a current path from BLB to ground, pulling BLB down to "0", while carbon nanotube field-effect transistor MN4 is turned off and MN3 is turned on, keeping the BL voltage unchanged. Due to the infinite input impedance of carbon nanotube field-effect transistors MN4 and MN6, this design ensures the stability of the storage node voltage during the read operation, significantly improving read performance, avoiding bit flipping during the read process, and enhancing read reliability.

[0027] The circuit uses differential signals for both writing and reading, which can effectively suppress common-mode noise and external interference on the bit lines, reduce the probability of incorrect sampling, and enhance the overall anti-interference capability.

[0028] In summary, as shown in the following Figure 1 The conventional 6T SRAM cell circuit shown is a comparative example. The comparison results of the storage node voltage during read operation between the SRAM cell circuits in this embodiment and the comparative example are as follows: Figure 3 As shown, the voltage fluctuation of the 11T CNFET SRAM cell circuit provided by this invention during the reading of data 1 is 16mV, which is 7% of that of the traditional 6T SRAM cell circuit. The comparison results of the read / write time and power consumption of the SRAM cell circuit in this embodiment and the comparative example are shown in the table below. The 11T CNFET SRAM cell circuit provided by this invention improves the speed of writing 0 by 79.07%, the speed of writing 1 by 85.19%, the speed of reading 0 by 38.18%, the speed of reading 1 by 38.18%, the power consumption of holding 0 by 68.86%, and the power consumption of holding 1 by 61.85%.

[0029] Table 1. Comparison of read / write times between 11T CNFET SRAM cell circuit and traditional 6T SRAM cell circuit. Write 0 5.35 1.12 79.07% Write 1 3.51 0.52 85.19% Read 0 0.55 0.34 38.18% Read 1 0.55 0.34 38.18%

[0030] Table 2 Comparison of Power Consumption Between 11T CNFET SRAM Cell Circuit and Traditional 6T SRAM Cell Circuit Hold 0 3.95 1.23 68.86% Hold 1 3.25 1.24 61.85%

[0031] The above description is merely a specific embodiment of the present invention. Any feature disclosed in this specification may be replaced by other equivalent or similar features unless otherwise specified. All disclosed features, or steps in all methods or processes, may be combined in any way except for mutually exclusive features and / or steps.

Claims

1. A low-power enhanced read-type 11T CNFET SRAM cell circuit, comprising: Transistors MN1~MN9, transistors MP1~MP2; characterized in that: The source of transistor MN1 and the drain of transistor MN3 are both connected to bit line BL; the source of transistor MN2 and the drain of transistor MN5 are both connected to complementary bit line BLB; the gates of transistors MN1 and MN2 are both connected to write word line WWL; and the gates of transistors MN3, MN5, and MN9 are all connected to read word line RWL. The source of transistor MN3 and the drain of transistor MN4 are connected; and the source of transistor MN5 and the drain of transistor MN6 are connected. The drain of transistor MN1, the drain of transistor MN7, the gate of transistor MN6, the drain of transistor MP1, and the gate of transistor MP2 are connected; the drain of transistor MN2, the drain of transistor MN8, the gate of transistor MN4, the gate of transistor MP1, and the drain of transistor MP2 are connected; the gate of transistor MN7, the gate of transistor MN8, and the source of transistor MN9 are connected; the drain of transistor MN9 is connected to the reference voltage VB. The sources of transistors MP1 and MP2 are connected to the power supply, while the sources of transistors MN4, MN6, MN7, and MN8 are connected to ground.

2. The low-power enhanced readability 11T CNFET SRAM cell circuit according to claim 1, characterized in that, Transistors MP1 and MP2 constitute a bistable latch structure.

3. The low-power enhanced read-type 11T CNFET SRAM cell circuit according to claim 1, characterized in that, Transistors MN1 and MN2 constitute a differential write circuit.

4. The low-power enhanced readability 11T CNFET SRAM cell circuit according to claim 1, characterized in that, During a read operation, transistor MN9 is turned on to bias transistors MN7 and MN8, making transistors MN7 and MN8 the resistive load of the bistable latch during the read operation.

5. The low-power enhanced readability 11T CNFET SRAM cell circuit according to claim 1, characterized in that, Transistors MN3, MN4, MN5, and MN6 constitute a high-impedance differential readout circuit.

6. The low-power enhanced readability 11T CNFET SRAM cell circuit according to claim 1, characterized in that, Transistors MN1~MN9 and transistors MP1~MP2 all employ carbon nanotube field-effect transistors.

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