Storage system and method of operating the same

Abstract

The present disclosure relates to a storage system and an operating method thereof. An operating method of a storage system includes receiving a first write command and first write data, the first write data including first reset data and first set data, counting a number of the first reset data, comparing the number of the first reset data with a first threshold value, storing the first write data in a first storage unit, checking a number of first turned-on storage cells in the first storage unit by providing a read voltage having a specific voltage level to the first storage unit, calculating a comparison value based on the number of the first turned-on storage cells, comparing the comparison value with a second threshold value to determine whether to perform a sneak path processing algorithm operation, and re-storing the write data in the first storage unit.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2025-0020834, filed with the Korean Intellectual Property Office on February 18, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The implementation methods relate to integrated circuit technology, and more specifically, to memory systems and methods of operation thereof. Background Technology

[0004] Recently, with the reduction in size, power consumption, performance improvement, and functional diversification of electronic devices, many electronic devices (such as computers and portable communication devices) require memory capable of storing information. Furthermore, research on memory with various characteristics is ongoing.

[0005] The memories under investigation also include those capable of storing data by utilizing the property that the memory switches between different resistance states depending on the voltage or current applied to it. Such memories include resistive random access memory (RRAM), phase-change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), electric fuse (E-fuse), and selector-only memory (SOM). Summary of the Invention

[0006] In one embodiment, an operation method of a storage system may include: receiving a first write command and first write data; counting the number of first reset data in the first write data; checking whether the number of first reset data is greater than a first threshold and storing the first write data in a first storage cell; checking the number of first conducting storage cells in the first storage cell by providing a read voltage having a set voltage level to the first storage cell; calculating a comparison value by comparing the number of first reset data with the number of first conducting storage cells; and checking whether the comparison value is equal to or less than a second threshold and storing the write data in the first storage cell.

[0007] In one embodiment, an operation method of a storage system may include: receiving a first write command and first write data; counting the number of first reset data in the first write data; checking whether the number of first reset data is equal to or less than a first threshold and storing the first write data in a first storage cell; and accumulating and storing the ratio of the first reset data to the first set data in the first write data.

[0008] In one embodiment, a storage system may include: a storage device including a plurality of storage cells; a controller configured to receive write commands and write data, configured to count the number of reset data for the write data, and configured to transmit the write commands and write data to the storage device; and a buffer memory configured to store the write data under the control of the controller, and configured to transmit the stored write data to the controller. Attached Figure Description

[0009] Figure 1 This is a diagram used to describe the storage cells of a storage device according to an embodiment of the present disclosure.

[0010] Figure 2 and Figure 3 This is a diagram used to describe the write operation of a storage device according to an embodiment of the present disclosure.

[0011] Figure 4 This is a diagram used to describe the read operation of a storage device according to an embodiment of the present disclosure.

[0012] Figure 5 and Figure 6 This is a diagram used to describe the creeping current of a storage device according to an embodiment of the present disclosure.

[0013] Figure 7 This is a flowchart of an operation method of a storage system according to an embodiment of the present disclosure.

[0014] Figure 8 It is used to describe references Figure 7 A diagram illustrating the set voltage reading operation.

[0015] Figure 9 , Figure 10A and Figure 10B It is used to describe references Figure 7 A diagram illustrating the operation method of the described stealth processing algorithm.

[0016] Figure 11 This is a diagram used to describe a storage system according to an embodiment of the present disclosure.

[0017] Figure 12 This is a flowchart of an operation method of a storage system according to another embodiment of the present disclosure. Detailed Implementation

[0018] Hereinafter, embodiments based on the technical spirit of this disclosure will be described with reference to the accompanying drawings.

[0019] Embodiments of this disclosure provide a technique for monitoring creeping currents.

[0020] It can improve the data storage reliability of the storage unit.

[0021] Figure 1 This is a diagram used to describe the storage cells of a storage device according to an embodiment of the present disclosure.

[0022] refer to Figure 1 According to embodiments of the present disclosure, the memory cell MC of the memory device can be disposed between the bit line BL and the word line WL. Furthermore, the memory cell MC can be electrically connected to the bit line BL and the word line WL. In this case, Figure 1 The diagram shows a bit line BL positioned above a word line WL. However, according to one embodiment, the bit line BL may be positioned below the word line WL. Furthermore, both the bit line BL and the word line WL may comprise a conductive material.

[0023] The storage cell MC may include a first electrode TE, a storage material MM, and a second electrode BE. The storage material MM may be disposed between the first electrode TE and the second electrode BE. In this case, both the first electrode TE and the second electrode BE may include conductive materials. The threshold voltage level of the storage material MM may vary depending on the direction of the current flowing through the storage material MM. The storage material MM may include chalcogenide series materials.

[0024] For example, a second electrode BE can be formed on a word line WL. Storage material MM can be formed on the second electrode BE. A first electrode TE can be formed on the storage material MM. A bit line BL can be formed on the first electrode TE. In this case, the first electrode TE, which is positioned higher than the second electrode BE, is referred to as the upper electrode TE depending on its formation position. The second electrode BE, which is positioned lower than the first electrode TE, is referred to as the lower electrode BE depending on its formation position.

[0025] Figure 2 and Figure 3 This is a diagram used to describe the write operation of a storage device according to an embodiment of the present disclosure.

[0026] Figure 2 This could be a diagram illustrating a write operation when the write current WC flows from the word line WL through the memory cell MC to the bit line BL. The write operation can be an operation that supplies voltage to the word line WL and the bit line BL, where the voltage level difference between the word line WL and the bit line BL is greater than the voltage level at which the memory cell MC can be turned on. In this case, a voltage higher than the voltage on the bit line BL can be supplied to the word line WL.

[0027] Such a write operation can be an operation that alters the properties of the memory material MMC, allowing current to flow more easily through the memory material MM in a first direction than in a second direction. In this case, the first direction could be the direction in which current flows from the word line WL through the memory material MM to the bit line BL. The second direction could be the direction in which current flows from the bit line BL through the memory material MM to the word line WL.

[0028] Figure 3 This could be a diagram illustrating a write operation when write current WC flows from bit line BL through memory cell MC to word line WL. The write operation can be an operation that supplies voltage to both bit line BL and word line WL, where the voltage level difference between them is greater than the voltage level at which memory cell MC can be turned on. In this case, a higher voltage can be supplied to bit line BL than to word line WL.

[0029] Such a write operation can be an operation that alters the properties of the memory material MM, allowing current to flow more easily through the MM in a second direction than in the first direction. In this case, the first direction could be the direction in which current flows from the word line WL through the memory material MM to the bit line BL. The second direction could be the direction in which current flows from the bit line BL through the memory material MM to the word line WL.

[0030] Figure 4 This is a diagram used to describe the read operation of a storage device according to an embodiment of the present disclosure.

[0031] refer to Figure 4 A read operation can be performed by providing a voltage higher than the word line WL to the bit line BL to identify the state of the memory cell MC. In this case, the read operation can be performed by causing the read current RC to move along the line... Figure 3 The write current WC flows in the same direction as the write current after the write operation begins, as shown in the diagram. Furthermore, the voltage level difference between the bit line BL and the word line WL after the read operation begins can correspond to the read voltage V. read The voltage level. Read the voltage V. read It can have a middle ground according to Figure 2 The threshold voltage level of the memory cell MC in the write operation shown is related to the level of the write operation. Figure 3 The voltage levels between the threshold voltage levels of the memory cell MC during the write operation shown.

[0032] Therefore, if the memory cell MC is executed Figure 4 The read operation shown indicates that the storage material properties of the storage cell MC, MMC, have been verified as follows: Figure 3As shown in the diagram, the write operation changes the flow of the write current WC from the bit line BL to the word line WL. Therefore, the read current RC can flow from the bit line BL through the conducted memory cell MC to the word line WL. At this time, due to the characteristics of the storage material MMC, it has already flowed through… Figure 3 The threshold voltage level of the memory cell MC changed by the write operation shown can be lower than the read voltage V. read The voltage level is such that the memory cell MC can be turned on.

[0033] like Figure 4 As shown, if the MMC for the storage material properties has been passed... Figure 2 If the memory cell MC, altered by the write operation shown, performs a read operation, the read current FRC may not flow. In this case, due to the storage material properties MMC, the current has already been transferred. Figure 2 The write operation shown alters the threshold voltage level of the memory cell MC to a level higher than the read voltage V. read The voltage level is low, so the memory cell MC may not be conducting. Therefore, the read current RC may not flow.

[0034] Having a higher reading voltage V read A memory cell MC with a low threshold voltage can be considered in a set state (SET). This has a higher threshold voltage than the read voltage V. read A high-level threshold voltage in the memory cell MC can be said to be in a reset state (RESET or RST).

[0035] In other words, the state of the memory cell MC can be obtained through Figure 3 The write operation shown will put the device in (for example, change it to) the set state. Furthermore, the state of the memory cell MC can be determined through... Figure 2 The write operation shown causes the memory cell MC to be in a reset state (e.g., become) RESET. In this case, the write operation that changes the state of the memory cell MC to the set state SET can be called a set write operation. The write operation that changes the state of the memory cell MC to the reset state RESET can be called a reset write operation.

[0036] Figure 5 and Figure 6 This is a diagram used to describe the creeping current of a storage device according to an embodiment of the present disclosure.

[0037] Figure 5 A memory array comprising multiple memory cells MC can be illustrated, with these memory cells MC connected between multiple word lines WL and multiple bit lines BL. In this case, the memory device may include a memory array comprising multiple memory cells MC.

[0038] The state of each memory cell in a plurality of memory cells MC can be changed to either a set state (SET) or a reset state (RESET) through a set write operation or a reset write operation. As mentioned above, the threshold voltage level of a memory cell MC in the set state (SET) can be lower than the threshold voltage level of a memory cell MC in the reset state (RESET).

[0039] Therefore, a relatively large amount of creeping current can flow through the memory cell MC in the set state compared to the memory cell MC in the reset state.

[0040] like Figure 5 As shown, when the number of memory cells MC in the set state is greater than the number of memory cells MC in the reset state, the creeping current flowing through the memory cell array including multiple memory cells MC will increase.

[0041] Figure 6 It can be a diagram used to describe the operation that causes an error in a read operation when the amount of creeping current increases.

[0042] Storage devices can perform a read operation to check whether the memory cell MC is turned on by detecting the voltage level of the bit line BL or word line WL.

[0043] Because the threshold voltage level of the memory cell MC in the set state (SET) is lower than the read voltage V. read The threshold voltage level of the memory cell MC is higher than the read voltage V, so the memory cell MC can be turned on. Because the threshold voltage level of the memory cell MC in the RESET state is higher than the read voltage V, the memory cell MC can be turned on. read The threshold voltage level of the memory cell MC is higher than the read voltage V, so the memory cell MC can be turned off. In other words, because the threshold voltage level of the memory cell MC in the RESET state is higher than the read voltage V, the threshold voltage level is higher than the read voltage V. read The voltage level is low, so the memory cell MC may not be turned on. In this case, the read voltage V supplied after the read operation begins... read The level can correspond to the difference in voltage levels applied across the memory cell MC. That is, the read voltage V... read The voltage level can correspond to the difference between the voltage levels of the bit line BL and the word line WL.

[0044] For example, the storage device can be configured to compare the level of a reference voltage with the voltage level of a specific node to determine whether the storage cell MC has been turned on after a read operation has begun, the voltage level of which rises due to the current flowing through the storage cell MC when it is turned on.

[0045] More specifically, for example, if the read voltage V is after the read operation has started. readWhen supplied to the memory cell MC, the memory cell MC is turned on and current is supplied to a specific node, then the voltage level of that specific node can be higher than the reference voltage level. At this time, the memory cell MC can be determined to be turned on. If, after the read operation begins, the read voltage V... read When current is supplied to the memory cell MC, if the memory cell MC is not turned on and no current is supplied to a specific node, then the voltage level of that specific node can be lower than the reference voltage level. In this case, the memory cell MC can be determined to be not turned on.

[0046] However, when the creeping current increases, although the memory cell MC is turned on after the read operation begins, the voltage level of a particular node may not be higher than the reference voltage level.

[0047] In this situation, the memory cell MC that is in the set state (SET) can be determined to be not yet turned on and incorrectly identified as being in the reset state (RESET), such as... Figure 6 As shown.

[0048] Figure 7 This is a flowchart of an operation method of a storage system according to an embodiment of the present disclosure.

[0049] refer to Figure 7 The operation method of the storage system according to the embodiments of the present disclosure may include a write command and write data receiving process S1, a reset data count process S2, a first check process S3, a first write operation execution process S4, a second write operation execution process S5, a set voltage read operation execution process S6, a count value comparison process S7, a second check process S8, a third write operation execution process S9, and a stealth processing algorithm execution process S10.

[0050] The write command and write data receiving process S1 may include a process of receiving write commands and write data from a storage device. For example, the write data may include reset data and set data. In this case, the write command may be a command instructing the storage device to store the write data. The write data may be data to be stored in the storage device. For example, the write command and write data receiving process S1 may include a process of transmitting the write command and write data from the host to the controller.

[0051] The reset data count process S2 can be a process of counting the number of reset data included in the written data. For example, the reset data count process S2 can include a process of counting the number of reset data in the written data received by the controller from the host.

[0052] The first inspection process S3 may include a process of comparing the number of counted reset data with a first threshold.

[0053] exist Figure 7 In one embodiment, during the first check process S3, if the number of counted reset data is equal to or less than the first threshold (no), the first write operation execution process S4 can be executed. However, the embodiments of this disclosure are not limited thereto. Specifically, in some embodiments, during the first check process S3, if the number of counted reset data is less than the first threshold (no), the method proceeds to S4.

[0054] The first write operation execution process S4 may include a process in which the storage device that received the write command stores the write data by transmitting the write command and write data to the storage device. For example, when the number of data counted by the controller is equal to or less than a first threshold (No), the first write operation execution process S4 may include a process in which the controller transmits the write command and write data received from the host to the storage device, and a process in which the storage device stores the write data in response to the received write command.

[0055] exist Figure 7 In one embodiment, when the number of counted reset data is greater than the first threshold (yes) in the first check process S3, the second write operation execution process S5 can be executed. However, the embodiments of this disclosure are not limited thereto. Specifically, in some embodiments, when the number of counted reset data is equal to or greater than the first threshold (yes) in the first check process S3, the method can proceed to S5.

[0056] The second write operation execution process S5 may include the process of the controller transmitting the write command and write data to the storage device and the storage device storing the write data after receiving the write command.

[0057] The voltage read operation execution process (or read operation execution process with a specific voltage) S6 can be a process executed after the second write operation execution process S5 has been executed when the number of reset data counted in the first check process S3 is greater than the first threshold (yes).

[0058] The set voltage read operation execution process S6 may include a process of reading the write data stored in the second write operation execution process S5 by using a read voltage having a specific (e.g., set) voltage level. For example, the set voltage read operation execution process S6 may include a process of providing a read voltage having a set voltage level to a memory cell that has stored write data in the second write operation execution process S5 and checking whether the memory cell is turned on. In this case, in order to check whether the memory cell is turned on in the set voltage read operation execution process S6, the read voltage having a set voltage level provided to the memory cell may be higher than the common read voltage (e.g., Figure 8 V in readThe level of the common read voltage can be higher than the threshold voltage level of a memory cell in the set state (SET) and lower than the threshold voltage level of a memory cell in the reset state (RESET). In this case, the level of the read voltage with the set voltage level can be higher than the threshold voltage level of a memory cell in the reset state (RESET).

[0059] The count comparison process S7 may include a process of comparing the number of memory cells turned on during the set voltage read operation execution process S6 with the number of reset data counted during the reset data count process S2. In some embodiments, the count comparison process S7 may include a process of calculating a comparison value based on the number of memory cells turned on, the number of counted reset data, or both. For example, the count comparison process S7 may include a process of calculating the difference between the number of counted reset data and the number of turned-on memory cells as a comparison value.

[0060] The second inspection process S8 may include comparing the comparison value calculated in the count value comparison process S7 with a second threshold to determine whether to perform the stealth processing algorithm operation in S10.

[0061] exist Figure 7 In one embodiment, when the comparison value calculated in the second checking process S8 is equal to or less than the second threshold (No), the third write operation execution process S9 can be executed. However, the embodiments of this disclosure are not limited thereto. Specifically, in some embodiments, when the comparison value calculated in the second checking process S8 is less than the second threshold (No), the method can proceed to S9.

[0062] The third write operation execution process S9 may include the process of the controller transmitting a write command and write data to the storage device, and the storage device that has received the write command storing the write data. The reason for executing the third write operation execution process S9 may be to re-execute the operation of storing reset data in the storage cell, because the state of the storage cell that was in the reset state RESET during the set voltage read operation execution process S6 can be changed to the set state SET.

[0063] exist Figure 7 In one embodiment, when the comparison value calculated in the second inspection process S8 is greater than the second threshold (yes), the stealth processing algorithm execution process S10 can be executed. However, the embodiments of this disclosure are not limited thereto. Specifically, in some embodiments, when the comparison value calculated in the second inspection process S8 is equal to or greater than the second threshold (yes), the method proceeds to S10.

[0064] When the comparison value calculated in the second inspection process S8 is greater than the second threshold (yes), the stealth processing algorithm execution process S10 may include a process of detecting that the stealth current is greater than a set amount and executing an algorithm to reduce the stealth current.

[0065] Figure 8 It is used to describe references Figure 7 A diagram illustrating the set voltage reading operation.

[0066] Figure 8 The read voltage V, which has a specific voltage level, supplied to the memory cell can be shown. read_s This is so that the status of the memory cell can be checked during the set voltage read operation execution process S6.

[0067] The read voltage V supplied to the memory cell after the common read operation begins. read It can have a voltage level between the threshold voltage level of a memory cell in the set state (SET) and the threshold voltage level of a memory cell in the reset state (RESET).

[0068] However, the voltage read operation execution process S6 may include providing a read voltage V to the memory cell having a level higher than the threshold voltage of the memory cell in the RESET state. read_s This is a process to check whether a memory cell is conducting. For example, when there is essentially no creeping current flowing through a cell with... Figure 8 When the threshold voltage shown in the memory cell is read, the voltage V is read. read_s It can have a specific level that is higher than the maximum threshold voltage of the memory cell in the RESET state.

[0069] The operation method of the storage system according to the embodiments of the present disclosure may count the number of reset data in the write data to be stored in the storage device and terminate after storing the write data in the storage device when the counted number of reset data is equal to or less than a first threshold.

[0070] However, in the operation method of the storage system according to the embodiments of this disclosure, when the amount of reset data in the write data to be stored in the storage device is greater than a first threshold, a set voltage read operation can be performed after the write data is stored in the storage device. The set voltage read operation can be an operation that checks whether a storage cell in the reset state (RESET) is turned on by providing a read voltage with a level higher than the threshold voltage of the storage cell. Therefore, in the set voltage read operation, it is necessary to check whether all storage cells in the set state (SET) and all storage cells in the reset state (RESET) are turned on. However, due to the creeping current, not all storage cells in the set state (SET) and all storage cells in the reset state (RESET) can be checked as turned on. Specifically, when the amount of creeping current increases, the number of storage cells checked as turned on can decrease.

[0071] Therefore, when the creeping current is relatively small, the number of memory cells turned on after the set voltage read operation begins can be greater than the number of counted reset data.

[0072] However, when the creeping current is relatively large, the number of memory cells turned on after the set voltage read operation begins can be less than the number of counted reset data.

[0073] Therefore, in the operation method of the storage system according to embodiments of the present disclosure, when the difference between the number of storage cells turned on after the start of the set voltage read operation and the count value of the reset data is greater than a second threshold, the creeping current can be detected as relatively large. In some embodiments, the creeping current can be determined to be relatively large when the number of storage cells turned off after the start of the set voltage read operation is greater than the second threshold. For example, the number of storage cells turned off after the start of the set voltage read operation can be obtained by subtracting the number of storage cells turned on after the start of the set voltage read operation from the total number of storage cells in the set state (SET) and the reset state (RST).

[0074] Furthermore, in the operation method of the storage system according to embodiments of this disclosure, when a large creeping current is detected, a creeping processing algorithm can be executed. In some embodiments, the creeping processing algorithm can perform the following operation: inverting the data value stored in the storage cell (as will be referred to below). Figure 9 (as described above), or reallocate specific data values ​​stored in the storage unit (as will be referred to below). Figure 10A and Figure 10B (as described), or perform both.

[0075] Figure 9 , Figure 10A and Figure 10BIt is used to describe references Figure 7 A diagram illustrating the operational method of the described stealth handling algorithm. In this case... Figure 9 , Figure 10A and Figure 10B This is merely an example of how the stealth processing algorithm works, but the implementation of this disclosure is not limited thereto.

[0076] Figure 9 A memory cell array comprising multiple memory cells can be shown.

[0077] refer to Figure 9 The memory cell array may include multiple memory cells electrically connected between multiple bit lines BL and multiple word lines WL. In this case, it is assumed that the number of memory cells in the set state (SET) is greater than the number of memory cells in the reset state (RESET). Since the threshold voltage level of the memory cells in the set state (SET) is lower than the threshold voltage of the memory cells in the reset state (RESET), the creeping current will increase when the number of memory cells in the set state (SET) becomes greater than the number of memory cells in the reset state (RESET).

[0078] In this case, by changing the state of the memory cell in the set state to the reset state and changing the state of the memory cell in the reset state to the set state, the number of memory cells in the reset state is greater than the number of memory cells in the set state, and the creeping current can be reduced.

[0079] Therefore, refer to Figure 9 The described stealth processing algorithm can be related to the algorithm that stores the data value in a memory cell by inverting the data value when the number of memory cells in the set state (SET) is greater than the number of memory cells in the reset state (RESET).

[0080] Figure 10A and 10B The following situation can be illustrated: in a specific line of the memory cell array, the number of memory cells in the SET state is greater than the number of memory cells in the RESET state.

[0081] refer to Figure 10AThe memory cell array may include multiple memory cells electrically connected between multiple bit lines BL and multiple word lines WL. In this case, it is assumed that the number of memory cells in the set state SET in a specific bit line BL_s is greater than the number of memory cells in the reset state RESET in other bit lines BL. Since the threshold voltage level of the memory cells in the set state SET is lower than the threshold voltage of the memory cells in the reset state RESET, the amount of creeping current flowing out of the specific bit line BL_s can be greater than the amount of creeping current flowing out of other bit lines BL.

[0082] In this case, the creeping current can be reduced by redistributing the data stored in the memory cells of a specific bit line BL_s to the memory cells of other bit lines BL.

[0083] refer to Figure 10B The memory cell array may include multiple memory cells electrically connected between multiple bit lines BL and multiple word lines WL. In this case, it is assumed that the number of memory cells in the set state SET in a particular word line WL_s is greater than the number of memory cells in the reset state RESET in other word lines WL. Since the threshold voltage level of the memory cells in the set state SET is lower than the threshold voltage of the memory cells in the reset state RESET, the amount of creeping current flowing out of the particular word line WL_s can be greater than the amount of creeping current flowing out of other word lines WL.

[0084] In this case, the creeping current can be reduced by redistributing the data stored in the memory cells of a specific word line WL_s to the memory cells of other word lines WL.

[0085] Therefore, the above reference Figure 10A and Figure 10B The described stealth processing algorithm can be related to the following algorithm: when the number of memory cells in the set state SET in a specific position line or a specific word line is greater than the number of memory cells in another line or word line, the algorithm reallocates the data stored in the memory cells of the specific position line or a specific word line.

[0086] Figure 11 This is a diagram used to describe a storage system according to an embodiment of the present disclosure.

[0087] refer to Figure 11 The storage system according to embodiments of the present disclosure may include a host 10, a controller 20, a buffer memory 30, and a storage device 40. In some embodiments, the storage device 40 may include a memory cell array, which includes a selector-only memory (SOM).

[0088] The controller 20 can receive commands and data from the host 10. Furthermore, the controller 20 can transmit data stored in the storage device 40 or the buffer memory 30 to the host 10.

[0089] The controller 20 can store data in the buffer memory 30. Furthermore, the controller 20 can receive data stored in the buffer memory 30.

[0090] The controller 20 can transmit commands and data received from the host 10 to the storage device 40. When the command is a write command, the controller 20 can transmit the write command and data to the storage device 40. In this case, the data received from the host 10 is the data to be written to the storage device 40, so it can be referred to as write data. When the command received from the host 10 is a read command, the controller 20 can transmit the read command to the storage device 40 and can transmit the data output from the storage device 40 to the host 10.

[0091] The operation of the storage system according to embodiments of this disclosure is described below. In this case, reference is made to... Figure 7 The operation method of the storage system is described using the example of the operation method of the described storage system.

[0092] The controller 20 can receive write commands and write data from the host 10. For example, the write data may include reset data and set data.

[0093] Controller 20 can count the number of reset data entries in the written data.

[0094] When the number of reset data counted by controller 20 is equal to or less than a first threshold, controller 20 can transmit the write command and write data received from host 10 to storage device 40. Thereafter, storage device 40 can perform a write operation to store the written data. In this case, when the number of counted reset data is equal to or less than the first threshold, the operation method of the storage system according to embodiments of this disclosure can be terminated after a write operation is performed on storage device 40.

[0095] When the number of reset data counts exceeds a first threshold, controller 20 can store the write data and the address where the write data will be stored in buffer memory 30, and then transmit the write command and write data to storage device 40. Storage device 40, having received the write command and write data, can store the write data. Afterward, controller 20 can receive the write data and address stored in buffer memory 30. Controller 20 can perform a set voltage read operation (or a read operation with a specific voltage) on storage device 40 based on the address received from buffer memory 30. That is, controller 20 can perform a read operation that provides a read voltage with a specific (e.g., set) voltage level to the storage cell at the location where the write data has been stored. In this case, the specific voltage level of the read voltage can be higher than the threshold voltage of the storage cell in the RESET state.

[0096] The controller 20 can compare the result of the read operation received from the storage device 40 with the reset data received from the buffer memory 30. That is, the controller 20 can check the number of active memory cells based on the result of the read operation received from the storage device 40, and can compare the number of active memory cells with the number of reset data.

[0097] Since the read operation is performed using a voltage level that is higher than the threshold voltage of the memory cell in the RESET state, the number of memory cells turned on can be greater than the amount of reset data when the creeping current is relatively low.

[0098] However, although the read operation is performed by using a voltage with a level higher than the threshold voltage of the memory cell in the RESET state, the number of memory cells turned on can be less than the amount of reset data if the creeping current is relatively large.

[0099] Therefore, the controller 20 can monitor the amount of creeping current based on a comparison between the number of activated memory cells and the amount of reset data.

[0100] When the controller 20 determines that the creeping current is relatively low, the controller 20 can control the storage device 40 to store the write data in the address received from the buffer memory 30.

[0101] When the controller 20 determines that the creeping current is relatively high, the controller 20 can execute a creeping processing algorithm on the storage device 40. Thereafter, the controller 20 can control the storage device 40 to store the write data in the address received from the buffer memory 30.

[0102] The storage system according to an embodiment of the present disclosure can be configured to determine that the creeping current is relatively large when the difference between the number of activated storage cells and the number of reset data is greater than a second threshold.

[0103] Figure 12 This is a flowchart of an operation method of a storage system according to another embodiment of the present disclosure. For example, a controller (e.g., Figure 11 The controller 20 in the present disclosure can execute the operation method according to the embodiments of the present disclosure.

[0104] refer to Figure 12 An operation method of a storage system according to another embodiment of the present disclosure may include a write command and write data receiving process S10, a data quantity counting reset process S20, a first check process S30, a first write operation execution process S40, a first ratio update process S50, a second check process S60, a second write operation execution process S70, a set voltage read operation execution process S80, a count value comparison process S90, a third check process S100, a third write operation execution process S110, a stealth processing algorithm execution process S120, and a second ratio update process S130.

[0105] The write command and write data receiving process S10 may include a process of receiving write commands and write data in the storage device. In this case, the write command may be a command instructing the storage device to store write data. The write data may be data to be stored in the storage device. For example, the write command and write data receiving process S10 may include a process of transmitting write commands and write data from the host to the controller.

[0106] The reset data count process S20 can be a process of counting the number of reset data included in the written data. For example, the reset data count process S20 can include a process by which the controller counts the number of reset data in the written data received from the host.

[0107] The first inspection process S30 may include a process of comparing the number of reset data counted with a first threshold.

[0108] exist Figure 12 In one embodiment, during the first check process S30, if the number of counted reset data is equal to or less than the first threshold (no), the first write operation execution process S40 can be executed. However, the embodiments of this disclosure are not limited thereto. Specifically, in some embodiments, during the first check process S30, if the number of counted reset data is less than the first threshold (no), the method can proceed to the first write operation execution process S40.

[0109] The write operation execution process S40 may include a process in which the memory device that received the write command stores the write data by transmitting the write command and write data to the memory device. For example, the first write operation execution process S40 may include a process in which the controller transmits the write command and write data received from the host to the memory device, and a process in which the memory device stores the write data in response to the received write command when the number of data counted by the controller is equal to or less than a first threshold (no).

[0110] After the first write operation execution process S40 is executed, the first proportional update process S50 can be executed.

[0111] The first ratio update process S50 may include a process of accumulating and storing the ratio of reset data to set data in the written data. For example, the first ratio update process S50 may include a process in which the controller calculates the ratio of reset data to set data in the written data and stores the ratio of reset data to set data in a buffer memory. In some embodiments, the controller may update the accumulated ratio of reset data to set data based on the ratio of reset data to set data in the written data received at S10. Specifically, the controller may update the accumulated ratio of reset data to set data by adding the amount of reset data in the written data to the amount of previously accumulated reset data, adding the amount of set data in the written data to the amount of previously accumulated set data, and dividing the increased amount of reset data by the increased amount of set data.

[0112] When the number of reset data counted in the first inspection process S30 is greater than the first threshold (yes), the second inspection process S60 can be executed.

[0113] The second checking process S60 may include a process of comparing the ratio of accumulated and stored reset data to set data with a second threshold. For example, the ratio of accumulated and stored reset data to set data before receiving write data at S10 may be compared with the second threshold. In this case, when the amount of reset data is greater than the amount of set data, the ratio of accumulated and stored reset data to set data may have a higher value. In other words, the ratio of reset data to set data in the write data received at S10 may have a value that increases as the amount of reset data in the write data becomes greater than the amount of set data. For example, the second checking process S60 may include a process by which the controller compares the ratio of accumulated and stored reset data to set data in the buffer memory with the second threshold.

[0114] When the ratio of the reset data to the set data accumulated and stored in the second inspection process S60 is equal to or less than the second threshold (no), the first write operation execution process S40 and the first ratio update process S50 can be executed.

[0115] exist Figure 12 In one embodiment, when the ratio of the reset data to the set data accumulated and stored in the second check process S60 is greater than the second threshold (yes), the second write operation execution process S70 can be executed. However, the embodiments of this disclosure are not limited thereto. Specifically, in some embodiments, when the ratio of the reset data to the set data accumulated and stored in the second check process S60 is equal to or greater than the second threshold (yes), the method can proceed to the second write operation execution process S70.

[0116] The second write operation execution process S70 may include a process in which the controller transmits a write command and write data to a storage device, and the storage device that has received the write command stores the write data.

[0117] After executing the second write operation execution process 70, the set voltage read operation execution process (or the read operation execution process with a specific voltage) S80 can be executed.

[0118] The set voltage read operation execution process S80 may include a process of reading the write data stored in the second write operation execution process S70 by using a read voltage having a specific (e.g., set) voltage level. For example, the set voltage read operation execution process S80 may include a process of providing a read voltage having a set voltage level to a memory cell that has stored write data in the second write operation execution process S70 and checking whether the memory cell is turned on. In this case, in order to check whether the memory cell is turned on in the set voltage read operation execution process S80, the read voltage having a set voltage level provided to the memory cell may have a level higher than the common read voltage level. For example, the level of the common read voltage may be higher than the threshold voltage level of the memory cell in the set state SET and lower than the threshold voltage level of the memory cell in the reset state RESET. In this case, the read voltage having a set voltage level may have a level higher than the threshold voltage level of the memory cell in the reset state RESET. More specifically, the voltage read operation execution process S80 may include, under the control of the controller, a process in which a memory device reads a memory cell by using a read voltage having a level higher than the threshold voltage of the memory cell in the RESET state, and provides the read result to the controller. In this case, the read result may include the number of memory cells that are turned on and the number of memory cells that are not turned on.

[0119] The count comparison process S90 may include a process of comparing the number of memory cells turned on during the set voltage read operation execution process S80 with the number of reset data counted during the reset data count process S20. In some embodiments, the count comparison process S90 may include a process of calculating a comparison value based on the number of counted reset data and the number of turned-on memory cells. For example, the count comparison process S90 may include a process of calculating the difference between the number of reset data and the number of turned-on memory cells as the comparison value.

[0120] The third inspection process S100 may include comparing the third threshold with the comparison value calculated in the count value comparison process S90 to determine whether to perform the stealth processing algorithm operation at S120.

[0121] exist Figure 12 In some embodiments, when the calculated comparison value in the third check process S100 is less than or equal to the third threshold (no), the third write operation execution process S110 can be executed. However, the embodiments of this disclosure are not limited thereto. Specifically, in some embodiments, when the calculated comparison value in the third check process S100 is less than the third threshold (no), the method can proceed to the third write operation execution process S110.

[0122] exist Figure 12 In one embodiment, when the calculated comparison value is greater than the third threshold in the third inspection process S100 (yes), the stealth processing algorithm execution process S120 can be executed. However, the embodiments of this disclosure are not limited thereto. Specifically, in some embodiments, when the calculated comparison value is equal to or greater than the third threshold in the third inspection process S100 (yes), the method can proceed to the stealth processing algorithm execution process S120.

[0123] The stealth processing algorithm execution process S120 may include a process of detecting that the stealth current is greater than a set amount when the comparison value calculated in the third checking process S100 is greater than a third threshold (yes), and executing an algorithm to reduce the stealth current.

[0124] After the stealth processing algorithm execution process 120 is executed, the third write operation execution process S110 can be executed.

[0125] The third write operation execution process S110 may include the process of the controller transmitting a write command and write data to the storage device, and the storage device that has received the write command storing the write data. The reason for executing the third write operation execution process S110 may be to re-execute the operation of storing reset data in the storage cell, because the storage cell that was in the reset state RESET during the set voltage read operation execution process S80 can be changed to the set state SET.

[0126] After the third write operation execution process S110 is executed, the second proportional update process S130 can be executed.

[0127] The second proportional update process S130 may include a process of accumulating and storing the ratio of reset data to set data in the written data. For example, the second proportional update process S130 may include a process in which the controller calculates the ratio of reset data to set data in the written data and stores the ratio of reset data to set data in a buffer memory.

[0128] Although some embodiments based on the technical spirit of this disclosure have been described above with reference to the accompanying drawings, these embodiments are provided only to describe embodiments according to the concept of this disclosure, and the various embodiments of this disclosure are not limited to the embodiments described above. Those skilled in the art to which this disclosure pertains can substitute, modify, and change the embodiments in various ways, and such substitutions, modifications, and changes may fall within the scope of the embodiments of this disclosure.

Claims

1. A method of operating a storage system, comprising: Receive a first write command and first write data, wherein the first write data includes first reset data and first set data; Count the number of the first reset data; Compare the quantity of the first reset data with a first threshold; The first data to be written is stored in the first storage unit; The number of first conducting memory cells in the first memory cell is checked by providing a read voltage with a specific voltage level to the first memory cell; A first comparison value is calculated based on the number of the first activated memory cells; The first comparison value is compared with the second threshold to determine whether to perform the stealth processing algorithm operation; as well as The first written data is then stored again in the first storage unit.

2. The operating method according to claim 1, wherein, The specific voltage level of the read voltage is higher than the threshold voltage of the memory cell in the reset state.

3. The operating method according to claim 1, wherein, Calculating the first comparison value includes: calculating the difference between the number of the first activated memory cells and the number of the first reset data as the first comparison value.

4. The operating method according to claim 1 further includes: Receive a second write command and second write data, wherein the second write data includes second reset data and second set data; The number of the second reset data is counted; Compare the quantity of the second reset data with the first threshold; as well as The second data to be written is stored in the second storage unit.

5. The operating method according to claim 1 further includes: Receive a third write command and third write data, wherein the third write data includes third reset data and third set data; The number of the third reset data is counted; Compare the quantity of the third reset data with the first threshold; The third data to be written is stored in the third storage unit; The number of second-conducting memory cells in the third memory cell is checked by providing the read voltage to the third memory cell; A second comparison value is calculated based on the number of the second activated memory cells; as well as The second comparison value is compared with the second threshold to determine whether the stealth processing algorithm operation is performed on the third storage unit.

6. The operating method according to claim 5, wherein, The specific voltage level of the read voltage is higher than the threshold voltage of the memory cell in the reset state.

7. The operating method according to claim 6, wherein, Calculating the second comparison value includes: calculating the difference between the number of the second activated memory cells and the number of the third reset data as the second comparison value.

8. A method of operating a storage system, comprising: Receive a first write command and first write data, wherein the first write data includes first reset data and first set data; Count the number of the first reset data; Compare the quantity of the first reset data with a first threshold; The first data to be written is stored in the first storage unit; as well as The ratio of the reset data to the set data is updated based on a first ratio of the first reset data to the first set data, the ratio of which has been accumulated and stored before the first write data is received.

9. The operating method according to claim 8, wherein, The first ratio has a value that increases as the quantity of the first reset data becomes greater than the quantity of the first set data.

10. The operating method according to claim 8, further comprising: Receive a second write command and second write data, wherein the second write data includes second reset data and second set data; The number of the second reset data is counted; Compare the quantity of the second reset data with the first threshold; Compare the updated ratio with the second threshold; The second data to be written is stored in the second storage unit; as well as The ratio being compared is updated based on a second ratio of the second reset data to the second set data.

11. The operating method according to claim 8, further comprising: Receive a third write command and third write data, wherein the third write data includes third reset data and third set data; The number of the third reset data is counted; Compare the quantity of the third reset data with the first threshold; Compare the updated ratio with the second threshold; The third data to be written is stored in the third storage unit; The number of first-conducting memory cells in the third memory cell is compared by providing a read voltage with a specific voltage level to the third memory cell; A comparison value is calculated based on the number of the first activated storage cells; The comparison value is compared with a third threshold to determine whether to perform the stealth processing algorithm operation; The third written data is then restored in the third storage unit; as well as The ratio being compared is updated based on the third ratio of the third reset data to the third set data.

12. The operating method according to claim 8, further comprising: Receive a fourth write command and fourth write data, wherein the fourth write data includes fourth reset data and fourth set data; The number of the fourth reset data is counted; The quantity of the fourth reset data is compared with the first threshold. Compare the updated ratio with the second threshold; The fourth write data is stored in the fourth storage unit; The number of second-conducting memory cells in the fourth memory cell is compared by providing a read voltage with a specific voltage level to the fourth memory cell; A comparison value is calculated based on the number of the second activated storage cells; The comparison value is compared with a third threshold; as well as When the comparison value is greater than the third threshold, a stealth processing algorithm operation is performed on the fourth storage unit; The fourth written data is then restored in the fourth storage unit; as well as The ratio being compared is updated based on the third ratio of the fourth reset data to the fourth set data.

13. A storage system, comprising: A storage device comprising multiple storage units; The controller: receives write commands and write data including reset data and set data, counts the number of reset data, and transmits the write commands and the write data to the storage device; and A buffer memory, which, under the control of the controller, stores the written data and transmits the stored written data to the controller.

14. The storage system according to claim 13, wherein, The controller stores the write data in the plurality of storage units by transmitting the write command and the write data to the storage device.

15. The storage system according to claim 14, wherein, The controller checks the number of active memory cells among the plurality of memory cells by providing a read voltage with a specific voltage level to the plurality of memory cells.

16. The storage system according to claim 15, wherein, The specific voltage level of the read voltage is higher than the threshold voltage of the memory cell in the reset state.

17. The storage system according to claim 16, wherein, The controller compares the count of the reset data with the number of the activated storage cells.

18. The storage system according to claim 17, wherein, The controller calculates a comparison value based on the number of activated storage cells and the count of reset data, and determines whether to perform a stealth processing algorithm operation on the storage device by comparing the comparison value with a third threshold.

19. The storage system according to claim 18, wherein, The stealth processing algorithm operation includes: reversing the data values ​​stored in the storage unit, or redistributing specific data values ​​stored in the storage unit, or both.

20. The storage system according to claim 18, wherein, The comparison value is the difference between the number of activated memory cells and the count of reset data. Wherein, when the difference between the number of activated memory cells and the count of reset data is greater than the third threshold, the controller executes the stealth processing algorithm operation on the memory device, and Specifically, when the difference between the number of activated storage units and the count of reset data is equal to or less than the third threshold, the controller stores the write data in the plurality of storage units.

21. The storage system according to claim 13, wherein, The buffer memory accumulates and stores a ratio, and the controller updates the accumulated and stored ratio based on a first ratio of the reset data to the set data of the written data.

22. The storage system according to claim 21, wherein, The controller: When the ratio of accumulation to storage is greater than the second threshold, the written data is stored in the plurality of storage units; as well as The memory device is used to perform a read operation by using a read voltage with a specific voltage level to obtain the number of memory cells that are turned on among the plurality of memory cells.

23. The storage system according to claim 22, wherein, The controller: When the difference between the number of activated storage cells and the number of reset data is greater than a third threshold, the storage device is made to perform a stealth processing algorithm operation.

24. The storage system according to claim 23, wherein, The stealth processing algorithm operation includes: reversing the data values ​​stored in the storage unit, or redistributing specific data values ​​stored in the storage unit, or both.

25. The storage system according to claim 22, wherein, The controller: When the difference between the number of the activated storage cells and the number of the reset data is equal to or less than a third threshold, the write data is stored in the plurality of storage cells.

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