Memory device, memory system, and electronic apparatus

Abstract

The present disclosure provides a memory device, a storage system, and an electronic device. The memory device includes a storage area including a plurality of memory banks each including a plurality of memory cells; an arithmetic area including a plurality of arithmetic units configured to perform an arithmetic process using data acquired from at least two memory banks including a first memory bank and a second memory bank; and the storage area is configured to perform an alternating access step in units of rows. In the alternating access step, a q-th row in a second target memory bank is activated before a last read operation on an n-th row in a first target memory bank, the first target memory bank being one of the first memory bank and the second memory bank, and the second target memory bank being the other of the first memory bank and the second memory bank.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a storage device, storage system, and electronic device. Background Technology

[0002] Semiconductor memory devices used in high-performance electronic systems can provide increased capacity and / or speed. These memory devices can store various types of information, such as data, and various types of arithmetic processing information, such as neural network arithmetic or the results of arithmetic processing. Processor-in-memory (PIM) type memory devices can be provided to perform some arithmetic operations in computing systems that provide large-capacity arithmetic and storage capabilities for internal processing. Summary of the Invention

[0003] This disclosure provides a storage device, a storage system, and an electronic device that at least improve the computing power of the storage device.

[0004] This disclosure provides a storage device, comprising: a storage area including a plurality of memory banks, each of the plurality of memory banks including a plurality of memory cells; an arithmetic area including a plurality of arithmetic units, at least one of the plurality of arithmetic units being configured to perform arithmetic processing using data obtained from at least two memory banks, the at least two memory banks including a first memory bank and a second memory bank; the storage area is configured to perform alternating access steps on a row-by-row basis; the alternating access step includes: performing a first access step to complete reading data from the current row of the first memory bank via multiple read operations, wherein... After the first access step, the second access step is executed to read data from the current row of the second memory bank through multiple read operations. The first access step and the second access step are executed alternately until the required data is read into the arithmetic unit. In the alternating access step, before the last read operation is performed on the data of the nth row in the first target memory bank, the qth row in the second target memory bank is activated. The first target memory bank is one of the first memory bank and the second memory bank, and the second target memory bank is the other of the first memory bank and the second memory bank. n and q are both positive integers greater than or equal to 1.

[0005] Optionally, the alternating access step includes: activating the nth row in the first target memory based on the first row address information, and performing m read operations sequentially to read the data of the nth row into the arithmetic unit, where m is a positive integer greater than 1; between the mkth read operation and the m-k+1th read operation in the m read operations, activating the qth row in the second target memory based on the second row address information, and after the m read operations are completed, reading the data of the qth row into the arithmetic unit, where 1≤k≤3, m>k, and k is a positive integer.

[0006] Optionally, the storage device includes: a command issuing module configured to provide a read command or a row operation command to the storage area, the row operation command including a row activation command; and a row-cutting control module configured to obtain whether a row-cutting condition has been met, the row-cutting condition being used to characterize that the mk-th read command has been provided and the (m-k+1)-th read command has not been provided; if yes, then the command issuing module is controlled to provide the storage area with a row activation command corresponding to the second row address information before providing the (m-k+1)-th read command to the storage area, wherein the (m-k+1)-th read command is used to trigger the (m-k+1)-th read operation; if no, then the command issuing module is controlled to continue providing one more read command to the storage area.

[0007] Optionally, determining whether the row-cutting condition has been met includes: obtaining the address information of the first column corresponding to each read operation in multiple read operations on the nth row; determining whether the row-cutting condition has been met based on the first column address information; or, obtaining the number of read operations performed on the nth row; determining whether the row-cutting condition has been met based on the number of read operations.

[0008] Optionally, the storage device further includes: a counter, configured to count the number of read operations performed to access the nth row for a read operation, to obtain a count value; if the count value reaches a preset value, an identification signal is generated, the identification signal being used to characterize that the row cutting condition has been met.

[0009] Optionally, the counter is integrated into the command issuing module.

[0010] Optionally, the row-switching control module includes: a command detection circuit connected to the command issuing module, configured to detect whether the current command is a read command; a row-switching analysis circuit configured to obtain whether the row-switching condition has been met; and a command scheduling circuit connected to the command issuing module, the command detection circuit, and the row-switching analysis circuit, configured to generate and output scheduling information if the current command is a read command and the row-switching condition has been met, wherein the scheduling information is used to trigger the command issuing module to provide a row activation command corresponding to the second row address information before providing the next read command.

[0011] Optionally, the storage device further includes a memory controller, wherein the command issuing module and the row cutting control module are both located in the memory controller.

[0012] Optionally, the storage device is further configured to receive a precharge command for the nth row in the first target memory after receiving the first read command for the qth row, so as to close the nth row.

[0013] Optionally, both the first row of address information and the second row of address information are provided by the host.

[0014] Optionally, the arithmetic area further includes multiple row address generation circuits, each of which corresponds to the arithmetic unit; wherein, the row address generation circuit is configured to generate a first internal row address and a second internal row address, the first internal row address serving as the first row address information and the second internal row address serving as the second row address information.

[0015] Optional, k is 1.

[0016] Optionally, the storage area and the computing area are located within the same chip; or, the storage area is located within a first chip, the computing area is located within a second chip, and the first chip and the second chip are bonded together.

[0017] This disclosure also provides a storage system including any of the storage devices described above.

[0018] In another aspect, this disclosure provides an electronic device including any of the storage devices described above, or including the storage system described above.

[0019] The technical solution provided in this disclosure has at least the following advantages: This disclosure provides a novel architecture for a storage device that can simultaneously activate row n of a first target memory and row q of a second target memory. Therefore, before completing the last read operation of row n of the first target memory, row q of the second target memory is activated first. That is, when the read operation of row n of the first target memory is completed, row q of the second target memory has already been activated and prepared. This can shorten or even eliminate the activation time required to activate row q of the second target memory, i.e., shorten the switching time from a row of the first target memory to reading a row of the second target memory. This allows row reading of the first memory and row reading of the second memory to be performed alternately, while reducing the data reading time between rows of different memory, thereby improving the computing power of the storage device. Attached Figure Description

[0020] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrative descriptions do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the figures in the drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 A functional block diagram of a storage device provided in an embodiment of this disclosure; Figure 2 A schematic diagram of the layout of the arithmetic logic unit and memory; Figure 3 for Figure 1 A timing diagram showing the relevant commands and line address information in the storage device shown; Figure 4 Another functional block diagram of the storage device provided in the embodiments of this disclosure; Figure 5 This is a flowchart illustrating a process for determining whether a row cutting condition has been met in a storage device. Figure 6 This is another flowchart illustrating whether the cutting condition has been met in a storage device; Figure 7 Another functional block diagram of a storage device provided in an embodiment of this disclosure; Figure 8 A timing diagram for related commands and data read by the arithmetic unit in related technologies; Figure 9A timing diagram of related commands and data read by the arithmetic unit in a storage device provided in some embodiments of this disclosure; Figure 10 Another functional block diagram of the storage device provided in the embodiments of this disclosure; Figure 11 Another functional block diagram of the storage device provided in the embodiments of this disclosure; Figure 12 Another functional block diagram of a storage device provided in an embodiment of this disclosure; Figure 13 This is a partial cross-sectional structural diagram of a storage device. Figure 14 and Figure 15 This diagram illustrates two different connections between the arithmetic logic unit (ALU) and the memory, as well as a data reading diagram. Figure 16 A block diagram of a storage system; Figure 17 A block diagram of an electronic device.

[0022] Explanation of reference numerals in the attached figures: 100. Storage device; 101. Storage area; 102. Arithmetic area; 111. Memory bank; 112. Arithmetic unit; BANK1. First memory bank; BANK2. Second memory bank; DATA. Data; SC1 / SC2. Sub-channels; BANKE. Odd memory bank; BANKO. Even memory bank; 11. Logic control circuit; ACT. Row activation command; Ld_xx / READ. Read command; PRE. Precharge command; DES. Cancel selection command; 201. Command issuing module; 202. Row cutting control module; 203. Counter; Flag. Identifier signal; 212. Command detection circuit; 222. Row cutting analysis circuit; 232. Command scheduling circuit; 200. Memory controller; 20. Row address generation circuit; 301. First chip; 302. Second chip; 401. Host; 402. Processing unit. Detailed Implementation

[0023] The computing power of storage devices in related technologies needs improvement. Computing-in-Memory (CIM) devices include multiple storage banks and multiple processing units (PUs). At least one PU can connect to multiple storage banks to retrieve the data required for computation, thus reducing data transfer costs and allowing for greater bandwidth. In CIM devices, the speed at which the PU reads data—the data bandwidth—is one of the bottlenecks for further improving computing power. Analysis reveals that to utilize data in storage banks most efficiently, the PU typically reads data from storage banks by reading all data from a single row, then switching to the next row in the same or a different storage bank, thus reading all rows of data at once for computation. This data includes, but is not limited to, model data such as weights, activation values, and scaling factors. With the development of Large Language Models (LLMs), the computing power requirements of CIM devices are increasing, necessitating higher data reading speeds to meet these demands. The time required for activation and switching between rows is long and the number of times is frequent, and its impact on computing power is becoming increasingly significant.

[0024] To at least solve or improve the above-mentioned technical problems, embodiments of this disclosure provide a storage device that, by adjusting the order of related commands during row switching of different storage banks, eliminates row activation time when operating on multiple rows of data, thereby improving the computing power of the storage device.

[0025] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0026] In the description of the embodiments of this disclosure, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary or secondary relationship of the indicated technical features. In the description of the embodiments of this disclosure, "multiple" means two or more, unless otherwise explicitly defined. Similarly, "multiple sets" refers to two or more sets (including two sets), and "multiple pieces" refers to two or more pieces (including two pieces).

[0027] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this disclosure. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0028] In the description of the embodiments of this disclosure, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A exists, A and B exist simultaneously, and B exists. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0029] In the description of the embodiments of this disclosure, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the embodiments of this disclosure and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the embodiments of this disclosure. For example, if the device or element in the illustration is inverted, then the element described as "below," "under," "below," or "bottom" of other elements or features will be oriented "above" or "top" of said other elements or features. Therefore, the term "below" may, depending on the context in which the term is used, encompass both above and below orientations, which will be obvious to those skilled in the art. Materials may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0030] In the description of the embodiments of this disclosure, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this disclosure according to the specific circumstances.

[0031] In the description of embodiments of this disclosure, the terms "about," "approximately," "roughly," or "about" for a numerical value referring to a specific parameter include the numerical value, and those skilled in the art will understand that the deviation from the numerical value is within acceptable tolerances of the specific parameter. For example, "about" or "about" for a numerical value may include additional numerical values ​​that are in the range of 90.0% to 110.0% of the numerical value, such as in the range of 95.0% to 105.0%, 97.5% to 102.5%, 99.0% to 101.0%, 99.5% to 100.5%, or 99.9% to 100.1%.

[0032] In the accompanying drawings corresponding to the embodiments of this disclosure, the thickness and / or area of ​​layers, films, panels, regions, etc., are enlarged for better understanding and ease of description. Throughout the specification, the same reference numerals denote the same elements. Furthermore, when describing a component as being "generally" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor on a portion of the edge of the entire surface.

[0033] In the description of embodiments of this disclosure, when a component "includes" another component, other components are not excluded unless otherwise stated, and may be further included. When a component (such as a layer, film, region, or substrate) is described as being on or on the surface of another component, the component may be "directly" located on the surface of the other component, or there may be an intermediate component between the two components. Conversely, when a component is described as being on the surface of another component, or a component is "directly" on another component, or another component is formed or disposed on the surface of a component, it indicates that there is no intermediate component between the two components. For simplicity and clarity, various components may be drawn at any scale. In the drawings, some components may be omitted for simplicity.

[0034] The terminology used in the description of the various embodiments herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the description of the various embodiments and the appended claims, the term "the component" is also intended to include the plural form unless the context clearly indicates otherwise.

[0035] The aforementioned components can refer to layers, films, regions, parts, structures, or plates, etc.

[0036] Figure 1 This is a functional block diagram of a storage device provided in an embodiment of the present disclosure.

[0037] refer to Figure 1The storage device 100 includes a storage area 101 and an arithmetic area 102. The storage area 101 includes multiple memory banks 111, each of which includes multiple memory cells. The arithmetic area 102 includes multiple arithmetic units 112, at least one of which is configured to perform arithmetic processing using data DATA obtained from at least two memory banks 111, including a first memory bank BANK1 and a second memory bank BANK2. The storage area 101 is configured to perform alternating access steps, row by row.

[0038] The alternating access steps include: performing a first access step to read data from the current row of the first storage bank BANK1 via multiple read operations, performing a second access step after the first access step to read data from the current row of the second storage bank BANK2 via multiple read operations, and alternating between the first access step and the second access step until the required data is read into the arithmetic unit 112.

[0039] In the alternating access step, before performing the last read operation on the data in the nth row of the first target memory, the qth row of the second target memory is activated first. The first target memory is one of the first memory BANK1 and the second memory BANK2, and the second target memory is the other of the first memory BANK1 and the second memory BANK2. n and q are both positive integers greater than or equal to 1.

[0040] In the above technical solution, although two different rows cannot be activated simultaneously within the same storage bank 111, two different rows can be activated simultaneously between two different storage banks 111, such as the first target storage bank and the second target storage bank. That is, the nth row of the first target storage bank and the qth row of the second target storage bank can be activated simultaneously. Therefore, before completing the last read operation of the nth row of the first target storage bank, the qth row of the second target storage bank is activated first. That is, when the read operation of the nth row of the first target storage bank is completed, the qth row of the second target storage bank has been activated and prepared. This can shorten or even eliminate the activation time required to activate the qth row of the second target storage bank, that is, shorten the switching time from switching from a row of the first target storage bank to reading a row of the second target storage bank. This allows the alternation of row reading in the first storage bank BANK1 and row reading in the second storage bank BANK2 to reduce the data reading time between rows of different storage banks 111, thereby improving the computing power of the storage device.

[0041] It is understood that, in the above technical solutions, whether compared to the switching time required to switch between different rows within the same storage device, or compared to the switching time required to read the current row of data in the previous storage device before reading the current row of data in the next storage device, the above technical solutions can shorten the switching time required to read different rows, thereby improving the data reading speed of the storage device and thus increasing computing power. Unless otherwise specified, the "switching time" mentioned in the embodiments of this disclosure can be understood as the duration between the end of reading the data of the previous row and the start of reading the data of the next row. The "previous row" and the "next row" can be different rows within the same storage device or different rows within different storage devices.

[0042] The storage devices provided in the embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings.

[0043] Storage device 100 may be a storage device that includes volatile memory cells. For example, storage device 100 may include various dynamic random access memory (DRAM), such as double data rate synchronous DRAM (DDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, DDR5 SDRAM, DDR6 SDRAM, or low power double data rate (LPDDR) SDRAM, LPDDR2 SDRAM, LPDDR3 SDRAM, LPDDR4 SDRAM, LPDDR5 SDRAM, LPDDR6 SDRAM, LPDDR7 SDRAM. The volatile memory cells may also include SRAM (static random-access memory).

[0044] In other embodiments, in addition to volatile memory cells, the storage device 100 may also include non-volatile memory cells such as NAND flash memory, NOR flash memory, RRAM, FRAM, PRAM, TRAM, or MRAM.

[0045] The storage device 100 can be connected to a host computer. The host computer can send command address signals to the storage device 100, and can also send data to or receive data from the storage device 100. The host computer can send command address signals to the storage device 100 to control it. Furthermore, the host computer can send data to or receive data from the storage device 100. The storage device 100 can receive data from the host and store the received data. The storage device 100 can read the stored data in response to a request from the host computer and send the read data back to the host computer.

[0046] The host can represent any device that communicates with the storage device 100, including any device that sends and / or receives data and command address signals. For example, the host may include at least one programmable or reconfigurable device. The programmable device may be a central processing unit (CPU), a digital signal processor (DSP), a graphics processing unit (GPU), a system-on-chip (SoC), or a neural network processing unit (NPU). The reconfigurable device may be a field-programmable gate array (FPGA).

[0047] The host can communicate with the storage device 100 based on any protocol. As an example, the host can communicate with the storage device 100 based on the following protocols: Serial Advanced Technology Attachment (SATA) interface, Peripheral Component Interconnect Fast (PCIe) interface, Universal Serial Bus (USB), Universal Flash Memory (UFS) interface, Embedded Multimedia Controller (eMMC) interface, etc.

[0048] The host computer can send command address signals to storage area 101 and / or arithmetic area 102 via a memory controller, wherein the memory controller can be integrated into the host computer or can be independent of the host computer. The memory controller can generate command information, address information, clock signals (or reference clocks), and data clock signals. The memory controller can output command information, address information, clock signals, and data clock signals to storage area 101 and / or arithmetic area 102. The memory controller can output data to storage area 101 or receive data from storage area 101. That is, storage device 100 can be a device for storing data. Command information can be signals indicating operations to be performed by storage device 100. For example, command information may include read, write, refresh, precharge, mode register, column address strobe, deselect, etc., but this disclosure is not limited thereto. For example, command information may vary depending on the specifications applied to storage device 100.

[0049] Each memory bank 111 has multiple memory cells, and the location of each memory cell can be accessed through its corresponding row (i.e., word line) and corresponding column (i.e., bit line). Access operations, including but not limited to read and write operations, can be performed on the memory cells corresponding to the selected row and selected column. That is, the location of the memory cell is accessed through its corresponding row (i.e., word line) and column (i.e., bit line). The memory bank 111 may include multiple word lines arranged along the row direction and may also include multiple bit lines arranged along the column direction. In some examples, the memory cells may be DRAM cells. It should be noted that the embodiments of this disclosure do not limit the type of memory cell; for example, the memory cell may also be any other non-volatile memory cell besides a DRAM cell.

[0050] Each memory bank 111 may include multiple memory sections. Different memory banks 111 may be implemented to include the same type of memory cells or to include different types of memory cells.

[0051] Multiple memory banks 111 can be divided into multiple memory groups (BGs) according to operational needs, with each memory group comprising a number of memory banks 111. For example, for a storage device 100 comprising 32 memory banks, the storage device 100 can be divided into 8 memory groups, with each memory group comprising 4 memory banks 111. As another example, for a storage device 100 comprising 16 memory banks, the storage device 100 can be divided into 4 memory groups, with each memory group comprising 4 memory banks 111. It is understood that the above are merely examples, and the embodiments disclosed herein do not limit the number of memory groups or the number of memory banks contained in each memory group.

[0052] Storage device 100 can be an in-memory computing device or a PIM device. Storage device 100 can operate in either storage mode or PIM mode. In some examples, a host or memory controller can control storage device 100, causing it to operate in either storage mode or PIM mode. When storage device 100 is operating in storage mode, it can perform data read or write operations on storage area 101. When storage device 100 is operating in PIM mode, it can perform read operations on the storage module and perform arithmetic operations on the read data. It can also perform write operations on storage area 101 to write the results of the arithmetic operations into storage area 101.

[0053] The arithmetic logic unit 112 can be configured to be connected to at least two memory banks 111 and to perform arithmetic processing using data DATA obtained from the at least two memory banks 111. This disclosure does not limit the correspondence between the arithmetic logic unit 112 and the memory banks 111; for example, the arithmetic logic unit 112 can be connected to three, four, or six memory banks 111. For ease of description, the two memory banks 111 connected to the same arithmetic logic unit 112 are defined as the first memory bank BANK1 and the second memory bank BANK2.

[0054] Figure 2 This is a schematic diagram of the layout of the arithmetic unit and the memory.

[0055] refer to Figure 2 In some examples, storage area 101 (reference) Figure 1 It may include one channel, and one channel corresponds to two sub-channels, which are identified as sub-channel SC1 and sub-channel SC2, respectively. For each sub-channel, there are multiple memory banks 111 arranged sequentially (see reference). Figure 1 Furthermore, the multiple storage banks 111 may include alternating odd-numbered storage banks BANKE and even-numbered storage banks BANKO. An arithmetic unit 112 can connect two adjacent odd-numbered storage banks BANKE and even-numbered storage banks BANKO. One of these odd-numbered storage banks BANKE and even-numbered storage banks BANKO can be defined as the first storage bank BANK1 (see reference). Figure 1 The other of the odd-numbered storage bank BANKE and the even-numbered storage bank BANKO can be defined as the second storage bank BANK2 (see reference). Figure 1 ).

[0056] Continue to refer to Figure 2A logic control circuit 11 may be arranged between the first memory bank BANK1 and the second memory bank BANK2. The logic control circuit 11 may include a row decoder and a column decoder, and the first memory bank BANK1 and the second memory bank BANK2 may share the row decoder and / or the column decoder. Multiple memory cells can be connected to the row decoder through multiple word lines and can be connected to the column decoder through bit lines.

[0057] It should be noted that, Figure 2 The connection relationship between each memory bank and the arithmetic unit shown is for illustrative purposes only. This embodiment does not limit the number of memory banks connected to the arithmetic unit or the location of each memory bank.

[0058] Understandably, the arithmetic unit 112 reads data from the storage unit of the storage bank 111 corresponding to the address information. The address information may include row address information and column address information. The row address information is used to indicate a row in the storage bank 111, and the column address information is used to indicate multiple columns in the storage bank 111. The row decoder can select at least one word line (i.e., a row) from multiple word lines by referring to the row address, and the column decoder can select multiple bit lines (i.e., multiple columns) by referring to the column address.

[0059] The arithmetic unit 112 can perform various arithmetic operations using the first memory bank BANK1 and the second memory bank BANK2. For example, arithmetic operations can include, but are not limited to, conversion operations such as mutual conversion between integers and floating-point numbers. Arithmetic operations can also include, but are not limited to, logical operations such as AND, OR, NAND, or XOR operations. Arithmetic operations can also include, but are not limited to, numerical operations such as addition, subtraction, multiplication, or division operations. Arithmetic operations can also include complex operations such as multiply-accumulate (MAC), convolution, matrix operations, and vector operations.

[0060] Arithmetic operations can also be operations based on large language models, and the operators involved can include, but are not limited to, the GEMV (General Matrix-Vector Multiplication) operator and the GEMM (General Matrix-Matrix Multiplication) operator. The GEMV operator multiplies a matrix by a vector, while the GEMM operator multiplies a matrix by another matrix.

[0061] After the arithmetic unit 112 performs arithmetic operations to obtain the corresponding result data, the result data can also be written from the arithmetic unit 112 to the first storage bank BANK1 and the second storage bank BANK2. That is, the storage device can also write the result data in the arithmetic unit 112 to the first storage bank BANK1 and the second storage bank BANK2.

[0062] For example, operations such as multiplication, accumulation, and addition require a large amount of data, while the amount of data that storage device 100 can obtain in a single read operation from storage bank 111 is limited, far less than the total amount of data contained in an entire row, and also less than the amount of data required for a single operation (including but not limited to model data such as weights, activation values, and scaling factors). Therefore, to complete the reading of the required data in the same row (the required data may be all the data in a row, or it may be a portion of the data in a row), multiple read commands are required to perform multiple read operations. Each read operation reads a portion of the data in the row, and through multiple read operations, the required data is read.

[0063] In some examples, the read operation process for a row of memory bank 111 includes: first, selecting / activating the target row (also called the specified row) using the row activation command (ACTIVE), and opening the target row. Then, selecting the specified column address using the read command (READ), strobing the data in the specified column, and outputting it through the data bus. The amount of data that can be output in a single read command is constrained by the chip's data bit width and burst length (BL). For example, if the chip's data bit width is W (unit: bits) and the burst length is BL, then the amount of data acquired in a single read command is W × BL bits. Typically, the value of W × BL is usually 64 bits to 256 bits; for example, the amount of data acquired in a single read command can be 64 bits, 128 bits, or 256 bits. In comparison, the total amount of data contained in a row of memory bank 111 is much larger than the amount of data transmitted in a single burst. Unless otherwise specified, the "target row" mentioned in this embodiment refers to the row that is activated / selected for reading data.

[0064] Therefore, in order to fully read the required data in the same row, multiple read commands need to be initiated while the target row remains in an active state. Each read command specifies a different column address in order to read the entire row of data in batches.

[0065] As can be seen from the above analysis, the mechanism for reading data from a row in storage bank 111 determines that the completion of reading the same row of data requires multiple read operations. That is, multiple read commands need to be issued to the same row in storage bank 111 to complete the reading of the data in that row. According to the JEDEC standard, the time interval between two adjacent read commands in multiple read commands for the same row must meet a preset interval. In this embodiment of the present disclosure, before performing the last read operation on the data of the nth row in the first target storage bank, a row activation command for the qth row in the second target storage bank is inserted between two adjacent read commands in the multiple read commands for the nth row. This is to pre-activate the qth row in the second target storage bank before completing the reading of the data of the nth row in the first target storage bank, so that the data of the qth row can be prepared in advance. The time required for the preparation of the data of the qth row overlaps with the reading time required for reading the remaining data of the nth row in the first target storage bank. In other words, the timing overhead required for cross-row switching between the first and second storage banks is completely hidden during the data reading operation of the other party. Thus, after reading the data of the nth row, there is no need to activate the qth row, thereby saving activation time. As a result, the reading of the data of the qth row can be performed faster, shortening the switching time between the first target storage and the second target storage.

[0066] JEDEC standards refer to open industry technical specifications developed and published by JEDEC (Solid State Technology Association, a global standards-setting body for the microelectronics industry), covering the electrical characteristics, timing parameters, packaging shapes, and testing methods of semiconductor memory devices (including DDR SDRAM, LPDDR SDRAM, HBM, etc.).

[0067] It is understandable that the nth row can be any row of the first target memory bank, and the qth row can also be any row of the second target memory bank. During the alternating access step, the switching of row reads between the first memory bank BANK1 and the second memory bank BANK2 can satisfy the above constraints.

[0068] The multiple word lines (i.e. multiple rows) in the first storage bank BANK1 can be defined as the first word lines WL1_1~WLx_1 arranged in order, where x is any integer greater than 1. The multiple word lines (i.e. multiple rows) in the second storage bank BANK2 can be defined as the second word lines WL1_2~WLi_2 arranged in order, where i is any integer greater than 1, and i and x can be the same or different.

[0069] In some examples, during the alternating access steps, the rows of the first memory bank BANK1 accessed in two adjacent first access steps can be two adjacent rows. For example, the two adjacent rows can be WL1_1 and WL2_1, meaning that the rows of the first memory bank BANK1 accessed in different first access steps can be accessed sequentially. Alternatively, the rows of the first memory bank BANK1 accessed in two adjacent first access steps can also be two non-adjacent rows. For example, the two non-adjacent rows can be WL2_1 and WL5_1, meaning that the rows of the first memory bank BANK1 accessed in different first access steps can be accessed randomly.

[0070] This disclosure does not limit the order in which the first memory bank BANK1 row is accessed in multiple first access steps. For example, the order in which the first memory bank BANK1 row is accessed in multiple first access steps can be a row-by-row ascending access order. In this way, adjacent rows can share local sensing amplifiers, avoiding frequent charging and discharging competition between different physical areas of the global data bus, thereby reducing dynamic power consumption, and the determined row address recursion mode simplifies the arbitration and scheduling logic of each command.

[0071] In some examples, during the alternating access steps, the rows of the second memory bank BANK2 accessed in two adjacent second access steps can be two adjacent rows. For example, the two adjacent rows can be WL1_2 and WL2_2, meaning that the rows of the second memory bank BANK2 accessed in different second access steps can be accessed sequentially. Alternatively, the rows of the second memory bank BANK2 accessed in two adjacent second access steps can also be two non-adjacent rows. For example, the two non-adjacent rows can be WL2_2 and WL5_2, meaning that the rows of the second memory bank BANK2 accessed in different second access steps can be accessed randomly.

[0072] This disclosure does not limit the order in which the second memory bank BANK2 rows are accessed in multiple second access steps. For example, the order in which the second memory bank BANK2 rows are accessed in multiple second access steps can be a row-by-row ascending access order. In this way, adjacent rows can share local sensing amplifiers, avoiding frequent charging and discharging competition between different physical areas of the global data bus, thereby reducing dynamic power consumption, and the determined row address recursion mode simplifies the arbitration and scheduling logic of each command.

[0073] Furthermore, in the alternating access steps, in adjacent first and second access steps, the order of rows accessed in the first access step of the first memory bank BANK1 can be the same or different from the order of rows accessed in the second access step of the second memory bank BANK2. This embodiment does not limit the relationship between the rows accessed in adjacent first and second access steps. For example, in adjacent first and second access steps, the order of rows accessed in the first access step of the first memory bank BANK1 can be the same as the order of rows accessed in the second access step of the second memory bank BANK2. For instance, the row accessed in the first access step is WL2_1, and the row accessed in the second access step following the first access step is WL2_2.

[0074] In some examples, in adjacent first and second access steps, the order of rows in the first memory bank BANK1 accessed in the first access step can be the same as the order of rows in the second memory bank BANK2 accessed in the second access step. In other words, the first row address information of the first memory bank BANK1 accessed in the first access step is the same as the second row address information of the second memory bank BANK2 accessed in the second access step; the main difference lies in the selected memory bank address information. Thus, the synchronous and sequential row addressing mode helps avoid the worst-case redundancy problem that may arise from random jumps. It replaces complex arbitration with a simplified row address recursion logic, reducing power consumption and control complexity without adding extra hardware overhead.

[0075] In some examples, the alternating access steps include: activating the nth row in the first target memory based on the address information of the first row, and performing m read operations in sequence to read the data of the nth row into the arithmetic unit, where m is a positive integer greater than 1; between the mkth read operation and the m-k+1th read operation in the m read operations, activating the qth row in the second target memory based on the address information of the second row, and after the m read operations are completed, reading the data of the qth row into the arithmetic unit 112, where 1≤k≤3, m>k, and k is a positive integer.

[0076] As discussed above, reading data from the current row of the first storage bank BANK1 can be done by reading all the data from the current row of the first storage bank BANK1, or by reading only a portion of the data from the current row of the first storage bank BANK1. This depends on the state of the data to be processed in the current row of the first storage bank BANK1. If the data to be processed is all the data in the current row of the first storage bank BANK1, then all the data is read out to the arithmetic unit; if the data to be processed is only a portion of the data in the current row of the first storage bank BANK1, then only a portion of the data is read out to the arithmetic unit 112.

[0077] Similarly, reading data from the current row of the second storage bank BANK2 can be done by reading all the data from the current row of the second storage bank BANK2, or by reading only a portion of the data from the current row of the second storage bank BANK2. This depends on the condition of the data to be processed in the current row of the second storage bank BANK2. If the data to be processed is all the data in the current row of the second storage bank BANK2, then all the data is read to the arithmetic unit; if the data to be processed is only a portion of the data in the current row of the second storage bank BANK2, then only a portion of the data is read to the arithmetic unit 112.

[0078] Correspondingly, m read operations can be used to read all or part of the data in the current row.

[0079] Activating row n in the first target memory based on the first row address information means activating / selecting row n as indicated by the first row address information in the first target memory, so that the data in row n is ready, and each read operation reads the data corresponding to a portion of the columns of row n. Activating row q in the second target memory based on the second row address information means activating / selecting row q as indicated by the second row address information in the second target memory, so that the data in row q is ready, and each read operation reads the data corresponding to a portion of the columns of row q.

[0080] Between the mk-th and m-k+1-th read operations in m read operations, the q-th row of the second target memory can be activated. This way, after the m read operations are completed, there is no need to perform row activation processing for the q-th row again, and the data of the q-th row can be directly read into the arithmetic unit. In this way, the activation time corresponding to the activation of the q-th row can be hidden in the reading step of the n-th row, thereby reducing the row switching time between different memory banks 111.

[0081] Understandably, k can be any value from 1 to 3, such as 1, 2, or 3. The value of k is related to tRAS(max) (Active to Precharge time_max, maximum row activation time) defined by the JEDEC standard, which refers to the maximum allowable time for a row to be precharged and turned off after being activated. If the value of k is too large, the waiting time between the activation of the q-th row of the second target memory and the receipt of the corresponding read command will be too long, which will increase the overall power consumption of the storage device and also cause charge leakage within the memory cell. Therefore, limiting k to the range of 1 to 3 can shorten the switching time between the first and second target memory while improving the accuracy of reading data from the pre-activated row.

[0082] Of course, in other examples, k can also be any integer greater than 3, as long as the operations on the q-th and n-th rows meet the timing requirements specified by JEDEC.

[0083] Figure 3 for Figure 1 A timing diagram showing the relevant commands and line address information in the storage device. Figure 3 In the command CMD, there are row activation commands (ACT), read commands (Ld_xx), and precharge commands (PRE). Command CMD also includes deselect commands (DES). Row address information includes row address information for the first target memory and row address information for the second target memory. Row address information B1_Rn indicates the nth row of the first target memory, and row address information B2_Rq indicates the qth row of the second target memory.

[0084] It should be noted that, Figure 3 This is merely to illustrate the command mapping relationship related to switching between the first target storage and the second target storage. Figure 3 The intervals between adjacent read commands, the number of read commands, and the time interval between the row activation command and the first read command for the first target memory are for illustrative purposes only and do not constitute a limitation. Similarly, the intervals between adjacent read commands, the number of read commands, and the time interval between the row activation command and the first read command for the second target memory are for illustrative purposes only and do not constitute a limitation.

[0085] Reference Figure 1 and Figure 3 Taking k=1 as an example, the working process of the storage device can include: Before performing the final read operation on the nth row of the first target memory, i.e., before sending the corresponding final read command Ld_xx, a row activation command ACT for the qth row of the second target memory is sent first. Then, the read command Ld_xx for the final read operation on the nth row of the first target memory is sent to complete the reading of data from the nth row of the first target memory. Next, the first read command Ld_xx for the qth row of the second target memory is sent to execute the first read operation step on the second target memory. Multiple read commands Ld_xx for the qth row of the second target memory are sent successively until, before performing the final read operation, i.e., before the last read command Ld_xx for the qth row, a row activation command ACT for the next row of the first target memory is sent first, followed by the last read command Ld_xx for the qth row of the second target memory. This process is repeated alternately until the required data is read.

[0086] In some examples, such as Figure 3 As shown, the storage device can be configured to receive a precharge command PRE for the nth row of the first target memory bank after receiving the last read command Ld_xx for the nth row of the first target memory bank and before receiving the first read command Ld_xx for the qth row of the second target memory bank, thereby turning off the nth row. In this way, turning off the nth row as soon as possible after completing the data reading of the nth row helps reduce the power consumption caused by turning on the nth row.

[0087] In other examples, the storage device can also be configured to receive a precharge command for the nth row in the first target memory after receiving the first read command for the qth row, thereby closing the nth row. This further reduces the switching time required to switch from the first target memory to the second target memory for reading the first data, thus further improving the computing power of the storage device.

[0088] Figure 4 Another functional block diagram of a storage device provided in an embodiment of this disclosure.

[0089] refer to Figure 4 The storage device includes a command issuing module 201 and a line cutting control module 202.

[0090] The command issuing module 201 is configured to provide the storage area 101 with a read command READ or a row operation command, the row operation command including the row activation command ACT.

[0091] The row-cutting control module 202 is configured to determine whether the row-cutting condition has been met. If so, the control command issuing module 201 provides the storage area 101 with a row activation command ACT corresponding to the second row address information before providing the (m-k+1)th read command READ to the storage area 101. The (m-k+1)th read command READ is used to trigger the (m-k+1)th read operation. If not, the control command issuing module 201 continues to provide the storage area 101 with one more read command READ.

[0092] The cut-off condition indicates that the mk-th read command has been provided, but the (m-k+1)-th read command has not been provided. In other examples, it can also be understood as indicating that the mk-th read operation has been performed, but the (m-k+1)-th read operation has not yet been performed.

[0093] The row-switching control module 202 can monitor the relationship between the current access address and the address of the opened / activated row (i.e., the nth row), and is also used to monitor whether the row-switching condition has been met. When it is determined that the row-switching condition has not been met (i.e., the access still falls within the currently activated row, and the mkth read command has not yet been provided), the command issuing module 201 does not need to insert an additional row activation command ACT, and can directly issue the subsequent read command READ. This avoids the timing penalties such as tRP (Row Precharge Time) and tRCD (RAS to CAS Delay) caused by unnecessary row precharge and row activation operations, which helps to shorten the interval between read commands READ and improve the utilization of the data bus. When the row-switching control module 202 determines that a row needs to be switched, it controls the command issuing module 201 to insert the corresponding row activation command ACT for the qth row in advance before the upcoming m-k+1th read command READ is issued. This predictive mechanism allows the time-consuming operation of row activation to overlap with the ongoing data transmission or command processing in time, thereby "hiding" the delay caused by row switching within the time window of the preceding operation.

[0094] By separating the functions of when to switch and when to issue commands, the line-switching control module 202 can be optimized independently without modifying the timing of the command-issuing module 201; similarly, the timing parameters in the command-issuing module 201 can be adjusted independently without affecting the address comparison and judgment logic. This architecture reduces design complexity and facilitates subsequent iterative upgrades. In other feasible examples, the line-switching control module 202 and the command-issuing module 201 can also be integrated into the same module, that is, the same module can be used to implement the functions of both the line-switching control module 202 and the command-issuing module 201, which facilitates more convenient scheduling of various commands.

[0095] The command issuing module 201 can be connected to the storage area 101. For example, the command issuing module 201 can be connected to both the first storage bank BANK1 and the second storage bank BANK2. The row cutting control module 202 can be connected to the command issuing module 201. For example, in some cases, the row cutting control module 202 can be located in the signal transmission path between the storage area 101 and the command issuing module 201.

[0096] Figure 5 This is a flowchart illustrating a process for determining whether a cutting condition has been met in a storage device.

[0097] refer to Figure 5 In some examples, the steps to determine whether the cut-off condition has been met include: S11. Obtain the address information of the first column corresponding to each read operation in the multiple read operations on the nth row.

[0098] S12. Based on the address information in the first column, determine whether the row cutting condition has been met. If yes, proceed to S13; otherwise, proceed to S14.

[0099] S13. Before providing the (m-k+1)th read command to the storage area, the control command issuing module first provides the storage area with a row activation command corresponding to the address information of the second row. The (m-k+1)th read command is used to trigger the (m-k+1)th read operation.

[0100] S14. The control command issuing module continues to provide a read command to the storage area.

[0101] Thus, by using the first column of address information corresponding to each read operation in multiple read operations, which is used to characterize the position of the data read in each read operation, or in other words, the first address information can reflect the number of read operations, it can be determined whether the read operation is the mkth read operation through the first column of address information.

[0102] It should be noted that in step S11, the first column address information corresponding to each read operation can be received, i.e., the first column address information corresponding to each read operation is obtained until the first target column address information is obtained. This first target column address information corresponds to the first column address information of the mk-th read operation, indicating that the corresponding read command is the mk-th read command. Alternatively, in step S11, the first column address information corresponding to each read operation can be received after several read operations. That is, the first column address information corresponding to the initial few read operations is not required. Instead, the first column address information corresponding to each read operation is obtained after several read operations until the first target column address information is obtained. This first target column address information corresponds to the first column address information of the mk-th read operation. This helps to reduce the amount of logical judgment in the row switching control module and thus reduce power consumption.

[0103] It is understandable that before step S11, the process may include S10, where the storage device enters PIM mode, and S101, where the row control module detects multiple consecutive read commands.

[0104] The consecutive read commands correspond to the commands for multiple read operations on the nth row of the first target memory. This means that the corresponding operation is to retrieve the data to be processed from the first memory and the second memory. Accordingly, step S11 needs to be executed.

[0105] Figure 6 This is another flowchart illustrating whether the cutting condition has been met in a storage device.

[0106] refer to Figure 6In other examples, the steps to determine whether the cut-off condition has been met include: S21. Obtain the number of read operations performed to access the nth row for a read operation.

[0107] S22. Based on the number of read operations, determine whether the row cutting condition has been met. If yes, proceed to S23; otherwise, proceed to S24.

[0108] S23. Before providing the m-k+1th read command to the storage area, the control command issuing module first provides the storage area with a row activation command corresponding to the address information of the second row. The m-k+1th read command is used to trigger the m-k+1th read operation.

[0109] S24. The control command issuing module continues to provide a read command to the storage area.

[0110] Thus, the number of read operations is used to determine whether the row cutting condition has been met. If the number of read operations is m-k+1, the row cutting condition has been met. If the number of read operations is less than m-k+1, the row cutting condition has not been met.

[0111] Before step S21, the process may include S20, where the storage device enters PIM mode, and S201, where the row-switching control module detects multiple consecutive read commands. These multiple consecutive read commands correspond to commands that perform multiple read operations on the nth row of the first target storage bank. This indicates that the corresponding operation is a data read operation to be processed from the first storage bank and the second storage bank. Accordingly, step S21 needs to be executed.

[0112] It should be noted that in step S21, each read operation requires a corresponding count, which can be performed using either addition or subtraction counting logic.

[0113] Figure 7 This is another functional block diagram for storage devices.

[0114] refer to Figure 7 The storage device may also include a counter 203, which is configured to count the number of read operations performed to access the nth row to perform a read operation, so as to obtain a count value; if the count value reaches a preset value, an identifier signal Flag is generated, which is used to indicate that the row cutting condition has been met.

[0115] The number of read operations is directly counted using counter 203. Counter 203 has a simple logic structure and low hardware overhead, and can achieve the counting of read operations with extremely low area and power consumption.

[0116] Counter 203 is also connected to row-switching control module 202, which receives the flag signal Flag output by counter 203. When the flag signal Flag indicates that the row-switching condition has been met, row-switching control module 202 controls command issuing module 201 to provide the (m-k+1)th read command to storage area 101 before providing the m-k+1th read command to storage area 101, first providing the row activation command ACT corresponding to the second row address information to storage area 101.

[0117] In some examples, if the flag signal is at a logic high level, it indicates that the row cutting condition has been met; if it is at a logic low level, it indicates that the row cutting condition has not been met. It is understood that, unless otherwise specified, the terms "high level" and "low level" in the embodiments of this disclosure are relative to the same command or signal, and can be understood as the common binary logic potentials in digital circuits of this art. They merely represent two relatively high and low potential states on the same signal line, and are not limited to specific voltage ranges, level standards, or supply voltages. A high-level period corresponds to a continuous time period during which the signal maintains a relatively higher potential; a low-level period corresponds to a continuous time period during which the signal maintains a relatively lower potential. A logic high level can correspond to logic "1", and a logic low level can correspond to logic "0".

[0118] Counter 203 can be connected to command issuing module 201 and / or storage area 101. Counter 203 is used to count the number of read operations performed on the same row. The way counter 203 counts the number of read operations performed on the nth row can be, but is not limited to, any of the following implementation methods: 1. Count the number of read commands (READ) received or issued. For example, counter 203 can be connected to command issuance module 201. Taking counter 203 as an adder counter as an example, every time command issuance module 201 issues a read command (READ) pointing to the nth row, counter 203 increments by 1 based on the current count value. This method has low implementation complexity and directly reflects the number of read requests initiated for the nth row, thus ensuring high counting accuracy.

[0119] 2. The number of clock cycles for data transmission from the nth row can be counted. It can be understood that the number of clock cycles for data transmission corresponding to one read operation is N1, where N1 can be an integer greater than or equal to 1. Based on the total number of clock cycles N2 for data transmission corresponding to the data read from the nth row, the number of read operations can be obtained. Taking N1 as 4 and counter 203 as an adder counter as an example, counter 203 increments by 1 for every 4 increments of N2. Taking N1 as 8 and counter 203 as an adder counter as an example, counter 203 increments by 1 for every 8 increments of N2.

[0120] In some embodiments, the counter 203 can be integrated into the command issuing module 201. This allows for full utilization of the existing address and command type information within the command issuing module 201, reusing the circuitry of the counter 203, thus simplifying its logic hardware implementation and avoiding the signal line extensions and interface logic introduced by adding an independent counter 203, thereby reducing chip area overhead. Furthermore, since the counting operation and the command issuing process can be in the same clock domain and processing pipeline, the counting result can be strictly synchronized with the command dispatch event, ensuring the accuracy and real-time performance of the count value. Simultaneously, this integration allows the counter 203 to be directly used for scheduling decisions within the command issuing module 201. For example, when the counter 203 detects that a read operation on the nth row has reached the row-cutting condition, it can directly trigger the row-cutting control module 202 to intervene or adjust the dispatch priority of subsequent commands, forming a fast closed-loop feedback, thereby significantly improving the response speed and further enhancing the overall scheduling efficiency of the memory device.

[0121] In other examples, the counter can be independent of the command issuing module, or it can be integrated into the line-cutting control module, or it can be positioned between the first memory and the arithmetic unit, and between the second memory and the arithmetic unit.

[0122] Figure 8 This is a timing diagram representing the relevant commands and data read by the arithmetic unit in related technologies. Figure 9 This is a timing diagram of related commands and data read by the arithmetic unit in a storage device provided in some embodiments of this disclosure. Figure 8 and Figure 9 Taking reading data from the first row of the first target memory and the first row of the second target memory as an example, in the relevant command CMD, ACT8b_1 and ACT_2 together constitute the row activation command ACT, Ld_xx is the read command, Precharge is the precharge command, and PU corresponds to the data read by the arithmetic unit. Furthermore, nLLD, tRTP, tRP, tRCD, and tRL_PU are the relevant timing requirements specified by the JEDEC standard. nLLD is the time interval between two adjacent read commands, tRTP (Read to Precharge) is the delay between the read command and the precharge command, tRL_PU is the time interval between a read command and the arithmetic unit reading the data, tRCD is the minimum time interval required from issuing the row activation command to issuing a read command for the activated target row, and tRP (Row Precharge Time) refers to the minimum time required to close the currently active row and "precharge" it in preparation for opening a new row. Figure 8 and Figure 9The text also illustrates the last read command in the first line of the first target memory.

[0123] like Figure 8 As shown, in related technologies, the switching time Timing1 between the first target memory and the second target memory is the sum of the durations of tRTP, tRP, and tRCD. For example... Figure 9 As shown, in some embodiments of this disclosure, the switching time Timing2 between the first target memory and the second target memory is nLLD. The switching time Timing2 is much shorter than the switching time Timing1, which means that compared with related technologies, the switching time between different memory can be significantly shortened, thereby improving the computing power of the storage device.

[0124] Understandable, Figure 9 In this configuration, the first read command for the second target memory is provided first, followed by the precharge command for the first row of the first target memory. Alternatively, as discussed earlier, the precharge command for the first row of the first target memory can be provided first, followed by the first read command for the second target memory.

[0125] Figure 10 This is another block diagram of a storage device.

[0126] refer to Figure 10 The line-cutting control module 202 may include a command detection circuit 212, a line-cutting analysis circuit 222, and a command scheduling circuit 232.

[0127] The command detection circuit 212 is connected to the command issuing module 201. The command detection circuit 212 is configured to detect whether the current command is a read command (READ).

[0128] The row-cutting analysis circuit 222 is configured to determine whether the row-cutting condition has been met.

[0129] The command scheduling circuit 232 is connected to the command issuing module, the command detection circuit 212, and the row-cutting analysis circuit 222. The command scheduling circuit 232 is configured to generate and output scheduling information SI if the current command is a read command READ and the row-cutting condition is met. The scheduling information SI is used to trigger the command issuing module 201 to provide a row activation command ACT corresponding to the second row address information before providing the next read command READ.

[0130] Reference Figure 5 , Figure 6 and Figure 10The command detection circuit 212 can also be used to detect whether there are multiple consecutive read commands. The row-cutting analysis circuit 222 can be connected to the command detection circuit 212. If the command detection circuit 212 detects multiple consecutive read commands, the row-cutting analysis circuit 222 can determine whether the row-cutting condition has been met. The method by which the row-cutting analysis circuit 222 determines whether the row-cutting condition has been met may include, but is not limited to, determining whether the row-cutting condition has been met based on the first column address information, or determining whether the row-cutting condition has been met based on the number of read operations. If the row-cutting condition is met, the command scheduling circuit 232 generates scheduling information for inserting a row activation command ACT corresponding to the second row address information before issuing the next read command READ.

[0131] It is understood that the row-slicing analysis circuit 222 may include the aforementioned counter 203 (see reference). Figure 7 The counter 203 outputs a flag signal Flag, which is provided to the command scheduling circuit 232. The command scheduling circuit 232 outputs scheduling information SI in response to the flag signal Flag.

[0132] Figure 11 This is another functional block diagram for a storage device.

[0133] refer to Figure 11 In some embodiments, the storage device may further include: a memory controller 200, a command issuing module 201, and a row cutting control module 202, all of which may be located in the memory controller 200.

[0134] The memory controller 200 is connected to both the storage area 101 and the arithmetic area 102. By placing the command issuing module 201 and the row-switching control module 202 within the memory controller 200, both modules can operate in the same clock domain, avoiding potential delays caused by different clock domains. This ensures that row activation commands are precisely inserted between adjacent read commands without affecting critical timing paths of the storage device. Furthermore, placing the command issuing module 201 and the row-switching control module 202 within the memory controller 200 reduces cost and power consumption, and allows the use of the existing command issuing module, avoiding excessive additional circuit area.

[0135] In addition, the command issuing module 201 and the row cutting control module 202 can be integrated into the row cutting planning module, and the row cutting planning module can be integrated into the memory controller 200.

[0136] In other examples, the line-switching control module can also be located within the host, or it can be located within storage area 101, for example, within the on-chip controller of the storage area.

[0137] Both the first and second line of address information can be provided to the storage device by the host. This helps reduce the hardware overhead of the storage device's internal logic. Since both lines of address information can be provided by the host, the combinational logic circuits related to address calculation within the storage device are saved, which helps reduce the area of ​​the storage device. In addition, since both lines of address information are provided by the host, the address mapping and decoding logic in related technologies can be followed without large-scale modifications to the storage device's interface, which helps shorten the product development cycle.

[0138] Of course, in some cases, the first and second lines of address information can also be generated internally by the storage device.

[0139] Figure 12 This is another functional block diagram for storage devices.

[0140] refer to Figure 12 In some examples, the arithmetic area 102 may also include multiple row address generation circuits 20, each of which corresponds to the arithmetic unit 112; wherein, the row address generation circuit 20 is configured to generate a first internal row address and a second internal row address, the first internal row address serving as first row address information and the second internal row address serving as second row address information.

[0141] In other words, the arithmetic area 102 includes a row address generation circuit 20, which generates first row address information and second row address information. This reduces the frequency of command interactions between the host and the storage device. The row address generation circuit 20 generates the first internal row address and the second internal row address according to a preset address generation rule, reducing the transmission load on the command bus. For example, the preset address rule may include, but is not limited to, incremental row-by-row access to the first target memory and incremental row-by-row access to the second target memory.

[0142] Figure 13 This is a partial cross-sectional structural diagram of a storage device.

[0143] refer to Figure 13 In some examples, storage area 101 (reference) Figure 1 It can be located within the first chip 301, and the arithmetic area 102 (see reference). Figure 1 The first chip 301 and the second chip 302 are bonded together and can be located within the second chip 302. That is, the storage area 101 and the processing area 102 are three-dimensional structures. The first chip 301 can be a storage chip, and the second chip 302 can be a logic chip.

[0144] The first chip 301 and the second chip 302 can be bonded together using methods including but not limited to hybrid bonding (HB).

[0145] In other examples, storage area 101 and arithmetic area 102 may also be located on the same chip. That is, storage area 101 and arithmetic area 102 are located on the same memory chip, and storage area 101 and arithmetic area 102 are two-dimensional on-die structures.

[0146] The embodiments disclosed herein do not limit the physical structure layout of the storage device; the storage device can be a two-dimensional structure or a three-dimensional structure.

[0147] Figure 14 and Figure 15 This diagram illustrates two different connections between the arithmetic logic unit (ALU) and the memory, as well as a data reading diagram. Figure 14 In the middle, the arithmetic unit 112 is connected to two memory banks, which are identified as BANK1 (as the first target memory bank) and BANK2 (the second target memory bank). Figure 15 In the process, the arithmetic unit 112 is connected to four memory banks. Data in memory banks BANK1_1 and BANK1_2 (both serving as the first target memory banks) can be read into the arithmetic unit 112 simultaneously, and data in memory banks BANK2_1 and BANK2_2 (both serving as the second target memory banks) can be read into the arithmetic unit 112 simultaneously. ROW 0 to ROW X refer to multiple rows (i.e., multiple word lines) in each memory bank.

[0148] refer to Figure 14 and Figure 15 The data reading process can be as follows: The data in ROW 0 of the first target storage BANK1 (or BANK1_1 and BANK1_2) is read into the arithmetic unit 112 in the order of Data 0 to Data k. Before reading the Data k data, a row activation command for ROW 0 of the second target storage BANK2 can be sent to activate ROW 0 of the second target storage BANK2 (or BANK2_1 and BANK2_2). Then, the data Data k (corresponding to identifier ①) in ROW 0 of the first target storage BANK1 (or BANK1_1 and BANK1_2) is read. Next, read the data Data k+1 (corresponding to identifier ②) to Data 2k+1 (corresponding to identifier ③) in the ROW 0 row of the second target storage BANK2 (or BANK2_1 and BANK2_2) sequentially; before reading the data Data 2k+2 in the ROW 0 row of the second target storage BANK2 (or BANK2_1 and BANK2_2), send the row activation command for the ROW 1 row of the first target storage BANK1 (or BANK1_1 and BANK1_2), and then read the data Data 2k+2 in the ROW 0 row of the second target storage BANK2 (or BANK2_1 and BANK2_2); Then, sequentially read the data Data 2k+3 (corresponding to identifier ④) to Data 3k+2 in the ROW 1 row of the first target storage BANK1 (or BANK1_1 and BANK1_2). Before reading the data Data 2k+3 in the ROW 1 row of the first target storage BANK1 (or BANK1_1 and BANK1_2), first send the row activation command for the ROW 1 row of the second target storage BANK2 (or BANK2_1 and BANK2_2), and then read the data Data 2k+3 in the ROW 1 row of the first target storage BANK1 (or BANK1_1 and BANK1_2).

[0149] This process is repeated until the required data is obtained.

[0150] In the above technical solution, before reading the data of the nth row of the first target storage, the qth row of the second target storage is activated first, so that the activation time corresponding to the row activation of the qth row overlaps with the time for reading the data of the nth row. This can shorten the switching time between the first target storage and the second target storage, improve the switching speed, and thus improve the data reading speed, thereby improving the computing power of the storage device.

[0151] For example, when reading the first and last data of a row between different memory banks, inserting a row activation command eliminates the time spent switching between rows, thus eliminating the row activation time of the next row when switching rows. Furthermore, inserting a precharge command for the nth row after the first read command for the qth row also eliminates the precharge time of the previous row (i.e., the qth row), thereby further improving the computing power of the storage device.

[0152] This disclosure also provides a storage system including a storage device, which can be an integrated circuit or a memory chip provided in any of the above embodiments. Therefore, the corresponding descriptions of the foregoing embodiments are also applicable to the embodiments of the storage system. To avoid redundancy, descriptions that are the same as or corresponding to the foregoing embodiments can be referred to the foregoing descriptions, and will not be repeated hereafter.

[0153] Figure 16 A block diagram of a storage system.

[0154] refer to Figure 16 The storage system may include the storage device 100 provided in any of the above embodiments.

[0155] The storage system may include a host 401 and a storage device 100, which may be the storage device described in any of the above embodiments.

[0156] In some embodiments, the storage system may be a storage device that includes volatile memory cells. For example, the storage system may include various dynamic random access memories (DRAMs), such as double data rate synchronous DRAM, DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, DDR5 SDRAM, DDR6 SDRAM, or low power double data rate SDRAM, LPDDR2 SDRAM, LPDDR3 SDRAM, LPDDR4 SDRAM, LPDDR5 SDRAM, LPDDR6 SDRAM, LPDDR7 SDRAM. The volatile memory cells may also include SRAM.

[0157] In other embodiments, the storage system may include, in addition to volatile memory cells, non-volatile memory cells such as NAND flash memory, NOR flash memory, RRAM, FRAM, PRAM, TRAM, or MRAM.

[0158] Storage devices may include memory modules, such as SIMM memory modules or DIMM memory modules. A memory module may include one or more memory blocks (RANKs), such as one RANK, two RANKs, or four or more RANKs.

[0159] Accordingly, this disclosure also provides an electronic device, which may include the storage device or storage system provided in any of the above embodiments. Therefore, the description of the above embodiments is also applicable to the embodiments of the following electronic device.

[0160] Figure 17 A block diagram of an electronic device.

[0161] refer to Figure 17The electronic device includes the storage device or storage system that can be provided in the above embodiments.

[0162] In some examples, the electronic device may include a storage device 100.

[0163] The electronic device may also include a processing unit 402, which is connected to the storage device 100.

[0164] The processing device 402 described above may refer to one or more processors. For example, the processing device 402 may include one or more central processing units (CPUs), or it may include a CPU and a graphics processing unit (GPU), or it may include an application processor and a coprocessor (e.g., a microcontroller unit or neural network processor). When the processing device 402 includes multiple processors, these processors may be integrated on the same chip or may be independent chips. A processor may include one or more physical cores, where a physical core is the smallest processing module.

[0165] Schematic, the processing device 402 may be implemented in at least one of the following hardware forms: Digital Signal Processing (DSP), Field Programmable Gate Array (FPGA), and Programmable Logic Array (PLA).

[0166] The processing device 402 may integrate one or a combination of several of the following: a central processing unit (CPU), a graphics processing unit (GPU), and a modem.

[0167] Electronic devices can include one or more of the following: smartphones, personal computers (PCs), mobile phones, video phones, e-book readers, desktop PCs, laptop PCs, netbooks, workstations, servers, personal digital assistants (PDAs), portable media players (PMPs), mobile medical devices, cameras, home appliances, medical devices, Internet of Things (IoT) devices, and wearable devices. Wearable devices can be accessory-type, fabric or clothing-type, body-attached type, or implantable circuit type. Accessory-type wearable devices can be, for example, watches, rings, bracelets, anklets, necklaces, glasses, contact lenses, or head-mounted displays (HMDs).

[0168] In some embodiments, the electronic device can also be used in large servers, such as data centers, HPC (High Performance Computing) products, or AI (Artificial Intelligence) computers.

[0169] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A memory device, comprising: include: The storage area includes multiple storage blocks, and each of the multiple storage blocks includes multiple storage units; The arithmetic area includes a plurality of arithmetic units, at least one of which is configured to perform arithmetic processing using data obtained from at least two storage banks, the at least two storage banks including a first storage bank and a second storage bank; The storage area is configured to perform alternating access steps on a row-by-row basis; the alternating access steps include: performing a first access step to read data from the current row of the first storage unit via multiple read operations, performing a second access step after the first access step to read data from the current row of the second storage unit via multiple read operations, and alternatingly performing the first access step and the second access step until the required data is read into the arithmetic unit. In the alternating access step, before performing the last read operation on the data in the nth row of the first target memory, the qth row of the second target memory is activated first. The first target memory is one of the first memory and the second memory, and the second target memory is the other of the first memory and the second memory. Both n and q are positive integers greater than or equal to 1.

2. The memory device of claim 1, wherein, The alternating access step includes: activating the nth row in the first target memory based on the first row address information, and performing m read operations in sequence to read the data of the nth row into the arithmetic unit, where m is a positive integer greater than 1; Between the mk-th and m-k+1-th read operations in the m read operations, the q-th row in the second target memory is activated based on the second row address information, and after the m read operations are completed, the data of the q-th row is read into the arithmetic unit, 1≤k≤3, m>k, and k is a positive integer.

3. The memory device of claim 2, wherein, The storage device includes: The command issuing module is configured to provide read commands or row operation commands to the storage area, wherein the row operation commands include row activation commands. The row-cutting control module is configured to determine whether a row-cutting condition has been met. The row-cutting condition indicates that the mk-th read command has been provided, but the (m-k+1)-th read command has not been provided. If so, the command issuing module is controlled to provide the storage area with a row activation command corresponding to the second row address information before providing the (m-k+1)-th read command to the storage area. The (m-k+1)-th read command is used to trigger the (m-k+1)-th read operation. If not, the command issuing module is controlled to continue providing one more read command to the storage area.

4. The memory device of claim 3, wherein, The determination of whether the cutting condition is met includes: Obtain the address information of the first column corresponding to each read operation in multiple read operations on the nth row; Based on the address information in the first column, determine whether the row cutting condition has been met; or... Get the number of read operations performed to access the nth row; Based on the number of read operations, determine whether the row cutting condition has been met.

5. The memory device of claim 4, wherein, The storage device further includes a counter, the counter being configured to, The number of read operations performed to access the nth row is counted to obtain a count value; If the count value reaches a preset value, an identification signal is generated, which is used to indicate that the cutting condition has been met.

6. The memory device of claim 5, wherein, The counter is integrated into the command issuing module.

7. The memory device of any one of claims 3 to 6, wherein, The row cutting control module includes: A command detection circuit is connected to the command issuing module, and the command detection circuit is configured to detect whether the current command is a read command. The row-cutting analysis circuit is configured to determine whether the row-cutting condition has been met. The command scheduling circuit, which is connected to the command issuing module, the command detection circuit, and the row-cutting analysis circuit, is configured to generate and output scheduling information if the current command is a read command and the row-cutting condition is met. The scheduling information is used to trigger the command issuing module to provide a row activation command corresponding to the second row address information before providing the next read command.

8. The storage device according to any one of claims 3 to 6, characterized in that, The storage device further includes: The memory controller, the command issuing module, and the row cutting control module are all located in the memory controller.

9. The storage device according to any one of claims 1 to 6, characterized in that, The storage device is also configured to receive a precharge command for the nth row in the first target memory after receiving the first read command for the qth row, so as to close the nth row.

10. The storage device according to any one of claims 2 to 6, characterized in that, Both the first row of address information and the second row of address information are provided by the host.

11. The storage device according to any one of claims 2 to 6, wherein the arithmetic area further comprises a plurality of row address generation circuits, each of the plurality of row address generation circuits corresponding to the arithmetic unit; wherein, The row address generation circuit is configured to generate a first internal row address and a second internal row address, wherein the first internal row address is used as the first row address information and the second internal row address is used as the second row address information.

12. The storage device according to any one of claims 2 to 6, characterized in that, k is 1.

13. The storage device according to any one of claims 1 to 6, characterized in that, The storage area and the computing area are located within the same chip; or, the storage area is located within a first chip, and the computing area is located within a second chip, with the first chip and the second chip being bonded together.

14. A storage system, characterized in that, Includes the storage device as described in any one of claims 1 to 13.

15. An electronic device, characterized in that, Includes the storage device as described in any one of claims 1 to 13, or the storage system as described in claim 14.

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