Memory device and erase method thereof

Abstract

A memory device and a method of testing the same, a memory device and a method of erasing the same. The memory device includes a memory array and a memory controller. The memory array includes a plurality of erase units formed in a plurality of semiconductor wells corresponding thereto. The memory controller is coupled to the memory array, and the memory controller performs an erase operation to erase the erase units corresponding to the semiconductor wells of the memory array. The memory controller biases the semiconductor wells with a first well bias voltage and a second well bias voltage during the erase operation, wherein the first well bias voltage is different from the second well bias voltage.

Description

Technical Field

[0001] This disclosure relates to a technique for preventing over-erasing, and more particularly to a memory device and erasing method thereof that can suppress over-erasing of memory cells in a memory device. Background Technology

[0002] In flash memory devices, memory cells are erased in units of a specific size. When an erase operation is performed on an erase cell, some cells are erased faster than others. In other words, each erase cell may have randomly distributed slow-erasing cells (i.e., slow bits) and fast-erasing cells (i.e., fast bits). However, regardless of whether they are fast or slow erase cells, the same erase voltage is applied to all cells in the erase cell until the erase operation is complete. Therefore, by the time the slow erase cells reach their target erase voltage, the fast erase cells may have already been over-erased. Thus, the erase operation results in many over-erased cells in the memory device. A novel memory device and its erase method are needed to suppress over-erasing of memory cells in the memory device. Summary of the Invention

[0003] The memory device of the present invention includes a memory array and a memory controller. The memory array includes a plurality of erase cells formed in a plurality of corresponding semiconductor wells. The memory controller is coupled to the memory array and performs an erase operation to erase the erase cells corresponding to the semiconductor wells of the memory array. During the erase operation, the memory controller biases the semiconductor wells with a first well bias voltage and a second well bias voltage, wherein the first well bias voltage is different from the second well bias voltage.

[0004] The present invention discloses an erasure method for a memory device, wherein the memory device includes a memory array and a memory controller. The erasure method includes the steps of biasing a top well pickup region of a semiconductor well with a first well bias voltage during an erasure operation by the memory controller, wherein the top well pickup region of the semiconductor well corresponds to an erasure cell of the memory array; and the steps of biasing a bottom well pickup region of the semiconductor well with a second well bias voltage during the erasure operation by the memory controller, wherein the bottom well pickup region of the semiconductor well corresponds to an erasure cell of the memory array. The first well bias voltage and the second well bias voltage are different.

[0005] Based on the above, during the erase operation, the semiconductor well corresponding to the erase cell of the memory device is biased by a first well bias voltage and a second well bias voltage. The first well bias voltage can bias the top well pickup region of the semiconductor well, and the second well bias voltage can bias the bottom well pickup region of the semiconductor well, and the second well bias voltage can be less than the first well bias voltage. Memory cells or memory segments located near the top well pickup region are erased faster than memory cells or memory segments located near the bottom well pickup region. Thus, the erase speed of the erase operation performed by the erase cell is controllable. Each erase cell may include multiple memory segments. When a specific erase segment passes the erase verification, a flag is set on the specific erase segment, and a countervoltage is applied to the word line connected to the specific erase segment to prevent further erasure in subsequent erase steps. An erase voltage is applied to the word line connected to memory segments that do not pass the erase verification. Thus, specific memory cells that pass the erase verification will not be further erased, thereby avoiding over-erasure. The memory controller can increase the second well bias voltage in response to a predetermined number of memory segments passing verification, thereby accelerating the erase operation.

[0006] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0007] Figure 1 These are schematic diagrams of a memory device illustrated in some embodiments;

[0008] Figure 2A and Figure 2B This is a schematic diagram of the erasing unit of the erasing device during an erasing operation, as shown in some embodiments;

[0009] Figure 3 This is a flowchart of an erasing method based on an erasing apparatus as shown in some embodiments. Detailed Implementation

[0010] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0011] Figure 1A schematic diagram of a memory device 100 according to some embodiments is shown. The memory device 100 includes a memory array 110, a memory controller 120, and a power supply circuit 130. The memory array 110 may include a plurality of memory cells (not shown) divided into a plurality of erase units 111_1 to 111_n, where n is a positive integer. Each erase unit may have a specific size (i.e., 64KB), but this disclosure is not intended to limit it. The size of each erase unit 111_1 to 111_n may vary depending on design requirements. Each erase unit 111_1 to 111_n may include a plurality of memory cells (not shown), and erase verification is performed on the memory cells of the erase units 111_1 to 111_n. The memory device 100 may be a NOR flash memory device or a NAND flash memory device, and this disclosure does not limit the memory device to any particular type of memory.

[0012] In some embodiments, erase cells 111_1 to 111_n of the memory array 110 are formed on semiconductor wells (not shown) corresponding to the erase cells 111_1 to 111_n. In one embodiment, each erase cell 111_1 to 111_n is formed on its corresponding semiconductor well. When an erase operation is performed on an erase cell, an appropriate bias voltage can be applied to the word line, bit line, and source line, which are connected to the memory cell of the erase cell. Furthermore, during the erase operation on the erase cells 111_1 to 111_n, different well bias voltages (i.e., a first well bias voltage V1 and a second well bias voltage V2) supplied by the power supply circuit 130 are applied to the semiconductor well bias voltages of the corresponding erase cells 111_1 to 111_n. The first well bias voltage V1 may be different from the second well bias voltage V2. In some embodiments, the second well bias voltage V2 is lower than the first well bias voltage V1. The semiconductor well may be a P-type semiconductor well, but this disclosure should not be limited thereto. In some alternative embodiments, the semiconductor well may be an N-type semiconductor well.

[0013] A power supply circuit 130 is connected to the memory array 110 and configured to generate and supply different voltages to the memory array 110 and the memory controller 120. The power supply circuit 130 can generate and supply appropriate voltages to bias word lines, bit lines, and source lines connected to memory cells of the memory array 110 during memory operations (e.g., read, write, and erase). Additionally, the power supply circuit 130 can generate and supply a first well bias voltage V1 and a second well bias voltage V2 during erase operations to bias the semiconductor wells corresponding to the erased cells. In some embodiments, the power supply circuit 130 may include a shared power source (not shown) for generating the first well bias voltage V1 and the second well bias voltage V2 for erase operations. In some alternative embodiments, the power supply circuit 130 may include a first power source (not shown) and a second power source (not shown) for generating the first well bias voltage V1 and the second well bias voltage V2, respectively.

[0014] Memory controller 120 is connected to memory array 110 and power supply circuit 130, and is configured to control the operation of memory array 110 and power supply circuit 130. Memory controller 120 can control power supply circuit 130 to generate and provide appropriate voltage to memory operations (i.e., read operations, write operations, and erase operations) performed on memory array 110. Memory controller 120 can control the timing of applying voltage to the memory cells of memory array 110 to perform memory operations. This disclosure does not limit the circuit structure of memory array 110, memory controller 120, and power supply circuit 130 of memory device 100.

[0015] Figure 2A A schematic diagram of an erasing unit 111 during an erasing operation is shown according to some embodiments. The erasing unit 111 may be... Figure 1Eraser unit 111 is any one of eraser units 111_1 to 111_n in memory array 110. Eraser unit 111 may be formed in a semiconductor well PWELL, and the semiconductor well PWELL includes a top well pickup region 113, a memory region 115, and a bottom well pickup region 117. During the erase operation, the top well pickup region 113 and the bottom well pickup region 117 may be biased with a first well bias voltage V1 and a second well bias voltage V2, respectively. The first well bias voltage V1 is different from the second well bias voltage V2. In some embodiments, the second well bias voltage V2 is lower than the first well bias voltage V1. Memory region 115 may include a plurality of memory segments 1151, 1153, 1155, and 1157, and each memory segment 1151 to 1157 may include a plurality of memory cells. The memory segments 1151 to 1157 can be arranged sequentially from the top well pick-up area 113 to the bottom well pick-up area 117.

[0016] Semiconductor wells (PWELLs) can have parasitic resistance, such as... Figure 2A Resistors R11, R12, R13, and R14 are shown in the diagram. Resistor R11 represents the parasitic resistance corresponding to the well region of memory segment 1151, resistor R12 represents the parasitic resistance corresponding to the well region of memory segment 1153, resistor R13 represents the parasitic resistance corresponding to the well region of memory segment 1155, and resistor R14 represents the parasitic resistance corresponding to the well region of memory segment 1157. In the current path from the top well pickup region 113 to the bottom well pickup region 117, resistors R11 to R14 cause a voltage drop along the current path. The current path may include points P1, P2, and P3 between memory segments 1151 and 1157. Specifically, point P1 may be located between memory segments 1151 and 1153, point P2 may be located between memory segments 1153 and 1155, and point P3 may be located between memory segments 1155 and 1157. Due to parasitic resistance along the current path from the top well pickup region 113 to the bottom well pickup region 117, a voltage drop occurs along the current path. The resistance of resistor R11 causes a voltage drop at point P1, the sum of the resistances of resistors R11 and R12 causes a voltage drop at point P2, and the sum of the resistances of resistors R11, R12, and R13 causes a voltage drop at point P3. Thus, the voltages at points P1, P2, and P3 can be voltages V11, V12, and V13, respectively, where the second well bias voltage V2 is less than voltage V13, voltage V13 is less than voltage V12, voltage V12 is less than voltage V11, and voltage V11 is less than the first well bias voltage V1.

[0017] During the erase operation of erase unit 111, top well pickup region 113 is biased with a first well bias voltage V1, and bottom well pickup region 117 is biased with a second well bias voltage V2. The second well bias voltage V2 is lower than the first well bias voltage V1. Due to the voltage drop along the current path from top well pickup region 113 to bottom well pickup region 117, the well regions corresponding to memory segments 1151 to 1157 are biased with different voltages. For example, the well region corresponding to memory segment 1151 can be biased with voltage V11, the well region corresponding to memory segment 1153 can be biased with voltage V12, the well region corresponding to memory segment 1155 can be biased with voltage V13, and the well region corresponding to memory segment 1157 can be biased with the second well bias voltage V2.

[0018] Because voltage V11 is greater than voltage V12, memory cells in memory segment 1151 can be erased faster than memory cells in memory segment 1153. In other words, erasing memory segment 1151 can be faster than erasing memory segment 1153. Similarly, erasing memory segment 1153 can be faster than erasing memory segment 1155, and erasing memory segment 1155 can be faster than erasing memory segment 1157. As a result, memory segments closer to the top well pick-up area 113 can be erased earlier than memory segments closer to the bottom well pick-up area 117.

[0019] In some embodiments, the memory controller 120 is further configured to perform erase verification to determine whether each memory cell in memory segments 1151 to 1157 has reached a target erase threshold. When it is determined that the memory cells in a particular memory segment have reached the target erase threshold, the particular memory segment passes the erase verification. In some embodiments, the memory controller 120 may perform erase verification sequentially from memory segments arranged from the top well pickup area 113 to the bottom well pickup area 117. Figure 2A Taking the erase unit 111 as an example, the memory controller 120 performs erase verification sequentially from memory segment 1151 to memory segment 1157.

[0020] In some embodiments, when a specific memory segment passes erase verification, the memory controller 120 is configured to set a flag on the specific memory segment. This flag indicates that the specific memory segment has passed erase verification, and the memory controller 120 may set a counter voltage to the word line connected to the memory cell of the specific memory segment to prevent further erasure during subsequent erase steps. The memory controller 120 may continue to perform subsequent erase steps on memory segments that have failed erase verification by applying an erase voltage to the word line connected to the memory cell of a memory segment that has failed erase verification. This disclosure does not limit the voltage levels of the counter voltage and the erase voltage to any specific values.

[0021] In some embodiments, in response to determining that a predetermined number of memory segments in the erase unit 111 have passed erase verification, the memory controller 120 may adjust the voltage level of the second well bias voltage V2 applied to the bottom well pickup region 117. The memory controller 120 may also adjust the voltage level of the first well bias voltage V1 as needed. The predetermined number of memory segments may be set to half the total number of memory segments in the erase unit 111, but this disclosure is not limited thereto.

[0022] Figure 2B This diagram illustrates an erase unit 111 during an erase operation, according to some embodiments, when a predetermined number of memory segments pass the erase verification. Figure 2A and Figure 2B Identical components are represented by the same element symbol. (See reference...) Figure 2B Assuming memory segments 1151 and 1153 have passed erase verification, while memory segments 1155 and 1157 have not, the memory controller 120 can set flags for memory segments 1151 and 1153 to indicate that these memory segments have passed erase verification. Simultaneously, the memory controller 120 can apply opposing voltages Vc to the word lines connected to memory segments 1151 and 1153 to prevent further erasure of these memory segments. The memory controller 120 can apply erase voltage Ve to the word lines connected to memory segments 1155 and 1157 to continue erasing memory segments 1155 and 1157.

[0023] When a predetermined number of memory segments have passed erase verification, the memory controller 120 can adjust the second well bias voltage V2 to voltage V2', where voltage V2' is greater than the second well bias voltage V2, thereby accelerating the erase speed of memory segments 1155 and 1157. In some embodiments, the voltage V2' biased to the bottom well pickup region 117 can be set to be substantially the same as the first well bias voltage V1 biased to the top well pickup region 113. In this way, over-erasure can be prevented while improving the overall erase speed of the erase operation on the erase unit 111. Thereby, the memory device 100 can reduce the risk of over-erasure when performing erase operations on erase units with randomly distributed slow and fast erase memory cells (or slow / fast erase bits).

[0024] Figure 3 The illustration shows some embodiments applicable to memory devices (i.e. Figure 1 A flowchart of an erasure method for a memory device 100 in the memory array is shown. In block 310, during the erasure operation, the memory controller biases the top well pickup region of the semiconductor well with a first well bias voltage, wherein the top well pickup region corresponds to the erase cell of the memory array. Figure 2A and Figure 3 As shown, during an erase operation, the memory controller can bias the top well pickup region 113 of the semiconductor well PWELL corresponding to the erase cell 111 of the memory array with a first well bias voltage V1. In block 320, during the erase operation, the memory controller biases the bottom well pickup region of the semiconductor well with a second well bias voltage, where the bottom well pickup region corresponds to the erase cell of the memory array. The first well bias voltage is different from the second well bias voltage. Figure 2A and Figure 3 As shown, the memory controller 120 can bias the bottom well pickup region 117 of the semiconductor well PWELL corresponding to the erase cell 111 of the memory array with a second well bias voltage V2 during an erase operation. The second well bias voltage V2 is different from the first well bias voltage V1.

[0025] According to embodiments disclosed herein, the memory array of a memory device may include erase cells formed in semiconductor wells. During an erase operation on an erase cell, the memory controller of the memory device may apply a first well bias voltage and a second well bias voltage to the semiconductor well corresponding to the erase cell. The top well pickup region of the semiconductor well is biased by the first well bias voltage, and the bottom well pickup region of the semiconductor well is biased by the second well bias voltage. The second well bias voltage may be less than the first well bias voltage. In this way, the erase speed of the memory cell or memory segment in the erase cell can be controlled by setting the first well bias voltage and the second well bias voltage. When a specific erase segment of the erase cell passes erase verification, a flag is set on the specific erase segment, and a countervoltage is applied to the word line connected to the specific memory segment to prevent further erasure in subsequent erase steps. Therefore, the risk of over-erasing a specific memory cell that has passed erase verification can be prevented. In response to a predetermined number of memory segments passing the erase verification, the memory controller can further increase the second well bias voltage, thereby accelerating the erase operation. Even if there are randomly distributed fast and slow erase cells in the erase cells of the memory array, the memory device can prevent the memory cells in the memory array from being over-erased.

[0026] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory device, characterized in that, include: A memory array including multiple erase units, wherein the multiple erase units are formed in multiple semiconductor wells corresponding to the multiple erase units; The memory controller performs an erase operation to erase the erase cells corresponding to the semiconductor wells of the memory array; The memory controller biases the semiconductor well with a first well bias voltage and a second well bias voltage during the erase operation, wherein the first well bias voltage is different from the second well bias voltage.

2. The memory device according to claim 1, characterized in that, The semiconductor well corresponding to the erasure unit includes: Top well pickup area; Bottom well pickup area; and The storage unit region includes multiple memory segments arranged from the top well pickup region to the bottom well pickup region, and each of the multiple memory segments includes multiple storage units. The memory controller biases the top well pickup region with the first well bias voltage and the bottom well pickup region with the second well bias voltage.

3. The memory device according to claim 2, characterized in that, Also includes: A power supply circuit, connected to the memory array, supplies a first well bias voltage to the top well pickup region of the semiconductor well during an erase operation, and supplies a second well bias voltage to the bottom well pickup region of the semiconductor well.

4. The memory device according to claim 3, characterized in that, The first well bias voltage and the second well bias voltage are supplied by a shared power source of the power supply circuit.

5. The memory device according to claim 3, characterized in that, The first well bias voltage is supplied by the first power source of the power supply circuit, and The second well bias voltage is supplied by a second power source of the power supply circuit, wherein the second power source is different from the first power source.

6. The memory device according to claim 2, characterized in that, The bias voltage of the second well is less than the bias voltage of the first well.

7. The memory device according to claim 2, characterized in that, Each of the plurality of memory segments in the memory cell region is biased by a well bias voltage. The well bias voltage is generated based on the voltage drop of the first well bias voltage or the second well bias voltage.

8. The memory device according to claim 7, characterized in that, The plurality of memory segments of the storage cell region correspond to a plurality of well regions, and The voltage drop along the current path between the top well pickup area and the bottom well pickup area results in the plurality of well areas being biased with different voltages during the erasure operation.

9. The memory device according to claim 8, characterized in that, Each of the plurality of well regions has parasitic resistance, and The multiple parasitic resistances of the multiple well regions cause the voltage drop along the current path between the top well pickup region and the bottom well pickup region.

10. The memory device according to claim 2, characterized in that, The memory controller is also configured to: An erase verification is performed on the erase unit to verify whether the erase operation on each of the plurality of memory segments in the memory cell region was successfully executed. A flag is set on at least one of the plurality of memory segments that have passed the erase verification. A countervoltage is set on the character line connected to at least one memory segment that has passed the erase verification, and Set the word line erase voltage on the word line connected to the memory segment that failed the erase verification.

11. The memory device according to claim 10, characterized in that, The memory controller is also configured to: Determine whether a predetermined number of memory segments among the plurality of memory segments of the semiconductor well have passed the erase verification, and The second well bias voltage is set as the third well bias voltage, wherein the third well bias voltage is greater than the second well bias voltage.

12. The memory device according to claim 11, characterized in that, The third well bias voltage is essentially the same as the first well bias voltage.

13. An erasing method for a memory device, the memory device comprising a memory array and a memory controller, the erasing method comprising: During the erase operation, the memory controller biases the top well pickup region of the semiconductor well with a first well bias voltage, the top well pickup region corresponding to the erase cell of the memory array; as well as During the erase operation, the memory controller biases the bottom well pickup region of the semiconductor well with a second well bias voltage, the bottom well pickup region corresponding to the erase cell of the memory array. The first well bias voltage is different from the second well bias voltage.

14. The erasure method according to claim 13, characterized in that, Also includes: During the erase operation, the first well bias voltage is provided by the power supply circuit of the memory device to the top well pickup region of the semiconductor well; as well as During the erase operation, the power supply circuit of the memory device provides the second well bias voltage to the bottom well pickup region of the semiconductor well.

15. The erasure method according to claim 13, characterized in that, The second well bias voltage is less than the first well bias voltage.

16. The erasure method according to claim 13, characterized in that, The semiconductor well corresponding to the erasure unit includes: The top well pickup area; The bottom well pickup area; and The storage cell region includes multiple memory segments, wherein the multiple memory segments are arranged from the top well pick-up region to the bottom well pick-up region. Each of the plurality of memory segments includes a plurality of memory cells, each of the plurality of memory segments of the memory cell region is biased by a well bias voltage, and the well bias voltage is generated based on the voltage drop of the first well bias voltage or the second well bias voltage.

17. The erasure method according to claim 16, characterized in that, The plurality of memory segments of the memory cell region correspond to a plurality of well regions, the plurality of well regions being biased by different voltages along the voltage drop on the current path between the top well pickup region and the bottom well pickup region. Each of the plurality of well regions has parasitic resistance, and The parasitic resistance of the well region causes the voltage drop along the current path between the top well pickup region and the bottom well pickup region.

18. The erasure method according to claim 16, characterized in that, Also includes: An erase verification is performed on the erase unit to verify whether the erase operation on each memory segment of the memory cell region was successfully executed. A flag is set on at least one of the plurality of memory segments that have passed the erase verification. A counter voltage is set on the word line connected to at least one memory segment that has passed the erase verification, and Set the word line erase voltage on the word line connected to the memory segment that failed the erase verification.

19. The erasure method according to claim 18, characterized in that, Also includes: Determine whether a predetermined number of memory segments among the plurality of memory segments of the semiconductor well have passed the erase verification, and The second well bias voltage is set as the third well bias voltage, wherein the third well bias voltage is greater than the second well bias voltage.

20. The erasure method according to claim 19, characterized in that, The third well bias voltage is essentially the same as the first well bias voltage.

Images