Shift register, gate drive circuit, display panel

Abstract

The present application relates to display technical field, especially disclose a kind of shift register, gate drive circuit, display panel, input module is used to according to first reference signal and second reference signal input signal is transmitted to first node;Voltage stabilizing control module is used to stabilize the potential at first node in at least part stage, voltage stabilizing control module is used to export first output signal according to the potential at first node;Output module is used to export second output signal according to first output signal and the potential at second node;First output signal includes first level and second level, first level is greater than second level, the duration of first level is less than the duration of second level;Second output signal includes third level and fourth level, third level is greater than fourth level, the duration of third level is greater than the duration of fourth level.The above-mentioned shift register can output two kinds of output signals with different waveforms at a time, and saves layout space.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a shift register, a gate driving circuit, and a display panel. Background Technology

[0002] With the continuous development of display technology, the application range of display panels is becoming wider and wider, and people's requirements for display panels are also getting higher and higher. Flat panel display devices based on Organic Light Emitting Display (OLED) technology have become the mainstream in display devices due to their advantages such as high image quality, power saving, thin body and wide range of applications, and are widely used in various consumer electronic products such as mobile phones, televisions, laptops, and desktop computers.

[0003] However, the display performance of OLED products currently needs improvement. Summary of the Invention

[0004] Therefore, it is necessary to provide a shift register, gate drive circuit, and display panel to address the issue of performance improvement in existing display products.

[0005] A shift register includes an input module, a voltage regulation control module, and an output module;

[0006] The input terminal of the input module is connected to the input signal, and the output terminal of the input module is connected to the first node. The input module is used to transmit the input signal to the first node according to the first reference signal and the second reference signal. The voltage regulation control module includes a first node, a second node, and an output terminal. The voltage regulation control module is used to stabilize the potential at the first node at least in a partial stage. The potential at the first node is the same as the potential at the second node. The voltage regulation control module is used to output a first output signal according to the potential at the first node. The output module is electrically connected to the output terminal of the voltage regulation control module and the second node, respectively. The output module is used to output a second output signal according to the first output signal and the potential at the second node. The first output signal includes a first level and a second level, wherein the first level is greater than the second level and the duration of the first level is less than the duration of the second level; the second output signal includes a third level and a fourth level, wherein the third level is greater than the fourth level and the duration of the third level is greater than the duration of the fourth level.

[0007] In one possible implementation, the input module includes a first transmission gate, the input terminal of which is connected to the input signal, the first control terminal of which is connected to the first reference signal, the second control terminal of which is connected to the second reference signal, and the output terminal of which is connected to the first node.

[0008] In one possible implementation, the first transmission gate includes a first transistor and a second transistor, the first terminal of the first transistor is connected to the first terminal of the second transistor and serves as the input terminal of the first transmission gate, the gate of the first transistor serves as the first control terminal of the first transmission gate, the gate of the second transistor serves as the second control terminal of the first transmission gate, and the second terminal of the first transistor is connected to the second terminal of the second transistor and serves as the output terminal of the first transmission gate.

[0009] In one possible implementation, the channel type of the first transistor is different from that of the second transistor.

[0010] In one possible implementation, the second reference signal is the inverted signal of the first reference signal.

[0011] In one possible implementation, the voltage regulation control module includes a first inverter, a second transmission gate, and a second inverter. The input terminal of the first inverter and the input terminal of the second transmission gate are connected to the first node. The output terminal of the first inverter is electrically connected to the input terminal of the second inverter and the output module. The output terminal of the first inverter serves as the output terminal of the voltage regulation control module. The output terminal of the second transmission gate and the output terminal of the second inverter are connected to the second node. The first control terminal of the second transmission gate is connected to the second reference signal, and the second control terminal of the second transmission gate is connected to the first reference signal.

[0012] In one possible implementation, the input terminal of the first inverter is connected to the output terminal of the input module, the first terminal of the first inverter is connected to a first voltage signal, the second terminal of the first inverter is connected to a second voltage signal, and the output terminal of the first inverter serves as the output terminal of the voltage regulation control module; wherein, the polarity of the first voltage signal and the second voltage signal are opposite.

[0013] In one possible implementation, the first voltage signal is greater than the second voltage signal.

[0014] In one possible implementation, the input terminal of the second transmission gate is connected to the input terminal of the first inverter and the output terminal of the input module, the first control terminal of the second transmission gate is connected to the second reference signal, the second control terminal of the second transmission gate is connected to the first reference signal, and the output terminal of the second transmission gate is connected to the output terminal of the second inverter.

[0015] In one possible implementation, the input terminal of the second inverter is connected to the output terminal of the first inverter, the first terminal of the second inverter is connected to the first voltage signal, the second terminal of the second inverter is connected to the second voltage signal, and the output terminal of the second inverter is connected to the second node.

[0016] In one possible implementation, the first inverter includes a third transistor and a fourth transistor, the gate of the third transistor is connected to the gate of the fourth transistor and serves as the input terminal of the first inverter, the first terminal of the third transistor serves as the first terminal of the first inverter, the first terminal of the fourth transistor serves as the second terminal of the first inverter, and the second terminal of the third transistor is connected to the second terminal of the fourth transistor and serves as the output terminal of the first inverter.

[0017] In one possible implementation, the channel type of the third transistor is different from that of the fourth transistor.

[0018] In one possible implementation, the second transmission gate includes a fifth transistor and a sixth transistor, the first terminal of the fifth transistor is connected to the first terminal of the sixth transistor and serves as the input terminal of the second transmission gate, the gate of the fifth transistor serves as the first control terminal of the second transmission gate, the gate of the sixth transistor serves as the second control terminal of the second transmission gate, and the second terminal of the fifth transistor is connected to the second terminal of the sixth transistor and serves as the output terminal of the second transmission gate.

[0019] In one possible implementation, the channel type of the fifth transistor is different from that of the sixth transistor.

[0020] In one possible implementation, the second inverter includes a seventh transistor and an eighth transistor, the gate of the seventh transistor being connected to the gate of the eighth transistor and serving as the input terminal of the second inverter, the first terminal of the seventh transistor serving as the first terminal of the second inverter, the first terminal of the eighth transistor serving as the second terminal of the second inverter, and the second terminal of the seventh transistor being connected to the second terminal of the eighth transistor and serving as the output terminal of the second inverter.

[0021] In one possible implementation, the channel type of the seventh transistor is different from that of the eighth transistor.

[0022] In one possible implementation, the output module includes a first output unit and a third transmission gate. The control terminal of the first output unit and the first control terminal of the third transmission gate are electrically connected to the output terminal of the voltage regulation control module. The first terminal of the first output unit is connected to a first voltage signal. The second terminal of the first output unit is connected to the output terminal of the third transmission gate as the output terminal of the output module. The second control terminal of the third transmission gate is connected to the second node. The input terminal of the third transmission gate is connected to a third reference signal.

[0023] In one possible implementation, the first output unit includes a ninth transistor, the first terminal of the ninth transistor serving as the first terminal of the first output unit, the gate of the ninth transistor serving as the control terminal of the first output unit, and the second terminal of the ninth transistor serving as the second terminal of the first output unit.

[0024] In one possible implementation, the third transmission gate includes a tenth transistor and an eleventh transistor. The first terminal of the tenth transistor is connected to the first terminal of the eleventh transistor and serves as the input terminal of the third transmission gate. The gate of the tenth transistor serves as the first control terminal of the third transmission gate. The gate of the eleventh transistor serves as the second control terminal of the third transmission gate. The second terminal of the tenth transistor is connected to the second terminal of the eleventh transistor and serves as the output terminal of the third transmission gate.

[0025] In one possible implementation, the channel type of the tenth transistor is different from that of the eleventh transistor, and the channel type of the ninth transistor is the same as that of the eleventh transistor.

[0026] In one possible implementation, the clock period of the first reference signal is the same as the clock period of the third reference signal, wherein the third reference signal is delayed by half a clock period relative to the first reference signal.

[0027] In one possible implementation, the signal waveform of the second reference signal is the same as that of the third reference signal.

[0028] In one possible implementation, the duration of the first level overlaps at least partially with the duration of the fourth level.

[0029] In one possible implementation, the duration of the first level is greater than the duration of the fourth level.

[0030] In one possible implementation, the potential signal at the first node is a first node signal, the potential signal at the second node is a second node signal, and the timing waveform of the first node signal is the same as the timing waveform of the second node signal.

[0031] In one possible implementation, the duration of the fifth level in the first node signal is the same as the duration of the first level in the first output signal; the fifth level is less than the first level.

[0032] In one possible implementation, the first output signal is the inverted signal of the first node signal.

[0033] In one possible implementation, the duration of the sixth level in the input signal is the same as the duration of the first level in the first output signal, the first node signal is delayed by half a clock cycle relative to the input signal, the clock cycle being the clock cycle of the first reference signal; the sixth level is less than the first level.

[0034] In one possible implementation, the first level is the same as the first voltage signal, the second level is the same as the second voltage signal; the third level is the same as the first voltage signal, the fourth level is the same as the seventh level of the third reference signal; and the seventh level is lower than the first level.

[0035] In one possible implementation, the first transistor, the third transistor, the fifth transistor, the seventh transistor, the ninth transistor, and the eleventh transistor have the same channel type, and the second transistor, the fourth transistor, the sixth transistor, the eighth transistor, and the tenth transistor have the same channel type.

[0036] In one possible implementation, the first transistor, the third transistor, the fifth transistor, the seventh transistor, the ninth transistor, and the eleventh transistor are all low-temperature polysilicon transistors, and the second transistor, the fourth transistor, the sixth transistor, the eighth transistor, and the tenth transistor are all metal-oxide transistors.

[0037] In one possible implementation, the first transistor, the third transistor, the fifth transistor, the seventh transistor, the ninth transistor, and the eleventh transistor are all P-channel transistors, and the second transistor, the fourth transistor, the sixth transistor, the eighth transistor, and the tenth transistor are all N-channel transistors.

[0038] A gate driving circuit includes n shift registers as described in any of the above embodiments, where n is a positive integer. The input terminal of the input module in the first-stage shift register is connected to an input signal, and the input terminal of the input module in the (i+1)th-stage shift register is connected to the second node of the i-th-stage shift register, where i = 1, 2, 3, ..., n.

[0039] In one possible implementation, the first output signal of the shift register at stage i+1 is delayed by a preset time relative to the first output signal of the shift register at stage i, and the second output signal of the shift register at stage i+1 is delayed by a preset time relative to the second output signal of the shift register at stage i.

[0040] In one possible implementation, the preset time is half a clock cycle of the first reference signal.

[0041] A display panel includes a pixel circuit and a gate driving circuit as described in any of the above embodiments, the gate driving circuit being used to provide a first output signal and a second output signal to the pixel circuit.

[0042] In one possible implementation, the display panel includes multiple rows of pixel circuits arranged in an array, with each level of the shift register corresponding to at least one row of pixel circuits.

[0043] In one possible implementation, the display panel further includes a driver chip, a third inverter, a fourth inverter, an input signal line, a first clock line, a second clock line, a third clock line, and a fourth clock line. The first terminal of the driver chip is electrically connected to the input terminal of the input module of the first-stage shift register through the input signal line. The first terminal of the driver chip is used to provide an input signal. The second end of the driver chip is electrically connected to the first clock line, and the first clock line is connected to the plurality of shift registers respectively. The second end of the driver chip is used to provide a first clock signal. The first clock signal is used as a first reference signal for the odd-level shift registers and as a third reference signal for the even-level shift registers. The second end of the driver chip is also electrically connected to the second clock line through the third inverter. The second clock line is connected to a plurality of shift registers respectively. The inverted first clock signal serves as the second reference signal connected to the odd-level shift registers. The third terminal of the driver chip is electrically connected to the third clock line, and the third clock line is connected to the plurality of shift registers respectively. The third terminal of the driver chip is used to provide a second clock signal. The second clock signal is used as a third reference signal for the odd-level shift registers and as a first reference signal for the even-level shift registers. The second terminal of the driver chip is also electrically connected to the fourth clock line through the fourth inverter. The fourth clock line is connected to a plurality of shift registers respectively. The inverted second clock signal serves as the second reference signal for the even-numbered shift registers.

[0044] In one possible implementation, the first clock line is electrically connected to the first control terminal of the first transmission gate and the second control terminal of the second transmission gate in the odd-level shift register, and the first clock line is electrically connected to the input terminal of the third transmission gate in the even-level shift register.

[0045] In one possible implementation, the second clock line is electrically connected to the second control terminal of the first transmission gate and the first control terminal of the second transmission gate in the odd-level shift register.

[0046] In one possible implementation, the third clock line is electrically connected to the first control terminal of the first transmission gate and the second control terminal of the second transmission gate in the even-level shift register, and the first clock line is electrically connected to the input terminal of the third transmission gate in the odd-level shift register.

[0047] In one possible implementation, the fourth clock line is electrically connected to the second control terminal of the first transmission gate and the first control terminal of the second transmission gate in the even-numbered shift register. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 This is a schematic diagram of the structure of one type of shift register provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of one type of input module provided in an embodiment of this application; Figure 3 A schematic diagram of the circuit structure of one type of input module provided in an embodiment of this application; Figure 4This is a schematic diagram of the structure of one of the voltage regulation control modules provided in the embodiments of this application; Figure 5 A schematic diagram of the circuit structure of one type of voltage regulation control module provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of one output module provided in an embodiment of this application; Figure 7 A schematic diagram of the circuit structure of one output module provided in an embodiment of this application; Figure 8 A schematic diagram of the circuit structure of one type of shift register provided in an embodiment of this application; Figure 9 This is a signal timing diagram of one type of shift register provided in an embodiment of this application; Figure 10 This is a schematic diagram of the structure of one type of gate drive circuit provided in an embodiment of this application; Figure 11 This is a schematic diagram of the structure of one type of display panel provided in an embodiment of this application; Figure 12 This is a timing waveform diagram of one type of display panel provided in an embodiment of this application. Detailed Implementation

[0050] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0052] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0053] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0054] In this application, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a direct connection or an indirect connection through an intermediate medium, or they can refer to the internal connection of two elements or the interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0055] In existing technologies, a shift register typically outputs only one type of timing waveform signal, such as a scan signal with a low-level pulse or a scan signal with a high-level pulse. When different signals are needed to control the operation of different transistors in a display panel, multiple shift registers must be designed to generate the required gate drive signals, which severely impacts the layout design.

[0056] Based on this, this application provides a shift register to solve at least one of the above-mentioned display problems.

[0057] Figure 1 This is a schematic diagram of the structure of one type of shift register provided in an embodiment of this application. In one possible implementation, the shift register 100 includes an input module 110, a voltage regulation control module 120, and an output module 130.

[0058] The input terminal of the input module 110 can be connected to the input signal SIN, and the output terminal of the input module 110 can be connected to the first node N1. The input module 110 can be used to transmit the input signal SIN to the first node N1 according to the first reference signal S1 and the second reference signal S1B. In some specific embodiments, the input terminal of the input module 110 can be connected to an input signal line to receive the input signal SIN, and the control terminal of the input module 110 can be connected to the first reference signal S1 and the second reference signal S1B. The first reference signal S1 and the second reference signal S1B can be used to control the on or off state of the input module 110, and the output terminal of the input module 110 can be connected to the first node N1.

[0059] The voltage regulation control module 120 may include a first node N1, a second node N2, and an output terminal. The voltage regulation control module 120 can be used to stabilize the potential at the first node N1 at least partially, where the potential at the first node N1 is the same as the potential at the second node N2. The voltage regulation control module 120 is used to output a first output signal Sn_n based on the potential at the first node N1. The output module 130 is electrically connected to the output terminal of the voltage regulation control module 120 and the second node N2, respectively. The output module 130 is used to output a second output signal Sn_p based on the first output signal Sn_n and the potential at the second node N2. The first output signal Sn_n includes a first level and a second level, where the first level is greater than the second level. For example, the first level is high and the second level is low. The duration of the first level is less than the duration of the second level, meaning the pulse width of the high level in the first output signal Sn_n is greater than the pulse width of the low level. The second output signal Sn_p includes a third level and a fourth level, where the third level is greater than the fourth level. For example, the third level is high and the fourth level is low. The duration of the third level is greater than the duration of the fourth level, meaning that the pulse width of the low level in the second output signal Sn_p is greater than the pulse width of the high level.

[0060] The single shift register 100 provided in this application can output a first output signal Sn_n and a second output level Sn_p with different signal waveforms, reducing the number of shift registers 100, effectively simplifying the circuit to save layout space, and is beneficial for narrow bezel design.

[0061] In the embodiments provided in this application, the effective level can refer to the level that plays a target role in subsequent applications. For example, when the shift register 100 is designed to provide a gate drive signal for the PMOS and to control the PMOS to turn on at a target time and remain off at the rest of the time, the effective level can refer to the level that turns the PMOS on, i.e., a low level; when the shift register 100 is designed to provide a signal that controls the PMOS to turn off at an appropriate time and turn on only at a target time, the effective level can refer to the level that turns the PMOS off, i.e., a low level.

[0062] In some embodiments, the effective level of the first output signal Sn_n can be a first level, and the effective level of the second output signal Sn_p can be a fourth level. Preferably, the first level is greater than the fourth level. That is, the first output signal Sn_n can be used as the gate drive signal of an NMOS transistor, and the first output signal Sn_p can be used as the gate drive signal of a PMOS transistor. It is evident that by utilizing the shift register provided in this application, a single shift register can output gate drive signals corresponding to two different channel type transistors, effectively reducing the number of shift registers when applied in a display panel.

[0063] Figure 2 This is a schematic diagram of the structure of one type of input module provided in an embodiment of this application. In one possible implementation, the input module 110 may include a first transmission gate 111. The function of the transmission gate (TG) circuit is that when the transmission gate circuit is open, the signal input to the transmission gate circuit can be transmitted to the output of the transmission gate, with the logical expression Y = A, where Y refers to the signal at the output of the transmission gate and A refers to the signal at the input of the transmission gate; when the transmission gate circuit is closed, the signal input to the transmission gate circuit cannot be transmitted to the output.

[0064] The input terminal of the first transmission gate 111 is connected to the input signal SIN. The first control terminal of the first transmission gate 111 is connected to the first reference signal S1, the second control terminal of the first transmission gate is connected to the second reference signal S1B, and the output terminal of the first transmission gate 111 is connected to the first node N1. When the first transmission gate 111 is turned on according to the first reference signal S1 and the second reference signal S1B, the input signal SIN can be transmitted to the first node N1. When the first transmission gate 111 is turned off according to the first reference signal S1 and the second reference signal S1B, the input signal SIN cannot be transmitted to the first node N1.

[0065] In embodiments of this disclosure, a transistor can refer to a device that includes at least a gate, a drain, and a source. In this disclosure, the first terminal of a transistor can be the drain and the second terminal can be the source, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. In embodiments of this disclosure, the first and second terminals of all or some transistors can be interchanged as needed.

[0066] It should be noted that the transistors in the embodiments of this application can be either N-type or P-type transistors. For N-type transistors, the on-level is high and the off-level is low. That is, when the gate of an N-type transistor is high, its first and second terminals are connected; when the gate of an N-type transistor is low, its first and second terminals are off. For P-type transistors, the on-level is low and the off-level is high. That is, when the control terminal of a P-type transistor is low, its first and second terminals are connected; when the control terminal of a P-type transistor is high, its first and second terminals are off. Furthermore, the on-level and off-level in the embodiments of this invention are general terms; the on-level refers to any level that enables the transistor to conduct, and the off-level refers to any level that enables the transistor to turn off / become off.

[0067] Figure 3This is a schematic diagram of the circuit structure of one input module provided in an embodiment of this application. In one possible implementation, the first transmission gate 111 may include a first transistor M1 and a second transistor M2. The first terminal of the first transistor M1 is connected to the first terminal of the second transistor M2 and serves as the input terminal of the first transmission gate 111. The gate of the first transistor M1 serves as the first control terminal of the first transmission gate 111, and the gate of the second transistor M2 serves as the second control terminal of the first transmission gate 111. The second terminals of the first transistor M1 and the second transistor M2 are connected and serve as the output terminal of the first transmission gate 111. More specifically, the first terminals of the first transistor M1 and the second transistor M2 may be connected to an input signal line, which can transmit the input signal SiIN to the first terminals of the first transistor M1 and the second transistor M2. The first transistor M1 is turned on or off according to the first reference signal S1, and the second transistor M2 is turned on or off according to the second reference signal S1B. Since the first transistor M1 and the second transistor M2 are connected in parallel, the first transmission gate 111 is turned on when either the first transistor M1 or the second transistor M2 is turned on, and the first transmission gate 111 is turned off when both the first transistor M1 and the second transistor M2 are turned off.

[0068] In one possible implementation, the channel type of the first transistor M1 is different from that of the second transistor M2. Specifically, when the first transistor M1 is an N-channel transistor, the second transistor M2 can be a P-channel transistor. In this case, when the first reference signal S1 is high, the first transistor M1 is turned on, and when the first reference signal S1 is low, the first transistor M1 is turned off. Correspondingly, when the second reference signal S1B is high, the second transistor M2 is turned off, and when the second reference signal S1B is low, the second transistor M2 is turned on. Thus, the effective level time of the first reference signal S1 is the same as the time when the first reference signal S1 is high, and the effective level time of the second reference signal S1B is the same as the time when the second reference signal S1B is low.

[0069] In other alternative embodiments, the first transistor M1 can also be a P-channel transistor, and the second transistor M2 can also be an N-channel transistor. In this case, when the first reference signal S1 is low, the first transistor M1 is turned on, and when the first reference signal S1 is high, the first transistor M1 is turned off. Similarly, when the second reference signal S1B is high, the second transistor M2 is turned on, and when the second reference signal S1B is low, the second transistor M2 is turned off. Thus, the effective pulse time of the first reference signal S1 is the same as the time when the first scan signal is low, and the effective pulse time of the second reference signal S1B is the same as the time when the second scan signal is high.

[0070] The active layer material of the N-channel transistor can include, but is not limited to, oxide semiconductor materials, such as indium gallium zinc oxide (IGZO), while the active layer material of the P-channel transistor can include, but is not limited to, low-temperature poly-silicon (LTPS) materials, which makes the P-channel transistor have higher mobility and the N-channel transistor have lower off-state leakage current.

[0071] In the shift register provided in this application, a first transmission gate 111 composed of a first transistor M1 and a second transistor M2 is used as the input module 110. The first transistor M1 is an LTPS P-type transistor with high mobility and high reliability, and the second transistor M2 is an n-type metal oxide transistor, which can realize lossless transmission of high-level signals and low-level signals to the first node N1.

[0072] In one possible implementation, the second reference signal S1B is the inverted signal of the first reference signal S1. That is, at any given time, the second reference signal S1B has the opposite polarity to the first reference signal S1, or the second reference signal S1B has the opposite level to the first reference signal S1. For example, when the first reference signal S1 is positive, the second reference signal S1B is negative; when the first reference signal S1 is negative, the second reference signal S1B is positive. Alternatively, when the first reference signal S1 is high, the second reference signal S1B is low; when the first reference signal S1 is low, the second reference signal S1B is high. Simultaneously, since the first transistor M1 and the second transistor M2 have different channel types, their turn-on levels are different. Therefore, the first transistor M1 and the second transistor M2 can be simultaneously turned on or off based on the first reference signal S1 and the second reference signal S1B.

[0073] Figure 4 This is a schematic diagram of the structure of a voltage regulation control module provided in one embodiment of this application. In one possible implementation, the voltage regulation control module 120 may include a first inverter 121, a second transmission gate 122, and a second inverter 123. The input terminal of the first inverter 121 and the input terminal of the second transmission gate 122 are connected to a first node N1. The output terminal of the first inverter 121 is electrically connected to the input terminal of the second inverter 123 and the output module 110. The output terminal of the first inverter 121 serves as the output terminal of the voltage regulation control module 120. The output terminals of the second transmission gate 122 and the second inverter 123 are connected to a second node N2. The first control terminal of the second transmission gate 122 is connected to a second reference signal S1B, and the second control terminal of the second transmission gate 122 is connected to a first reference signal S1.

[0074] The function of an inverter is to invert a signal and then output it. Its logical expression is Y = For example, when the input signal of the inverter is high, the output signal is low; when the input signal of the inverter is low, the output signal is high. Alternatively, when the input signal of the inverter is positive, the output signal is negative; when the input signal of the inverter is negative, the output signal is positive. The input terminal of the first inverter 121 is connected to the first node N1, and the output terminal of the first inverter 121 serves as the output terminal of the voltage regulation control module 120. The output terminal of the voltage regulation control module 120 is used to output the first output signal Sn_n. That is, the first inverter is used to invert the potential signal at the first node N1 and output it as the first output signal Sn_n. Meanwhile, since the input terminal of the second inverter 123 is electrically connected to the output terminal of the first inverter 121, and the output terminal of the second inverter 123 is connected to the second node N2, the second inverter 123 can invert the first output signal Sn_n. That is, the signal transmitted by the second inverter 123 to the second node N2 is the inverse signal of the first output signal Sn_n.

[0075] The input of the second transmission gate 122 is connected to the first node N1, and the output of the second transmission gate 122 is connected to the second node N2. When the second transmission gate 122 is turned on according to the first reference signal S1 and the second reference signal S1B, the signal at the first node N1 can be transmitted to the second node N2. When the second transmission gate 122 is turned off according to the first reference signal S1 and the second reference signal S1B, the signal at the first node N1 cannot be transmitted to the second node N2. The potential of the second node N2 is determined based on the output signal of the second transmission gate 122 and the output signal of the second inverter 123.

[0076] In one possible implementation, the input terminal of the first inverter 121 is connected to the output terminal of the input module 110. The first terminal of the first inverter 121 is connected to a first voltage signal VGH, and the second terminal is connected to a second voltage signal VGL. The output terminal of the first inverter 121 serves as the output terminal of the voltage regulation control module 120. The first voltage signal VGH and the second voltage signal VGL are opposite. For example, the first voltage signal VGH is high and the second voltage signal VGL is low; or the first voltage signal VGH is low and the second voltage signal VGL is high. Alternatively, the first voltage signal VGH is positive and the second voltage signal VGL is negative; or the first voltage signal VGH is negative and the second voltage signal VGL is positive.

[0077] In a preferred embodiment, the first voltage signal VGH is greater than the second voltage signal VGL, that is, the first voltage signal VGH is at a high level and the second voltage signal VGL is at a low level. Further, the first voltage signal VGH can be a high level greater than zero, and the second voltage signal VGL can be the first voltage signal VGH less than zero.

[0078] In one possible implementation, the first voltage level is the same as the first voltage signal VGH, the second voltage level is the same as the second voltage signal VGL, and the third voltage level is the same as the first voltage signal VGH. That is, the shift register 100 provided in this application can output a scan signal with a high-level pulse and a scan signal with a low-level pulse.

[0079] The first inverter 121 outputs its inverted signal according to the signal at the first node N1. When the potential at the first node N1 is low, the first inverter 121 outputs the first voltage signal VGH; when the potential at the first node N1 is high, the first inverter 121 outputs the second voltage signal VGL.

[0080] In one possible implementation, the input terminal of the second transmission gate 122 can be connected to the input terminal of the first inverter 121 and the output terminal of the input module 110. The first control terminal of the second transmission gate 122 can be connected to the second reference signal S1B, the second control terminal of the second transmission gate 122 can be connected to the first reference signal S1, and the output terminal of the second transmission gate 122 can be connected to the output terminal of the second inverter 122. In a preferred implementation, the on / off state of the second transmission gate 122 is opposite to that of the first transmission gate 121; that is, when the first transmission gate 121 is open, the second transmission gate 122 is off; when the first transmission gate 121 is off, the second transmission gate 122 is open.

[0081] In one possible implementation, the input of the second inverter 123 is connected to the output of the first inverter 121. The first terminal of the second inverter 123 is connected to the first voltage signal VGH, the second terminal of the second inverter 123 is connected to the second voltage signal VGL, and the output of the second inverter 123 is connected to the second node N2. The first inverter 121 outputs its inverted signal according to its output (i.e., the first output signal Sn_n). When the first output signal Sn_n is low, the second inverter 123 outputs the first voltage signal VGH; when the first output signal Sn_n is high, the second inverter 123 outputs the second voltage signal VGL.

[0082] Figure 5This is a schematic diagram of the circuit structure of one of the voltage regulation control modules provided in the embodiments of this application. In one possible implementation, the first inverter 121 may include a third transistor M3 and a fourth transistor M4. The gate of the third transistor M3 is connected to the gate of the fourth transistor M4 and serves as the input terminal of the first inverter 121. The first terminal of the third transistor M3 serves as the first terminal of the first inverter 121, and the first terminal of the fourth transistor M4 serves as the second terminal of the first inverter 121. The second terminal of the third transistor M3 is connected to the second terminal of the fourth transistor M4 and serves as the output terminal of the first inverter 121.

[0083] More specifically, the gates of both the third transistor M3 and the fourth transistor M4 are connected to the first node N1. That is, the conduction or deactivation of the third transistor M3 and the fourth transistor M4 is controlled according to the voltage level at the first node N1. The first terminal of the third transistor M3 is connected to a first voltage signal VGH, and the first terminal of the fourth transistor M4 is connected to a second voltage signal VGL. The second terminals of the third transistor M3 and the fourth transistor M4 are electrically connected as the output terminal of the first inverter 121. Because the channel types of the third transistor M3 and the fourth transistor M4 are different, at any given time, one of the third transistor M3 and the fourth transistor M4 is turned on according to the potential at the first node N1. For example, when the level at the first node N1 is the on level of the third transistor M3, the third transistor M3 is on and the fourth transistor M4 is off, then the third transistor M3 transmits the first voltage signal VGH to the output of the first inverter 121; when the level at the first node N1 is the on level of the fourth transistor M4, the fourth transistor M4 is on and the third transistor M3 is off, then the fourth transistor M4 transmits the second voltage signal VGL to the output of the first inverter 121.

[0084] In a preferred embodiment, the channel type of the third transistor M3 is different from that of the fourth transistor M4. That is, when the third transistor M3 is an N-channel transistor, the fourth transistor M4 is a P-channel transistor; when the third transistor M3 is a P-channel transistor, the fourth transistor M4 is an N-channel transistor.

[0085] In a preferred embodiment, the third transistor M3 is a P-channel transistor, and the fourth transistor M4 is an N-channel transistor. That is, the third transistor M3 is turned on when the voltage level is low and turned off when the voltage level is high; the fourth transistor M4 is turned on when the voltage level is high and turned off when the voltage level is low. Since the third transistor M3 is turned on when the voltage level is low, its first terminal is connected to the first voltage signal VGH. Therefore, the |Vgs| of the third transistor M3 is larger, meaning that the third transistor M3 turns on faster and more completely. As a result, the first voltage signal VGH can be transmitted to the output terminal of the first inverter 121 more quickly, so that the first voltage signal VGH can be used as the first level of the first output signal Sn_n. Similarly, since the fourth transistor M4 is turned on when the voltage level is high, its first terminal is connected to the second voltage signal VGL. Therefore, the fourth transistor M4 turns on faster and more completely, so that the second voltage signal VGL can be transmitted to the output terminal of the first inverter 121 more quickly, so that the second voltage signal VGL can be used as the second level of the first output signal Sn_n.

[0086] In existing designs, bootstrap circuits are typically used to address low-level loss, resulting in complex circuitry and a falling edge step in the output, along with unstable voltage at low output levels. In contrast, the shift register provided in this application utilizes a high-reliability LTPS P-type transistor and a low-leakage-current N-type oxide transistor to construct an inverter. The LTPS P-type transistor provides a more stable and faster high level (VGH), while the N-type oxide transistor provides a more stable and faster low level (VGL). Stable high and low levels can be output without setting an extremely low level, and the output signal does not exhibit any step-like voltage fluctuations.

[0087] In one possible implementation, the second transmission gate 122 may include a fifth transistor M5 and a sixth transistor M6. The first terminal of the fifth transistor M5 is connected to the first terminal of the sixth transistor M6 and serves as the input terminal of the second transmission gate 122. The gate of the fifth transistor M5 serves as the first control terminal of the second transmission gate 123. The gate of the sixth transistor M6 serves as the second control terminal of the second transmission gate 123. The second terminal of the fifth transistor M5 is connected to the second terminal of the sixth transistor M6 and serves as the output terminal of the second transmission gate 123.

[0088] More specifically, the first terminals of the fifth transistor M5 and the sixth transistor M6 can be connected to the first node N1. The fifth transistor M5 is turned on or off according to the second reference signal S1B, and the sixth transistor M6 is turned on or off according to the first reference signal S1. Since the fifth transistor M5 and the sixth transistor M6 are connected in parallel, the second transmission gate 122 is turned on when either the fifth transistor M5 or the sixth transistor M6 is turned on, and the second transmission gate 122 is turned off when both the fifth transistor M5 and the sixth transistor M6 are turned off simultaneously.

[0089] In one possible implementation, the channel type of the fifth transistor M5 is different from that of the sixth transistor M6. That is, when the fifth transistor M5 is an N-channel transistor, the sixth transistor M6 is a P-channel transistor; when the fifth transistor M5 is a P-channel transistor, the sixth transistor M6 is an N-channel transistor.

[0090] In one possible implementation, the second reference signal S1B is the inverted signal of the first reference signal S1. Simultaneously, since the polarities of the conduction levels of the fifth transistor M5 and the sixth transistor M6 are opposite, the fifth transistor M5 and the sixth transistor M6 are simultaneously turned on or off based on the first reference signal S1 and the second reference signal S1B. In a preferred implementation, the channel type of the fifth transistor M5 is the same as that of the third transistor M3, and the channel type of the sixth transistor M6 is the same as that of the fourth transistor M4. In this case, both the third transistor M3 and the sixth transistor M6 are turned on or off according to the first reference signal S1, and both the fourth transistor M4 and the fifth transistor M5 are turned on or off according to the second reference signal S1B. Therefore, the on / off states of the first transmission gate 111 and the second transmission gate 122 are opposite.

[0091] In one possible implementation, the second inverter 123 may include a seventh transistor M7 and an eighth transistor M8. The gate of the seventh transistor M7 is connected to the gate of the eighth transistor M8 and serves as the input terminal of the second inverter 123. The first terminal of the seventh transistor M7 serves as the first terminal of the second inverter 123, and the first terminal of the eighth transistor M8 serves as the second terminal of the second inverter 123. The second terminal of the seventh transistor M7 is connected to the second terminal of the eighth transistor M8 and serves as the output terminal of the second inverter 123.

[0092] More specifically, the gates of both the seventh transistor M7 and the eighth transistor M8 are connected to the output of the first inverter 121. That is, the seventh transistor M7 and the eighth transistor M8 are turned on or off according to the first output signal Sn_n output by the first inverter 121. The first terminal of the seventh transistor M7 is connected to the first voltage signal VGH, and the first terminal of the eighth transistor M8 is connected to the second voltage signal VGL. The second terminals of the seventh transistor M7 and the eighth transistor M8 are electrically connected as the output of the second inverter 123. Since the channel types of the seventh transistor M7 and the eighth transistor M8 are different, at any given time, one of the seventh transistor M7 and the eighth transistor M8 is turned on according to the first output signal Sn_n. For example, when the level of the first output signal Sn_n is the on-level of the seventh transistor M7, the seventh transistor M7 is on and the eighth transistor M8 is off. Then, the seventh transistor M7 transmits the first voltage signal VGH to the output of the second inverter 123. When the level of the first output signal Sn_n is the on-level of the eighth transistor M8, the eighth transistor M8 is on and the seventh transistor M7 is off. Then, the eighth transistor M8 transmits the second voltage signal VGL to the output of the second inverter 123. Preferably, the seventh transistor M7 is on when the level is low and off when the level is high; the eighth transistor M8 is on when the level is high and off when the level is low.

[0093] In a preferred embodiment, the channel type of the seventh transistor M7 is different from that of the eighth transistor M8. That is, when the seventh transistor M7 is an N-channel transistor, the eighth transistor M8 is a P-channel transistor; when the seventh transistor M7 is a P-channel transistor, the eighth transistor M8 is an N-channel transistor.

[0094] In a preferred embodiment, the seventh transistor M7 is a P-channel transistor, and the eighth transistor M8 is an N-channel transistor. That is, the seventh transistor M7 is turned on when the voltage level is low and turned off when the voltage level is high; the eighth transistor M8 is turned on when the voltage level is high and turned off when the voltage level is low. Similarly, by setting the seventh transistor M7 as a P-channel transistor and the eighth transistor M8 as an N-channel transistor, the second inverter 123 can output effectively without setting an extremely low voltage level, and can output a more stable signal faster without producing a step in the output signal.

[0095] Figure 6This is a schematic diagram of the structure of one output module provided in an embodiment of this application. In one possible implementation, the output module 130 may include a first output unit 131 and a third transmission gate 132. The control terminal of the first output unit 131 and the first control terminal of the third transmission gate 132 are electrically connected to the output terminal of the voltage regulation control module 120. The first terminal of the first output unit 131 is connected to a first voltage signal VGH. The second terminal of the first output unit 131 is connected to the output terminal of the third transmission gate 132 as the output terminal of the output module 130. The second control terminal of the third transmission gate 132 is connected to a second node N2. The input terminal of the third transmission gate 132 is connected to a third reference signal S2.

[0096] The first output unit 131 can be turned on or off according to the signal output by the voltage regulation control module 120. When the first output unit 131 is turned on, it can transmit the first voltage signal VGH to the output terminal of the output module 130. That is, at least part of the first voltage signal VGH in the second output signal Sn_p output by the output module 130 can be provided by the first output unit 131.

[0097] The third transmission gate 132 is turned on or off according to the signal at the second node N2 and the first output signal Sn_n. When the third transmission gate 132 is turned on, the third reference signal S2 connected to the input terminal of the third transmission gate 132 can be transmitted to the output terminal of the output module 130. When the second transmission gate 122 is closed, the third reference signal S2 cannot be transmitted to the output terminal of the output module 130.

[0098] Figure 7 The circuit structure diagram of one output module provided in the embodiment of this application is shown. In one possible implementation, the first output unit 131 may include a ninth transistor M9. The first terminal of the ninth transistor M9 may be used as the first terminal of the first output unit 131, the gate of the ninth transistor M9 may be used as the control terminal of the first output unit 131, and the second terminal of the ninth transistor M9 may be used as the second terminal of the first output unit 131.

[0099] More specifically, the first terminal of the ninth transistor M9 is connected to the first voltage signal VGH, the gate of the ninth transistor M9 is connected to the output terminal of the voltage regulator output module 120, and the second terminal of the ninth transistor M9 is connected to the output terminal of the third transmission gate 132. After the ninth transistor M9 is turned on, the first voltage signal VGH can be transmitted to the output terminal of the output module 130.

[0100] In one possible implementation, the third transmission gate 132 may include a tenth transistor M10 and an eleventh transistor M11. The first terminal of the tenth transistor M10 is connected to the first terminal of the eleventh transistor M11 and serves as the input terminal of the third transmission gate 132. The gate of the tenth transistor M10 can serve as the first control terminal of the third transmission gate 132, and the gate of the eleventh transistor M11 can serve as the second control terminal of the third transmission gate 132. The second terminal of the tenth transistor M10 is connected to the second terminal of the eleventh transistor M11 and serves as the output terminal of the third transmission gate 132.

[0101] More specifically, the first terminals of the tenth transistor M10 and the eleventh transistor M11 can be connected to the output terminals of the voltage regulation control module 120. The tenth transistor M10 is turned on or off according to the first output signal Sn_n output by the voltage regulation control module 120, and the eleventh transistor M11 is turned on or off according to the potential at the second node N2. Since the tenth transistor M10 and the eleventh transistor M11 are connected in parallel, the third transmission gate 132 is turned on when either the tenth transistor M10 or the eleventh transistor M11 is turned on, and the third transmission gate 132 is turned off when both the tenth transistor M10 and the eleventh transistor M11 are turned off.

[0102] In one possible implementation, the channel type of the tenth transistor M10 is different from that of the eleventh transistor M11. That is, when the tenth transistor M10 is an N-channel transistor, the eleventh transistor M11 is a P-channel transistor; when the tenth transistor M10 is a P-channel transistor, the eleventh transistor M11 is an N-channel transistor.

[0103] In one possible implementation, the second reference signal S1B is the inverted signal of the first reference signal S1. Simultaneously, since the polarities of the conduction levels of the fifth transistor M5 and the sixth transistor M6 are opposite, the fifth transistor M5 and the sixth transistor M6 are simultaneously turned on or off based on the first reference signal S1 and the second reference signal S1B. In a preferred implementation, the channel type of the fifth transistor M5 is the same as that of the third transistor M3, and the channel type of the sixth transistor M6 is the same as that of the fourth transistor M4. In this case, both the third transistor M3 and the sixth transistor M6 are turned on or off according to the first reference signal S1, and both the fourth transistor M4 and the fifth transistor M5 are turned on or off according to the second reference signal S1B. Therefore, the on / off states of the first transmission gate 111 and the second transmission gate 122 are opposite.

[0104] In one possible implementation, the channel type of the tenth transistor M10 is different from that of the eleventh transistor M11, and the channel type of the ninth transistor M9 is the same as that of the eleventh transistor M11. That is, when the tenth transistor M10 is an N-channel transistor, the ninth transistor M9 and the eleventh transistor M11 are P-channel transistors; when the tenth transistor M10 is a P-channel transistor, the ninth transistor M9 and the eleventh transistor M11 are N-channel transistors.

[0105] In one possible implementation, the clock period of the first reference signal S1 may be the same as the clock period of the third reference signal S2, wherein the third reference signal S2 is delayed by half a clock period relative to the first reference signal S1.

[0106] In a preferred embodiment, the first reference signal S1 is the first clock signal SCK1, the second reference signal S1B is the inverted signal SCK1B of the first clock signal, and the third reference signal S2 is the second clock signal SCK2.

[0107] LTPS TFTs (Thin Film Transistors) offer advantages such as high mobility and stable characteristics. Conventional 8T2C Scan circuits are based on p-type LTPS TFT circuits, but they suffer from signal loss and other issues. Existing Scan circuits require a bootstrap circuit to mitigate signal loss, leading to complex circuit design. Furthermore, there is a falling edge step when outputting the EM signal (light emission control signal, typically with a high effective level), and potential instability occurs when outputting a low level.

[0108] This application provides a dual-output shift register 100 based on complementary thin-film transistors (TFTs). The shift register 100 includes 11 transistors and has no capacitors. A single shift register 100 can output two different output signals, saving layout space. In the transmission gate constructed within the shift register 100, high-mobility and high-reliability LTPSTFTs are used to output high-level signals without loss. N-type oxide TFTs are used to construct inverters and transmission gates, and the output signal is generated using the inverters and transmission gates. Compared to conventional 8T2C, it can output without extremely low levels and can output low-level signals without loss. The output signal does not produce a step, solving the problem of threshold voltage loss. The shift register 100 provided in this application uses two complementary transistor types, P-type and N-type, to construct the transmission gates and inverters, using these transmission gates and inverters to solve the threshold voltage loss problem and improve the waveform quality of the output signal.

[0109] In one possible implementation, the shift register 100 includes at least one of a metal-oxide-semiconductor (MODS) transistor and a low-temperature polysilicon (LTPS) transistor. The LTPS transistor is a transistor fabricated using low-temperature polysilicon as the active semiconductor layer; the MODS transistor is a transistor fabricated using metal-oxide-semiconductor (MODS) material as the active semiconductor layer. The LTPS transistor can be a P-type transistor or an N-type transistor, and the MODS transistor can be an N-type transistor.

[0110] In one possible implementation, the shift register 100 may include at least one metal-oxide-semiconductor (MODS) transistor and at least one low-temperature polycrystalline silicon (LTPS) transistor. The MODS material may be, for example, at least one of IGZO (Indium Gallium Zinc Oxide), IGTO (Indium Gallium Tin Oxide), and IZTO (Indium Zinc Tin Oxide). That is, the shift register 100 may be a circuit fabricated using LTPO (Low Temperature Poly Silicon-Oxide) technology, which is a hybrid OLED backplane technology combining LTPS (Low Temperature Polycrystalline Silicon) and IGZO (Indium Gallium Zinc Oxide). In one possible implementation, at least one of the first transistor M1, the second transistor M2, and the third transistors M3 through M11 is a MODS transistor, and at least one is an LTPS transistor.

[0111] In one possible implementation, the first transistor M1, the third transistor M3, the fifth transistor M5, the seventh transistor M7, the ninth transistor M9, and the eleventh transistor M11 have the same channel type, and the second transistor M2, the fourth transistor M4, the sixth transistor M6, the eighth transistor M8, and the tenth transistor M10 have the same channel type.

[0112] In one possible implementation, the first transistor M1, the third transistor M3, the fifth transistor M5, the seventh transistor M7, the ninth transistor M9, and the eleventh transistor M11 are all low-temperature polysilicon transistors (LTPS), and the second transistor M2, the fourth transistor M4, the sixth transistor M6, the eighth transistor M8, and the tenth transistor M10 are all metal-oxide transistors (MOTs). Further, the first transistor M1, the third transistor M3, the fifth transistor M5, the seventh transistor M7, the ninth transistor M9, and the eleventh transistor M11 are P-type LPS, which are turned on according to a second voltage signal VGL (low level) and turned off according to a high level; the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 are N-type MOTs, which are turned on according to a first voltage signal VGH (high level) and turned off according to a low level.

[0113] Figure 8 This is a schematic diagram of the circuit structure of one type of shift register provided in an embodiment of this application. Figure 9 This is a signal timing diagram of one type of shift register provided in an embodiment of this application. Figure 9 Applicable to, for example Figure 8 The shift register 100 shown in this embodiment is combined with... Figure 8 and Figure 9 The working process of the shift register provided in one embodiment of this application is described in detail, but it should not be construed as a limitation on the scope of the invention patent.

[0114] In one possible implementation, the operation of the shift register 100 may include a first stage t1, a second stage t2, and a third stage t3. Figure 9 In this context, t0 can represent the initial stage. The initial stage can refer to the shift register 100 being in a non-working state, or it can also refer to the third stage t3 in the previous working process. Figure 9 In the diagram, VN1 is the potential signal at the first node N1, i.e., the first node signal; VN2 is the potential signal at the second node N2, i.e., the second node signal.

[0115] In the initial stage t0, the input signal SIN can be low, the first reference signal S1 is high, the second reference signal S1B is low, and the third reference signal S2 is low. The first transistor M1 is off according to the first reference signal S1, the second transistor M2 is off according to the second reference signal S1B, the third transistor M3 is on according to the second reference signal S1B, and the fourth transistor M3 is on according to the first reference signal S1. That is, the first transmission gate 111 is off, and the second transmission gate 122 is on. The first node N1 maintains the potential (high level) from the previous stage. When the first node N1 is high, the third transistor M3 is off, the fourth transistor M4 is on, and the fourth transistor M4 transmits the second voltage signal VGL to the output of the voltage regulation control module 120. That is, at this time, the level of the first output signal Sn_n is low. When the first output signal Sn_n is low, the seventh transistor M7 is on, the eighth transistor M8 is off, the ninth transistor M9 is on, and the tenth transistor M10 is off. The seventh transistor M7 transmits the first voltage signal VGH to the second node N2, meaning the potential at the second node N2 is high. The first voltage signal VGH is transmitted to the output terminal of the output module 130 through the ninth transistor, meaning the second output signal Sn_p outputs a high level.

[0116] In the first stage t1, the input signal SIN can be low, the first reference signal S1 is low, the second reference signal S1B is high, and the third reference signal S2 is high. The first transistor M1 is turned on according to the first reference signal S1, the second transistor M2 is turned on according to the second reference signal S1B, the third transistor M3 is turned off according to the second reference signal S1B, and the fourth transistor M3 is turned off according to the first reference signal S1. That is, the first transmission gate 111 is turned on, and the second transmission gate 122 is turned off. The first transmission gate 111 transmits the input signal SIN to the first node N1, meaning the potential of the first node N1 is low at this time. When the first node N1 is low, the third transistor M3 is turned on, and the fourth transistor M4 is turned off. The third transistor M3 transmits the first voltage signal VGH to the output of the voltage regulation control module 120, meaning the level of the first output signal Sn_n is high at this time. When the level of the first output signal Sn_n is high, the seventh transistor M7 is turned off, the eighth transistor M8 is turned on, the ninth transistor M9 is turned off, and the tenth transistor M10 is turned on. The eighth transistor M8 transmits the second voltage signal VGL to the second node N2, meaning the potential at the second node N2 is low. The tenth transistor M10 transmits the third reference signal S2 to the output terminal of the output module 130. At this time, the second reference signal S2 is high, so the second output signal Sn_p remains high.

[0117] In the second stage t2, the input signal SIN can be high, the first reference signal S1 is high, the second reference signal S1B is low, and the third reference signal S2 is low. The first transistor M1 is off according to the first reference signal S1, the second transistor M2 is off according to the second reference signal S1B, the third transistor M3 is on according to the second reference signal S1B, and the fourth transistor M3 is on according to the first reference signal S1. That is, the first transmission gate 111 is off, and the second transmission gate 122 is on. The first node N1, under the action of the voltage regulation control module 120, maintains the same level as in the previous stage, i.e., it remains low. When the first node N1 is low, the third transistor M3 is on, and the fourth transistor M4 is off. The third transistor M3 transmits the first voltage signal VGH to the output of the voltage regulation control module 120, meaning the first output signal Sn_n is high at this time. When the first output signal Sn_n is high, the seventh transistor M7 is off, the eighth transistor M8 is on, the ninth transistor M9 is off, and the tenth transistor M10 is on. The eighth transistor M8 transmits the second voltage signal VGL to the second node N2, meaning the potential at the second node N2 is low. The tenth transistor M10 transmits the third reference signal S2 to the output terminal of the output module 130. At this time, the second reference signal S2 is low, therefore the level of the second output signal Sn_p is low.

[0118] In the third stage t3, the input signal SIN can be high, the first reference signal S1 is low, the second reference signal S1B is high, and the third reference signal S2 is high. The first transistor M1 is turned on according to the first reference signal S1, the second transistor M2 is turned on according to the second reference signal S1B, the third transistor M3 is turned off according to the second reference signal S1B, and the fourth transistor M3 is turned off according to the first reference signal S1. That is, the first transmission gate 111 is turned on, and the second transmission gate 122 is turned off. The first transmission gate 111 transmits the input signal SIN to the first node N1, meaning the potential of the first node N1 is high at this time. When the first node N1 is high, the third transistor M3 is turned off, and the fourth transistor M4 is turned on. The fourth transistor M4 transmits the second voltage signal VGL to the output of the voltage regulation control module 120, meaning the level of the first output signal Sn_n is low at this time. When the level of the first output signal Sn_n is low, the seventh transistor M7 is turned on, the eighth transistor M8 is turned off, the ninth transistor M9 is turned on, and the tenth transistor M10 is turned off. The seventh transistor M7 transmits the first voltage signal VGH to the second node N2, meaning the potential at the second node N2 is high. The ninth transistor M9 transmits the first voltage signal VGH to the output terminal of the output module 130, meaning the second output signal Sn_p outputs a high level.

[0119] In one possible implementation, based on Figure 9As can be seen in this embodiment, the first output signal Sn_n has a first level of high and a second level of low; the first level lasts for one clock cycle, while the second level lasts for more than one clock cycle. The second output signal Sn_p has a third level of high and a fourth level of low; the third level lasts for more than one clock cycle, while the fourth level lasts for half a clock cycle. The first level is greater than the fourth level. The durations of the first and fourth levels overlap at least partially, and the duration of the first level is greater than the duration of the fourth level.

[0120] In one possible implementation, the timing waveform of the first node signal VN1 is the same as the timing waveform of the second node signal VN2.

[0121] In one possible implementation, the duration of the fifth level in the first node signal VN1 is the same as the duration of the first level in the first output signal Sn_n. The fifth level in the first node signal VN1 is a low level. That is, the duration of the low level in the first node signal VN1 is the same as the duration of the high level in the first output signal Sn_n. Since the first node signal is the input signal of the first inverter 121, and the first output signal Sn_n is the output signal of the first inverter 121, the first node signal VN1 and the first output signal Sn_n are inverted signals.

[0122] In one possible implementation, the duration of the sixth level in the input signal SIN is the same as the duration of the first level in the first output signal Sn_n. The sixth level in the input signal SIN is low, that is, the duration of the low level in the input signal SIN is the same as the duration of the high level in the first output signal Sn_n. The first node signal VN1 is delayed by half a clock cycle relative to the input signal SIN by the first reference signal S1. In the shift register 100 provided in this application, the voltage regulation control module 120 can be used as a static random-access memory (SRAM) to temporarily store the input signal SIN. In this embodiment, the input signal SIN is temporarily stored and output after a half-clock cycle delay.

[0123] In one possible implementation, the first voltage level is the same as the first voltage signal VGH, the second voltage level is the same as the second voltage signal VGL, the third voltage level is the same as the first voltage signal VGH, and the fourth voltage level is the same as the seventh voltage level of the third reference signal. The seventh voltage level is low, meaning the seventh voltage level is lower than the first voltage level.

[0124] Figure 10This is a schematic diagram of one type of gate driving circuit provided in an embodiment of this application. The present invention can also provide a gate driving circuit 10, which may include the shift register 100 described in any of the above embodiments, possessing the beneficial effects of the shift register 100 in any embodiment of this application, which will not be repeated here. The gate driving circuit 10 may include n groups of shift registers 100, where n is a positive integer. For example, the gate driving circuit 10 may include 1 group, 2 groups, 5 groups, or 10 groups of shift registers 100. Multiple groups of shift registers 100 are cascaded together. Each shift register 100 can be configured to generate a first output signal Sn_n and a second output signal Sn_p.

[0125] The cascaded connection of n shift registers 100 can be specifically as follows: the input terminal of the input module 110 in the first-stage shift register 100 is connected to the input signal SIN; the input terminal of the input module 110 in the (i+1)th-stage shift register 100 is connected to the second node N2 of the ith-stage shift register 100, where i = 1, 2, 3, ..., n. Here, i can be equal to 1, 2, 3, 4, 5, 6, 7, 8, 9, or n, etc. For example, the input terminal of the input module 110 in the second-stage shift register 100 is connected to the second node N2 in the first-stage shift register 100; the input terminal of the input module 110 in the third-stage shift register 100 is connected to the second node N2 in the second-stage shift register 100, and so on, with the input terminal of the input module 110 in the nth-stage shift register 100 connected to the second node N2 in the (n-1)th-stage shift register 100.

[0126] In one possible implementation, the first output signal Sn_n output by the (i+1)th stage shift register 100<i+1> The first output signal Sn_n relative to the output of the i-th stage shift register 100 The second output signal Sn_p of the (i+1)th stage shift register is delayed by a preset time.<i+1> The second output signal Sn_p relative to the output of the i-th stage shift register A preset delay time is specified. In a preferred embodiment, the preset time is half a clock cycle, where the clock cycle is the clock cycle of the first reference signal.

[0127] In the gate driving circuit 10 provided in this application, the potential at the second node N2 in the previous stage shift register 100 is used as the input signal SIN of the next stage shift register 100. Since the potential at the second node N2 is the same as the potential at the first node N1 in each stage shift register 100, and the potential at the first node N1 is shifted by half a clock cycle relative to the signal input to the shift register 100, the potential at the second node N2 is also delayed by half a clock cycle relative to the signal input to the shift register 100. Simultaneously, since the first output signal Sn_n and the second output signal Sn_p in each stage shift register 100 are both delayed by half a clock cycle relative to the effective level of the input signal SIN, that is, in the gate driving circuit, the first output signal Sn_n and the second output signal Sn_p output by the next stage shift register 100 are both delayed by half a clock cycle relative to the first output signal Sn_n and the second output signal Sn_p output by the previous stage shift register 100.

[0128] Figure 11 This is a schematic diagram of the structure of a display panel provided in one embodiment of this application. The present invention can also provide a display panel 1, which may include the gate driving circuit 10 described in any of the above embodiments. The display panel 1 may include one or more sets of pixel circuits (not shown). Multiple pixel circuit arrays are arranged in multiple rows, wherein the pixel circuits can be configured to generate driving signals and drive the light-emitting units to emit light using the driving signals. Each stage shift register 100 in the gate driving circuit 10 is connected to at least one row of pixel circuits. Each stage shift register 100 can provide a first output signal Sn_n and a second output signal Sn_p to the corresponding connected at least one row of pixel circuits. For example, the first output signal Sn_n can be used as an EM signal in the pixel circuit, or the first output signal Sn_n can be used as a scan signal for an N-type transistor in the pixel circuit; the second output signal Sn_p can be used as a scan signal for a P-type transistor in the pixel circuit.

[0129] The display panel 1 can be applied to any product or component with display function, including but not limited to the following categories: mobile phones, televisions, digital cameras, tablet computers, laptops, desktop monitors, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control equipment, touch interactive terminals, etc. The embodiments of the present invention do not impose any special limitations on this.

[0130] Please see Figure 11 The display panel 1 may also include a driver chip 210, a third inverter 220, a fourth inverter 230, an input signal line L5, a first clock line L1, a second clock line L2, a third clock line L3, and a fourth clock line L4. The first terminal of the driver chip 210 is electrically connected to the input terminal of the input module 110 in the first-stage shift register 100 through the input signal line L5. The first terminal of the driver chip 210 can be used to provide the input signal SIN.

[0131] The second terminal of the driver chip 210 can be electrically connected to the first clock line L1. The first clock line L1 is connected to multiple shift registers 100 respectively. The second terminal ky of the driver chip 210 is used to provide a first clock signal SCK1. The first clock signal SCK1 can be used as the first reference signal S1 for the odd-level shift registers 100 and as the third reference signal S2 for the even-level shift registers 100. That is, the driver chip 210 can output the first clock signal SCK1 to the first clock line L1. The first clock line L1 can be connected to different nodes of different shift registers 100 to provide the corresponding shift registers 100 with the required signals. Here, odd-level and even-level can refer to the cascaded positions of the shift registers 100 in the gate driver circuit 10. For example, the odd-level shift register 100 can be the first-level shift register 100, the third-level shift register 100, ..., the 15th-level shift register 100, etc.; the even-level shift register 100 can be the second-level shift register 100, the fourth-level shift register 100, ..., the 20th-level shift register 100, etc.

[0132] In some other implementations, the first clock signal SCK1 can also be used as the third reference signal S2 connected to the odd-level shift register 100, and the first clock signal SCK1 can be used as the first reference signal S1 of the even-level shift register 100.

[0133] In a preferred embodiment, the first clock line L1 can be electrically connected to the first control terminal of the first transmission gate 111 and the second control terminal of the second transmission gate 122 in the odd-level shift register 100, and the first clock line L1 can be electrically connected to the input terminal of the third transmission gate 132 in the even-level shift register 100.

[0134] The second terminal of the driver chip 210 can also be electrically connected to the second clock line L2 via a third inverter 220. The second clock line L2 is connected to multiple shift registers 100 respectively, and the inverted first clock signal SCK1B serves as the second reference signal S1B for the odd-level shift registers 100. That is, the third inverter 220 can be used to invert the first clock signal SCK1 output from the second terminal of the driver chip 210 to obtain the inverted first clock signal SCK1B and transmit it to the second clock line L2. The second clock line L2 can be connected to different nodes of different shift registers 100 to provide the corresponding shift register 100 with the required signal.

[0135] In a preferred embodiment, the second clock line L2 can be electrically connected to the second control terminal of the first transmission gate 111 and the first control terminal of the second transmission gate 122 in the odd-level shift register 100.

[0136] The third terminal of the driver chip 210 can be electrically connected to the third clock line L3. The third clock line L3 is connected to multiple shift registers 100 respectively. The third terminal of the driver chip 210 is used to provide a second clock signal SCK2. The second clock signal SCK2 serves as the third reference signal S2 for the odd-level shift registers 100 and as the first reference signal S1 for the even-level shift registers 100. That is, the driver chip 210 can output the second clock signal SCK2 to the second clock line L2. The second clock line L2 can be connected to different nodes of different shift registers 100 to provide the required signals to the corresponding shift registers 100.

[0137] In a preferred embodiment, the third clock line L3 can be electrically connected to the first control terminal of the first transmission gate 111 and the second control terminal of the second transmission gate 122 in the even-level shift register 100, and the first clock line L1 is electrically connected to the input terminal of the third transmission gate 132 in the odd-level shift register 100.

[0138] The second terminal of the driver chip 210 can also be electrically connected to the fourth clock line L4 through the fourth inverter 230. The fourth clock line L4 is connected to multiple shift registers 100 respectively. The inverted second clock signal SCK2B can be used as the second reference signal S2 connected to the even-numbered shift registers 100.

[0139] Figure 12 This is a timing waveform diagram of one type of display panel provided in an embodiment of this application. Figure 12 Applicable to Figure 11 The display panel shown is Figure 11 The gate drive circuit 10 in the display panel 1 shown includes a 4-stage shift register 100. In some other embodiments, the number of shift registers 100 cascaded in the gate drive circuit 10 in the display panel can be reasonably set according to actual application requirements.

[0140] Figure 11 In the first-stage shift register 100, the input terminal of the input module is electrically connected to the input signal line L5 to receive the input signal SIN. That is, the input signal SIN received in the first-stage shift register 100 originates from the driver chip 210. The input terminal of the second-stage shift register 100 is electrically connected to the second node N2 in the first-stage shift register 100. That is, the input signal SIN received in the second-stage shift register 100 is the potential at the second node N2 in the first-stage shift register 100. The input terminal of the third-stage shift register 100 is electrically connected to the second node N2 in the second-stage shift register 100. That is, the input signal SIN received in the third-stage shift register 100 is the potential at the second node N2 in the second-stage shift register 100. The input terminal of the input module of the fourth-stage shift register 100 is electrically connected to the second node N2 in the third-stage shift register 100. That is, the input signal SIN connected to the fourth-stage shift register 100 is the potential at the second node N2 in the third-stage shift register 100.

[0141] Please participate Figure 11 and Figure 12 The first-stage shift register 100 can output the first output signal Sn_n <1> Second output signal Sn_p <1> The second-stage shift register 100 can output the first output signal Sn_n <2> Second output signal Sn_p <2> The third-stage shift register 100 can output the first output signal Sn_n <3> Second output signal Sn_p <3> The fourth-stage shift register 100 can output the first output signal Sn_n <4> Second output signal Sn_p <4> It can be seen that the first output signal Sn_n and the second output signal Sn_p output by each stage shift register 100 are delayed by a preset time relative to the first output signal Sn_n and the second output signal Sn_p output by the previous stage shift register 100. This preset time is half a clock cycle of the first clock signal SCK1.

[0142] This invention also provides a display device, which may include the shift register described in any of the above embodiments. The display device may include one or more sets of shift registers. The shift registers can be configured to generate gate drive signals for controlling the operation of switching transistors. Similarly, this display device can be applied to any product or component with display functionality, including but not limited to the following categories: mobile phones, televisions, digital cameras, tablet computers, laptops, desktop monitors, smart bracelets, smart glasses, automotive displays, medical devices, industrial control equipment, touch interactive terminals, etc. This invention does not impose any special limitations on these categories.

[0143] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0144] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0145] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A shift register, characterized in that, It includes an input module, a voltage regulation control module, and an output module; The input terminal of the input module is connected to the input signal, and the output terminal of the input module is connected to the first node. The input module is used to transmit the input signal to the first node according to the first reference signal and the second reference signal. The voltage regulation control module includes a first node, a second node, and an output terminal. The voltage regulation control module is used to stabilize the potential at the first node at least in a partial stage. The potential at the first node is the same as the potential at the second node. The voltage regulation control module is used to output a first output signal according to the potential at the first node. The output module is electrically connected to the output terminal of the voltage regulation control module and the second node, respectively. The output module is used to output a second output signal according to the first output signal and the potential at the second node. The first output signal includes a first level and a second level, wherein the first level is greater than the second level and the duration of the first level is less than the duration of the second level; The second output signal includes a third level and a fourth level, wherein the third level is greater than the fourth level and the duration of the third level is greater than the duration of the fourth level.

2. The shift register according to claim 1, characterized in that, The input module includes a first transmission gate, the input terminal of the first transmission gate is connected to the input signal, the first control terminal of the first transmission gate is connected to the first reference signal, the second control terminal of the first transmission gate is connected to the second reference signal, and the output terminal of the first transmission gate is connected to the first node. Preferably, the first transmission gate includes a first transistor and a second transistor, the first terminal of the first transistor is connected to the first terminal of the second transistor and serves as the input terminal of the first transmission gate, the gate of the first transistor serves as the first control terminal of the first transmission gate, the gate of the second transistor serves as the second control terminal of the first transmission gate, and the second terminal of the first transistor is connected to the second terminal of the second transistor and serves as the output terminal of the first transmission gate. Preferably, the channel type of the first transistor is different from the channel type of the second transistor; Preferably, the second reference signal is the inverted signal of the first reference signal.

3. The shift register according to claim 1 or 2, characterized in that, The voltage regulation control module includes a first inverter, a second transmission gate, and a second inverter. The input terminal of the first inverter and the input terminal of the second transmission gate are connected to the first node. The output terminal of the first inverter, the input terminal of the second inverter, and the output module are electrically connected. The output terminal of the first inverter serves as the output terminal of the voltage regulation control module. The output terminal of the second transmission gate and the output terminal of the second inverter are connected to the second node. The first control terminal of the second transmission gate is connected to the second reference signal, and the second control terminal of the second transmission gate is connected to the first reference signal. Preferably, the input terminal of the first inverter is connected to the output terminal of the input module, the first terminal of the first inverter is connected to a first voltage signal, the second terminal of the first inverter is connected to a second voltage signal, and the output terminal of the first inverter serves as the output terminal of the voltage regulation control module; wherein, the first voltage signal is greater than the second voltage signal. Preferably, the input terminal of the second transmission gate is connected to the input terminal of the first inverter and the output terminal of the input module, the first control terminal of the second transmission gate is connected to the second reference signal, the second control terminal of the second transmission gate is connected to the first reference signal, and the output terminal of the second transmission gate is connected to the output terminal of the second inverter. Preferably, the input terminal of the second inverter is connected to the output terminal of the first inverter, the first terminal of the second inverter is connected to the first voltage signal, the second terminal of the second inverter is connected to the second voltage signal, and the output terminal of the second inverter is connected to the second node.

4. The shift register according to claim 3, characterized in that, The first inverter includes a third transistor and a fourth transistor. The gate of the third transistor is connected to the gate of the fourth transistor and serves as the input terminal of the first inverter. The first terminal of the third transistor serves as the first terminal of the first inverter. The first terminal of the fourth transistor serves as the second terminal of the first inverter. The second terminals of the third transistor and the fourth transistor are connected and serve as the output terminal of the first inverter. Preferably, the channel type of the third transistor is different from that of the fourth transistor; Preferably, the second transmission gate includes a fifth transistor and a sixth transistor, the first terminal of the fifth transistor is connected to the first terminal of the sixth transistor and serves as the input terminal of the second transmission gate, the gate of the fifth transistor serves as the first control terminal of the second transmission gate, the gate of the sixth transistor serves as the second control terminal of the second transmission gate, and the second terminal of the fifth transistor is connected to the second terminal of the sixth transistor and serves as the output terminal of the second transmission gate. Preferably, the channel type of the fifth transistor is different from that of the sixth transistor; Preferably, the second inverter includes a seventh transistor and an eighth transistor, the gate of the seventh transistor is connected to the gate of the eighth transistor and serves as the input terminal of the second inverter, the first terminal of the seventh transistor serves as the first terminal of the second inverter, the first terminal of the eighth transistor serves as the second terminal of the second inverter, and the second terminal of the seventh transistor is connected to the second terminal of the eighth transistor and serves as the output terminal of the second inverter. Preferably, the channel type of the seventh transistor is different from that of the eighth transistor.

5. The shift register according to claim 4, characterized in that, The output module includes a first output unit and a third transmission gate. The control terminal of the first output unit and the first control terminal of the third transmission gate are electrically connected to the output terminal of the voltage regulation control module. The first terminal of the first output unit is connected to a first voltage signal. The second terminal of the first output unit is connected to the output terminal of the third transmission gate as the output terminal of the output module. The second control terminal of the third transmission gate is connected to the second node. The input terminal of the third transmission gate is connected to a third reference signal. Preferably, the first output unit includes a ninth transistor, the first terminal of the ninth transistor serves as the first terminal of the first output unit, the gate of the ninth transistor serves as the control terminal of the first output unit, and the second terminal of the ninth transistor serves as the second terminal of the first output unit. Preferably, the third transmission gate includes a tenth transistor and an eleventh transistor, the first terminal of the tenth transistor is connected to the first terminal of the eleventh transistor and serves as the input terminal of the third transmission gate, the gate of the tenth transistor serves as the first control terminal of the third transmission gate, the gate of the eleventh transistor serves as the second control terminal of the third transmission gate, and the second terminal of the tenth transistor is connected to the second terminal of the eleventh transistor and serves as the output terminal of the third transmission gate. Preferably, the channel type of the tenth transistor is different from that of the eleventh transistor, and the channel type of the ninth transistor is the same as that of the eleventh transistor. Preferably, the clock period of the first reference signal is the same as the clock period of the third reference signal, and the third reference signal is delayed by half a clock period relative to the first reference signal. Preferably, the signal waveform of the second reference signal is the same as the signal waveform of the third reference signal.

6. The shift register according to claim 1, characterized in that, The duration of the first level overlaps at least partially with the duration of the fourth level; Preferably, the duration of the first level is greater than the duration of the fourth level; Preferably, the potential signal at the first node is a first node signal, the potential signal at the second node is a second node signal, and the timing waveform of the first node signal is the same as the timing waveform of the second node signal. Preferably, the duration of the fifth level in the first node signal is the same as the duration of the first level in the first output signal; The fifth level is lower than the first level; Preferably, the first output signal is the inverted signal of the first node signal; Preferably, the duration of the sixth level in the input signal is the same as the duration of the first level in the first output signal, the first node signal is delayed by half a clock cycle relative to the input signal, and the clock cycle is the clock cycle of the first reference signal; the sixth level is less than the first level. Preferably, the first level is the same as the first voltage signal, and the second level is the same as the second voltage signal; The third level is the same as the first voltage signal, and the fourth level is the same as the seventh level of the third reference signal; The seventh level is lower than the first level; Preferably, the first transistor, the third transistor, the fifth transistor, the seventh transistor, the ninth transistor, and the eleventh transistor have the same channel type, and the second transistor, the fourth transistor, the sixth transistor, the eighth transistor, and the tenth transistor have the same channel type. Preferably, the first transistor, the third transistor, the fifth transistor, the seventh transistor, the ninth transistor, and the eleventh transistor are all low-temperature polycrystalline silicon transistors, and the second transistor, the fourth transistor, the sixth transistor, the eighth transistor, and the tenth transistor are all metal-oxide transistors. Preferably, the first transistor, the third transistor, the fifth transistor, the seventh transistor, the ninth transistor, and the eleventh transistor are all P-channel transistors, and the second transistor, the fourth transistor, the sixth transistor, the eighth transistor, and the tenth transistor are all N-channel transistors.

7. A gate driving circuit, characterized in that, It includes n shift registers as described in any one of claims 1-6, where n is a positive integer, wherein the input terminal of the input module in the first-stage shift register is connected to the input signal, and the input terminal of the input module in the (i+1)th-stage shift register is connected to the second node of the i-th-stage shift register, i=1,2,3,…,n.

8. The gate driving circuit according to claim 7, characterized in that, The first output signal of the shift register at stage i+1 is delayed by a preset time relative to the first output signal of the shift register at stage i, and the second output signal of the shift register at stage i+1 is delayed by a preset time relative to the second output signal of the shift register at stage i. Preferably, the preset time is half a clock cycle of the first reference signal.

9. A display panel, characterized in that, It includes a pixel circuit and a gate driving circuit as described in any one of claims 7 to 8, wherein the gate driving circuit is used to provide a first output signal and a second output signal to the pixel circuit.

10. The display panel according to claim 9, characterized in that, The display panel includes multiple rows of pixel circuits arranged in an array, and each level of the shift register is connected to at least one row of pixel circuits. Preferably, the display panel further includes a driver chip, a third inverter, a fourth inverter, an input signal line, a first clock line, a second clock line, a third clock line, and a fourth clock line. The first terminal of the driver chip is electrically connected to the input terminal of the input module of the first-stage shift register through the input signal line. The first terminal of the driver chip is used to provide an input signal. The second end of the driver chip is electrically connected to the first clock line, and the first clock line is connected to the plurality of shift registers respectively. The second end of the driver chip is used to provide a first clock signal. The first clock signal is used as a first reference signal for the odd-level shift registers and as a third reference signal for the even-level shift registers. The second end of the driver chip is also electrically connected to the second clock line through the third inverter. The second clock line is connected to a plurality of shift registers respectively. The inverted first clock signal serves as the second reference signal connected to the odd-level shift registers. The third terminal of the driver chip is electrically connected to the third clock line, and the third clock line is connected to the plurality of shift registers respectively. The third terminal of the driver chip is used to provide a second clock signal. The second clock signal is used as a third reference signal for the odd-level shift registers and as a first reference signal for the even-level shift registers. The second terminal of the driver chip is also electrically connected to the fourth clock line through the fourth inverter. The fourth clock line is connected to a plurality of shift registers respectively. The inverted second clock signal serves as the second reference signal for the even-numbered shift registers. Preferably, the first clock line is electrically connected to the first control terminal of the first transmission gate and the second control terminal of the second transmission gate in the odd-level shift register, and the first clock line is electrically connected to the input terminal of the third transmission gate in the even-level shift register. Preferably, the second clock line is electrically connected to the second control terminal of the first transmission gate and the first control terminal of the second transmission gate in the odd-level shift register; Preferably, the third clock line is electrically connected to the first control terminal of the first transmission gate and the second control terminal of the second transmission gate in the even-numbered shift register, and the first clock line is electrically connected to the input terminal of the third transmission gate in the odd-numbered shift register. Preferably, the fourth clock line is electrically connected to the second control terminal of the first transmission gate and the first control terminal of the second transmission gate in the even-numbered shift register.

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