Programmable data selector, memory chip automated test equipment, data selection method and computer program product

Abstract

The embodiment of the application discloses a programmable data selector, a storage chip automatic test device, a data selection method and a computer program product, and belongs to the technical field of storage chip testing. The programmable data selector comprises: a pin data selection path, which is used for pre-encoding basic data items of an input end to obtain pin data sets corresponding to output end pins, and then gating the pin data sets to obtain output data corresponding to each pin; and a pin control data processing path, which is arranged in parallel with the pin data selection path, and is used for selecting a plurality of pin control signals from a global control signal source, and then distributing the selected plurality of pin control signals to corresponding pins after unified delay processing. The application can significantly reduce the consumption of multiplexer and register resources.

Description

Technical Field

[0001] This application relates to the field of memory chip testing technology, and in particular to a programmable data selector, automated testing equipment for memory chips, a data selection method, and a computer program product. Background Technology

[0002] In automated test equipment (ATE) for memory chips, the programmable data selector (PDS) module typically consumes a significant amount of multiplexer (MUX) combinational logic and register resources to generate the test vectors required for chip testing. This is especially true in high-speed test equipment, where parallel testing is usually required to improve test efficiency. As the number of channels increases, the consumption of multiplexer and register resources increases exponentially. Summary of the Invention

[0003] This application provides a programmable data selector, an automated testing device for memory chips, a data selection method, and a computer program product to significantly reduce the consumption of multiplexer and register resources.

[0004] In a first aspect, embodiments of this application provide a programmable data selector, applied to an automated testing equipment for memory chips, the programmable data selector comprising: The pin data selection path is used to pre-encode the basic data items of the input terminal, obtain the pin dataset corresponding to the output terminal pin, and then select the pin dataset to obtain the output data corresponding to each pin. The pin control data processing path is set in parallel with the pin data selection path. It is used to select multiple pin control signals from the global control signal source, and after uniformly delaying the selected multiple pin control signals, it is assigned to their respective corresponding pins.

[0005] In at least one possible implementation, the pin control data processing path includes: A shared multi-tap register chain is used to perform unified delay processing on selected multi-pin control signals and provide multiple tap outputs with different delay cycle numbers; The signal distribution module, connected to the shared multi-tap register chain, is used to select a set of delayed multi-channel pin control signals from the tap output of the corresponding channel according to the delay period required for each pin, and select the leading edge pin control signal and trailing edge pin control signal of the pin from the set of multi-channel pin control signals and the fixed level signal.

[0006] In at least one possible implementation, the programmable data selector further includes: The storage module, whose output is connected to the input of the pin data selection path, is used to store several sets of basic data items. Each set of basic data items is pre-configured as a set of pin data selection control words corresponding to the test cycle. The register module is used to receive and store external configuration information, which includes at least pin control configuration information corresponding to the test cycle.

[0007] In at least one possible implementation, the pin data selection path specifically includes: The precoding module is used to select a control word set identifier based on the externally input pin data, obtain the encoding value of the basic data item of this pin from the storage module, and select a preset number of encoding values ​​as candidate encoding values ​​for this pin from the basic data item according to the pin control configuration information obtained from the register module. The gating module, cascaded with the precoding module, is used to map the candidate encoded value of this pin to the corresponding test vector signal or fixed level signal as pin data output.

[0008] In at least one possible implementation, the pin data selection path further includes: A pin data delay module, cascaded with the gating module, applies a programmable periodic write delay and / or read delay to the selected pin data; The number of cycles for the programmable cycle write delay and / or read delay is determined by the preset delay configuration information in the register module.

[0009] In at least one possible implementation, the programmable data selector further includes: A real-time data inversion signal generation circuit, connected to the input of the precoding module, is used to generate a real-time data inversion signal for each channel for precoding and output it to the precoding module; and / or The address bus toggle signal generation circuit is connected to the input terminals of the precoding module and the gating module, and is used to generate address bus toggle signals for each channel for precoding and gating, and output them to the precoding module and the gating module.

[0010] In at least one possible implementation, the pin data includes at least expected data and / or drive data; The pin control signals include comparator enable signals and / or drive enable signals; The external configuration information also includes an operation mode enable signal, which includes at least one of the following: real-time data exchange mode enable, test vector exchange mode enable, real-time data flip mode enable, exchange mode control enable, dual non-return-to-zero waveform enable, and address flip mode enable. The test vector signal includes at least one of the following: address signal, data signal, read signal, write signal, mode signal, control signal, general enable signal, address bus toggle signal, and parity check signal. The input signal of the real-time data flip signal generation circuit comes from at least one of the following: read signal, write signal, mode signal, control signal, and general enable signal; The storage module also stores address toggle selection information. The address bus toggle signal generation circuit is specifically used to select address bits from address signals, read signals, write signals, mode signals and control signals according to the address toggle selection information in the storage module, XOR the selected address bits with a fixed value preset in the register module, generate an address bus toggle signal according to the number of 1s after XOR, and output it to the precoding module and the gating module.

[0011] Secondly, embodiments of this application provide an automated testing device for memory chips, including a programmable data selector as described in the first aspect.

[0012] Thirdly, embodiments of this application provide a data selection method, applied to a programmable data selector in an automated testing equipment for memory chips, comprising: After pre-encoding the input basic data items to obtain the pin dataset corresponding to the output pin, the pin dataset is gating to obtain the output data corresponding to each pin. In parallel, multiple pin control signals are selected from the global control signal source, and after uniform delay processing, the selected multiple pin control signals are assigned to their respective corresponding pins.

[0013] In at least one possible implementation, the step of selecting multiple pin control signals from a global control signal source, performing a unified delay on the selected multiple pin control signals, and then assigning them to their respective corresponding pins specifically includes: Generate multiple pin control signals for each channel from the original test pattern signal; The multi-pin control signals generated for each channel will be uniformly delayed, and multiple tap outputs with different delay period numbers will be provided. Each tap output corresponds to a set of delayed multi-pin control signals. Based on the required delay period for each pin, a set of delayed multi-pin control signals is selected from the tap output of the corresponding channel, and the leading edge pin control signal and trailing edge pin control signal are selected from the set of multi-pin control signals and the fixed level signal.

[0014] In at least one possible implementation, it also includes: The input basic data items are obtained from several sets of basic data items pre-stored in the storage module, and each set of basic data items is configured as a set of pin data selection control words corresponding to the test cycle; The register module receives and stores external configuration information, which includes at least pin control configuration information corresponding to the test cycle.

[0015] In at least one possible implementation, the precoding and gating specifically include: Select the control word set identifier based on the pin data, and obtain the encoded value of the basic data item of this pin from the storage module; Based on the pin control configuration information obtained from the register module, a preset number of encoding values ​​are selected from the basic data items as candidate encoding values ​​for this pin; The candidate encoded value of this pin is mapped to the corresponding test vector signal or fixed level signal and used as the pin data output.

[0016] In at least one possible implementation, it also includes: Apply programmable periodic write and / or read delays to the selected pin data; The number of cycles for the programmable cycle write delay and / or read delay is determined by the preset delay configuration information in the register module.

[0017] In at least one possible implementation, it also includes: Generate a real-time data toggle signal for each channel for precoding; and / or Generate an address bus toggle signal for each channel for precoding and gating, and use it in the precoding and gating steps.

[0018] In at least one possible implementation, the pin data includes expected data and drive data; The pin control signals include comparator enable signals and drive enable signals; The test vector signal includes at least one of the following: address signal, data signal, read signal, write signal, mode signal, control signal, general enable signal, address bus toggle signal, and parity check signal. In the step of generating the real-time data flip signal, the input signal comes from at least one of the following: read signal, write signal, mode signal, control signal, and general enable signal. The storage module also stores address toggle selection information. The specific steps for generating the address bus toggle signal include: selecting an address bit from the address bus signal and the control signal according to the address toggle selection information in the storage module; XORing the selected address bit with a fixed value preset in the register module; and generating an address bus toggle signal output according to the number of 1s after XORing.

[0019] Fourthly, embodiments of this application provide a computer program product comprising: computer program code, which, when executed on a computer, causes the computer to perform the steps in the data selection method as described in the third aspect.

[0020] The beneficial effects of this application are: This application embodiment separates control data with fixed data types and simple processing logic from business data with varied data types and complex processing logic by independently setting up pin data selection paths for processing pin data and pin control data processing paths for processing pin control data. By pre-encoding and gating the pin data, the configuration of MUX resources is greatly reduced. Furthermore, the pin control data is first processed with a unified shared delay before being allocated to its respective pin, which reduces register resources by a factor of two, thereby significantly reducing the consumption of multiplexer and register resources. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the structure of a programmable data selector according to an embodiment of this application.

[0023] Figure 2 This is a structural diagram of a specific implementation of the programmable data selector according to an embodiment of this application.

[0024] Figure 3 This is a circuit diagram of an automated testing device for memory chips according to an embodiment of this application.

[0025] Figure 4 This is a circuit diagram of a programmable data selector according to an embodiment of this application.

[0026] Figure 5 This is a schematic diagram of the expected data delay of a programmable data selector according to an embodiment of this application.

[0027] Figure 6 This is a schematic diagram of the comparator enable data delay of the programmable data selector in an embodiment of this application.

[0028] Figure 7 This is a flowchart illustrating the data selection method according to an embodiment of this application.

[0029] Figure 8 This is a schematic diagram of the pin control data processing flow in the data selection method of this application embodiment.

[0030] Figure 9 This is a schematic diagram of the pin data selection process in the data selection method of this application embodiment.

[0031] Explanation of reference numerals in the attached figures: 1. Pin data selection path; 11. Precoding module; 12. Gating module; 13. Pin data delay module; 2. Pin-controlled data processing path; 21. Shared multi-tap register chain; 22. Signal distribution module; 3. Storage module; 4. Register module; 5. Real-time data flip signal generation circuit; 6. Address bus toggle signal generation circuit. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be described in detail below with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0033] It should be noted that: throughout the accompanying drawings, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions; in the description of this application, the terms "center," "longitudinal," "lateral," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this application; in the description of this application, "first," "second," etc., are only used to distinguish each other, and do not indicate their degree of importance or order, etc.

[0034] In the description of this application, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to fixed connections, movable connections, or detachable connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to the internal communication between two components, etc. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0035] The overall architecture of a memory chip ATE (Automatic Test Equipment) typically includes: a host computer (running the test program), an Algorithmic Pattern Generator (ALPG), a PDS (Programming Dataset), a Timing Generator (TG), a driver, and a comparator. The host computer writes the periodic configuration set to the PDS's storage module via an Advanced eXtensible Interface (AXI) and writes the configuration information to the PDS's register module via an Advanced Peripheral Bus (APB) interface. After the test starts, the ALPG outputs the periodic configuration set index and the original test vector signal to the PDS according to the test sequence. The PDS generates pin data and pin control signals for the TG according to the aforementioned embodiment. The TG synthesizes the final waveform and outputs it to the memory chip under test via a driver. Simultaneously, it uses a comparator to collect the data returned by the chip and compares it with the expected value, outputting the test result.

[0036] In the ATE (Automatic Test Equipment) of memory chips, PDS is used to generate test pattern sequences such as driver pattern, expected pattern, driver enable pattern, and comparator enable pattern for each pin. It can also configure delay parameters to achieve write latency (WL) / read latency (RL) and supports interleave mode to improve test efficiency.

[0037] In existing technologies, PDS typically consumes significant MUX combinational logic and register resources to generate the test vectors required for chip testing. This is especially true in high-speed test equipment, which often needs to support parallel testing to improve efficiency. As the number of ways increases, resource consumption multiplies. Furthermore, the implementation of read / write latency for chip pins places particularly high demands on register resources.

[0038] In view of this, the embodiments of this application aim to provide a programmable data selector with low resource consumption and easy portability to different models, which is applied to automated testing equipment for memory chips. For ease of understanding, some terms appearing in the various embodiments of this application will be explained first: Basic data items: These refer to the raw data units stored in storage module 3, including but not limited to PDS DATA A encoded values, PDS DATA B encoded values, PDS DATA D encoded values, and PDS DATA E encoded values ​​(PDS DATA A / B / D / E). Each basic data item provides encoded information for the waveform edge position of the corresponding pin.

[0039] Pin data includes driver pattern and expected pattern. Driver pattern is the signal output by the ATE to the device under test (DUT); expected pattern is the signal that the ATE expects to read back from the DUT, used for comparison with the actual output.

[0040] Pin dataset: refers to a set of intermediate data corresponding to each pin of the output terminal after pre-encoding processing.

[0041] Pin control signals: These are the enable signals used to control the operation of the drivers and comparators in the TG, including driver enable signals DRE1, DRE2 (DRE1-2), etc., and comparator enable signals CPE1, CPE2, CPE3, CPE4 (CPE1-4), etc. DRE controls when the driver is turned on, and CPE controls when the comparators in the timing generator are working.

[0042] Tap: The output terminal of each register in the register chain.

[0043] Pin control configuration information: This refers to the external configuration information stored in the register module used to configure the operating mode of the pin control data processing path, including the following: Control signal source selection information: used to independently select one pin control signal from the global control signal source (including comparator enable signals CPE1-4 and drive enable signals DRE1-2) for each pin; Delay configuration information: Used to configure the number of delay cycles for shared delay modules, such as comparator enable delay cycle number cpe_dly_num, and the number of write delay (WL) and / or read delay (RL) cycles for pin data delay modules, such as driver enable delay cycle number dre_dly_num, expected data delay cycle number exp_dly_num, driver data delay cycle number dr_dly_num, etc.

[0044] Cycle configuration set: This refers to the set of pin data selection control words, also known as the Cycle Palette (CYP) in this embodiment. It is the sum of all data selection configuration words for all pins corresponding to a test cycle, pre-stored in storage module 3. It is provided by ALPG every cycle and supports dynamic switching. Each cycle configuration set contains the basic data item encoding values ​​and address toggling selection information required for each pin in that cycle.

[0045] Periodic configuration set index: This is the pin data selection control word set identifier, an address signal provided by ALPG used to index the corresponding periodic configuration set from storage module 3, which can be dynamically changed for each channel per test cycle.

[0046] Fixed-level signals: including fixed high (FIXH) and fixed low (FIXL) signals, are used to generate test vectors that are constant 0 or constant 1, providing constant logic values ​​when expected data is generated.

[0047] Address Toggle Selection Information (AINV ADDR): An encoded value stored in the cycle configuration set, used to indicate which address bits the address bus toggle signal generation circuit 6 should select for XOR comparison. Its specific bit width and meaning can be configured through register module 4.

[0048] Operating mode enable signals include: rdsm_en for Real-time Data Swap Mode (RDSM), psm_en for Pattern Swap Mode (PSM), rinv_en for Real-Time Invert (RINV) mode, smc_en for Swap Mode Control (SMC), dnrz_en for Double Non-Return to Zero (DNRZ) waveform, and ainv_en for Address Invert (AINV) mode. These operating mode enable signals are a separate type of external configuration information, stored in register module 4, and used to control the filtering logic of precoding module 11.

[0049] Test vector signals include address signals (X0-23, Y0-23), data signals (D0-17, SD0-17), read signal R, write signal W, mode signals (M1, M2), control signals (C0-31), general-purpose enable signals (E0-7), address bus inversion (ABI) signals, and parity (PARI) signals. These signals are generated by ALPG and serve as the input source for the PDS.

[0050] N: WAY number, representing the number of channels for parallel testing; P: Number of pins per channel, indicating the number of pins contained in each test channel; D: Number of basic data items, representing the total number of raw data items that can be selected for each pin; k: Number of candidate encoded values, representing the number of candidate encoded values ​​output after precoding (i.e., the preset number); M: Maximum delay cycles, indicating the maximum clock cycle delay supported by the programmable delay module; S: Number of control signal sources, representing the total number of global control signal sources; MUX: Used to select one of multiple input signals as the output.

[0051] Please refer to Figure 1 The programmable data selector provided in this application embodiment includes: Pin data selection path 1 is used to pre-encode the basic data items of the input terminal, obtain the pin dataset corresponding to the output terminal pin, and then select the pin dataset to obtain the output data corresponding to each pin. Pin control data processing path 2 is set in parallel with pin data selection path 1. It is used to select multiple pin control signals from the global control signal source, perform unified delay processing on the selected multiple pin control signals, and then allocate them to their respective corresponding pins.

[0052] In existing memory chip ATE (Automatic Test Array) technologies, PDS (Programmable Specs) typically employ a "full parallel selection" architecture: each pin directly selects the required test vector from all basic data items (such as PDS DATA A / B / D / E), resulting in a linear increase in combinational logic (MUX) resources with the product of the number of pins and data items. Simultaneously, the delay processing of pin control signals (such as drive enable and comparator enable) uses an independent register chain for each, causing sequential logic (register) resources to increase linearly with the product of the number of pins and delay cycles. These two types of resource waste are independent yet coexist, resulting in excessive chip area and dynamic power consumption.

[0053] In this embodiment, by configuring pin data selection path 1 as a "precoding → gating" pipeline and pin control data processing path 2 as a "selection → unified delay → allocation" pipeline, and enabling the two paths to operate in parallel, the combinational logic and sequential logic resources are optimized respectively. Compared with the prior art, this embodiment reduces the number of MUX inputs from N×P×D to N×P×k (k is usually much smaller than D) and the number of delay registers from N×P×M to M, achieving a dual-order-of-magnitude optimization of combinational logic and sequential logic.

[0054] In FPGAs or ASICs, the pin data selection path 1 and pin control data processing path 2 of this application embodiment are instantiated as two independent hardware modules in parallel. The front end of the pin data selection path 1 is connected to the storage module, and the back end is connected to the TG; the front end of the pin control data processing path 2 is connected to the test vector signal output of the ALPG, and the back end is also connected to the TG. There is no data interaction between the two paths; waveform synthesis is only performed on the output side via the TG. During operation, the ALPG provides a cycle configuration set index in each test cycle. The pin data selection path 1 reads the basic data items from the storage module 3 based on this index and completes precoding and gating. At the same time, the pin control data processing path 2 selects the corresponding control signal source according to the register configuration and completes unified delay and allocation. The two paths operate in parallel pipelined mode without blocking each other.

[0055] In at least one possible implementation, please refer to Figure 2 The pin control data processing path 2 specifically includes: The shared multi-tap register chain 21 is used to perform unified delay processing on all selected pin control signals and provide multiple tap outputs with different delay cycle numbers; The signal distribution module 22 is connected to the shared multi-tap register chain 21 and is used to select a set of delayed multi-channel pin control signals from the tap output of the corresponding channel according to the delay period required for each pin, and select the leading edge pin control signal and trailing edge pin control signal of the pin from the set of multi-channel pin control signals and fixed level signals.

[0056] In existing technologies, the control signal (such as CPE / DRE) for each pin is selected from the global control signal source and immediately sent to its own independent delay register chain. When the number of pins is large (e.g., more than 128) and the number of delay cycles is large (e.g., 4 or 8), the register resource consumption is huge (N×P×M). In addition, the delay chain for each pin is independent and cannot be shared, resulting in resource redundancy.

[0057] In this embodiment, by introducing a shared multi-tap register chain 21, the control signals of all pins first pass through the same set of shared delay resources, and then are allocated to each pin as needed. The number of registers is reduced from N×P×M to N×M, resulting in a resource saving ratio of P times.

[0058] In the embodiments of this application, please refer to Figure 6 Each channel selects multiple output pin control signals from the global raw test vector signals (including read command R, write command W, mode signal M1-2, general enable signal E0-7, control signal C0-31, etc.) through combinational logic, such as comparator enable signals CPE1-4 (4 channels in total). The 4 CPE signals output by each channel are concatenated into a 4×WAY_NUM bit-width data (e.g., ...). Figure 6 cpe_dly(0) in the middle), and output in parallel to the shared multi-tap register chain 21.

[0059] After performing unified delay processing on the spliced ​​bus, the shared multi-tap register chain 21 provides multiple tap outputs with different delay cycle numbers. For example, tap 0 corresponds to a 0-cycle delay, tap 1 corresponds to a 1-cycle delay, and so on, with tap M corresponding to an M-cycle delay. Each pin, based on its required delay cycle number (determined by cpe_dly_num in register module 4), retrieves the delayed 4×WAY_NUM bit-width data (e.g., ...) from the corresponding tap in the shared chain through a tap selection MUX. Figure 6 cpe_dly(x) in the middle.

[0060] The signal distribution module 22 can be implemented using a set of tapped selection MUXs. Each pin, through a single selection MUX, independently selects the comparator enable signal for that pin from the delayed CPE1-4 signals, the fixed high-level signal FIXH, and the fixed low-level signal FIXL. Figure 6The leading edge comparator enable signal is pin_cpe_l, and the trailing edge comparator enable signal is pin_cpe_t. The processing logic for the drive enable signal DRE1-2 is the same as that for the comparator enable signal CPE1-4, and will not be described again.

[0061] In a traditional independent delay chain, each pin requires an M-level register, and the number of registers increases linearly when the number of pins is large.

[0062] In this embodiment, a shared multi-tap register chain 21 allows all pins to share a single set of register resources. Each pin obtains an independent number of delay cycles (0-M cycles) by selecting different taps. The total number of registers is N×M. Furthermore, the tap selection MUX allows each pin to still flexibly configure its delay, preserving the flexibility of each pin independently selecting its delay cycle.

[0063] The shared multi-tap register chain 21 in this embodiment can be implemented using M D flip-flops (registers) connected end-to-end. The output of the first-stage register is a 1-cycle delay signal (tap 1), the output of the second-stage register is a 2-cycle delay signal (tap 2), and so on, with the output of the M-stage register being an M-cycle delay signal (tap M). All taps are connected in parallel to the input terminals of the pin selection MUX of the signal distribution module 22. Each pin selects the required tap through its dedicated tap selection MUX (e.g., an M:1 MUX). For example, if a pin requires a 2-cycle delay, its tap selection MUX is configured to select tap 2. The value of M can be set through parameterized configuration according to the maximum required delay period of the device (e.g., M=4, 8, or 16).

[0064] In at least one possible implementation, please continue to refer to Figure 2 The programmable data selector further includes: Storage module 3, whose output is connected to the input of the pin data selection path 1, is used to store several sets of basic data items. Each set of basic data items is pre-configured as a set of pin data selection control words corresponding to the test cycle. Register module 4 is used to receive and store external configuration information, which includes at least pin control configuration information corresponding to the test cycle.

[0065] In existing ATE (Automatic Test Equipment) technologies, pin configuration information for each test cycle is typically stored directly in the instruction memory. This requires storing a large amount of raw data per cycle, resulting in wasted storage resources. Furthermore, the configuration information is tightly coupled with the test process, making it impossible to separate configuration from execution and limiting the flexible implementation of interleave mode.

[0066] In this embodiment, multiple sets of period configuration sets are pre-stored through storage module 3. Each configuration set corresponds to a test cycle. When the test is executed, only the period configuration set index needs to be provided to quickly switch the pin configuration of the entire cycle, which greatly reduces the real-time data transmission bandwidth and supports dynamic switching of test modes for each cycle, thus realizing efficient interleaved testing. External configuration information, such as operation mode enable, delay configuration, and control signal selection, is centrally stored through register module 4, which facilitates dynamic adjustment of test parameters by the software.

[0067] The storage module 3 in this embodiment can be implemented using SRAM. It provides an AXI2SRAM interface externally, allowing the host computer software to write periodic configuration set data via the AXI bus. Internally, it provides a read interface, with the read address being the periodic configuration set index (CYP number) provided by ALPG. The read data bit width matches the total bit width of all pin basic data items. Each periodic configuration set contains the encoded values ​​of all pin basic data items, such as PDS DATA A / B / D / E and address flip selection information AINV ADDR.

[0068] Register module 4 can use the APB interface to allow software to write various configuration information, including but not limited to: operation mode enable (RDSM, PSM, RINV, SMC, DNRZ, AINV, etc.), delay cycle number (exp_dly_num, cpe_dly_num, etc.), control signal source selection (CPE / DRE source selection for each pin), etc.

[0069] In at least one possible implementation, please continue to refer to Figure 2 The pin data selection path 1 specifically includes: The precoding module 11 is used to select a control word set identifier based on the externally input pin data, obtain the encoding value of the basic data item of the pin from the storage module 3, and select a preset number of encoding values ​​as candidate encoding values ​​for the pin from the basic data item based on the pin control configuration information obtained from the register module 4. The gating module 12, cascaded with the precoding module 11, is used to map the candidate encoding value of this pin to the corresponding test vector signal or fixed level signal as pin data output.

[0070] In existing technologies, each pin requires a large MUX to directly select the output from all basic data items (e.g., D=64-128), which can easily lead to an explosion of combinational logic resources. In addition, the relationship between the pre-encoded filtering criteria (test mode configuration signal) and the basic data items is complex, and direct full selection cannot utilize the commonalities between modes for resource reuse.

[0071] In this embodiment, the precoding module 11 dynamically selects a small number (e.g., 2) of candidate encoded values ​​from the basic data items according to the test mode configuration signal, thereby reducing the MUX size of the subsequent gating module 12 from D-to-1 to 2-to-1 or 4-to-1. When D is large, the combinational logic saving ratio is as high as 90% or more. At the same time, the precoding logic is separated from the gating logic, which facilitates parameterized configuration and design reuse.

[0072] The inputs to the precoding module 11 in this embodiment include: the encoded values ​​of the basic data items of this pin (e.g., four encoded values: PDS DATA A, B, D, and E) read from the storage module 3, and the test mode configuration signals (including mode enable signals such as RDSM, PSM, RINV, SMC, DNRZ, and AINV, and their corresponding C0, M2, and C15 signals) obtained from the register module 4. Based on these configuration signals, the precoding module 11 uses combinational logic to select two candidate encoded values ​​from the four basic encoded values, referred to as PORT A and PORT B, respectively. For example, when RDSM is enabled, PDS DATA D and PDS DATA E are used as PORT A and PORT B ​​in the C0 cycle; when PSM is enabled, the switching states between PDS DATA A and PDS DATA B, and between PDS DATA D and PDS DATA E, are set in real time in the M2 cycle. The gating module maps PORT A and PORT B ​​to specific test vector signal lines (such as X0-23, Y0-23, D0-17, etc.) or fixed-level signals (FIXH / FIXL), which serve as the pin data for the final output to the delay module. The mapping relationship can be configured as pass-through or XOR logic through register module 4.

[0073] Please refer to Figure 2 In at least one possible implementation, the pin data selection path 1 further includes: The pin data delay module 13 is cascaded with the gating module 12 to apply a programmable periodic write delay and / or read delay to the gating pin data; The number of cycles for the programmable cycle write delay and / or read delay is determined by the preset delay configuration information in the register module 4.

[0074] In the interface timing requirements of memory chips (such as DDR SDRAM and NAND Flash), write operations and read operations often require different cycle delays (WL / RL). In existing technologies, delay chains are configured independently for the data path of each pin, resulting in register resource consumption increasing linearly with the number of pins.

[0075] Although this embodiment does not employ a shared delay on the pin data selection path 1 (because the data content is different and cannot be shared), it avoids wasting MUX resources through coordination with the preceding pre-encoding-gating module. Specifically, the pin data delay module 13 enables the data path to have independent programmable cycle delay capabilities, meeting the WL / RL requirements of different memory chips. Simultaneously, the delay module itself can be parametrically designed, with the delay cycle number configured by the register module, requiring no hardware modification. After cascading with the pre-encoding module 11 and the gating module 12, the data path forms a complete three-stage pipeline of "pre-encoding → gating → delay," with overall resource consumption significantly lower than traditional solutions.

[0076] The pin data delay module 13 in this embodiment can be implemented using a multi-level register chain and a tap selection MUX. Although similar to the independent delay chain in the prior art, its overall scale is controllable due to the optimization of the preceding MUX. Its input is the pin data output from the gating module (each bit width corresponds to one register chain). The number of delay cycles is configured by the expected data delay (exp_dly_num) and the drive data delay (dvr_dly_num) in the register module. By configuring different delay values, write latency (drive data delay corresponding cycles during write operations) and read latency (expected data delay corresponding cycles during read operations) can be achieved. For example, when WL=2 is required, dvr_dly_num is set to 2, and the drive data is output 2 cycles after the read / write command is issued; when RL=3 is required, exp_dly_num is set to 3, and the expected data is compared with the DUT output 3 cycles after the read command is issued.

[0077] In at least one possible implementation, please continue to refer to Figure 2 The programmable data selector further includes: Real-time data inversion signal generation circuit 5, connected to the input terminal of the precoding module 11, is used to generate real-time data inversion signals for precoding each channel and output them to the precoding module 11; and / or Address bus toggle signal generation circuit 6 is connected to the input terminal of the gating module 12 and is used to generate address bus toggle signals for each channel for precoding and gating, and output to the precoding module 11 and the gating module 12.

[0078] During memory chip testing, it is often necessary to toggle the data bus in real time (e.g., to test the data line reversal function of the memory) or toggle the address bus (to reduce synchronous switching noise and power consumption). In existing technologies, these toggle logics are usually calculated in real time by ALPG when the test vector (pattern) is generated, which increases the complexity of ALPG.

[0079] In this embodiment, by integrating the real-time data toggle signal generation circuit 5 and the address bus toggle signal generation circuit 6 within the PDS, the original test vector signal generated by the ALPG is directly used as input to generate the toggle signal in hardware. This eliminates the need for additional calculations by the ALPG, reducing its burden and improving test efficiency. The RINV signal is output to the precoding module 11 to dynamically reverse the polarity of the driving data or desired data; the ABI signal is output to the gating module 12 to indicate whether the address bus has toggleed in the current cycle, and the gating module 12 adjusts the address signal output accordingly. The two circuits can be enabled independently or operate simultaneously, enhancing test flexibility.

[0080] The inputs to the real-time data toggle signal generation circuit 5 include a read signal (R), a write signal (W), mode signals (M1, M2), control signals (C0-31), and general-purpose enable signals (E0-7). Based on the configuration of register module 4, it selects one of these signals (e.g., toggle occurs when a write command is valid) and outputs the real-time data toggle signal RINV. This signal is connected to precoding module 11, which determines whether to invert the data bit-by-bit based on RINV when generating PORT A / B.

[0081] The address bus toggle signal generation circuit 6 receives the following inputs: address signals (X0-23, Y0-23), read signal R, write signal W, mode signals (M1, M2), control signals (C0-31), and address toggle selection information (AINVADDR) from the storage module 3. The address bus toggle signal generation circuit 6 selects address bits from these signals based on the AINV ADDR encoding value. It then performs a bitwise XOR operation between the selected address bits and a fixed value preset in the register module 4. The number of "1"s in the XOR result is counted. If more than half are present, ABI=1 is output (indicating the address bus needs to be toggleed); otherwise, 0 is output. The ABI signal is connected to the gating module 12, which determines whether to invert the address bus signal before outputting it.

[0082] In at least one possible implementation, the pin data includes expected data and drive data; The pin control signals include comparator enable signals and drive enable signals; The external configuration information also includes an operation mode enable signal, which includes at least one of the following: real-time data exchange mode enable, test vector exchange mode enable, real-time data flip mode enable, exchange mode control enable, dual non-return-to-zero waveform enable, and address flip mode enable. The test vector signal includes at least one of the following: address signal, data signal, read signal, write signal, mode signal, control signal, general enable signal, address bus toggle signal, and parity check signal. The input signal of the real-time data flip signal generation circuit comes from at least one of the following: read signal, write signal, mode signal, and general enable signal; The storage module 3 also stores address toggle selection information. The address bus toggle signal generation circuit 6 is specifically used to select address bits from address signals, read signals, write signals, mode signals and control signals according to the address toggle selection information in the storage module 3, XOR the selected address bits with a fixed value preset in the register module 4, generate an address bus toggle signal according to the number of 1s after XOR, and output it to the precoding module 11 and the gating module 12.

[0083] Compared with the prior art, the embodiments of this application have the following outstanding advantages: At least one embodiment of this application changes the traditional full-parallel data selection mode when selecting pin data. It adopts a serial processing architecture of "pre-encoding → gating → delay", which effectively avoids repeatedly instantiating the full data selector for each pin's PDSDATA A / B / D / E, greatly reducing the number of MUX trees and saving combinational logic resources.

[0084] At least one embodiment of this application changes the traditional parallel delay mode when configuring the delay of pin control data, and adopts an architecture of "select first, delay then reuse". By placing the delay module in front and sharing it, the resource waste of multiple independent delay units is eliminated and register resources are saved.

[0085] At least one implementation method of the embodiments of this application adopts a parameterized implementation method. The number of WAYs, I / O pins, Driver pins, delay cycles, etc. can be modified by parameters or registers, which is highly flexible and applicable to automated testing equipment for memory chips with different technical requirements.

[0086] Based on the above embodiments, this application also provides an automated testing device for memory chips, including a programmable data selector as described in any at least one of the foregoing embodiments.

[0087] In this embodiment, by integrating the PDS described in any at least one of the foregoing embodiments into the complete memory chip ATE, it can be practically applied to the mass production testing of memory chips, giving full play to the advantages of low resources and high flexibility, thereby significantly reducing the overall hardware cost of the ATE (due to the reduction of PDS resources, a smaller FPGA or ASIC can be selected) and dynamic power consumption, while realizing support for higher parallelism (more WAY) and interleaved test modes, and improving test throughput.

[0088] Please refer to Figure 7Based on the above embodiments, this application also provides a data selection method, applied to a programmable data selector in an automated testing equipment for memory chips, including: In step S100, the input basic data items are pre-encoded to obtain the pin dataset corresponding to the output pins. Then, the pin dataset is gating to obtain the output data corresponding to each pin. In step S200, multiple pin control signals are selected from the global control signal source in parallel, and after uniform delay processing, the selected multiple pin control signals are assigned to their respective pins.

[0089] Please refer to Figure 8 In at least one possible implementation, the step of uniformly delaying and allocating the selected multi-pin control signals to their respective corresponding pins specifically includes: In step S101, a multiplexed pin control signal is generated for each channel from the original test pattern signal; In step S102, the multi-pin control signals generated for each channel are uniformly delayed, and multiple tap outputs with different delay period numbers are provided. Each tap output corresponds to a set of delayed multi-pin control signals. In step S103, based on the delay period required for each pin, a set of delayed multi-channel pin control signals is selected from the tap output of the corresponding channel, and the leading edge pin control signal and trailing edge pin control signal of the pin are selected from the set of multi-channel pin control signals and the fixed level signal.

[0090] In at least one possible implementation, please refer to Figure 9 The data selection method in this application embodiment further includes: In step S300, the input basic data items are obtained from several sets of basic data items pre-stored in the storage module 3, and each set of basic data items is configured as a set of pin data selection control words corresponding to the test cycle. In step S400, external configuration information is received and stored through register module 4. The external configuration information includes at least pin control configuration information corresponding to the test cycle.

[0091] In at least one possible implementation, the precoding and gating specifically include: In step S301, a control word set identifier is selected based on the pin data, and the encoded value of the basic data item of this pin is obtained from the storage module 3; In step S201, based on the pin control configuration information obtained from the register module 4, a preset number of encoding values ​​are selected from the basic data items as candidate encoding values ​​for this pin; In step S202, the candidate encoding value of this pin is mapped to the corresponding test vector signal or fixed level signal and output as pin data.

[0092] In at least one possible implementation, it also includes: In step S203, a programmable periodic write delay and / or read delay are applied to the selected pin data; The number of cycles for the programmable cycle write delay and / or read delay is determined by the preset delay configuration information in the register module 4.

[0093] In at least one possible implementation, it also includes: In step S500, a real-time data flip signal for each channel is generated for precoding.

[0094] In at least one possible implementation, it also includes: In step S600, an address bus toggle signal is generated for each channel for precoding and strobing.

[0095] In at least one possible implementation, the storage module 3 further stores address toggle selection information, and the step of generating the address bus toggle signal specifically includes: selecting address bits from address signals, read signals, write signals, mode signals and control signals according to the address toggle selection information in the storage module 3, XORing the selected address bits with a fixed value preset in the register module 4, and generating an address bus toggle signal output according to the number of 1s after XOR.

[0096] Given that the data selection method provided in this application is a method embodiment that corresponds one-to-one with the aforementioned programmable data selector, the technical effects of any implementation described in the aforementioned programmable data selector embodiments can be directly applied to the data selection method in this application, and will not be repeated one by one.

[0097] A specific implementation example of an embodiment of this application is described in detail below.

[0098] This example provides a low-resource, highly flexible programmable data selector and corresponding data selection method for memory chip testing, aiming to solve the problem of excessive resource consumption in traditional test architectures. This example primarily optimizes logic resources by refactoring the two core processes of "pin data selection" and "pin control data processing," employing a hierarchical optimization and resource-sharing strategy.

[0099] First, optimization of the pin data selection function (three-level cascaded optimization strategy).

[0100] This example uses a three-stage serial processing architecture of "precoding → gating → delay" to replace the full parallel selection mode of existing technologies: Pattern precoding (candidate set selection): First, based on the test mode configuration (controllable per pin), for each pin in each WAY, the leading and trailing edge encoded values ​​of the driving data and expected data are pre-selected from the basic pin data items (PDS DATA A / B / D / E) to narrow down the data candidate set; Test vector gating (signal determination): Based on the precoding results above, select the specific test vector signal required for each pin from the narrowed candidate set.

[0101] Apply pin-level delay: Apply pin-level read / write latency to the selected signal to complete the final data output preparation.

[0102] Second, optimization of the pin control data selection function (select first, delay then reuse architecture).

[0103] This example uses a processing flow of "source selection → unified delay → final allocation": Control signal source selection: Prioritize the selection logic of the control signal source for each WAY (including CPE1-4 and DRE1-2) to determine the potential set of control signals.

[0104] Unified delay processing: The possible control signal selection results are uniformly delayed. By placing the delay module at the front, the delay unit can be shared by multiple signal sources.

[0105] Single-pin control data allocation: Based on the delayed signal, the final single-pin control data allocation is performed and output to the specific pin.

[0106] Please refer to Figure 3 This example provides a low-resource, highly flexible programmable data selector and data selection method for memory chip testing, primarily applied in ASIC / FPGA chips of memory chip ATE (Automatic Test Equipment). This module, situated between the ALPG and TG modules, receives configuration commands and source data from the ALPG, generates test vectors conforming to specific timing requirements, and outputs them to the TG module, which then ultimately generates the test waveform. The module design is as follows: Storage Module 3 (MEM): Externally, it provides an AXI2SRAM interface for software to read and write SRAM; internally, it is a read interface for matching pin data item widths. This module stores several sets of basic data items for the pins, each set called a CyclePalette (CYP), including the data selection information for PDS DATA A / B / D / E of all pins, as well as the selection information AINV ADDR for address toggling. The PDS module uses the CYP number (adjustable per WAY per cycle) as the read address to retrieve the pin data items and address toggling selection information.

[0107] Register Module 4 (REG): It provides an APB interface for software to read and write registers. The multiplexing controller module uses this module to receive external configuration information, including PDS operation mode enable, delay period, RINV selection, CPE1-4 selection, DRE1-2 selection, and CPE and DRE selection information for each pin.

[0108] Programmable Data Selection Module (PDS): As the core processing unit for data selection, it contains multiple parallel controller instances, the number of which is determined by the number of WAYs supported by the device, and is parameterized and configurable. Each instantiated module inputs the test vector signal of its current WAY (X0-23, Y0-23, D0-17, SD0-17, C0-31, E0-7, R, W, M1-2, PARI, etc.), and simultaneously inputs various configuration information from register module 4. For example... Figure 4 The diagram illustrates the implementation structure of a WAY programmable data selection logic. This module contains the following functional sub-modules: Real-time data flip signal generation circuit module 5 (RINV) This module is used to generate a real-time invert (RINV) signal for each WAY, with data selected from test vector signals such as R, W, M1-2, C0-31, and E0-7.

[0109] Address bus toggle signal generation circuit 6-module (ABI) This module is used to generate the Address Bus Invert (ABI) signal for each WAY. The address bits are selected from test vector signals such as X0-23, Y0-23, R, W, M1-2, and C0-31 based on the AINV ADDR encoding value. After selection, they are XORed with a preset fixed value in the register module, and the ABI invert signal is generated based on the number of 1s after the XOR.

[0110] Pin data selection path 1 module (Pin data multiplexer(n sets)) This module is used to generate the expected data and drive data for each pin of each WAY. The implementation can be divided into the following three steps: Based on the CYP number, the PDS DATA A / B / D / E encoded values ​​of this pin are obtained from storage module 3. Using the RDSM, PSM, RINV, SMC, DNRZ, and AINV mode enable signals input from register module 4, as well as the corresponding C0, M2, RINV, C15, DNRZ, and ABI signals, two values ​​are selected from PDS DATA A / B / D / E as the PORT A and PORT B ​​encoded values.

[0111] The PORT A and PORT B ​​encoded values ​​of this pin are mapped to the corresponding test vector signals, including X0-23, Y0-23, D0-17, SD0-17, R, W, M1-2, C0-31, ABI, PARI, etc., as PORT A and PORT B ​​signals.

[0112] The leading edge drive data and trailing edge drive data correspond to PORT A and PORT B ​​signals, respectively, while the leading edge expected data and trailing edge expected data are selected from FIXL, FIXH, PORT A, and PORT B ​​signals.

[0113] Pin control data processing path 2 module (Pin control data multiplexer) This module is used to generate control signals for this WAY, including CPE1-4 and DRE1-2, and the data is selected from the test vector signals such as R, W, M1-2, C0-31, and E0-7 of this WAY.

[0114] Compared to the traditional method of repeatedly instantiating the full data selector for each PDS DATA A / B / D / E pin, this example uses a method of filtering out the encoded value first and then using the full data selector, which reduces the use of MUX combinational logic by about half.

[0115] Delay module (DELAY) The delay module is used to add programmable delays to pin data and pin control data, such as the comparator enable leading edge selection signal cpe_l_sel, the comparator enable trailing edge selection signal cpe_t_sel, the driver enable leading edge selection signal dre_l_sel, and the driver enable trailing edge selection signal dre_t_sel, to implement WL / RL. This module includes the following two sub-modules, as follows: Pin data delay module 13 Taking the expected data delay as an example (the logic driving the data delay is exactly the same), the structure is as follows: Figure 5 As shown. The expected data exp_data of all WAYs of a certain pin output by the PDS module is delayed for n cycles through a multi-level flip-flop (Flip-Flop, FF) (exp_dly(1) → exp_dly(n-1) → exp_dly(n+1)) (n is a configurable parameter); the delay data corresponding to the number of cycles is selected according to the value of exp_dly_num (0-n) input by register module 4, and finally the expected data pin_exp_data of the number of pins per channel x pin_num is output to the TG module.

[0116] Pin-controlled data delay module Taking comparator enable data delay as an example (the driver enable delay logic is exactly the same), the structure is as follows: Figure 6 As shown. First, all CPE1-4 of the WAY output from the PDS module are concatenated from low to high according to the WAY number, and then a multi-stage flip-flop is used to perform an M-cycle delay (M is a configurable parameter). Based on the cpe_dly_num value (which ranges from 0 to M) input from register module 4, the corresponding delay data for the number of cycles is selected; finally, based on the CPE leading and trailing edge selection signals, the leading and trailing edge comparator enable data for all WAYs of that pin is selected from the delay data and output to TG.

[0117] The interface signals between PDS and TG include: PDS data valid signal pds_vld, PDS last data indication signal pds_last, PDS drive data pds_dr_data, PDS expected data pds_exp_data, PDS drive enable signal pds_dre_data, and PDS comparator enable signal pds_cpe_data.

[0118] Unlike existing technologies where control data for each pin is selected first and then delayed, this example places the delay module in the front and shares it globally, completely eliminating the waste of resources from multiple independent delay units and significantly reducing the amount of register resources used.

[0119] This application also provides a computer program product, which includes computer program code that, when run on a computer, causes the computer to perform the steps of the method in any of the possible implementations of the foregoing embodiments.

[0120] Those skilled in the art will recognize that the functions described in the embodiments of this application in one or more of the above examples can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0121] Note that the above are merely preferred embodiments and the technical principles employed in this application. Those skilled in the art will understand that this application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of this application, the scope of which is determined by the scope of the appended claims.

Claims

1. A programmable data selector, applied in automated testing equipment for memory chips, characterized in that, The programmable data selector includes: The pin data selection path is used to pre-encode the basic data items of the input terminal, obtain the pin dataset corresponding to the output terminal pin, and then select the pin dataset to obtain the output data corresponding to each pin. The pin control data processing path is set in parallel with the pin data selection path. It is used to select multiple pin control signals from the global control signal source, and after performing unified delay processing on the selected multiple pin control signals, it is assigned to their respective corresponding pins. The pin control data processing path includes: A shared multi-tap register chain is used to perform unified delay processing on the selected multiple pin control signals and provide multiple tap outputs with different delay cycle numbers; The signal distribution module, connected to the shared multi-tap register chain, is used to select a set of delayed multi-channel pin control signals from the tap output of the corresponding channel according to the delay period required for each pin, and select the leading edge pin control signal and trailing edge pin control signal of the pin from the set of multi-channel pin control signals and the fixed level signal. The pin data selection path specifically includes: The precoding module is used to select a control word set identifier based on the externally input pin data, obtain the encoding value of the basic data item of this pin, and select a preset number of encoding values ​​as candidate encoding values ​​for this pin from the basic data item according to the pin control configuration information. The gating module, cascaded with the precoding module, is used to map the candidate encoded value of this pin to the corresponding test vector signal or fixed level signal as pin data output.

2. The programmable data selector according to claim 1, characterized in that, The programmable data selector further includes: The storage module, whose output is connected to the input of the pin data selection path, is used to store several sets of basic data items. Each set of basic data items is pre-configured as a set of pin data selection control words corresponding to the test cycle. The register module is used to receive and store external configuration information, which includes at least pin control configuration information corresponding to the test cycle.

3. The programmable data selector according to claim 2, characterized in that, The pin data selection path also includes: A pin data delay module, cascaded with the gating module, applies a programmable periodic write delay and / or read delay to the selected pin data; The number of cycles for the programmable cycle write delay and / or read delay is determined by the preset delay configuration information in the register module.

4. The programmable data selector according to claim 3, characterized in that, The programmable data selector also includes: A real-time data flip signal generation circuit is connected to the input terminal of the precoding module to generate a real-time data flip signal for each channel for precoding and output it to the precoding module. and / or The address bus toggle signal generation circuit is connected to the input terminals of the precoding module and the gating module, and is used to generate address bus toggle signals for each channel for precoding and gating, and output them to the precoding module and the gating module.

5. The programmable data selector according to claim 4, characterized in that: The pin data includes expected data and drive data; The pin control signals include comparator enable signals and drive enable signals; The external configuration information also includes an operation mode enable signal, which includes at least one of the following: real-time data exchange mode enable, test vector exchange mode enable, real-time data flip mode enable, exchange mode control enable, dual non-return-to-zero waveform enable, and address flip mode enable. The test vector signal includes at least one of the following: address signal, data signal, read signal, write signal, mode signal, control signal, general enable signal, address bus toggle signal, and parity check signal. The input signal of the real-time data flip signal generation circuit comes from at least one of the following: read signal, write signal, mode signal, control signal, and general enable signal; The storage module also stores address toggle selection information. The address bus toggle signal generation circuit is specifically used to select address bits from address signals, read signals, write signals, mode signals and control signals according to the address toggle selection information in the storage module, XOR the selected address bits with a fixed value preset in the register module, generate an address bus toggle signal according to the number of 1s after XOR, and output it to the precoding module and the gating module.

6. An automated testing device for memory chips, characterized in that, Includes the programmable data selector as described in any one of claims 1-5.

7. A data selection method, applied to a programmable data selector in an automated testing equipment for memory chips, characterized in that, include: After pre-encoding the input basic data items to obtain the pin dataset corresponding to the output pin, the pin dataset is gating to obtain the output data corresponding to each pin. In parallel, multiple pin control signals are selected from the global control signal source, and after uniform delay processing, the selected multiple pin control signals are assigned to their respective corresponding pins; Specifically, the step of selecting multiple pin control signals from a global control signal source, performing uniform delay processing on the selected multiple pin control signals, and then assigning them to their respective corresponding pins includes: Generate multiple pin control signals for each channel from the original test pattern signal; The multi-pin control signals generated for each channel will be uniformly delayed, and multiple tap outputs with different delay period numbers will be provided. Each tap output corresponds to a set of delayed multi-pin control signals. Based on the required delay period for each pin, select a set of delayed multi-channel pin control signals from the tap output of the corresponding channel, and select the leading edge pin control signal and trailing edge pin control signal for that pin from the set of multi-channel pin control signals and the fixed level signal. The process of pre-encoding the input basic data items to obtain the pin dataset corresponding to the output pins, and then gating the pin dataset to obtain the output data corresponding to each pin, specifically includes: Select the control word set identifier based on the pin data, and obtain the encoded value of the basic data item of this pin from the storage module; Based on the pin control configuration information obtained from the register module, a preset number of encoding values ​​are selected from the basic data items as candidate encoding values ​​for this pin; The candidate encoded value of this pin is mapped to the corresponding test vector signal or fixed level signal and used as the pin data output.

8. The data selection method according to claim 7, characterized in that, Also includes: The input basic data items are obtained from several sets of basic data items pre-stored in the storage module, and each set of basic data items is configured as a set of pin data selection control words corresponding to the test cycle; The register module receives and stores external configuration information, which includes at least pin control configuration information corresponding to the test cycle.

9. The data selection method according to claim 8, characterized in that, Also includes: Apply programmable periodic write and / or read delays to the selected pin data; The number of cycles for the programmable cycle write delay and / or read delay is determined by the preset delay configuration information in the register module.

10. The data selection method according to claim 9, characterized in that, Also includes: Generate a real-time data toggle signal for each channel for precoding; and / or Generate address bus toggle signals for each channel for precoding and strobing.

11. The data selection method according to claim 10, characterized in that: The pin data includes expected data and drive data; The pin control signals include comparator enable signals and drive enable signals; The test vector signal includes at least one of the following: address signal, data signal, read signal, write signal, mode signal, control signal, general enable signal, address bus toggle signal, and parity check signal. The input signal of the real-time data flip signal generation circuit comes from at least one of the following: read signal, write signal, mode signal, control signal, and general enable signal; The storage module also stores address toggle selection information. The specific steps for generating the address bus toggle signal include: selecting address bits from address signals, read signals, write signals, mode signals and control signals according to the address toggle selection information in the storage module; XORing the selected address bits with a fixed value preset in the register module; and generating an address bus toggle signal output based on the number of 1s after XORing.

12. A computer program product, characterized in that, The computer program product includes: computer program code, which, when run on a computer, causes the computer to perform the steps of the data selection method as described in any one of claims 7-11.

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