Solid state drive burn-in test method, apparatus, and storage medium

Abstract

The application discloses a solid state disk aging test method, equipment and storage medium, the method comprises the following steps: based on file access heat, the logical space of the solid state disk is divided into hot data area, warm data area and cold data area; the probe block of storing known data mode is set in the hard disk; the read voltage scanning is executed to the probe block, the voltage-bit error rate characteristic curve is generated and the sensitive voltage offset interval is identified; the interval is taken as the main disturbance direction, the adaptive read voltage disturbance of the negative offset is mainly applied to the hot data area and / or the warm data area, and the charge leakage effect is simulated; the bit error rate is obtained by reading the probe block in real time during the disturbance process, and the read voltage offset is dynamically adjusted as the closed-loop feedback; the equivalent storage time is calculated according to the real-time acquisition data and the temperature history accumulation, and the aging evaluation result is obtained. The application can efficiently expose the data retention defects, realize the quantifiable aging evaluation, and is suitable for the solid state disk reliability test field.

Description

Technical Field

[0001] This application relates to the field of solid-state drive reliability testing technology, and in particular to a solid-state drive aging test method, equipment and storage medium. Background Technology

[0002] Solid-state drives (SSDs) have become the mainstream storage devices in data centers and consumer electronics due to their advantages such as high-speed read / write speeds, low power consumption, and strong shock resistance. However, as NAND flash memory technology continues to shrink and storage density continues to increase (from SLC to MLC, TLC, and even QLC), the oxide layer of flash memory cells becomes thinner, and their charge retention capability decreases significantly. This makes flash memory cells more susceptible to various types of device and circuit-level noise. Therefore, the long-term reliability of SSDs, especially their data retention capability, is crucial for ensuring data security.

[0003] Retention errors, caused by the leakage of charge within memory cells over time, are a primary source of flash memory errors. As the number of program / erase (P / E) cycles increases, holes form in the oxide layer, causing stored electrons to escape and resulting in a threshold voltage drift. The read reference voltage of a flash memory cell systematically changes with its retention age (time elapsed since programming). Different regions of flash memory may have different retention ages and therefore different optimal read reference voltages. When the threshold voltage deviation of a memory cell exceeds the read voltage threshold, a data error occurs.

[0004] Existing aging test methods have the following shortcomings: First, it lacks application-layer semantics. Test loads are mostly full-disk sequential or random read / write operations, failing to simulate the hot / cold point distribution of file access and the frequent metadata updates characteristic of real-world scenarios. Traditional simple reliability tests for read interference and data retention cannot provide the same threshold voltage offset and memory cell error results as actual use. This leads to poor correlation between test results and field failure modes.

[0005] Second, the efficiency of data retention in exposing defects is low. Static high-temperature baking or simple random writing is insufficient to fully stimulate slow degradation effects such as charge leakage and read interference within a limited period. Conventional read retry mechanisms only adjust the read voltage during passive error correction, failing to utilize voltage disturbances as an active means to accelerate testing.

[0006] Third, aging assessment lacks a quantitative time benchmark. Existing accelerated aging methods (such as increasing temperature) struggle to establish a quantitative mapping relationship between the stress during accelerated testing and the equivalent actual storage time, making it difficult to extrapolate test results to real-world long-term storage scenarios.

[0007] Fourth, there is a lack of correlation between temperature history and aging process. Most tests did not systematically collect and analyze the temperature history of SSDs during actual testing, failing to incorporate the cumulative temperature effect into the aging assessment system, resulting in discrepancies between the assessment results and the actual aging state. Summary of the Invention

[0008] In view of this, this application provides a solid-state drive aging test method, device and storage medium to solve the above problems.

[0009] To solve the above-mentioned technical problems, this application adopts the following technical solution: providing a solid-state drive aging test method, including the following steps: Based on the monitoring results of file access frequency, the logical space of the solid-state drive under test is divided into hot data area, warm data area and cold data area. Set up at least one probe block in the solid-state drive, and the probe block stores a known data pattern; Perform a voltage scan on the probe block to generate a voltage-bit error rate characteristic curve, and identify the voltage offset interval that is sensitive to changes in bit error rate based on the characteristic curve; With the sensitive voltage offset range as the main perturbation direction, a dynamic closed-loop adaptive read voltage perturbation is applied to the hot data region and / or warm data region. The perturbation is mainly negative offset to simulate the charge leakage effect. During the adaptive read voltage disturbance process, the probe block is read in real time to obtain its bit error rate; The bit error rate of the probe block is used as closed-loop feedback to dynamically adjust the offset of the read voltage. Based on the real-time data collected during the adaptive read voltage disturbance process and the temperature history of the solid-state drive (SSD), the equivalent storage time of the SSD is calculated cumulatively, and the aging assessment result of the SSD is obtained based on the real-time data collected and the equivalent storage time.

[0010] To solve the above-mentioned technical problems, another technical solution adopted in this application is: to provide a solid-state drive aging test device, comprising: The partitioning module is used to divide the logical space of the solid-state drive under test into hot data area, warm data area and cold data area based on the monitoring results of file access popularity. The configuration module is used to configure at least one probe block in the solid-state drive, and the probe block stores a known data pattern. The scanning module is used to perform a voltage scan on the probe block, generate a voltage-bit error rate characteristic curve, and identify voltage offset intervals that are sensitive to changes in bit error rate based on the characteristic curve. The perturbation module is used to apply a dynamic closed-loop adaptive read voltage perturbation to the hot data area and / or warm data area with the sensitive voltage offset range as the main perturbation direction. The perturbation is mainly negative offset to simulate the charge leakage effect. The reading module is used to read the probe block in real time and obtain its bit error rate during adaptive reading voltage disturbance. The adjustment module is used to dynamically adjust the offset of the read voltage using the bit error rate of the probe block as closed-loop feedback. The output module is used to calculate the equivalent storage time of the solid-state drive based on the real-time data collected during the adaptive read voltage disturbance process and the temperature history of the solid-state drive, and to obtain the aging evaluation result of the solid-state drive based on the real-time data collected and the equivalent storage time.

[0011] To solve the above-mentioned technical problems, another technical solution adopted in this application is: to provide a computer device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor executes the program to implement the solid-state drive aging test method as described above.

[0012] To solve the above-mentioned technical problems, another technical solution adopted in this application is: to provide a computer-readable storage medium having a computer program stored thereon, wherein the program, when executed by a processor, implements the solid-state drive aging test method as described above.

[0013] Compared to existing technologies, this invention overcomes the problem of poor correlation between traditional full-disk sequential or random read / write tests and actual failure modes by using file-level semantic monitoring and differentiated data distribution to achieve test loads that closely resemble real-world application scenarios. This makes the test results highly correlated with actual failure modes in the field. Through adaptive voltage closed-loop perturbation primarily using negative offset, it actively simulates charge leakage effects, which can more efficiently expose data retention defects compared to fixed voltage bias. By dynamically adjusting the read voltage offset based on the probe block bit error rate using closed-loop feedback, the test process can adaptively explore the optimal voltage offset range, avoiding exceeding the ECC error correction capability range and achieving a balance between accelerated aging and data integrity protection. By accumulating and calculating equivalent storage time and combining it with temperature history, a quantifiable aging assessment time benchmark is established, allowing test results to be extrapolated to actual long-term storage scenarios, providing a scientific basis for solid-state drive reliability assessment. Attached Figure Description

[0014] Figure 1 This is a flowchart illustrating one embodiment of the solid-state drive aging test method of the present invention.

[0015] Figure 2 This is a functional module diagram of one embodiment of the solid-state drive aging test device of the present invention.

[0016] Figure 3 This is a schematic diagram of the structure of a computer device according to an embodiment of the present invention.

[0017] Figure 4This is a schematic diagram of the structure of a computer-readable storage medium according to an embodiment of the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0019] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0020] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0021] Figure 1 This is a flowchart illustrating the solid-state drive aging test method according to an embodiment of the present invention. It should be noted that if substantially the same results are obtained, the method in this embodiment is not necessarily identical. Figure 1 The illustrated process sequence is limited. For example... Figure 1 As shown, the solid-state drive aging test method includes the following steps: Step S1: Based on the monitoring results of file access popularity, the logical space of the solid-state drive under test is divided into hot data area, warm data area and cold data area.

[0022] Specifically, install an operating system on the SSD under test and partition the entire disk into a single partition. Deploy at least three types of typical applications: databases (such as MySQL and PostgreSQL), browsers and office software (such as Chrome and WPS Office), and build environments (such as GCC and CMake). Write automated scripts to simulate real user behavior. The scripts should include operations such as database read / write transactions, web browsing, document editing and saving, and code compilation, and run continuously for at least 30 minutes to accumulate sufficient file access statistics.

[0023] The operating system's file system monitoring interface (Windows ETW / Minifilter, Linux fanotify) is used to record all file access paths, access frequencies, and read / write sizes in real time. A list of hot files is generated every 10 minutes, sorted by access frequency. Based on file popularity, the logical space of the SSD under test is divided into three regions: a hot data region (approximately 30% of the logical capacity) for storing the original content of frequently accessed hot files and file system metadata (including directory entries, inode tables, etc.); a warm data region (approximately 40%) for storing semi-structured data accessed in a medium-frequency manner; and a cold data region (approximately 30%) for storing static verification benchmark data. An independent partition (or separate namespace) is created in the cold data region, formatted as an independent file system, and a full partition TRIM (NVMe format or blkdiscard) is performed before writing a known fixed data pattern (all 0x55 or pseudo-random sequence). The checksum (SHA256) is then calculated and saved.

[0024] Furthermore, an "Instructions to not perform garbage collection" message is sent to the cold data area via NVMe Dataset Management commands (Non-rotating medium, Sequential write hint), and it is recorded whether this message is actually adopted by the firmware (indirectly determined by reading garbage collection-related counters in SMART). If the message is found to be ignored, it is noted in the final report that "the cold data area may be affected by GC interference".

[0025] Furthermore, environmental parameters are monitored by reading the power management chip and temperature sensor via SMBus / I²C: the temperature range is -10~85℃ (covering the test stress range and safety boundaries), and the monitoring is based on the SSD's nominal voltage (e.g., 3.3V or 12V). The allowable voltage fluctuation range is ±10%, and the temperature fluctuation does not exceed 0.5℃ / min. When environmental parameters exceed the threshold, an alarm is triggered and the test is paused.

[0026] Furthermore, optimize the operating system: disable Windows SuperFetch and Linux read-ahead functionality to avoid interference from read-ahead operations on cold data verification.

[0027] Step S2: Set up at least one probe block in the solid-state drive, the probe block storing known data patterns.

[0028] Specifically, probe blocks are arranged at a preset density in the hot data area, warm data area, and cold data area. One 4KB probe is embedded every 20GB of logical capacity in the hot and warm data areas, and one 4KB probe is embedded every 100GB in the cold data area (density reduced, read interval extended to 60 seconds to minimize read interference). Probe blocks are stored as hidden files (e.g., .probe_block_xxxx) and set to read-only. Each probe block stores a known pseudo-random sequence (e.g., PRBS-31), records its starting logical block address and original data, and is used for subsequent accurate calculation of the bit error rate.

[0029] Before starting the stress test, exclude all hidden files corresponding to probe blocks by using file system filtering drivers or the file / path exclusion function of the stress tool (such as fio's --exclude parameter or --directory to limit the working directory), ensuring that probe block data is not overwritten. If using a custom stress script, check whether the LBA range contains the probe block address before writing and skip it.

[0030] Step S3: Perform a voltage scan on the probe block to generate a voltage-bit error rate characteristic curve, and identify the voltage offset interval that is sensitive to changes in bit error rate based on the characteristic curve.

[0031] Specifically, a voltage scan is performed on the cold data area and the selected probe block: at the nominal read decision voltage Within the range of -12% to +5% (with the main direction being negative, simulating charge leakage), the voltage offset is incremented in coarse steps of 20mV. It should be noted that all voltage offset percentages are relative to the nominal read decision voltage (in mV) defined by the NAND flash memory manufacturer. At each offset point, a probe block is read, the bit error rate is calculated, and a voltage-bit error rate characteristic curve is generated. The negative offset range with the largest rate of change in bit error rate (e.g., -8% to -4%) is identified as the sensitive voltage offset range.

[0032] The optimal read reference voltage of a flash memory cell changes systematically with its retention age. Flash memory in different regions may have different retention ages and different optimal read reference voltages. By identifying sensitive regions through voltage scanning, the voltage offset range most prone to triggering errors can be accurately located, providing a basis for subsequent adaptive perturbation.

[0033] Step S4: Apply a dynamic closed-loop adaptive read voltage perturbation to the hot data region and / or warm data region with the sensitive voltage offset range as the main perturbation direction. The perturbation is mainly negative offset to simulate the charge leakage effect.

[0034] Specifically, using the identified sensitive voltage offset range as the primary perturbation direction, a dynamic closed-loop adaptive read voltage perturbation is applied to the hot and warm data regions. The perturbation is predominantly negative, as data retention errors are caused by charge leakage over time, which leads to a negative drift in the threshold voltage of the memory cell. Therefore, by actively shifting the read voltage negatively, the simulation of charge leakage effects can be accelerated, effectively exposing data retention defects.

[0035] Different perturbation strategies are adopted for different regions: the offset range of the hot data region is -10% to +3%, with a step size of 5mV in the sensitive region and 15mV in the non-sensitive region. The initial adjustment interval is 2 seconds, which can be dynamically adjusted between 1 and 8 seconds according to the bit error rate change rate; the offset range of the warm data region is -8% to +2%, with a fixed step size of 10mV and a fixed interval of 4 seconds; the cold data region adopts a fixed offset of -3% and does not perform dynamic scanning to minimize read interference.

[0036] The actual perturbation range of each region is a subset of the aforementioned scanning range (-12% to +5%). If the identified sensitive interval exceeds the perturbation range of a certain region, then within that region, we can only approach its boundary; this is a reasonable trade-off for a conservative strategy.

[0037] Furthermore, different heat regions use independent feature curves and perturbation strategies. Hot data regions can accept more aggressive negative perturbations, while cold data regions are more conservative. This is semantic-aware linkage.

[0038] Step S5: During the adaptive reading voltage disturbance process, read the probe block in real time and obtain its bit error rate.

[0039] Specifically, during the adaptive read voltage disturbance process, each probe block is periodically read at a preset frequency to calculate the raw bit error rate (RBER). The RBER is the most direct and core health indicator reflecting the data retention status of NAND flash memory.

[0040] Step S6: Use the bit error rate of the probe block as closed-loop feedback to dynamically adjust the offset of the read voltage.

[0041] Specifically, the bit error rate (BER) of the probe block is used as a closed-loop feedback signal to dynamically adjust the offset of the read voltage. When the BER of the probe block shows an upward trend, it indicates that the current voltage offset is effectively stimulating the charge leakage effect, and the offset can be maintained or appropriately increased to accelerate aging exposure. When the rate of change of the BER slows down, the adjustment interval can be appropriately extended. When the BER exceeds the preset backoff BER threshold, the voltage backoff mechanism is triggered. This closed-loop control strategy enables the testing process to adaptively explore the most effective voltage offset range while avoiding data loss due to exceeding the error correction code's capability.

[0042] Dynamic interval adjustment rules (applicable only to hot data areas; warm / cold data areas are excluded): If the change rate of the probe block correction bit error rate is <5% for two consecutive times, the interval is increased (maximum 8 seconds); if the change rate of the bit error rate is >20%, the interval is shortened (minimum 1 second). The change rate is defined as: ; in, Indicates the rate of change. This indicates the bit error rate read at the current moment. This indicates the bit error rate of the most recent historical read. If This can be directly considered as a rate of change of 0.

[0043] Step S7: Based on the real-time data collected during the adaptive read voltage disturbance process and the temperature history of the solid-state drive, calculate the equivalent storage time of the solid-state drive, and obtain the aging assessment result of the solid-state drive based on the real-time data collected and the equivalent storage time.

[0044] Specifically, based on the real-time data collected during the adaptive read voltage disturbance process, such as the probe block bit error rate, voltage offset, and number of read retry attempts, as well as the temperature history of the solid-state drive, the equivalent storage time is calculated cumulatively, and the aging assessment result of the solid-state drive is obtained comprehensively.

[0045] The equivalent storage time is calculated using a piecewise cumulative Arrhenius model: the time axis is divided into sufficiently small intervals (e.g., every 1 minute), and the temperature within each interval is... Take the average temperature of the SMART chip during this time period, duration The interval length. The equivalent storage time increment within this interval. for: ; in, The activation energy is 1.0 eV. Boltzmann's constant, At room temperature (take 25℃ = 298K). For the first Chip temperature within a time interval, The duration of the interval.

[0046] Total equivalent time obtained ,in This represents the total number of intervals. All temperatures T in the model refer to the internal temperature of the NAND chip (preferably using the chip temperature reported by SMART); if the chip temperature cannot be obtained, the SSD case temperature will be used with thermal resistance correction, and the approximation method will be noted in the report. It is strictly forbidden to use ambient chamber temperature or case temperature instead of chip temperature.

[0047] The evaluation results include the error rate distribution of each data area, the equivalent storage time-error rate curve, and failure mode determination.

[0048] The calibration process for the equivalent storage time model is as follows: The model uses thermal acceleration (temperature) as the main accelerating factor and is based on the Arrhenius equation; the reading voltage offset is used as an observation indicator of equivalent aging, rather than a direct input.

[0049] For the NAND flash memory models of the SSDs under test, calibration was performed according to wear cycles (P / E cycle ranges: 0~500, 500~1500, 1500~3000, 3000~5000). Experimental conditions: Temperature stress was set at 50℃, 70℃, and 85℃. After writing fixed data to each sample, it was baked at the corresponding temperature for different times (1, 3, 7, 14, and 30 days).

[0050] After baking, read the voltage at room temperature (25°C) and measure the negative offset of the read voltage required to reach the target reference RBER. .

[0051] Target reference RBER selection: It is recommended to use the industry-typical default value, and SLC should be selected. MLC take TLC QLC take If the RBER threshold for the first read retry triggered by the SSD controller is known, this value can also be used. If the NAND type cannot be determined, the default value is used. .

[0052] Calibration procedure: For each group (wear level, temperature, baking time), the reading starts from the nominal voltage and gradually shifts negatively (in 5mV steps). After each shift, the probe block is read and the RBER is calculated. When the RBER first falls below or equals the target reference RBER, the current shift is recorded. If the offset to the limit (e.g., -15%) is still not reached, then record... This is the limit value, and it should be marked "Not Reached" in the report. Record the following parameters: wear level, temperature T, and baking time. , .

[0053] Model establishment: The thermal acceleration factor is based on the Arrhenius formula: ; in, The experimental temperature (unit: Kelvin).

[0054] For a given wear level, establish a target reference RBER. With equivalent storage time Lookup table: .

[0055] In actual testing, when it is necessary to query the equivalent time corresponding to a certain voltage offset, an interpolation method is used. In actual testing, the equivalent time under that wear state is first obtained by interpolation based on the current wear count P. Then use this The value is retrieved from a lookup table to obtain the corresponding equivalent storage time. Interpolation of the wear count: Assume the current wear count P falls within the gear range. Inside, corresponding The values ​​are respectively and Then linear interpolation is obtained. If P exceeds the maximum gear, then the maximum gear will be used. The values ​​are labeled "extrapolation". This model supports bidirectional interpolation within monotonic intervals.

[0056] It should be noted that this model is an engineering approximation based on limited experimental data, used for relative comparisons between different stress schemes and for determining test termination; it does not represent absolute physical time. The report must clearly specify the specific conditions and error range of the calibration experiment.

[0057] Furthermore, the operating system page file can be placed on a separate small-capacity SSD or RAM disk (to avoid interference), or placed on the target SSD to simulate real resource contention. If placed on the target SSD, its LBA range is added to the mapping table and treated as hot data. This configuration can be enabled or disabled based on actual testing needs.

[0058] This embodiment utilizes file-level semantic monitoring and differentiated data distribution to simulate real-world application scenarios, overcoming the poor correlation between traditional full-disk sequential or random read / write tests and actual failure modes. This ensures test results are highly correlated with field failure modes. By employing adaptive voltage closed-loop perturbation primarily based on negative offset, it actively simulates charge leakage effects, more efficiently exposing data retention defects compared to fixed voltage bias. Through dynamic adjustment of the read voltage offset using probe block bit error rate as closed-loop feedback, the test process adaptively explores the optimal voltage offset range, avoiding exceeding the ECC error correction capability and achieving a balance between accelerated aging and data integrity protection. By accumulating equivalent storage time and combining it with temperature history, a quantifiable aging assessment time benchmark is established, allowing test results to be extrapolated to actual long-term storage scenarios, providing a scientific basis for SSD reliability assessment.

[0059] Furthermore, in some embodiments, step S1 specifically includes: 1. Monitor file access operations at the operating system level to identify hot and cold files.

[0060] Specifically, all file I / O operations are captured in real time using the file system monitoring interface provided by the operating system. On Windows platforms, ETW (Event Tracing for Windows) or the Minifilter driver can be used; on Linux platforms, the fanotify (File System Notification) interface can be used. Monitoring content includes: file path, access type (read / write), access size, and access timestamp. All monitoring data is written to a circular buffer, and statistical results are summarized every 10 minutes.

[0061] Based on access statistics over a period of time (e.g., the last hour), files are sorted by access frequency. The top 30% of files with the highest access frequency are marked as hot files (e.g., database transaction logs, index files, browser cache, etc.), the bottom 30% of files with the lowest access frequency are marked as cold files (e.g., archived data, backup files, etc.), and the rest are lukewarm files.

[0062] Furthermore, the dynamic updating of the hot file list is based on the continuous accumulation of access statistics (frequency, read / write size) recorded in file access operations. Every 10 minutes, a new hot file list is recalculated and generated based on statistical data from the past period (e.g., the last hour). This process is memory-based, requiring no file system scanning and thus offering high execution efficiency. If a file appears in the new list that was not previously in the mapping table, its LBA range is obtained by calling the file system interface and added to the mapping table.

[0063] 2. Based on file popularity, the logical space of the solid-state drive under test is divided into a hot data area, a warm data area, and a cold data area. The hot data area is used to store high-frequency access data, the cold data area is used to store static verification benchmark data, and the warm data area is used to store medium-frequency access data.

[0064] Specifically, the hot data area is used to store frequently accessed data, including database log files, data files, browser cache directories, and temporary files from office software. These files are frequently read and written in actual use, and the flash memory blocks they reside in are subjected to high programming / erase cycle stress, resulting in a faster aging rate.

[0065] The cold data area is used to store static verification benchmark data. It is written with a known fixed data pattern (all 0x55 or pseudo-random sequence), and the SHA256 checksum is calculated and saved. During the test, the cold data area is not subjected to active read / write pressure. It is only periodically read from probe blocks for monitoring to maintain a clean benchmark state for final verification.

[0066] The warm data area is used to store intermediate frequency access data. A pseudo-random semi-structured data file (approximately 1GB per file) is generated in the newly created directory, and the content simulates user data.

[0067] 3. Construct and dynamically maintain a mapping table from logical addresses to file paths.

[0068] Specifically, the current logical block address (LBA) range for each file is obtained through the file system retrieval pointer interface. On Windows, FSCTL_GET_RETRIEVAL_POINTERS is used, and on Linux, FIEMAP is used. The mapping table is stored in SQLite or JSON format and contains fields such as: file path, starting LBA, ending LBA (or a list of LBA ranges), popularity level, and last update timestamp.

[0069] Dynamic maintenance of the mapping table is achieved by monitoring file modification, renaming, and deletion events through the file system monitoring interface. The LBA range of a file is re-acquired and the mapping table is updated only when the file content is rewritten, causing a change in the LBA range. During testing, the operating system's automatic defragmentation and TRIM automatic reclamation functions are disabled to maintain the accuracy of the mapping table.

[0070] This embodiment achieves precise mapping from upper-level file semantics to lower-level physical addresses through accurate monitoring of file access frequency and dynamic maintenance of the mapping table, providing a data foundation for subsequent error tracking and fault location.

[0071] Furthermore, data errors are inevitable during the long-term use of solid-state drives (SSDs). However, traditional testing methods can only report the logical block address where the error occurred, failing to associate the error with the specific file at the upper level. This makes it difficult for testers to determine the type of data corresponding to the error (database logs, user documents, or system files), let alone optimize firmware strategies or adjust the data layout of the storage system accordingly. Therefore, some embodiments also include error tracing steps: 1. When a disk error is detected, extract the logical address of the fault.

[0072] Specifically, continuously monitor disk hardware error events in the operating system logs. On the Windows platform, monitor Event ID 153 (disk error) and Event ID 7 (device error); on the Linux platform, monitor I / O error information in dmesg. Simultaneously monitor error status in the NVMe command completion queue, including error codes in the command completion status field.

[0073] When an error is detected, a reverse tracing script is immediately triggered to parse and extract the fault logic block address (LBA) from the error log.

[0074] 2. By querying the mapping table, the fault is located to a specific file, and the error is used as the source of analysis data for the fault correlation graph in the aging assessment results.

[0075] Specifically, the file path to which the LBA belongs is searched in the semantic-LBA mapping table. Since files may not be stored contiguously (file fragmentation exists), one LBA may correspond to multiple file ranges; in this case, all matching results are returned.

[0076] If the SSD manufacturer provides a real-time physical address lookup interface, this interface can be used to convert LBAs into physical coordinates (Channel, Die, Plane, Block). Since garbage collection and wear leveling may alter the mapping, these coordinates only represent an approximate location at the moment of the query; the report must clearly indicate the "approximate coordinates" and the query timestamp. If the firmware supports this, it is recommended to temporarily reduce the frequency of proactive garbage collection (rather than completely freezing GC) to avoid sudden drops in write performance or controller protection; this operation should be noted in the report. If GC behavior cannot be modified, accept the coordinate drift as a reflection of normal firmware behavior.

[0077] Record the following information into the fault correlation graph database (SQLite format): timestamp, fault LBA, file path (first-level location result), physical coordinates (if available), current voltage offset, current temperature (SMART chip temperature), cumulative equivalent storage time at the time of fault occurrence, and error type (correctable / uncorrectable). In the final aging assessment report, the number of errors for each file path can be counted, and a two-dimensional heatmap of file type-physical location can be drawn (if second-level location information is available), identifying which file types are more prone to errors, thereby guiding targeted optimization of the storage system.

[0078] Furthermore, the rate of data retention error generation is closely related to temperature. High temperatures accelerate charge leakage, causing data retention errors to manifest more quickly. Therefore, in some embodiments, a multiphysics co-stress step is also included in the adaptive read voltage perturbation process: 1. Actively apply temperature control to solid-state drives to create a synergistic effect between voltage disturbances and temperature stress.

[0079] Specifically, during the adaptive read voltage disturbance process, temperature control is actively applied to the solid-state drive (SSD), creating a synergistic effect between voltage disturbance and temperature stress. Temperature control can be achieved through an environmental chamber (such as the ESPEC SU-241) or a thermoelectric cooler (TEC) in conjunction with a liquid / air cooling system. The environmental chamber solution achieves temperature control accuracy up to [insert accuracy here]. Suitable for segmented temperature stress; the TEC solution can achieve The temperature change rate is suitable for cumulative triggering variants that require a fast temperature response.

[0080] Deploy a temperature sensor (accuracy) on the surface of the SSD housing. This is used for monitoring and recording. Throughout the test, the internal temperature of the NAND chip must be continuously read via the NVMe SMART log page (Temperature Sensor field) at sampling intervals not exceeding 1 minute, and the timestamp must be recorded. If the SMART temperature cannot be obtained at a certain sampling point, a linear interpolation of the valid temperature values ​​before and after it is used, and the missing interval is noted in the report.

[0081] 2. Temperature control is either segmented temperature stress or cumulative triggering temperature stress; segmented temperature stress includes multiple preset temperature stages arranged in chronological order; cumulative triggering temperature stress is triggered when the cumulative duration of the negative offset of the reading voltage exceeding the preset proportional threshold reaches a preset value, triggering a heating cycle.

[0082] Specifically, temperature control employs one of two mutually exclusive options: Option 1: Segmented temperature stress: Segmented temperature stress testing divides the entire testing process into multiple preset temperature stages arranged in chronological order. In this embodiment, it is divided into three temperature stages (each stage lasting at least one hour, which can be adjusted according to the actual testing objective): Low temperature stage (30) ( ): Simulates the idle state at room temperature. During this stage, the SSD is in a low-temperature environment, and the charge leakage rate is slow, which can be used as a reference baseline.

[0083] Medium temperature stage (45) ( ): Simulates a light load heating state. During this stage, the temperature rises, charge leakage accelerates, and data retention defects begin to appear.

[0084] High temperature stage (55) ( ): Simulates high-load or high-temperature environmental conditions. This stage features the highest temperature and the fastest charge leakage rate, most effectively accelerating the exposure of data retention defects.

[0085] During phase switching, the temperature should rise and fall at the maximum rate allowed by the equipment. Specific values ​​are not mandatory, but the actual rate must be recorded and noted in the report. Throughout the test, adaptive voltage disturbances continue to operate, unaffected by temperature phase switching.

[0086] The main reason for using segmented temperature stress instead of continuous temperature variation is to avoid timing conflicts with high-frequency voltage perturbations on a second-level scale. Voltage perturbations have adjustment intervals of 2 to 8 seconds, while temperature changes involve thermal inertia (on a second to minute level), resulting in a significant difference in time scale. Segmented temperature stress restricts temperature changes to an hourly time scale, allowing voltage perturbations to operate stably within each temperature range without interference. After testing, the RBER variation and error distribution within each temperature range are statistically analyzed to assess the impact of temperature on data retention.

[0087] Option 2: Cumulative Triggered Temperature Stress: Cumulative triggering temperature stress is used to simulate the short-term synergistic effect of voltage offset and temperature. It requires temperature control equipment to support rapid temperature change (such as TEC solution). Its triggering logic is: when the cumulative duration of the negative offset of the read voltage exceeding the preset proportional threshold reaches the preset value, the temperature rise cycle is triggered.

[0088] Specifically, this refers to the cumulative duration during which the absolute value of the negative voltage offset exceeds 6% (a preset percentage threshold). Only when the absolute value of the negative offset... Accumulation begins during normal operation and pauses under other conditions (including during temperature cycling). The accumulation period ends when the preset value is reached (typically 30 to 120 seconds, recommended for plastic-encapsulated SSDs). At 60 seconds, a temperature rise cycle is triggered: the SSD casing temperature is raised from 30°C. Rise to 55 (heating rate) Hold for 3 minutes, then... The rate recovered to 30 After the loop completes, the cumulative timer is reset to zero and the accumulation starts again. The minimum loop interval is set to 10 minutes to avoid excessively frequent temperature changes that could cause thermal shock damage to the SSD.

[0089] A large offset voltage (negative offset exceeding 6%) means that the SSD is in a state close to its limit of read voltage. If a temperature shock is added at this time, it can effectively simulate the degradation acceleration effect that occurs simultaneously with high temperature environment and read voltage drift in real use scenario, while avoiding direct timing conflict with second-level voltage disturbance.

[0090] It should be noted that the two temperature control schemes mentioned above are mutually exclusive and can only be chosen one at a time. Unless otherwise specified, this embodiment preferably adopts Scheme 1 (ambient temperature chamber + segmented temperature stress). Scheme 2 should only be selected when it is necessary to simulate the short-term synergistic effect of voltage deviation and temperature and the temperature control equipment supports rapid temperature change; the selection should be noted in the report.

[0091] 3. Based on the chip temperature history collected in real time during the test, the cumulative equivalent storage time of the solid-state drive is calculated by summing the data in time segments.

[0092] Specifically, regardless of which temperature control scheme is adopted, the cumulative equivalent storage time must be calculated by summing up the NAND chip temperature history collected in real time during the test.

[0093] The cumulative equivalent storage time is calculated as follows: The timeline of the entire test process is divided into several preset unit intervals (e.g., each interval is 1 minute), and the temperature within each interval is... Take the average NAND chip temperature reported by SMART within this time period (or the arithmetic mean if the sampling frequency is higher). The duration of this interval is... The equivalent storage time increment corresponding to this interval is a function of the interval duration and the temperature-related acceleration factor. The total equivalent storage time is obtained by accumulating the increments of each interval.

[0094] The temperature reference point must be the internal temperature of the NAND chip (preferably the chip temperature reported by SMART). It is strictly forbidden to use the set temperature of the ambient temperature chamber or only the temperature recorded during phase switching as a substitute for the chip temperature. If the chip temperature cannot be obtained due to SSD firmware limitations, the SSD casing temperature should be used with an added thermal resistance correction value for estimation, and the approximate method should be clearly noted in the report.

[0095] Regardless of the temperature control strategy employed, the internal temperature sensor of the SSD must be read in real time via SMART. If the internal temperature exceeds 75°C... Immediately stop heating and activate forced air cooling to lower the temperature to 50°C. The voltage disturbance will be paused immediately, and testing will resume once the temperature stabilizes. If the temperature exceeds 85°C... If the test fails, the entire test will be terminated and an overheating alarm will be recorded.

[0096] The cumulative equivalent storage time, calculated based on real-time chip temperature history, has different uses in different data areas: the equivalent storage time in the hot data area is used for both probe block refresh judgment (e.g., 2-year threshold) and adaptive test termination conditions (e.g., 8-year threshold); the equivalent storage time in the warm and cold data areas is only used for probe block refresh judgment (e.g., 2-year threshold) and does not participate in any termination conditions. This design ensures that probe blocks in the warm / cold data areas can be refreshed based on the actual thermal aging degree, avoiding baseline drift failure due to long-term lack of refresh without write pressure, while not affecting test termination decisions.

[0097] Furthermore, during the adaptive read voltage perturbation process, if the read voltage is continuously shifted negatively, it will eventually exceed the error correction code (ECC) capability of the NAND flash memory controller. Once the bit error rate exceeds the maximum correctable capability of the ECC, uncorrectable errors will occur, resulting in permanent data loss. Therefore, in some embodiments, dynamically adjusting the read voltage offset specifically includes an intelligent backoff mechanism, which includes: 1. Preset a backoff error rate threshold based on the error correction code capability of the solid-state drive or the type of NAND flash memory.

[0098] Specifically, the backoff bit error rate threshold is determined based on the error correction code capability of the solid-state drive (SSD) or the type of NAND flash memory. If the ECC capability limit of the SSD controller is known (i.e., the maximum correctable RBER claimed by the controller), then the backoff bit error rate threshold is taken as... Setting a safety factor of 0.8 is to leave a margin and avoid reaching the ECC error correction limit.

[0099] If the ECC capability limit cannot be determined, then a default value based on industry-standard LDPC capability will be adopted according to the NAND flash memory type, and the upper limit of the default value will not exceed [the specified value]. .

[0100] If the NAND type cannot be determined (e.g., SSD is not publicly disclosed), the default value is used. (Covering mainstream TLC scenarios).

[0101] 2. When the bit error rate of the probe block exceeds the backoff bit error rate threshold, the current read voltage is backed up to the offset when the backoff was not triggered last time, and the current offset interval is marked as a dangerous interval. In subsequent disturbances, this interval is avoided or the number of probes in this interval is limited.

[0102] Specifically, when the bit error rate of the probe block exceeds the backoff bit error rate threshold, a backoff operation is immediately triggered: the current read voltage is backed up to an offset where the most recent bit error rate was 50% lower than the current backoff bit error rate threshold (this offset needs to be continuously recorded in memory). If this level has never been reached, the voltage is backed up to 0% of the nominal voltage offset. This offset interval is marked as a "danger zone," and subsequent disturbances avoid this interval, or only probe once with a maximum step size of 15mV, and back off immediately after the probe.

[0103] Furthermore, if a dangerous zone triggers backoff three times consecutively, that zone will be marked as permanently blocked (24 hours), during which no probes will be made. After 24 hours, or when the wear count in that zone increases to more than 1000, it will be automatically unblocked and reprobeed once to reflect potential changes in demand after aging. As the flash memory ages, its optimal read voltage may shift, and the previously dangerous zone may become safe.

[0104] Furthermore, during the test, the threshold can be adaptively fine-tuned based on the actual read retry trigger frequency. If no backoff is triggered for one hour, the threshold can be increased by 20% (but not exceeding the ECC capability limit or the upper limit of the default type); if backoff is too frequent (more than 10 times per hour), the threshold can be decreased by 20% (but not lower than one-tenth of the ECC capability limit or the lower limit of the default type).

[0105] Furthermore, traditional SSD aging tests typically employ a "fixed-duration run, post-analysis" model, resulting in low testing efficiency and significant resource waste. Some SSDs may exhibit obvious signs of degradation early in the testing process, while others may remain in good condition throughout the entire testing cycle. Performing the same testing duration on all SSDs leads to the problem of "testing good drives for too long and bad drives for too short a time." Therefore, in some embodiments, the adaptive read voltage perturbation process also includes risk prediction and active probe scheduling steps. 1. Collect multi-dimensional features including file extension type, voltage offset sensitivity, erase / write wear count, read retry count, current chip temperature, and cumulative equivalent storage time; among which, voltage offset sensitivity is the average slope of the voltage-bit error rate characteristic curve within the sensitive voltage offset range.

[0106] Specifically, during the adaptive voltage disturbance reading process, the following multi-dimensional features are collected in real time: (1) File extension type: Based on the file path, predefined categories include .log, .db, .cache, .bin, .tmp and others (using one-hot encoding). Different file types have different access patterns and write frequencies, and have different effects on SSD wear.

[0107] (2) Voltage offset sensitivity: defined as the average slope of the voltage-bit error rate characteristic curve within the sensitive voltage offset range (-8% to -4%) (unit: RBER increment / mV). This feature reflects the sensitivity of the current data area to voltage offset. The higher the sensitivity, the worse the data retention in that area, and the more prone it is to errors due to charge leakage. This feature is recalculated and updated every 24 hours or whenever the cumulative equivalent storage time of the hot data area increases by 2 years (whichever comes first).

[0108] (3) Erasure wear count: Obtained from SMART data (SMART attribute 241 corresponds to NAND write volume, which can be converted into P / E cycle consumption). If the platform supports physical address lookup, the number of erases for each physical block can be obtained from the flash conversion layer; otherwise, it is set to global SMART wear leveling count and marked as "approximate value".

[0109] (4) Number of read retry attempts: The total number of read retry triggers within the current statistical period is read from the NVMe log page.

[0110] (5) Current chip temperature: Prioritize the NAND chip internal temperature reported by SMART, with a sampling interval of no more than 1 minute.

[0111] (6) Cumulative equivalent storage time: calculated based on the cumulative temperature history in segments.

[0112] 2. Utilize machine learning models to predict the risk score of errors occurring in each data region within a future time period based on multidimensional features.

[0113] Specifically, a binary classifier is trained using XGBoost, labeled with "whether at least one correctable error will occur within the next hour".

[0114] The training and update strategies are as follows: (1) Pre-training: Train the initial XGBoost model using public NAND aging datasets (such as the SNIA SSD dataset) or laboratory historical data.

[0115] (2) Initial adaptation: During the first 2 hours of this test, the actual generated feature-label pairs are collected, and then full retraining (training from scratch, using the same hyperparameters) is performed. The parameters of the pre-trained model are used as the initial starting point to continue training for a small number of rounds (or full retraining is performed directly). Full retraining can better preserve the knowledge of early samples.

[0116] (3) Periodic retraining: During the testing process, every 60 minutes (or every 200 newly added samples), a new XGBoost model (with the same hyperparameters as the pre-trained model) is trained from scratch using all feature-label pairs accumulated up to the current time, replacing the original model. If full retraining cannot be performed due to performance reasons, incremental training can be degraded (loading the current model and continuing training for 10 rounds). Retraining is performed in the background and does not affect the main testing process. To avoid overfitting, a minimum sample size (e.g., 500 samples) can be set before starting the first periodic training.

[0117] The model outputs a risk score (0 to 1, representing the probability that the prediction belongs to the positive class, i.e., an error will occur within the next hour). After each model retraining, the ROC curve is calculated using the most recently accumulated validation set (the last 20% of samples), and the probability threshold corresponding to the point with the largest Youden's J (sensitivity + specificity - 1) is selected as the new dynamic threshold. If there is no validation set, the default threshold of 0.3 is used (because the positive class is scarce, the threshold is lowered to improve recall).

[0118] 3. When the risk score exceeds the dynamic threshold, a probe reading operation is actively inserted for verification, and the verification result is stored as a new sample in the training database; the dynamic threshold is dynamically determined based on the performance index of the machine learning model on the validation set.

[0119] Specifically, the risk prediction model is run every 20 minutes to obtain a risk score for each file (or region). When the risk score exceeds the current dynamic threshold, a probe reading operation is proactively inserted: 4KB of data is read once under normal voltage and once under the current disturbance voltage to verify whether there are correctable errors. The results of each probe reading are stored as new labels in the training sample database, and the model is updated uniformly by periodic retraining.

[0120] Furthermore, traditional aging tests typically use a fixed duration (e.g., 96 hours or 168 hours), executing the entire test cycle regardless of the actual aging state of the SSD. This "one-size-fits-all" approach is inefficient: for SSDs aging rapidly, defects may be fully exposed long before the preset duration, making further testing a waste of time; for SSDs aging slowly, the fixed duration may not be sufficient to fully expose potential defects. Therefore, in some embodiments, during adaptive read voltage perturbation, the following termination conditions are monitored in real time; when any of the following conditions are met, the closed-loop perturbation is exited and the test is terminated: a) The cumulative equivalent storage time reaches a preset first threshold, and the error rate of the probe block remains below the safe error rate threshold.

[0121] Specifically, the cumulative equivalent storage time reaches a preset first threshold (preferably 8 years in this invention), and during this period, the bit error rate of the probe block remains consistently lower than the security bit error rate threshold. The security bit error rate threshold is set to... If ECC capabilities cannot be determined, the default value will be used. The physical meaning of this condition is: if the SSD has already withstood the aging stress equivalent to 8 years of natural storage, but the probe block error rate remains at a safe level (far below the ECC error correction limit), it indicates that the SSD has good data retention capabilities and no further testing is needed. This corresponds to the scenario of "stopping good drives early".

[0122] b) Multiple consecutive voltage offset scans did not trigger any read retry operations, and the bit error rate of the probe block was lower than the safe bit error rate threshold.

[0123] Specifically, in two consecutive rounds (every 30 minutes) of voltage offset scanning of the hot data area (range -10% to +3%), no read retry was triggered, and the bit error rate of the probe block was below the safe bit error rate threshold. The physical meaning of this condition is that even under a full-range voltage scan (covering the negative offset range most likely to trigger errors), the SSD still did not trigger any read retry, indicating that its read voltage margin is sufficient and its data retention capability is excellent. This is also a scenario of "good drives stopping early".

[0124] c) The machine learning model predicts that the risk scores for each data region are all lower than the current dynamic threshold, and no correctable errors are found in multiple rounds of active probe reading operations.

[0125] Specifically, the machine learning model predicts that the risk scores for all data regions are below the current dynamic threshold, and two consecutive rounds of active probe readings have not revealed any correctable errors. The physical meaning of this condition is that the machine learning model, after integrating multi-dimensional features, determines that all regions are unlikely to produce errors within the next hour, and active probe verification confirms this judgment. This corresponds to the scenario of "system stability, no further monitoring required."

[0126] d) The test duration reaches the preset maximum test time.

[0127] Specifically, the test duration reaches a preset maximum value (preferably 96 hours in this invention) as a minimum termination condition to prevent the test from running indefinitely due to abnormal circumstances.

[0128] In this embodiment, the above four termination conditions are monitored in real time during the adaptive voltage disturbance process. When any one of the conditions is met, the closed-loop disturbance is exited and the test is terminated.

[0129] Furthermore, the probe block is the core tool of this invention for monitoring the bit error rate. However, with the extension of test time and the accumulation of aging stress, the probe block itself will also experience charge leakage and data degradation. This means that the probe block, which is intended to measure the degree of aging, is itself aging. If the probe block is not refreshed, its baseline bit error rate will continuously drift, leading to distorted measurement results. Therefore, in some embodiments, the probe blocks are distributed at a preset density in different data areas of the solid-state drive, and a refresh mechanism parallel to adaptive read voltage perturbation is provided. 1. When the cumulative equivalent storage time of the probe block exceeds the preset refresh threshold, the probe block is rewritten and its baseline bit error rate is updated.

[0130] Specifically, probe blocks are distributed at a preset density in different data areas of the solid-state drive: one 4KB probe is embedded every 20GB of logical capacity in hot and warm data areas, and one 4KB probe is embedded every 100GB in cold data areas (density is reduced, and the read interval is extended to 60 seconds to minimize read interference). The probe blocks are stored as hidden files and set to read-only attributes. File system filtering or file path exclusion functions of stress tools ensure that the probe block data is not overwritten.

[0131] The probe block refresh mechanism operates in parallel with the adaptive read voltage perturbation. Every 12 hours, a check is performed. For all regions (hot, warm, cold) of the probe block, based on the cumulative equivalent storage time (using a uniformly segmented Arrhenius model), when the cumulative equivalent storage time of the region containing the probe block exceeds a preset refresh threshold (preferably 2 years in this invention), the probe block is rewritten, maintaining the same known pseudo-random sequence, and the refresh timestamp is recorded.

[0132] After each refresh, wait 100ms for the charge distribution to stabilize, then immediately read the probe block once, and record the original RBER of this read as the new baseline bit error rate. Simultaneously record the baseline value from the previous refresh. and its timestamp.

[0133] 2. Between two refreshes, a linear interpolation method is used to calculate the drift compensation amount based on the refresh time interval and the current cumulative equivalent storage time, so as to obtain the corrected bit error rate. The corrected bit error rate is used for closed-loop feedback.

[0134] Specifically, the baseline bit error rate (BER) of the probe block gradually drifts over time between two refreshes. To accurately measure the BER change caused by voltage disturbances (rather than the BER change caused by baseline drift), BER drift compensation is required.

[0135] Let the last refresh time be... The baseline value is The current refresh time is The baseline value is Then, for any time between two refreshes... baseline value for: ; for The time remaining until the next refresh will be used temporarily. As a constant baseline, the next segment of interpolation will be performed after the next refresh.

[0136] The bit error rate is obtained each time a probe block is read. Then, calculate the corrected bit error rate: ; in The function ensures that the corrected bit error rate is non-negative; negative values ​​are caused by reading noise fluctuations and are considered 0. This corrected bit error rate is used for closed-loop feedback.

[0137] Initial baseline processing: Before the test begins (after the first write to the probe block), immediately measure the initial baseline. Before the first refresh, the baseline at all times is taken from this initial value.

[0138] Anomaly detection: If the corrected bit error rate is 0 for three consecutive reads, but the wear count of other probe blocks or SMART in the same area increases significantly, it is determined that this probe block may be faulty (e.g., data is accidentally overwritten). It should be forced to refresh in advance and the event log should be marked.

[0139] Figure 2 A schematic diagram of the functional modules of the solid-state drive aging test device according to an embodiment of the present invention is shown. Figure 2 As shown, the solid-state drive aging test device 20 includes a partitioning module 21, a setting module 22, a scanning module 23, a disturbance module 24, a reading module 25, an adjustment module 26, and an output module 27.

[0140] The partitioning module 21 is used to divide the logical space of the solid-state drive under test into a hot data area, a warm data area, and a cold data area based on the monitoring results of file access popularity. Setting module 22 is used to set at least one probe block in the solid-state drive, the probe block storing a known data pattern; The scanning module 23 is used to perform a voltage scan on the probe block, generate a voltage-bit error rate characteristic curve, and identify voltage offset intervals that are sensitive to changes in bit error rate based on the characteristic curve. The disturbance module 24 is used to apply a dynamic closed-loop adaptive read voltage disturbance to the hot data area and / or warm data area with the sensitive voltage offset range as the main disturbance direction. The disturbance is mainly negative offset to simulate the charge leakage effect. The reading module 25 is used to read the probe block in real time and obtain its bit error rate during the adaptive reading voltage disturbance process; Adjustment module 26 is used to dynamically adjust the offset of the read voltage using the bit error rate of the probe block as closed-loop feedback. Output module 27 is used to calculate the equivalent storage time of the solid-state drive based on the real-time data collected during the adaptive read voltage disturbance process and the temperature history of the solid-state drive, and to obtain the aging evaluation result of the solid-state drive based on the real-time data collected and the equivalent storage time.

[0141] Optionally, the partitioning module 21 performs the operation of dividing the logical space of the solid-state drive under test into a hot data area, a warm data area, and a cold data area based on the monitoring results of file access frequency, specifically including: Monitor file access operations at the operating system level to identify hot and cold files; Based on file popularity, the logical space of the solid-state drive under test is divided into a hot data area, a warm data area, and a cold data area. The hot data area is used to store high-frequency access data, the cold data area is used to store static verification benchmark data, and the warm data area is used to store medium-frequency access data. Build and dynamically maintain a mapping table from logical addresses to file paths.

[0142] Optionally, an error tracking module is also included for: When a disk error is detected, extract the logical address of the fault; By querying the mapping table, the fault is located to a specific file, and the error is used as the source of analytical data for the fault correlation graph in the aging assessment results.

[0143] Optionally, it also includes a multiphysics-based coordinated stress module, used during the adaptive read voltage perturbation process performed by the perturbation module 24, for: Temperature control is actively applied to the solid-state drive to create a synergistic effect of voltage disturbance and temperature stress. The temperature control is either segmented temperature stress or cumulative trigger temperature stress. Segmented temperature stress includes multiple preset temperature stages arranged in chronological order. Cumulative trigger temperature stress is triggered when the cumulative duration of the negative offset of the read voltage exceeding a preset proportional threshold reaches a preset value. Based on the chip temperature history collected in real time during the test, the cumulative equivalent storage time of the solid-state drive is calculated by summing the data in time segments.

[0144] Optionally, dynamically adjusting the offset of the read voltage specifically includes an intelligent backoff mechanism: A backoff error rate threshold is preset based on the error correction code capability of the solid-state drive or the type of NAND flash memory; When the bit error rate of the probe block exceeds the backoff bit error rate threshold, the current read voltage is backed up to the offset when the backoff was not triggered last time, and the current offset interval is marked as a dangerous interval. During subsequent disturbances, this interval is avoided or the number of probes in this interval is limited.

[0145] Optionally, it also includes a risk prediction and active probe scheduling module, which, during the adaptive voltage perturbation process executed by the perturbation module 24, is used for: The system collects multi-dimensional features including file extension type, voltage offset sensitivity, erase / write wear count, read retry count, current chip temperature, and cumulative equivalent storage time; among which, voltage offset sensitivity is the average slope of the voltage-bit error rate characteristic curve within the sensitive voltage offset range. Using machine learning models, the risk score of errors occurring in each data region within a future time period is predicted based on multidimensional features. When the risk score exceeds the dynamic threshold, a probe reading operation is actively inserted for verification, and the verification result is stored as a new sample in the training database. The dynamic threshold is dynamically determined based on the performance metrics of the machine learning model on the validation set.

[0146] Optionally, a test termination module is also included, which, during the adaptive voltage reading disturbance process performed by the disturbance module 24, is used to: monitor the following termination conditions in real time; and exit the closed-loop disturbance and terminate the test when any of the following conditions are met: a) The cumulative equivalent storage time reaches a preset first threshold, and the bit error rate of the probe block remains below the security bit error rate threshold. b) Multiple consecutive voltage offset scans did not trigger any read retry operations, and the bit error rate of the probe block was lower than the safe bit error rate threshold; c) The machine learning model predicts that the risk scores for each data region are all lower than the current dynamic threshold, and no correctable errors are found in multiple rounds of active probe reading operations; d) The test duration reaches the preset maximum test time.

[0147] Optionally, the probe blocks are distributed at a preset density in different data areas of the solid-state drive, and a refresh mechanism is set up in parallel with adaptive read voltage perturbation: When the cumulative equivalent storage time of the probe block exceeds the preset refresh threshold, the probe block is rewritten and its baseline bit error rate is updated. Between two refreshes, a linear interpolation method is used to calculate the drift compensation amount based on the refresh time interval and the current cumulative equivalent storage time, so as to obtain the corrected bit error rate. The corrected bit error rate is used for closed-loop feedback.

[0148] For other details regarding the implementation techniques of each module in the solid-state drive aging test device in the above embodiments, please refer to the description in the solid-state drive aging test method in the above embodiments, which will not be repeated here.

[0149] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For apparatus embodiments, since they are basically similar to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0150] Please see Figure 3 , Figure 3 This is a schematic diagram of the structure of a computer device according to an embodiment of the present invention. Figure 3 As shown, the computer device 30 includes a processor 31 and a memory 32 coupled to the processor 31. The memory 32 stores program instructions. When the program instructions are executed by the processor 31, the processor 31 performs the steps of the solid-state drive aging test method described in any of the above embodiments.

[0151] The processor 31 can also be referred to as a Central Processing Unit (CPU). The processor 31 may be an integrated circuit chip with signal processing capabilities. The processor 31 can also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. A general-purpose processor can be a microprocessor or any conventional processor.

[0152] See Figure 4 , Figure 4 This is a schematic diagram of the structure of a computer-readable storage medium according to an embodiment of the present invention. The computer-readable storage medium of this embodiment stores program instructions 41 capable of implementing the above-described solid-state drive aging test method. These program instructions 41 can be stored in the computer-readable storage medium in the form of a software product, including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned computer-readable storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks, or computer devices such as computers, servers, mobile phones, and tablets.

[0153] In the several embodiments provided in this application, it should be understood that the disclosed computer devices, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, or indirect coupling or communication connection between devices or units, and may be electrical, mechanical, or other forms.

[0154] Furthermore, the functional units in the various embodiments of this invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated units described above can be implemented in hardware or as software functional units. The above are merely embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made based on the description and drawings of this application, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A solid-state drive aging test method, characterized in that, Includes the following steps: Based on the monitoring results of file access frequency, the logical space of the solid-state drive under test is divided into hot data area, warm data area and cold data area. At least one probe block is provided in the solid-state drive, and the probe block stores a known data pattern; A voltage scan is performed on the probe block to generate a voltage-bit error rate characteristic curve, and the voltage offset interval sensitive to changes in bit error rate is identified based on the characteristic curve. With the sensitive voltage offset range as the perturbation direction, a dynamic closed-loop adaptive read voltage perturbation is applied to the hot data region and / or the warm data region. The perturbation is mainly negative offset to simulate the charge leakage effect. During the adaptive read voltage perturbation process, the probe block is read in real time to obtain its bit error rate; The bit error rate of the probe block is used as closed-loop feedback to dynamically adjust the offset of the read voltage. Based on the real-time data collected during the adaptive read voltage disturbance process and the temperature history of the solid-state drive, the equivalent storage time of the solid-state drive is calculated cumulatively, and the aging assessment result of the solid-state drive is obtained based on the real-time data collected and the equivalent storage time. Specifically, the dynamically adjusted read voltage offset includes an intelligent backoff mechanism: A backoff error rate threshold is preset based on the error correction code capability of the solid-state drive or the type of NAND flash memory; When the bit error rate of the probe block exceeds the backoff bit error rate threshold, the current read voltage is backed up to the offset when the backoff was not triggered last time, and the current offset interval is marked as a dangerous interval. In subsequent disturbances, this interval is avoided or the number of attempts in this interval is limited. The adaptive read voltage disturbance process also includes risk prediction and active probe scheduling steps: The system collects multidimensional features including file extension type, voltage offset sensitivity, erase / write wear count, read retry count, current chip temperature, and cumulative equivalent storage time; wherein, the voltage offset sensitivity is the average slope of the voltage-bit error rate characteristic curve within the sensitive voltage offset range; Using a machine learning model, the risk score of errors occurring in each data region within a future time period is predicted based on the aforementioned multidimensional features; When the risk score exceeds the dynamic threshold, a probe reading operation is actively inserted for verification, and the verification result is stored as a new sample in the training database; wherein, the dynamic threshold is dynamically determined based on the performance index of the machine learning model on the validation set; During the adaptive read voltage disturbance process, the following termination conditions are monitored in real time; when any of the following conditions are met, the closed-loop disturbance is exited and the test is terminated: a) The cumulative equivalent storage time reaches a preset first threshold, and the bit error rate of the probe block remains below the security bit error rate threshold. b) No read retry operation was triggered after multiple consecutive rounds of voltage offset scanning, and the bit error rate of the probe block was lower than the safe bit error rate threshold; c) The machine learning model predicts that the risk scores for each data region are all lower than the current dynamic threshold, and no correctable errors are found in multiple rounds of the active probe reading operation; d) The test duration reaches the preset maximum test time.

2. The solid-state drive aging test method according to claim 1, characterized in that, Based on the monitoring results of file access frequency, the logical space of the solid-state drive under test is divided into a hot data area, a warm data area, and a cold data area, including: Monitor file access operations at the operating system level to identify hot and cold files; Based on file popularity, the logical space of the solid-state drive under test is divided into a hot data area, a warm data area, and a cold data area. The hot data area is used to store high-frequency access data, the cold data area is used to store static verification benchmark data, and the warm data area is used to store medium-frequency access data. Build and dynamically maintain a mapping table from logical addresses to file paths.

3. The solid-state drive aging test method according to claim 2, characterized in that, It also includes error tracking steps: When a disk error is detected, extract the logical address of the fault; By querying the mapping table, the fault is located to a specific file, and the error is used as the source of analysis data for the fault correlation graph in the aging assessment results.

4. The solid-state drive aging test method according to claim 1, characterized in that, The adaptive read voltage perturbation process also includes a multi-physics field coordinated stress step: Temperature control is actively applied to the solid-state drive to create a synergistic effect of voltage disturbance and temperature stress. The temperature control is either segmented temperature stress or cumulative triggered temperature stress. The segmented temperature stress includes multiple preset temperature stages arranged in chronological order. The cumulative triggered temperature stress is triggered when the cumulative duration of the negative offset of the read voltage exceeding a preset proportional threshold reaches a preset value, thus triggering a heating cycle. Based on the chip temperature history collected in real time during the test, the cumulative equivalent storage time of the solid-state drive is calculated by summing the data in time segments.

5. The solid-state drive aging test method according to claim 1, characterized in that, The probe blocks are distributed at a preset density in different data areas of the solid-state drive, and a refresh mechanism is provided in parallel with the adaptive read voltage perturbation: When the cumulative equivalent storage time of the probe block exceeds the preset refresh threshold, the probe block is rewritten and its baseline bit error rate is updated. Between two refreshes, a linear interpolation method is used to calculate the drift compensation amount based on the refresh time interval and the current cumulative equivalent storage time to obtain the corrected bit error rate, which is used for the closed-loop feedback.

6. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the solid-state drive aging test method as described in any one of claims 1 to 5.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the solid-state drive aging test method as described in any one of claims 1 to 5.

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