Solid state disk wear leveling performance test method, device and storage medium

Abstract

This invention discloses a method, device, and storage medium for testing the wear leveling performance of a solid-state drive (SSD). The method includes: initializing the SSD under test to establish a full-disk static cold data state; dividing the logical space into hot and cold zones, performing high-frequency overwrites on the hot zones and low-frequency writes on the cold zones; stopping writes and entering a cache emptying pre-cleaning period; after pre-cleaning, starting a static observation window; acquiring the NAND write rate sequence within the static observation window and extracting time-domain and frequency-domain features; recording static migration pulse events when jointly determined to be continuous oscillations with a low-frequency broad spectrum; acquiring the minimum number of erases before and after the static observation window; if the number increases, accumulating the effective trigger count; if the number does not increase but a pulse event is recorded, accumulating the waveform anomaly count; iterating repeatedly until a preset number of rounds is reached; and generating a judgment result based on the effective trigger count and waveform anomaly count. This invention achieves accurate and reliable testing of static wear leveling performance.

Description

Technical Field

[0001] This application relates to the field of solid-state drive testing technology, and in particular to a method, device and storage medium for testing the wear leveling performance of a solid-state drive. Background Technology

[0002] Solid-state drives (SSDs) use NAND flash memory as their storage medium, and the physical characteristics of NAND flash memory determine that each storage block has a limited write / erase (P / E) lifespan. To extend the lifespan of SSDs, modern SSD controller chips have wear leveling algorithms embedded in their flash memory transition layers. Static wear leveling, in particular, actively moves long-dormant, cold data during background idle periods to reduce the overall wear distribution across the drive, which is crucial for extending SSD lifespan.

[0003] However, existing technologies for verifying the effectiveness of static wear leveling algorithms have the following prominent problems: First, static wear leveling is designed as a background idle task with extremely low scheduling priority. Under continuous saturated write load, the controller suppresses static migration to ensure foreground IO performance, inevitably leading to a false negative conclusion of "static wear leveling not activated" in traditional stress testing schemes. Second, existing schemes directly monitor the NAND write rate after high-pressure writing ends, but at this time, cache write-back generates a large number of initial pulses, which can easily misjudge cache write-to-disk or regular garbage collection as static migration. Third, existing schemes attempt to determine whether static migration has occurred by comparing data verification fingerprints or querying physical addresses, but static migration is a lossless data migration where the data content remains unchanged, and L2P mapping is entirely managed by the controller firmware. The host cannot perceive changes in physical addresses, making the above determination methods infeasible at the physical level. Fourth, existing schemes monitor background rates through / sys / block / sdX / stat, but this interface only records the completion status of host-issued IO. After the host stops writing, the counter permanently stops increasing, failing to reflect internal background operations of the SSD. Fifth, existing technologies lack alternative decision-making schemes when the minimum number of full-disk erases cannot be obtained, resulting in insufficient versatility of the testing methods. Summary of the Invention

[0004] In view of this, this application provides a method, device and storage medium for testing wear leveling performance of solid-state drives to solve the above problems.

[0005] To solve the above-mentioned technical problems, one technical solution adopted in this application is: providing a method for testing the wear leveling performance of a solid-state drive, comprising: Step S1: Initialize the solid-state drive under test, establish an initial state in which all data on the drive is static cold data, and obtain the baseline value of the idle NAND write rate in the initial state. Step S2: Divide the logical address space into hot and cold areas, perform high-frequency overwrite on the hot areas without Trim instructions, and perform low-frequency write on the cold areas. Step S3: When the high-frequency overwrite reaches the preset termination condition, stop writing and enter the cache emptying pre-purification period. After the pre-purification is completed, start the static observation window. Step S4: Within the static observation window, acquire the NAND write rate sequence and extract the time-domain and frequency-domain features from it. When the time domain exhibits continuous oscillation and the frequency domain exhibits a low-frequency broadband pattern, record the static transfer pulse event. Step S5: Obtain the minimum number of erases for the entire disk before and after the static observation window. If the minimum number of erases for the entire disk increases after the static observation window ends, accumulate the effective trigger count. If the minimum number of erases for the entire disk does not increase but a static moving pulse event is recorded, accumulate the waveform abnormality count. Step S6: Repeat steps S2 to S5 until the preset number of cycles is reached. Generate a wear leveling performance determination result based on the effective trigger count and waveform abnormality count.

[0006] To solve the above-mentioned technical problems, another technical solution adopted in this application is: providing a solid-state drive wear leveling performance testing device, comprising: The initialization module is used to initialize the solid-state drive under test, establish an initial state in which all data on the drive is static cold data, and obtain the baseline value of the idle NAND write rate in the initial state. The write module is used to divide the logical address space into hot and cold areas, perform high-frequency overwrite writes without Trim instructions on the hot areas, and perform low-frequency writes on the cold areas. The pre-cleaning module is used to stop writing and enter the cache emptying pre-cleaning period when the high-frequency overwrite reaches the preset termination condition. After the pre-cleaning is completed, the static observation window is started. The recording module is used to acquire the NAND write rate sequence within the static observation window and extract time-domain and frequency-domain features from it. When the time domain exhibits continuous oscillation and the frequency domain exhibits low-frequency broadband, the static transfer pulse event is recorded. The counting module is used to obtain the minimum number of erases for the entire disk before and after the static observation window. If the minimum number of erases for the entire disk increases after the static observation window ends, the effective trigger count is accumulated. If the minimum number of erases for the entire disk does not increase but a static moving pulse event is recorded, the waveform abnormality count is accumulated. The judgment module is used to generate a wear leveling performance judgment result based on the effective trigger count and waveform abnormality count when the above operations are performed by the writing module, pre-cleaning module, recording module and counting module until the preset number of cycles is reached.

[0007] To solve the above-mentioned technical problems, another technical solution adopted in this application is: to provide a computer device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor executes the program to implement the solid-state drive wear leveling performance testing method as described above.

[0008] To solve the above-mentioned technical problems, another technical solution adopted in this application is: to provide a computer-readable storage medium storing a computer program thereon, wherein when the program is executed by a processor, it implements the solid-state drive wear leveling performance testing method as described above.

[0009] Compared to existing technologies, this invention actively stops host writing and introduces a cache emptying pre-cleaning period. After cache emptying, a static observation window is initiated, reducing the timing pollution of subsequent signal identification caused by the initial pulses generated by cache write-back. This helps reduce the false positive rate of misclassifying cache writes as static relocation in existing technologies. A joint identification method using time-domain and frequency-domain features is employed. By detecting the continuous oscillation of the second derivative in the time domain and the low-frequency broadband characteristics of the power spectrum in the frequency domain, it can distinguish between the single-peak pulses of conventional garbage collection and the discrete main frequency of SLC folding and the static relocation waveform, reducing the false positive rate caused by interference signals. Whether the minimum number of erases increases before and after the static observation window is used as the criterion for whether static wear leveling is triggered. This criterion is based on the monotonically increasing physical characteristic of NAND Flash erase counts and is not affected by the specific implementation strategy of the controller, making it applicable to the verification of static wear leveling algorithms from different manufacturers. By employing a dual statistical mechanism of effective trigger counting and waveform anomaly counting, effective trigger counting corresponds to confirmed events where the minimum number of erases across the entire disk increases, while waveform anomaly counting corresponds to suspected events where only waveform signals exist but the minimum number of erases across the entire disk does not increase. This mechanism can preserve potentially valid signals in boundary scenarios where the minimum number of erases across the entire disk does not increase, which helps reduce the false negative rate that may result from a single criterion. Establishing a repeatable test starting point and wear gradient through initialization and differentiated writing in hot and cold partitions helps ensure the comparability of results from multiple rounds of cyclic testing. Attached Figure Description

[0010] Figure 1 This is a flowchart illustrating an embodiment of the solid-state drive wear leveling performance testing method of the present invention.

[0011] Figure 2 This is a functional module diagram of an embodiment of the solid-state drive wear leveling performance testing device of the present invention.

[0012] Figure 3 This is a schematic diagram of the structure of one embodiment of the computer device of the present invention.

[0013] Figure 4 This is a schematic diagram of the structure of one embodiment of the computer-readable storage medium of the present invention. Detailed Implementation

[0014] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0015] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0016] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0017] Figure 1 This is a flowchart illustrating the solid-state drive wear leveling performance testing method according to an embodiment of the present invention. It should be noted that if substantially the same results are obtained, the method in this embodiment is not necessarily identical. Figure 1 The illustrated process sequence is limited. For example... Figure 1 As shown, the solid-state drive wear leveling performance testing method includes the following steps: Step S1: Initialize the solid-state drive under test, establish an initial state in which all data on the drive is static cold data, and obtain the baseline value of the idle NAND write rate in the initial state.

[0018] It should be noted that in this embodiment, a Linux test platform (Ubuntu 22.04 LTS) and an Intel D3-S4510 enterprise-grade SATA SSD (480GB, 3D TLC NAND) are used as the solid-state drive under test, and fio is used as the IO generation tool and smartctl as the SMART information reading tool for illustrative purposes. It should also be noted that those skilled in the art can choose other equivalent operating system platforms and toolsets to implement this method based on the actual test environment and the type of SSD under test; the specific choices in this embodiment do not constitute a limitation on the scope of protection of this invention.

[0019] Specifically, on a Linux system, the command `blkdiscard -f / dev / sda` is used to issue Deallocate / Trim commands to the entire disk, 1. removing the mapping relationship between LBAs and physical blocks. Then, sequential writes are used to fill the entire disk's logical space twice: the first fill maps all LBAs to physical blocks, and the second fill ensures that old data is overwritten, establishing an initial state where "all disk data is static cold data." After filling is complete, the `smartctl -x / dev / sda | grep “Total_LBAs_Written”` reads the NAND physical write total field in the SMART attribute. This value is polled at a fixed period (e.g., 5 seconds), and the ratio of the difference between two consecutive polling results to the time interval is calculated to obtain the baseline value of the idle NAND write rate, which is measured to be 0.2 MB / s in this example. Simultaneously, the initial maximum and minimum number of erases are recorded; in this example, the initial minimum number of erases, EC_min, is 38.

[0020] Step S2: Divide the logical address space into hot and cold areas, perform high-frequency overwrite on the hot areas without Trim instructions, and perform low-frequency write on the cold areas.

[0021] Specifically, the user logical address space of the solid-state drive (SSD) is divided into logical hot zones and logical cold zones. In this embodiment, LBA 0~380GB is designated as a hot zone (approximately 79% of the total disk capacity), and LBA 380GB~480GB is designated as a cold zone (approximately 21% of the total disk capacity). This division is only used for data marking and statistics and does not involve operations on the physical OP space. Overwrite operations without Deallocate / Trim instructions are performed on the logical hot zones. Specifically, fio initiates 4KB random writes, with a queue depth (QD) set to 32 and a write volume of 64GB per round (approximately twice the SLC cache capacity to ensure sufficient entry into the steady-state write phase). No Trim instructions are included during the write process, forcing the controller to trigger a complete "read-merge-erase-write" garbage collection process in the hot zones. Simultaneously, low-frequency write operations are performed on the logical cold zones at a frequency of 1GB data block every 6 minutes to keep the physical blocks in the cold zones in a relatively low-wear state. During the process of high-frequency writing in hot zones and low-frequency writing in cold zones, the NAND write rate is continuously monitored through SMART polling.

[0022] Step S3: When the high-frequency overwrite reaches the preset termination condition, stop writing and enter the cache emptying pre-purification period. After the pre-purification is completed, start the static observation window.

[0023] Specifically, when the high-frequency coverage write in the hot zone reaches the preset termination condition (in this embodiment, this means completing a 64GB data write, lasting approximately 5 minutes), all host write commands are stopped being sent to the solid-state drive under test. Then, a cache emptying pre-cleaning period begins. The pre-cleaning duration is determined as follows: In this embodiment, the user configured the cache capacity parameter C=6144MB (6GB), and the baseline idle NAND speed is 0.2MB / s. Therefore, the pre-cleaning duration is calculated as max(6144 / (0.2×2), 30)=max(15360, 30), with an upper limit of 120 seconds. During the pre-cleaning period, the NAND write rate is continuously monitored at 5-second intervals. After the pre-cleaning period begins, the NAND write rate rapidly decreases from approximately 320MB / s during the high-voltage write phase, stabilizing at 0.3~0.4MB / s after approximately 90 seconds. When the NAND write rate drops back to the idle NAND write rate baseline plus a preset tolerance (in this embodiment, the tolerance is set to 2MB / s, i.e., dropping back to within 2.2MB / s) for 5 consecutive samplings (i.e., 25 consecutive seconds), the pre-cleaning is considered successful, and the static observation window is initiated. In this embodiment, the 5 consecutive sampling values ​​between the 100th and 120th seconds of pre-cleaning all meet the drop-back condition, therefore, pre-cleaning ends at 120 seconds and the static observation window is initiated.

[0024] Step S4: Within the static observation window, acquire the NAND write rate sequence and extract the time-domain and frequency-domain features from it. When the time domain exhibits continuous oscillation and the frequency domain exhibits a low-frequency broadband pattern, record the static transfer pulse event.

[0025] Specifically, after pre-cleaning meets the standards, a static observation window is initiated. The NAND write rate is continuously recorded at a fixed sampling period of 5 seconds, forming a rate time series R(t). The total duration of the static observation window is preset to 60 seconds, collecting 13 rate sampling points (including the starting point). After obtaining the NAND write rate sequence, the time-domain features are extracted as follows: the first derivative of the rate sequence is calculated. and second derivative The number of sign changes of the second derivative within a sliding window (10 seconds, i.e., 2 sampling points) is counted. When the number of sign changes exceeds a preset oscillation threshold (3 times / 10 seconds in this embodiment) and this state continues for more than a preset minimum duration (10 seconds in this embodiment), it is determined that the time domain exhibits continuous oscillation. In this embodiment, during the 35th to 55th seconds of the static observation window, the rate sequence exhibits a fluctuation pattern of 6→12→8→14→7, and the sign change of the second derivative is (+, -, +, -) alternating 4 times, exceeding the threshold of 3 times / 10 seconds, and lasting for 20 seconds, which is determined to be continuous oscillation in the time domain. Subsequently, a Fast Fourier Transform (FFT) is performed on the sampling points corresponding to the determination of continuous oscillation in the time domain to calculate the power spectral density P(f) and the peak concentration of the power spectrum. The peak concentration is the ratio of the maximum power spectral density to the average power spectral density. In this embodiment, there are a total of 5 sampling points during the oscillation period. After performing FFT, the peak concentration of the power spectrum is 1.68, which is lower than the first preset concentration threshold of 2.0, indicating that the frequency domain exhibits a low-frequency broadband spectrum. If both the time domain exhibits continuous oscillation and the frequency domain exhibits a low-frequency broadband spectrum, a static transfer pulse event is recorded.

[0026] Step S5: Obtain the minimum number of erases for the entire disk before and after the static observation window. If the minimum number of erases for the entire disk increases after the static observation window ends, accumulate the effective trigger count. If the minimum number of erases for the entire disk does not increase but a static moving pulse event is recorded, accumulate the waveform abnormality count.

[0027] Specifically, before starting the static observation window, the minimum number of erases required for the entire disk's physical blocks is read via SMART or a vendor-specific command, and denoted as... In this embodiment, the read value is 42. After the static observation window ends, the minimum number of erases for the entire disk physical block is read again and recorded as... In this embodiment, the read value is 44. The difference is calculated. Since the value is greater than 1, it is determined that the static wear leveling performed an erasure operation on the physical block with the minimum number of erasures, and the "Static Leveling Effective Trigger Count" is incremented by one. Simultaneously, because a static transfer pulse event was recorded in step S4 of this round, and... This round is counted as a valid trigger. If it occurs If the difference is 0 but a static moving pulse event is recorded in step S4, then this round is marked as "waveform abnormal" and counted in the waveform abnormal count, but not in the valid trigger count.

[0028] Step S6: Repeat steps S2 to S5 until the preset number of cycles is reached. Generate a wear leveling performance determination result based on the effective trigger count and waveform abnormality count.

[0029] Specifically, it is determined whether the current cycle number has reached the preset cycle number N (in this embodiment, N=30 cycles). If not, the process returns to step S2 to continue executing the next round of high-frequency writing to hot areas and low-frequency writing to cold areas. If 30 cycles have been reached, the test is stopped, and a wear leveling performance determination result is generated based on the effective trigger count and waveform anomaly count recorded in all cycles. In this embodiment, after 30 cycles of testing, the effective trigger count is 27, the waveform anomaly count is 2, and the no-event cycle is 1. The effective trigger rate is 27 / 30×100%=90.0%. Simultaneously, the maximum number of erases on the entire disk after all cycles are obtained. and minimum number of erases Calculate the extreme wear span ratio Since the effective trigger rate is 90.0% (not less than the first preset threshold of 30%) and the wear extreme value span ratio of 1.36 does not exceed the second preset threshold of 2.0, the static wear leveling function of the solid-state drive is determined to be effective, and the wear leveling algorithm as a whole is effective.

[0030] This invention proactively stops host writes and introduces a cache emptying pre-cleaning period. After cache emptying, a static observation window is initiated, reducing the timing pollution of subsequent signal identification caused by the initial pulses generated by cache write-back. This helps reduce the false positive rate of misclassifying cache writes as static relocation in existing technologies. A joint identification method using time-domain and frequency-domain features is employed. By detecting the continuous oscillation of the second derivative in the time domain and the low-frequency broadband characteristics of the power spectrum in the frequency domain, it can distinguish between the single-peak pulses of conventional garbage collection and the discrete main frequency of SLC folding and the static relocation waveform, reducing the false positive rate caused by interference signals. Whether the minimum number of erases increases before and after the static observation window is used as the criterion for whether static wear leveling is triggered. This criterion is based on the monotonically increasing physical characteristic of NAND Flash erase counts and is not affected by the specific implementation strategy of the controller, making it applicable to the verification of static wear leveling algorithms from different manufacturers. By employing a dual statistical mechanism of effective trigger counting and waveform anomaly counting, effective trigger counting corresponds to confirmed events where the minimum number of erases across the entire disk increases, while waveform anomaly counting corresponds to suspected events where only waveform signals exist but the minimum number of erases across the entire disk does not increase. This mechanism can preserve potentially valid signals in boundary scenarios where the minimum number of erases across the entire disk does not increase, which helps reduce the false negative rate that may result from a single criterion. Establishing a repeatable test starting point and wear gradient through initialization and differentiated writing in hot and cold partitions helps ensure the comparability of results from multiple rounds of cyclic testing.

[0031] Furthermore, to address the technical problem that insufficient pre-cleaning may occur due to inaccurate SSD cache capacity estimation or differences in controller firmware behavior, resulting in cache write-back activity still interfering with accurate identification of static migration within the static observation window, in addition to the above embodiments, other embodiments further include the following after pre-cleaning: 1. Record the peak NAND write rate during the pre-cleaning period.

[0032] Specifically, in actual testing, the NAND write rate gradually decreases from its high-voltage peak after the pre-cleaning period begins. To ensure that pre-cleaning is fully completed and cached data is indeed emptied, this embodiment continuously records the NAND write rate at each sampling point every 5 seconds during the pre-cleaning period, and extracts the maximum value as the peak NAND write rate during the pre-cleaning period. This peak typically occurs in the early stages of pre-cleaning, representing the most intense phase of cache write-back.

[0033] 2. When the pre-cleaning is completed, determine whether the current NAND write rate meets the preset conditions. The preset conditions include that the current NAND write rate does not exceed the peak value of the maximum NAND write rate multiplied by the first preset percentage, or that the current NAND write rate does not exceed the baseline value of the idle NAND write rate plus the first preset tolerance.

[0034] Specifically, the preset conditions include the following two scenarios: Scenario 1: The current NAND write rate does not exceed the peak value of the maximum NAND write rate multiplied by a first preset percentage. In this embodiment, the first preset percentage is set to 10%, meaning the current rate does not exceed 10% of the peak value. For example, if the peak value of the maximum NAND write rate monitored during pre-cleaning is 280MB / s, then the current rate must not exceed 28MB / s. Scenario 2: The current NAND write rate does not exceed the idle NAND write rate baseline value plus a first preset tolerance. In this embodiment, the first preset tolerance is 2MB / s, meaning the current rate must not exceed the idle baseline (0.2MB / s) plus 2MB / s = 2.2MB / s. Meeting either of the above two scenarios is considered to satisfy the preset conditions.

[0035] 3. If not met, extend the pre-purification preset time and re-verify until the preset conditions are met or the preset maximum number of extensions is reached.

[0036] Specifically, if the current NAND write rate does not meet the above preset conditions, the pre-cleaning preset time is extended (in this embodiment, the preset extension time is 30 seconds) and re-verification is performed. After each extension, it is determined again whether the current rate meets the preset conditions. If not, the extension continues until the conditions are met or the preset maximum number of extensions is reached. In this embodiment, the preset maximum number of extensions is 3, that is, a maximum extension of 90 seconds. If the current rate still does not meet the preset conditions after reaching the maximum number of extensions, an alarm log is recorded and the system is forced to enter a static observation window.

[0037] This embodiment improves the consistency and reliability of test results by setting dynamic pre-purification termination conditions based on the measured peak rate and extending the re-verification mechanism to ensure that each pre-purification reaches a fully emptied state.

[0038] Furthermore, to address the technical issue that SSDs with different interface protocols have different internal architectures and rate variation characteristics, and that using a uniform polling period may cause NVMe SSDs to lose waveform details due to excessively large sampling intervals, or cause SATA SSDs to increase unnecessary system overhead due to excessively small sampling intervals, in other embodiments based on the above embodiments, obtaining the NAND write rate sequence includes: The NAND physical write volume field in the SMART attribute is polled at a fixed period. The ratio of the difference between two consecutive polling results to the time interval is calculated to obtain the NAND write rate. The fixed period is determined according to the interface protocol type of the solid-state drive: if the solid-state drive is NVMe protocol, the first preset period is used; if the solid-state drive is SATA protocol, the second preset period is used. The second preset period is greater than the first preset period.

[0039] Specifically, in this embodiment, the sole primary path to obtain the NAND write rate sequence is: polling the NAND physical write total field in the SMART attribute at fixed intervals, calculating the ratio of the difference between two adjacent polling results to the time interval, and obtaining the NAND write rate. Specifically, for NVMe protocol SSDs, the media_units_written field is read using the SMART log reading function of the NVMe management tool, or proprietary attributes from manufacturers such as Intel / Micron (such as F1 attribute values) are read. For SATA protocol SSDs, the Total_LBAs_Written attribute is read using the SMART reading function of the SATA management tool.

[0040] The fixed polling period is determined based on the interface protocol type of the solid-state drive. The physical basis is that NVMe protocol SSDs usually have a large capacity of built-in DRAM cache, and NVMe queue depth is high, command processing speed is fast, and the rate of internal background operations changes more rapidly, requiring a shorter polling period to capture the detailed features of rate fluctuations; while SATA protocol SSDs have a limited AHCI queue depth (maximum 32), relatively slow command processing speed, and a larger time constant of background operation rate changes, so a longer polling period can be used without losing key features.

[0041] Specifically, if the solid-state drive uses the NVMe protocol, a first preset period is used, which is set to 5 seconds in this embodiment; if the solid-state drive uses the SATA protocol, a second preset period is used, which is set to 10 seconds in this embodiment. The second preset period is longer than the first preset period.

[0042] It is important to note that this method explicitly prohibits the use of the ` / sys / block / sdX / stat` interface for NAND speed monitoring. Field 7 (number of sectors written) in this interface only records the completion status of host-issued I / O; once the host stops writing, this counter permanently stops incrementing and cannot reflect NAND physical write activity generated by background GC, static migration, or other operations within the SSD. This embodiment ensures that NAND write behavior within the controller can still be captured after the host stops writing by directly polling the total physical write volume in the SMART attribute.

[0043] Furthermore, to address the technical problem that relying solely on temporal rate fluctuations cannot distinguish between static migration and background operations such as SLC folding and regular GC, which also generate rate fluctuations, leading to an extremely high false positive rate, in addition to the above embodiments, other embodiments extract temporal features including: Calculate the first and second derivatives of the NAND write rate sequence, count the number of sign changes of the second derivative within the sliding window, and when the number of sign changes exceeds the preset oscillation threshold and continues to exceed the preset minimum duration, the time domain exhibits continuous oscillation.

[0044] Specifically, after obtaining the NAND write rate sequence R(t), the time-domain features are extracted according to the following steps: The first step is to calculate the first derivative (rate of change): ΔR(t) = R(t) - R(t-1), with units of MB / s². The first derivative reflects the instantaneous direction and magnitude of the rate of change.

[0045] The second step is to calculate the second derivative (acceleration): Δ²R(t) = ΔR(t) - ΔR(t-1), with units of MB / s³. The second derivative reflects the trend of the rate of change of velocity, and its sign indicates a change in the direction of the rate of change.

[0046] The third step is to count the number of sign changes of the second derivative within the sliding window. In this embodiment, the sliding window length is set to 10 seconds, corresponding to 2 sampling points (sampling interval of 5 seconds). Within the sliding window, the signs (positive, negative, zero) of adjacent second derivative values ​​are compared, and a count is made each time the sign changes. When the number of sign changes exceeds a preset oscillation threshold (preset to 3 times / 10 seconds in this embodiment) and the duration of this state exceeds a preset minimum duration (preset to 10 seconds in this embodiment, i.e., at least 3 consecutive sampling points), it is determined that the time domain exhibits continuous oscillation.

[0047] For example, when the rate sequence exhibits a fluctuation of 6→12→8→14→7, the signs of its second derivative are (+, -, +, -) in sequence. The sign changes 4 times within a 10-second window, exceeding the threshold of 3 times. Furthermore, this fluctuation lasts for 20 seconds (4 sampling points), exceeding the 10-second threshold. Therefore, it is determined that the time domain exhibits continuous oscillation.

[0048] Extracting frequency domain features includes: For the sampling points that are determined to be continuously oscillating in the time domain, perform a fast Fourier transform to calculate the power spectral density and the peak concentration of the power spectrum. The peak concentration is the ratio of the maximum power spectral density to the average power spectral density. When the peak concentration is lower than the first preset concentration threshold, the frequency domain exhibits a low-frequency broadband spectrum.

[0049] Specifically, a Fast Fourier Transform (FFT) is performed on the sampling points identified as exhibiting continuous oscillations in the time domain. Before performing the FFT, it is necessary to ensure that the number of sampling points meets the analysis requirements. In this embodiment, there are 5 sampling points during the oscillation period, which satisfies the priority scheme condition of at least 5 sampling points, so the FFT is performed directly on these sampling points. The sampling interval is 5 seconds, therefore the sampling frequency is... =1 / 5=0.2Hz, Nyquist frequency =0.1Hz. Calculate the power spectral density after performing an FFT. The effective frequency analysis range is 0.02Hz to 0.1Hz (excluding DC components and frequencies higher than Nyquist).

[0050] Then the peak concentration of the power spectrum is calculated: Peak concentration = That is, the maximum power spectral density With the average power spectral density The ratio of peak concentration to peak concentration. This index reflects the degree of concentration of spectral energy: if the energy is concentrated on one or a few frequencies (such as periodic pulses generated by SLC folding or regular GC), the peak concentration is high (preset to be greater than 3.0 in this embodiment); if the energy is dispersed over a wide frequency range (such as random background activity generated by static relocation), the peak concentration is low (preset to be less than 2.0 in this embodiment).

[0051] In this embodiment, the peak concentration of the FFT power spectrum during the oscillation period is 1.68, which is lower than the first preset concentration threshold of 2.0, indicating that the frequency domain exhibits a low-frequency broadband spectrum. If both continuous oscillation in the time domain and a low-frequency broadband spectrum are simultaneously satisfied, a static transfer pulse event is recorded.

[0052] This embodiment introduces frequency domain FFT power spectrum peak concentration analysis and utilizes the essential differences in frequency domain between different types of background operations (static transfer presents a low-frequency broadband spectrum, while SLC folding / conventional GC presents a discrete main frequency) to achieve accurate identification of static transfer pulses, greatly reducing the false judgment rate.

[0053] Furthermore, to address the technical problem that when the frequency domain determination result is in a boundary ambiguity region (peak concentration between 2.0 and 3.0), a definitive conclusion cannot be drawn based on the joint time-domain and frequency-domain determination, potentially leading to missed detection of actual static relocation activities, in addition to the above embodiments, other embodiments further include, after extracting the frequency domain features: 1. If the frequency domain characteristics do not show either low-frequency broadband or discrete main frequency, then calculate the background migration intensity ratio. The background migration intensity ratio is the ratio of the NAND write volume per unit time within the static observation window to the NAND write volume per unit time before the high-frequency coverage write reaches the preset termination condition.

[0054] 2. If the background migration intensity ratio exceeds the preset threshold, the current round will be marked as a weak trigger and included in the valid trigger count.

[0055] Specifically, in actual testing, the frequency domain characteristics of some rounds lie in the boundary region between the low-frequency broadband and the discrete dominant frequency, that is, the peak concentration is between the first preset concentration threshold of 2.0 and the discrete dominant frequency determination threshold of 3.0 (i.e., 2.0 ≤ peak concentration ≤ 3.0). In this scenario of ambiguous boundaries, a simple joint determination in the time domain and frequency domain cannot provide a definitive conclusion. Therefore, this embodiment provides a backup determination scheme.

[0056] When the frequency domain characteristics do not exhibit either low-frequency broadband (peak concentration < 2.0) or discrete dominant frequency (peak concentration > 3.0), the Background Migration Intensity Ratio (BMIR) is calculated. The Background Migration Intensity Ratio is the ratio of the amount of NAND write per unit time within the static observation window to the amount of NAND write per unit time before the high-frequency overlay write reaches the preset termination condition.

[0057] The numerator is the amount of NAND physical writes per unit time within the current static observation window (i.e., the average NAND rate during the static window), and the denominator is the average NAND rate during the last 2 minutes of the immediately preceding pressurization phase (as the baseline for steady-state write strength). In this embodiment, the average NAND rate during the static window is 8.175 MB / s, and the average NAND rate during the last 2 minutes of the preceding pressurization phase is 76.5 MB / s, so BMIR = 8.175 / 76.5 = 0.107.

[0058] If the background migration intensity ratio exceeds a preset threshold (the preset threshold is 0.05 in this embodiment), the current round is marked as "weak trigger" and counted in the valid trigger count. BMIR=0.107 exceeds the 0.05 threshold, therefore this round is marked as weak trigger and counted in the valid trigger count.

[0059] This embodiment introduces the background relocation intensity ratio as a supplementary quantitative indicator, providing an objective quantitative basis for judging scenarios with ambiguous boundaries, and further improving the coverage and accuracy of the test method.

[0060] Furthermore, to address the significant differences in response speed among different SSDs to the same load under fixed load conditions, which may lead to some SSDs being overloaded (latency spikes, IO completion timeouts) or underloaded (insufficiently stimulating the controller's background behavior) and affecting the effectiveness and stability of testing, in addition to the above embodiments, other embodiments further include the following when performing high-frequency overwrite and low-frequency write operations: 1. Collect the average write latency and maximum write latency at a preset collection period. If the average write latency exceeds the preset latency threshold, calculate the coefficient of variation of the maximum write latency within the preset time window. If the coefficient of variation exceeds the first preset coefficient of variation threshold and the average write latency continues to rise, halve the write queue depth. If the coefficient of variation is lower than the second preset coefficient of variation threshold and the average write latency is stable and high but no longer continues to rise, maintain the current write queue depth.

[0061] 2. If the average write latency further increases to a preset multiple of the preset latency threshold, the average write completion latency will be collected at a preset collection period, and an interrupt signal or a first termination signal will be sent to the process performing the write operation to trigger the process to exit normally; if the process does not exit after receiving the first termination signal for a preset timeout period, a second termination signal will be sent to forcibly terminate the process, and the device recovery operation will be performed before continuing to the next round of testing.

[0062] In this embodiment, when performing high-frequency overwrite and low-frequency write operations, the average write latency is collected at a preset sampling period (set to 1 second in this embodiment). ) and maximum write latency ( The average write latency can be obtained by using the latency logging function of the IO load generation tool to calculate the average completion latency of each IO operation. The maximum write latency can be obtained by using the maximum latency recording function of the IO load generation tool. When the average write latency exceeds a preset latency threshold... (In this embodiment) The dynamic load adjustment process is triggered when the time is 10ms.

[0063] After triggering, the coefficient of variation (CV) of the maximum write latency within a preset time window (set to 10 seconds in this embodiment) is first calculated. ,in, The standard deviation of the maximum write latency. This represents the average maximum write latency. The coefficient of variation measures the dispersion of the maximum latency and can effectively reflect the stability of the SSD's internal operating state.

[0064] If the CV exceeds the first preset coefficient of variation threshold (set to 0.5 in this embodiment) and the average write latency continues to rise, it is determined to be in a "garbage collection overload" or "frequent SLC cache overflow" state. In this state, the SSD controller is busy with internal garbage collection, and the foreground IO latency fluctuates drastically. At this time, the write queue depth (QD) is halved (e.g., reduced from 32 to 16), and the thinktime is increased (e.g., increased from 0 to 100ms) to reduce the pressure of host IO and give the controller more time to complete internal operations.

[0065] If the CV is lower than the second preset coefficient of variation threshold (set to 0.2 in this embodiment) and the average write latency is consistently high but no longer continues to rise, it is determined to be in a "bandwidth bottleneck" state. In this state, the SSD has reached its physical write limit, the latency is consistently high but does not fluctuate drastically, and further increasing the load will not improve throughput. At this time, the current write queue depth is maintained, and no further pressure is applied.

[0066] If the average write latency further increases to a preset multiple of the preset latency threshold (set to 2 times in this embodiment, i.e., exceeding 20ms), the average write completion latency is collected at a preset collection period, and an interrupt signal (SIGINT) or a first termination signal (SIGTERM) is sent to the process performing the write operation to trigger the process to exit normally. If the process does not exit after receiving the first termination signal for a preset timeout period (set to 30 seconds in this embodiment), a second termination signal (SIGKILL) is sent to forcibly terminate the process, and a device recovery operation is performed (including waiting 5 seconds to ensure DMA operation timeout release, releasing the page cache, and reopening the device file descriptor) before continuing to the next round of testing.

[0067] If the current QD has dropped to 1 but the latency is still higher than the threshold, it is determined to be an SSD anomaly, triggering a test pause and recording an alarm. If the latency recovers to below the threshold, the queue depth is gradually restored to the original value in steps (e.g., every 10 seconds + 1) to avoid secondary oscillations.

[0068] This embodiment accurately distinguishes between "GC overload" and "bandwidth bottleneck" by using dynamic load adjustment based on the coefficient of variation of IO latency, and adopts the optimal adjustment strategy for each, thus achieving adaptive load adjustment and ensuring that the test can be executed stably on different SSDs.

[0069] Furthermore, to address the significant differences in SMART attribute support among different brands and models of commercial SSDs, and the technical issue that some SSDs do not provide the EC_min field, causing the main criterion to fail to execute, in other embodiments based on the above embodiments, when obtaining the minimum number of full disk erases fails, the alternative value for the minimum number of full disk erases is obtained in the following priority order: First priority: Read the minimum wear count value from the SMART attribute as the replacement value for the minimum number of erases for the entire disk.

[0070] Second priority: If the minimum wear count value is not found in the SMART attribute, then parse the NVMe Telemetry log page to obtain the minimum wear count value for each die, and take the minimum wear count value among the minimum wear count values ​​for each die as the replacement value for the minimum number of erases for the entire disk.

[0071] Specifically, in some commercial SSDs, the SMART log does not provide a minimum number of full-disk erases field, making the EC_min primary criterion in step S5 unusable directly. Therefore, this embodiment provides a two-level degradation alternative strategy.

[0072] First priority: Read the minimum wear count value from the SMART attribute as the alternative value for the minimum number of erases on the entire disk. Some SSD manufacturers provide this value in the SMART attribute. Or a similar field, which directly records the minimum number of erases across all physical blocks on the entire disk. If this field exists, it is directly read as... value.

[0073] Second priority: If the minimum wear count value is not found in the SMART attribute, then parse the NVMe Telemetry log page to obtain the minimum wear count value for each die. For NVMe protocol SSDs, read the specified log page using the Telemetry log reading function of the NVMe management tool, parse the minimum wear count value for each die, and take the minimum value among all die minimum wear count values ​​as the replacement value for the minimum number of erases for the entire disk.

[0074] Furthermore, this embodiment also provides a third-level degradation replacement strategy.

[0075] Third priority: If neither of the above two levels can be obtained, then abandon the single round. Quantitative method. In this case, the final value is determined by combining the life-cycle wear range growth rate with the global BMIR mean. Specifically, if the initial stage of testing can estimate... (Based on approximate values ​​obtained from vendor-customized logs or pre-experiments), then calculate .like If the wear level is less than 0.5 and the global BMIR mean is less than 0.05, output "Wear leveling is effective (conservative conclusion)"; if... If the wear leveling index is >2.5 and the global BMIR mean is ≥0.10, output "Wear leveling failure"; if it falls between these two values, output "Conclusion cannot be quantified, full original data provided for manual analysis". If it is also impossible to estimate, the global BMIR mean will be used directly for judgment: if the global BMIR mean is <0.05, the output will be "No significant evidence of relocation, wear equalization may be ineffective"; if the global BMIR mean is ≥0.10, the output will be "Significant evidence of background relocation exists, wear equalization is suspected to be effective"; if 0.05≤global BMIR mean<0.10, the output will be "The conclusion is unclear, manual review is recommended".

[0076] This embodiment employs a three-level degradation and replacement strategy. By trying alternative solutions one by one, a meaningful diagnostic conclusion can still be given through the joint judgment of BMIR+WESR, thus achieving universal compatibility across all brands.

[0077] Furthermore, to address the technical problem that a single indicator (such as only the effective trigger rate or only the wear range) cannot fully reflect the actual performance of the wear leveling algorithm and may lead to misjudgments, in addition to the above embodiments, other embodiments generate wear leveling performance determination results based on the effective trigger count and waveform anomaly count, including: 1. Calculate the ratio of effective trigger count to total number of cycles as the effective trigger rate; if the effective trigger rate is lower than the first preset threshold, the static wear leveling function is deemed to have failed.

[0078] 2. After all cycles are completed, obtain the maximum number of erases and the minimum number of erases for the entire disk. Calculate the wear extreme value span ratio. The wear extreme value span ratio is the difference between the maximum number of erases and the minimum number of erases for the entire disk divided by the minimum number of erases for the entire disk plus one.

[0079] 3. If the wear extreme value span ratio exceeds the second preset threshold and the effective trigger count is lower than the third preset threshold, the wear leveling algorithm is determined to be in overall failure.

[0080] Specifically, after all iterations are completed, the determination result is generated according to the following steps: The first step is to calculate the effective trigger rate. Effective trigger rate = Effective trigger count / Total number of cycles × 100%. In this embodiment, the total number of cycles N = 30, the effective trigger count is 27, and the effective trigger rate = 27 / 30 × 100% = 90.0%. If the effective trigger rate is lower than the first preset threshold (in this embodiment, the first preset threshold is set to 30%), the static wear leveling function is determined to be faulty. In this embodiment, an effective trigger rate of 90.0% is not lower than 30%, so this failure determination is not triggered.

[0081] The second step is to obtain the maximum number of erases on the entire disk after all loops have finished. Minimum number of erases for the entire disk Calculate the extreme wear span ratio Wear extreme value span ratio = ( - ) / ( +1). Adding one to the denominator ensures that when... The mathematical expression is stable and will not exhibit division by zero errors. In this embodiment, =105, =44, =(105-44) / (44+1)=61 / 45=1.36.

[0082] The third step involves a joint determination based on the wear extreme value span ratio and the effective trigger count. If the wear extreme value span ratio exceeds a second preset threshold (set to 2.0 in this embodiment) and the effective trigger count is lower than a third preset threshold (set to an effective trigger rate of 50%, corresponding to 15 counts in this embodiment), then the wear leveling algorithm is determined to be a complete failure. In this embodiment, =1.36 does not exceed 2.0, and the effective trigger count is not less than 15 times out of 27, therefore the overall failure judgment is not triggered.

[0083] This embodiment achieves a comprehensive and accurate evaluation of wear balancing effectiveness by jointly determining the effective trigger rate and the wear extreme value span ratio, combined with dual verification of process indicators and final value indicators.

[0084] Figure 2 A schematic diagram of the functional modules of the solid-state drive wear leveling performance testing device according to an embodiment of the present invention is shown. Figure 2 As shown, the solid-state drive wear leveling performance testing device 20 includes an initialization module 21, a writing module 22, a pre-cleaning module 23, a recording module 24, a counting module 25, and a judgment module 26.

[0085] Initialization module 21 is used to initialize the solid-state drive under test, establish an initial state in which all data on the drive is static cold data, and obtain the baseline value of the idle NAND write rate in the initial state. The write module 22 is used to divide the logical address space into hot and cold areas, perform high-frequency overwrite without Trim instructions on the hot areas, and perform low-frequency write on the cold areas. The pre-cleaning module 23 is used to stop writing and enter the cache emptying pre-cleaning period when the high-frequency overwrite reaches the preset termination condition, and start the static observation window after the pre-cleaning is completed. Recording module 24 is used to acquire the NAND write rate sequence within the static observation window and extract time-domain and frequency-domain features from it. When the time domain exhibits continuous oscillation and the frequency domain exhibits low-frequency broadband, it records static transfer pulse events. The counting module 25 is used to obtain the minimum number of erases of the entire disk before and after the static observation window. If the minimum number of erases of the entire disk increases after the static observation window ends, the effective trigger count is accumulated. If the minimum number of erases of the entire disk does not increase but a static moving pulse event is recorded, the waveform abnormality count is accumulated. The judgment module 26 is used to generate a wear leveling performance judgment result based on the effective trigger count and waveform abnormal count when the above operations are performed by the writing module 22, the pre-cleaning module 23, the recording module 24, and the counting module 25 until the preset number of cycles is reached.

[0086] Optionally, after pre-purification, the pre-purification module 23 is also used for: Record the peak NAND write rate during the pre-cleaning period; When the pre-cleaning is finished, it is determined whether the current NAND write rate meets the preset conditions. The preset conditions include that the current NAND write rate does not exceed the peak value of the maximum NAND write rate multiplied by the first preset percentage, or the current NAND write rate does not exceed the baseline value of the idle NAND write rate plus the first preset tolerance. If the conditions are not met, the pre-purification preset time will be extended and re-verified until the preset conditions are met or the preset maximum number of extensions is reached.

[0087] Optionally, the recording module 24 performs the operation of acquiring the NAND write rate sequence, specifically including: The NAND physical write volume field in the SMART attribute is polled at a fixed period. The ratio of the difference between two consecutive polling results to the time interval is calculated to obtain the NAND write rate. The fixed period is determined according to the interface protocol type of the solid-state drive: if the solid-state drive is NVMe protocol, the first preset period is used; if the solid-state drive is SATA protocol, the second preset period is used. The second preset period is greater than the first preset period.

[0088] Optionally, the operation of extracting temporal features performed by the recording module 24 specifically includes: Calculate the first and second derivatives of the NAND write rate sequence, count the number of sign changes of the second derivative within the sliding window, and when the number of sign changes exceeds the preset oscillation threshold and continues to exceed the preset minimum duration, the time domain exhibits continuous oscillation. The specific operations performed by the recording module 24 to extract frequency domain features include: For the sampling points that are determined to be continuously oscillating in the time domain, perform a fast Fourier transform to calculate the power spectral density and the peak concentration of the power spectrum. The peak concentration is the ratio of the maximum power spectral density to the average power spectral density. When the peak concentration is lower than the first preset concentration threshold, the frequency domain exhibits a low-frequency broadband spectrum.

[0089] Optionally, after extracting the frequency domain features, the recording module 24 is also used for: If the frequency domain features do not show either low-frequency broadband or discrete main frequency, then calculate the background migration intensity ratio. The background migration intensity ratio is the ratio of the NAND write volume per unit time within the static observation window to the NAND write volume per unit time before the high-frequency coverage write reaches the preset termination condition. If the background migration intensity ratio exceeds the preset threshold, the current round will be marked as a weak trigger and included in the valid trigger count.

[0090] Optionally, when performing high-frequency overwrite and low-frequency write operations, the write module 22 is also used for: The average write latency and maximum write latency are collected at a preset collection period. If the average write latency exceeds a preset latency threshold, the coefficient of variation of the maximum write latency within a preset time window is calculated. If the coefficient of variation exceeds the first preset coefficient of variation threshold and the average write latency continues to rise, the write queue depth is halved. If the coefficient of variation is lower than the second preset coefficient of variation threshold and the average write latency is stable and high but no longer continues to rise, the current write queue depth is maintained. If the average write latency rises further to a preset multiple of the preset latency threshold, the average write completion latency is collected at a preset collection period, and an interrupt signal or a first termination signal is sent to the process performing the write operation to trigger the process to exit normally; if the process does not exit after receiving the first termination signal for a preset timeout period, a second termination signal is sent to forcibly terminate the process, and the device recovery operation is performed before continuing to the next round of testing.

[0091] Optionally, if obtaining the minimum number of erases for the entire disk fails, alternative values ​​for the minimum number of erases for the entire disk are obtained in the following priority order: First priority: Read the minimum wear count value in the SMART attribute as the replacement value for the minimum number of erases for the entire disk; Second priority: If the minimum wear count value is not found in the SMART attribute, then parse the NVMe Telemetry log page to obtain the minimum wear count value for each die, and take the minimum wear count value among the minimum wear count values ​​for each die as the replacement value for the minimum number of erases for the entire disk.

[0092] Optionally, the determination module 26 performs the operation of generating a wear leveling effectiveness determination result based on the valid trigger count and waveform anomaly count, specifically including: The effective trigger rate is calculated as the ratio of the effective trigger count to the total number of cycles. If the effective trigger rate is lower than the first preset threshold, the static wear leveling function is deemed to have failed. After all cycles are completed, obtain the maximum number of erases and the minimum number of erases on the entire disk. Calculate the wear extreme value span ratio, which is the difference between the maximum number of erases and the minimum number of erases on the entire disk divided by the minimum number of erases on the entire disk plus one. If the wear extreme value span ratio exceeds the second preset threshold and the effective trigger count is lower than the third preset threshold, the wear leveling algorithm is determined to be a complete failure.

[0093] For other details regarding the implementation of the technical solutions for each module in the solid-state drive wear leveling performance testing device in the above embodiments, please refer to the description in the solid-state drive wear leveling performance testing method in the above embodiments, which will not be repeated here.

[0094] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For apparatus embodiments, since they are basically similar to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0095] Please see Figure 3 , Figure 3 This is a schematic diagram of the structure of a computer device according to an embodiment of the present invention. Figure 3As shown, the computer device 30 includes a processor 31 and a memory 32 coupled to the processor 31. The memory 32 stores program instructions. When the program instructions are executed by the processor 31, the processor 31 performs the steps of the solid-state drive wear leveling performance test method of any of the above embodiments.

[0096] The processor 31 can also be referred to as a Central Processing Unit (CPU). The processor 31 may be an integrated circuit chip with signal processing capabilities. The processor 31 can also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. A general-purpose processor can be a microprocessor or any conventional processor.

[0097] See Figure 4 , Figure 4 This is a schematic diagram of the structure of a computer-readable storage medium according to an embodiment of the present invention. The computer-readable storage medium of this embodiment stores program instructions 41 capable of implementing the above-described solid-state drive wear leveling performance testing method. These program instructions 41 can be stored in the computer-readable storage medium in the form of a software product, including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods of various embodiments of this application. The aforementioned computer-readable storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks, or computer devices such as computers, servers, mobile phones, and tablets.

[0098] In the several embodiments provided in this application, it should be understood that the disclosed computer devices, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, or indirect coupling or communication connection between devices or units, and may be electrical, mechanical, or other forms.

[0099] Furthermore, the functional units in the various embodiments of this invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated units described above can be implemented in hardware or as software functional units. The above are merely embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made based on the description and drawings of this application, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method for testing the wear leveling performance of a solid-state drive, characterized in that, include: Step S1: Initialize the solid-state drive under test, establish an initial state in which all data on the drive is static cold data, and obtain the baseline value of the idle NAND write rate in the initial state. Step S2: Divide the logical address space into hot and cold areas, perform high-frequency overwrite on the hot areas without Trim instructions, and perform low-frequency write on the cold areas. Step S3: When the high-frequency overwrite reaches the preset termination condition, stop writing and enter the cache emptying pre-purification period. After the pre-purification is completed, start the static observation window. Step S4: Within the static observation window, acquire the NAND write rate sequence and extract time-domain and frequency-domain features from it. When the time domain exhibits continuous oscillation and the frequency domain exhibits low-frequency broadband, record the static transfer pulse event. Step S5: Obtain the minimum number of full disk erases before and after the static observation window. If the minimum number of full disk erases increases after the static observation window ends, accumulate the effective trigger count. If the minimum number of full disk erases does not increase but the static moving pulse event is recorded, accumulate the waveform abnormality count. Step S6: Repeat steps S2 to S5 until the preset number of cycles is reached, and generate a wear leveling performance determination result based on the effective trigger count and the waveform abnormality count.

2. The solid-state drive wear leveling performance testing method according to claim 1, characterized in that, After pre-purification, the process also includes: Record the peak NAND write rate during the pre-cleaning period; When the pre-cleaning is completed, it is determined whether the current NAND write rate meets the preset conditions. The preset conditions include that the current NAND write rate does not exceed the peak value of the maximum NAND write rate multiplied by a first preset percentage, or that the current NAND write rate does not exceed the baseline value of the idle NAND write rate plus a first preset tolerance. If the conditions are not met, the pre-purification preset time will be extended and re-verified until the preset conditions are met or the preset maximum number of extensions is reached.

3. The solid-state drive wear leveling performance testing method according to claim 1, characterized in that, The process of obtaining the NAND write rate sequence includes: The NAND physical write volume field in the SMART attribute is polled at a fixed period. The ratio of the difference between two consecutive polling results to the time interval is calculated to obtain the NAND write rate. The fixed period is determined according to the interface protocol type of the solid-state drive: if the solid-state drive is an NVMe protocol, a first preset period is used; if the solid-state drive is a SATA protocol, a second preset period is used. The second preset period is greater than the first preset period.

4. The solid-state drive wear leveling performance testing method according to claim 1, characterized in that, Extracting time-domain features includes: Calculate the first and second derivatives of the NAND write rate sequence, count the number of sign changes of the second derivative within the sliding window, and when the number of sign changes exceeds a preset oscillation threshold and continues to exceed a preset minimum duration, the time domain exhibits continuous oscillation. Extracting frequency domain features includes: For the sampling points that are determined to be continuously oscillating in the time domain, perform a fast Fourier transform to calculate the power spectral density and the peak concentration of the power spectrum. The peak concentration is the ratio of the maximum power spectral density to the average power spectral density. When the peak concentration is lower than a first preset concentration threshold, the frequency domain exhibits a low-frequency broadband spectrum.

5. The solid-state drive wear leveling performance testing method according to claim 1, characterized in that, After extracting frequency domain features, the process also includes: If the frequency domain features do not exhibit low-frequency broadband or discrete main frequency, then the background relocation intensity ratio is calculated. The background relocation intensity ratio is the ratio of the NAND write volume per unit time within the static observation window to the NAND write volume per unit time before the high-frequency coverage write reaches the preset termination condition. If the background relocation intensity ratio exceeds a preset threshold, the current round will be marked as a weak trigger and included in the valid trigger count.

6. The solid-state drive wear leveling performance testing method according to claim 1, characterized in that, When performing the high-frequency overwrite and the low-frequency write, the method further includes: The average write latency and maximum write latency are collected at a preset collection period. If the average write latency exceeds a preset latency threshold, the coefficient of variation of the maximum write latency within a preset time window is calculated. If the coefficient of variation exceeds a first preset coefficient of variation threshold and the average write latency continues to rise, the write queue depth is halved. If the coefficient of variation is lower than a second preset coefficient of variation threshold and the average write latency is stable at a high level but no longer continues to rise, the current write queue depth is maintained. If the average write latency further increases to a preset multiple of the preset latency threshold, the average write completion latency is collected at a preset collection period, and an interrupt signal or a first termination signal is sent to the process performing the write operation to trigger the process to exit normally; if the process does not exit after receiving the first termination signal for a preset timeout period, a second termination signal is sent to forcibly terminate the process, and the device recovery operation is performed before continuing to the next round of testing.

7. The solid-state drive wear leveling performance testing method according to claim 1, characterized in that, If obtaining the minimum number of erases for the entire disk fails, alternative values ​​for the minimum number of erases for the entire disk are obtained in the following priority order: First priority: Read the minimum wear count value from the SMART attribute as the replacement value for the minimum number of erases for the entire disk; Second priority: If the minimum wear count value does not exist in the SMART attribute, then parse the NVMe Telemetry log page to obtain the minimum wear count value of each die, and take the minimum value among the minimum wear count values ​​of each die as the replacement value of the minimum number of wipes for the entire disk.

8. The solid-state drive wear leveling performance testing method according to claim 1, characterized in that, The wear leveling performance determination result is generated based on the effective trigger count and the waveform anomaly count, including: The effective trigger count is calculated as the ratio of the effective trigger count to the total number of cycles as the effective trigger rate; if the effective trigger rate is lower than a first preset threshold, the static wear leveling function is determined to be ineffective. After all cycles are completed, obtain the maximum number of erases and the minimum number of erases on the entire disk, and calculate the wear extreme value span ratio. The wear extreme value span ratio is the difference between the maximum number of erases and the minimum number of erases on the entire disk divided by the minimum number of erases on the entire disk plus one. If the wear extreme value span ratio exceeds the second preset threshold and the effective trigger count is lower than the third preset threshold, then the wear leveling algorithm is determined to be a complete failure.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the solid-state drive wear leveling performance testing method as described in any one of claims 1 to 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the solid-state drive wear leveling performance testing method as described in any one of claims 1 to 8.

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