A multi-layer distributed reconfigurable shared bist architecture and a test method thereof

Abstract

This invention discloses a multi-layer distributed reconfigurable shared BIST architecture and its testing method, applicable to two-layer or higher three-dimensional vertically stacked SRAM storage arrays. The shared BIST architecture of this invention employs a three-level distributed hardware architecture: a global overall control BIST, layer-specific control BISTs, and array sub-BISTs. Combined with cross-layer hardware reuse, TSV test channels, layered low-power scheduling, parallel testing, precise fault location, and redundancy repair, it constitutes a complete test system that can be directly implemented. This invention also provides a testing method based on the multi-layer distributed reconfigurable shared BIST architecture, replacing conventional testing methods and solving the problems of large area overhead, low efficiency, high power consumption, insufficient fault coverage, and poor inter-layer coordination inherent in traditional BIST architectures that cannot adapt to 3D stacked SRAMs.

Description

Technical Field

[0001] This invention relates to the field of storage testing technology, and in particular to a multi-layered distributed reconfigurable shared BIST architecture and its testing method. Background Technology

[0002] Three-dimensional (3D) stacked static random access memory (SRAM) relies on through silicon via (TSV) vertical interconnect and multi-layer wafer bonding integration technology, and has significant advantages in terms of storage density and transmission bandwidth, and has become a core high-speed cache solution for high-end chips.

[0003] Traditional built-in self-test (BIST) architectures for memory are designed for single-layer chips. When applied to 3D stacked SRAMs, they suffer from technical problems such as high load on centralized control units, lengthy global routing, and poor stability. Each SRAM layer has its own independently configured BIST circuit, which consumes a lot of hardware resources and increases area overhead and cost dramatically. They only support single-layer serial testing and cannot achieve multi-layer parallel testing, resulting in low testing efficiency. They lack dedicated testing mechanisms for inter-layer TSVs, microbumps, and vertical interconnects, and cannot fully cover defects in 3D integrated structures. Test power consumption is highly concentrated, fault location accuracy is low, and they do not support heterogeneous capacity and heterogeneous bit width mixed stacking adaptation, resulting in extremely poor circuit versatility, portability, and scalability.

[0004] Currently, no existing technology, both domestically and internationally, has proposed a 3D SRAM multi-layer reconfigurable shared BIST architecture that features hierarchical decoupling, cross-layer hardware sharing, global collaborative scheduling, and integrated testing of storage and interconnection. There is a significant gap in related technical solutions. Summary of the Invention

[0005] The purpose of this invention is to provide a multi-layer distributed reconfigurable shared BIST architecture and its testing method to solve the problem that traditional single-layer centralized BIST architecture cannot adapt to 3D stacked SRAM.

[0006] To address the aforementioned technical issues, this invention provides a multi-layer distributed reconfigurable shared BIST architecture, applicable to two-layer or higher three-dimensional vertically stacked SRAM storage arrays. It employs a three-level distributed hardware architecture consisting of a global overall control BIST, a layer-specific control BIST, and array sub-BISTs. Combined with cross-layer hardware reuse, TSV test channels, layered low-power scheduling, parallel testing, precise fault location, and redundancy repair, it constitutes a complete test system that can be directly implemented. The multi-layer distributed reconfigurable shared BIST architecture includes: a global overall control BIST module, a layer-specific control BIST module, an array sub-BIST module, a TSV test bus, cross-layer reconfigurable shared hardware, a layered power consumption and clock management module, and a fault location and redundancy repair module. The global master control BIST module is located in the top logic area of ​​the chip and serves as the core of global unified scheduling. Each layer domain control BIST module communicates bidirectionally with the global master control BIST module through the TSV test bus. Each layer of SRAM is independently configured with a layer domain control BIST module, which is electrically connected to all array sub-BIST modules in the same layer. Only one set of cross-layer reconfigurable shared hardware is set up and uniformly allocated and scheduled by the global master control BIST module to achieve time-sharing multiplexing of the entire storage layer without the need for independent configuration of each layer.

[0007] In one implementation, the cross-layer reconfigurable shared hardware includes a high-precision linear shift register vector generator, a response compressor, a standard March algorithm operation unit, and a fault determination unit; and is shared globally across multiple layers and dynamically time-division multiplexed.

[0008] In one embodiment, the global master control BIST module mainly consists of a configuration register group, a global scheduling controller, a fault summary unit, a result output unit, a mode selection unit, and a reconfiguration control unit; The configuration register group is used to receive external test commands and complete the configuration of test algorithms, enable signals, number of test layers, and working modes. The global scheduling controller is used to issue synchronization control signals, layer selection signals, and test start signals. The fault aggregation unit is used to receive fault information uploaded from each level and complete data integration, address parsing and location marking. The mode selection unit enables switching between four modes: fully parallel testing, group testing, single-layer testing, and bypass testing. The reconfiguration control unit is used for shared hardware allocation and cross-layer reuse control.

[0009] In one implementation, each SRAM layer is configured with a lightweight layer-domain control BIST module, and a single-layer layer-domain control BIST module consists of a local control unit, a signal transceiver unit, a fault buffer unit, and a power management unit. The local control unit independently executes the test process of this layer and controls the BIST sub-modules of this layer to work synchronously. The signal transceiver unit completes data interaction with the global control center, adjacent levels, and shared hardware. The fault caching unit temporarily stores fault information of this layer, reducing the transmission load of the upper layer. The power management unit enables independent start-up and shutdown of the clock and power supply for this layer, achieving layered low-power operation.

[0010] In one implementation, each layer of the three-dimensional vertically stacked SRAM memory array integrates several independent SRAM macrocells, and each SRAM macrocell has a lightweight array sub-BIST module embedded inside. The array sub-BIST module consists of a simplified vector driving unit, a read / write control unit, a data comparison unit, and a response compression unit. The array sub-BIST module only completes basic stimulus input, data comparison, and fault signal output, while complex computational logic is uniformly executed by the top-level shared hardware.

[0011] In one embodiment, the TSV test bus consists of independent vertical interconnect channels, which are divided into a control bus, a data bus, and a fault bus. It is completely physically isolated from the functional signal paths, does not occupy functional ports and timing resources, and can realize the on / off status detection of the TSV itself.

[0012] In one implementation, the hierarchical power consumption clock control module implements independent power gating and clock gating for each layer, which is independently controlled by the layer-specific control BIST module. The layer under test is powered on and the timing is adjusted, while the non-test layers are kept powered off, effectively reducing peak power consumption and dynamic power consumption.

[0013] In one implementation, the fault location and redundancy repair module receives the output signal from the global control BIST module, latches the fault physical address, automatically maps redundant storage units, and completes the replacement of the fault unit.

[0014] This invention provides a multi-layer distributed reconfigurable shared BIST architecture and its testing method. It achieves multi-layer collaborative parallel testing through an intra-layer, inter-layer, and global BIST architecture, and establishes cross-layer reconfigurable shared hardware modules. This allows multi-layer stacked SRAMs to share a set of high-precision test vector generation, response data compression, standard test algorithm operation, and fault analysis and processing circuits, thereby improving testing efficiency while reducing hardware overhead. It is applicable to various high-performance three-dimensional integrated memory chips, processors, and artificial intelligence chips, and has extremely high engineering application value. Attached Figure Description

[0015] Figure 1 The overall system architecture block diagram provided by this invention.

[0016] Figure 2 A schematic diagram of the internal structure of a single-layer BIST provided by this invention.

[0017] Figure 3 The present invention provides a cross-layer hardware reuse structure diagram.

[0018] Figure 4 The present invention provides an overall testing workflow diagram. Detailed Implementation

[0019] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a more detailed account of the multi-layered distributed reconfigurable shared BIST architecture and its testing method proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0020] This invention discloses a multi-layer distributed reconfigurable shared BIST architecture and its testing method, applicable to two-layer or higher three-dimensional vertically stacked SRAM storage arrays. It employs a three-level distributed hardware architecture: a global overall control BIST, layer-specific control BISTs, and array sub-BISTs. Combined with cross-layer hardware reuse, dedicated TSV test channels, layered low-power scheduling, parallel testing, precise fault location, and redundancy repair, it constitutes a directly implementable complete testing system. The overall system architecture diagram is shown below. Figure 1 As shown.

[0021] In this embodiment, the 3D SRAM is a multi-layer vertically stacked structure, with each layer integrating several independent SRAM macrocells. The overall BIST architecture includes: a global control BIST module and layer-specific control BIST modules (layer-specific BIST1, ..., layer-specific BIST). N ), array sub-BIST modules (array BIST1, ..., array BIST) N It includes a dedicated TSV test bus, cross-layer reconfigurable shared hardware, a hierarchical power consumption and clock management module, and a fault location and redundancy repair module.

[0022] The global master control BIST module is located in the top logic area of ​​the chip and serves as the global unified scheduling core. Each layer domain control BIST module communicates bidirectionally with the global master control BIST module through the TSV test bus. Each SRAM layer is independently configured with a layer domain control BIST module, which is electrically connected to all array sub-BIST modules in the same layer. Only one set of cross-layer reconfigurable shared hardware is set up and uniformly allocated and scheduled by the global master control BIST module, realizing time-sharing multiplexing of the entire storage layer. There is no need for independent configuration of each layer, which greatly reduces hardware redundancy and area overhead.

[0023] The global master control (BIST) module mainly consists of a configuration register group, a global scheduling controller, a fault aggregation unit, a result output unit, a mode selection unit, and a reconfiguration control unit. The configuration register group receives external test commands and configures the test algorithm, enable signal, number of test layers, and operating mode. The global scheduling controller issues synchronization control signals, layer selection signals, and test start signals. The fault aggregation unit receives fault information uploaded from each layer and performs data integration, address resolution, and location marking. The mode selection unit switches between four modes: fully parallel testing, group testing, single-layer testing, and bypass testing. The reconfiguration control unit is used for shared hardware allocation and cross-layer multiplexing control.

[0024] Each SRAM layer is configured with a lightweight layer-domain controlled BIST module. The internal structure of a single-layer layer-domain controlled BIST module is as follows: Figure 2 As shown, it consists of a local control unit, a signal transceiver unit, a fault buffer unit, and a power management unit. The local control unit independently executes the test process of this layer and controls the synchronous operation of the BIST modules of this layer's array sub-modules; the signal transceiver unit completes data interaction with the global master control, adjacent layers, and shared hardware; the fault buffer unit temporarily stores fault information of this layer, reducing the transmission load of the upper layer; the power management unit realizes independent start-up and shutdown of the clock and power supply of this layer, achieving layered low-power operation.

[0025] Each SRAM macrocell embeds a lightweight array sub-BIST module, which consists of a simplified vector drive unit, a read / write control unit, a data comparison unit, and a response compression unit. The array sub-BIST module only handles basic stimulus input, data comparison, and fault signal output. Complex computational logic is uniformly executed by the top-level shared hardware, resulting in extremely low hardware overhead and a very small footprint.

[0026] The dedicated TSV test bus consists of independent vertical interconnect channels, divided into control bus, data bus, and fault bus. It is completely physically isolated from the functional signal paths, does not occupy functional ports or timing resources, and can also realize the on / off status detection of the TSV itself.

[0027] The core innovative structure of this invention is cross-layer reconfigurable shared hardware, such as... Figure 3 As shown, it includes a high-precision linear shift register (LFSR) vector generator, a response compressor, a standard March algorithm operation unit, and a fault determination unit; and it is shared globally across multiple layers and dynamically time-division multiplexed, reducing redundant circuits at the source and significantly reducing area and power consumption costs.

[0028] The layered power consumption and clock control module implements independent power gating and clock gating for each layer, which is independently controlled by the layer-specific control BIST module. The layer under test is powered on and the timing is adjusted, while the non-test layers remain powered off, effectively reducing peak power consumption and dynamic power consumption.

[0029] The fault location and redundancy repair module receives the output signal from the global control BIST module, latches the physical address of the fault, automatically maps redundant memory units, and completes the replacement of the faulty unit, effectively improving chip yield and reliability.

[0030] The complete workflow of the architecture of this invention is as follows: Figure 4 After the chip powers on, the system initializes. The global control BIST module completes the configuration parameters, test mode, algorithm parameters, and stacking layer configuration. The global scheduling controller issues layer enable commands to turn on the power and clock of the layer under test, while non-test layers remain low-power off. The reconfigured control unit allocates shared hardware and connects the corresponding layer test links. The global control BIST module synchronously issues start commands, and each layer executes the standard test process in parallel. The array sub-BIST modules complete read / write detection, data comparison, response compression, and fault reporting. Fault information is initially processed by the layer-specific control and then uploaded to the global control BIST module. The global control BIST module completes fault compression, parsing, and location, and outputs fault information. The system automatically completes redundancy repair and result output, completing all tests.

[0031] This invention establishes a three-level distributed collaborative structure of global overall control, hierarchical domain control, and array sub-BIST. Through a dedicated TSV test bus, cross-layer reconfigurable shared hardware modules, hierarchical power consumption management modules, and fault diagnosis and redundancy repair modules, it achieves full coverage testing of 3DSRAM.

[0032] This invention improves upon the traditional BIST architecture by proposing an intra-layer-inter-layer-global BIST architecture to achieve multi-layer collaborative parallel testing. It establishes cross-layer reconfigurable shared hardware modules, and multi-layer stacked SRAMs share a single high-precision test vector generation, response data compression, standard test algorithm operation, and fault analysis and processing circuit, thereby improving testing efficiency while reducing hardware overhead. It is applicable to various high-performance three-dimensional integrated memory chips, processors, and artificial intelligence chips, and has extremely high engineering application value.

[0033] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A multi-layered distributed reconfigurable shared BIST architecture, characterized in that, It is suitable for two-layer and above three-dimensional vertically stacked SRAM storage arrays. It adopts a three-level distributed hardware architecture of global master control BIST, layer domain control BIST, and array sub-BIST. Combined with cross-layer hardware reuse, TSV test channel, layered low-power scheduling, parallel testing, precise fault location and redundancy repair, it constitutes a complete test system that can be directly implemented. The multi-layer distributed reconfigurable shared BIST architecture includes: a global overall control BIST module, a layer-specific control BIST module, an array sub-BIST module, a TSV test bus, cross-layer reconfigurable shared hardware, a layered power consumption and clock management module, and a fault location and redundancy repair module. The global master control BIST module is located in the top logic area of ​​the chip and serves as the core of global unified scheduling. Each layer domain control BIST module communicates bidirectionally with the global master control BIST module through the TSV test bus. Each layer of SRAM is independently configured with a layer domain control BIST module, which is electrically connected to all array sub-BIST modules in the same layer. Only one set of cross-layer reconfigurable shared hardware is set up and uniformly allocated and scheduled by the global master control BIST module to achieve time-sharing multiplexing of the entire storage layer without the need for independent configuration of each layer.

2. The multi-layered distributed reconfigurable shared BIST architecture as described in claim 1, characterized in that, The cross-layer reconfigurable shared hardware includes a high-precision linear shift register vector generator, a response compressor, a standard March algorithm operation unit, and a fault determination unit; and it is shared globally across multiple layers and dynamically time-division multiplexed.

3. The multi-layered distributed reconfigurable shared BIST architecture as described in claim 1, characterized in that, The global master control BIST module mainly consists of a configuration register group, a global scheduling controller, a fault aggregation unit, a result output unit, a mode selection unit, and a reconfiguration control unit; The configuration register group is used to receive external test commands and complete the configuration of test algorithms, enable signals, number of test layers, and working modes. The global scheduling controller is used to issue synchronization control signals, layer selection signals, and test start signals. The fault aggregation unit is used to receive fault information uploaded from each level and complete data integration, address parsing and location marking. The mode selection unit enables switching between four modes: fully parallel testing, group testing, single-layer testing, and bypass testing. The reconfiguration control unit is used for shared hardware allocation and cross-layer reuse control.

4. The multi-layered distributed reconfigurable shared BIST architecture as described in claim 1, characterized in that, Each SRAM layer is configured with a lightweight layer-domain control BIST module. A single-layer layer-domain control BIST module consists of a local control unit, a signal transceiver unit, a fault buffer unit, and a power management unit. The local control unit independently executes the test process of this layer and controls the BIST sub-modules of this layer to work synchronously. The signal transceiver unit completes data interaction with the global control center, adjacent levels, and shared hardware. The fault caching unit temporarily stores fault information of this layer, reducing the transmission load of the upper layer. The power management unit enables independent start-up and shutdown of the clock and power supply for this layer, achieving layered low-power operation.

5. The multi-layered distributed reconfigurable shared BIST architecture as described in claim 1, characterized in that, Each layer of the three-dimensional vertically stacked SRAM storage array integrates several independent SRAM macrocells, and each SRAM macrocell has a lightweight array sub-BIST module embedded inside. The array sub-BIST module consists of a simplified vector driving unit, a read / write control unit, a data comparison unit, and a response compression unit. The array sub-BIST module only completes basic stimulus input, data comparison, and fault signal output, while complex computational logic is uniformly executed by the top-level shared hardware.

6. The multi-layered distributed reconfigurable shared BIST architecture as described in claim 1, characterized in that, The TSV test bus consists of independent vertical interconnect channels, divided into control bus, data bus, and fault bus. It is completely physically isolated from the functional signal path, does not occupy functional ports and timing resources, and can realize the on / off status detection of TSV itself.

7. The multi-layered distributed reconfigurable shared BIST architecture as described in claim 1, characterized in that, The layered power consumption and clock control module implements independent power gating and clock gating for each layer, which is independently controlled by the layer-specific control BIST module. The layer under test is powered on and the timing is adjusted, while the non-test layers are kept powered off, effectively reducing peak power consumption and dynamic power consumption.

8. The multi-layered distributed reconfigurable shared BIST architecture as described in claim 1, characterized in that, The fault location and redundancy repair module receives the output signal from the global control BIST module, latches the physical address of the fault, automatically maps redundant storage units, and completes the replacement of the faulty unit.

9. A testing method based on the multi-layered distributed reconfigurable shared BIST architecture according to any one of claims 1-8, characterized in that, The process includes the following steps: After the chip is powered on, the system initializes, and the global control BIST module completes the configuration parameters, test mode, algorithm parameters, and stacking layer configuration; the global scheduling controller issues a layer enable command to turn on the power and clock of the layer under test, while the non-test layers remain low-power off; the reconfigured control unit allocates shared hardware and connects the corresponding layer test links; the global control BIST module synchronously issues a start command, and each layer executes the standard test process in parallel. The array sub-BIST module completes read / write detection, data comparison, response compression, and fault reporting; after preliminary processing by the layer-level sub-control, the fault information is uploaded to the global control BIST module; the global control BIST module completes fault compression, parsing, and location, and outputs the fault information. The system automatically completes redundancy repair and results output, completing all tests.

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