A solid state disk abnormal power-off test method and test system

Abstract

The application discloses a solid state disk abnormal power-off test method and a test system. The method comprises the following steps: sending an IO command for triggering power-off judgment to a solid state disk to be tested; acquiring the response time of each IO command from the time of sending to the current time in real time; generating a power-off trigger signal when the response time of any IO command exceeds a preset timeout threshold and the completion confirmation signal of the IO command has not been received; outputting the power-off trigger signal through a physical control channel to cut off the power supply of the solid state disk to be tested; acquiring a pre-calibrated delay duration, calculating the actual power-off occurrence time of the solid state disk after the solid state disk is powered on again, locking the logical address set in the write state within the preset time period before and after the actual power-off occurrence time; and performing consistency verification on the data in the logical address set. The application can reliably implement abnormal power-off when the solid state disk is in a high-load processing stage, and improve the stability and repeatability of the power-off test.

Description

Technical Field

[0001] This application belongs to the field of solid-state drive technology, specifically relating to a method and system for testing abnormal power loss of solid-state drives. Background Technology

[0002] Solid-state drives (SSDs) have been widely used in various computing devices due to their advantages such as high-speed read / write speeds and low power consumption. However, in real-world use, abnormal power loss is a significant factor threatening the reliability of SSDs, potentially leading to data loss, file system corruption, or even device boot failure. Therefore, abnormal power loss testing has become an indispensable reliability verification step before SSDs leave the factory and during the research and development phase.

[0003] Current abnormal power-down tests mostly use preset timings and fixed periods to trigger power outages, and then verify the data integrity after power is restored. They cannot specifically implement power-downs during periods of high internal load processing. Furthermore, when executing a power-down action, the SSD relies on its own data transmission or control interface to transmit the power-down command to the power supply. When the SSD experiences internal blockage due to high load, the data transmission and control interfaces may fail to respond properly to external signals, resulting in unreliable delivery and execution of the power-down command. This leads to insufficient stability and repeatability of the test. Summary of the Invention

[0004] This application provides a method and system for testing abnormal power loss of solid-state drives (SSDs), which can reliably implement abnormal power loss when the SSD is under high load processing, improve the stability and repeatability of power loss testing, and enhance verification efficiency while improving fault location accuracy.

[0005] To address the aforementioned technical problems, this application provides a method for testing abnormal power loss in solid-state drives, comprising the following steps: Send an I / O command to the solid-state drive under test to trigger a power failure detection; Record the sending time of each IO command and obtain the response time of each IO command from the sending time to the current time in real time; When the response time of any IO command exceeds a preset timeout threshold and the completion confirmation signal of the IO command has not been received, a power failure trigger signal is generated. The power-down trigger signal is output through a physical control channel that is independent of the data transmission interface and control interface of the solid-state drive under test, so as to cut off the power supply to the solid-state drive under test. Record the time when the power failure trigger signal is issued, and obtain the pre-calibrated delay duration, which is the time interval from the issuance of the power failure trigger signal to the actual cut-off of the power supply to the solid-state drive; After the solid-state drive is powered on again, the actual time of power failure of the solid-state drive is calculated based on the time of the power failure trigger signal and the delay time, and the set of logical addresses in the writing state within a preset time period before and after the actual time of power failure is locked. Perform a consistency check on the data within the logical address set to obtain the fault check result.

[0006] As a further improvement to this application, the IO commands include at least file system log update commands, inode modification commands, and partition table operation commands.

[0007] As a further improvement to this application, the generation of the power-down trigger signal includes: A state feature vector is constructed based on the multi-source operating state characteristics of the tested solid-state drive; the multi-source operating state characteristics include at least the response time of each IO command, the temperature change rate, and the change rate of the operating state parameters of the tested solid-state drive; The state feature vector is input into a pre-trained state assessment model to obtain the confidence level that the tested solid-state drive has entered a high-risk working state. When the confidence level exceeds a preset threshold, and the response time exceeds a preset timeout threshold and the completion confirmation signal has not been received, the power failure trigger signal is generated.

[0008] As a further improvement of this application, when the power failure trigger signal is generated, the power failure trigger signal is output in advance by the pre-calibrated delay time so that the actual power failure time is aligned with the target high-risk window; The target high-risk window is a time period of preset duration, starting from the moment when the response time exceeds the preset timeout threshold and the completion confirmation signal has not yet been received.

[0009] As a further improvement to this application, the physical control channel is any one of a GPIO channel, an independent USB channel, or an Ethernet control channel.

[0010] As a further improvement to this application, after cutting off the power supply to the tested solid-state drive, the method further includes: The temperature of the environment in which the solid-state drive under test is located is controlled to change according to a preset temperature change process, and the solid-state drive under test is controlled to be in a power-off and static state during the temperature change process. After the temperature change process is completed, the solid-state drive is powered on again.

[0011] As a further improvement to this application, the set of logical addresses in a write state within a preset time period before and after the actual power failure time includes: The sending time, starting logical address, and address length of each write operation are recorded in real time through a circular buffer. The circular buffer is retrieved based on the calculated actual power outage time. Obtain all logical address ranges in write state within a preset time period before and after the actual power failure time to obtain the logical address set.

[0012] As a further improvement to this application, the step of performing consistency verification on the data within the logical address set includes: The data within the logical address set are subjected to a first check, a second check, and a third check in sequence; The first verification includes checking the integrity of the file system logs on the tested solid-state drive and whether the directory structure is continuous. The second verification includes comparing the current data in the logical address set with the preset feature code written before the power failure, and judging whether the flash memory translation layer mapping relationship is abnormal based on the comparison result; The third verification includes reading the monitoring logs of the tested solid-state drive through a standard protocol and statistically analyzing the changes in operating status parameters before and after a power outage.

[0013] As a further improvement to this application, after obtaining the fault verification result, the method further includes: The degradation characteristics of the tested solid-state drive after the power outage are obtained, and the degradation characteristics include at least the growth rate of the number of bad blocks and the changes in the operating status parameters. The first-order and second-order rates of change of the degradation characteristics are calculated to construct a power-loss erosion index; wherein the power-loss erosion index is a multi-dimensional vector composed of the first-order and second-order rates of change; The values ​​of each dimension in the power loss erosion index are compared with the values ​​of the corresponding dimensions in the preset benchmark vector. When the value of any dimension exceeds the corresponding threshold in the preset benchmark vector, the test on the solid-state drive under test is terminated.

[0014] As a further improvement to this application, this application also provides a solid-state drive abnormal power loss testing system, including: The sending unit is used to send IO commands to the solid-state drive under test to trigger power failure detection; The acquisition unit is used to record the sending time of each IO command and to acquire the response time of each IO command from the sending time to the current time in real time; The generation unit is used to generate a power-down trigger signal when the response time of any IO command exceeds a preset timeout threshold and the completion confirmation signal of the IO command has not yet been received. An execution unit is configured to output the power-down trigger signal through a physical control channel independent of the data transmission interface and control interface of the solid-state drive under test, so as to cut off the power supply to the solid-state drive under test. The acquisition unit is used to record the time when the power failure trigger signal is issued and to obtain a pre-calibrated delay duration, wherein the delay duration is the time interval from the issuance of the power failure trigger signal to the actual cut-off of the power supply to the solid-state drive; The locking unit is used to calculate the actual power failure time of the solid-state drive based on the time of the power failure trigger signal and the delay time after the solid-state drive is powered on again, and lock the set of logical addresses in the write state within a preset time period before and after the actual power failure time. The verification unit is used to perform consistency verification on the data within the logical address set and obtain the fault verification result.

[0015] This application provides a method and system for testing abnormal power loss of a solid-state drive (SSD). The method sends I / O commands to the SSD under test to trigger a power loss determination, synchronously records the sending time of each I / O command, and calculates the response time from the sending time in real time. When the response time of any I / O command exceeds a preset threshold and no completion confirmation is received, a power loss trigger signal is generated. Compared to the conventional method of fixed-time triggering, this method ensures that the power loss action occurs during the high-load processing phase of the SSD, more closely reflecting the actual sudden power loss conditions in operation. The power loss trigger signal is output through a physical control channel independent of the SSD's data transmission interface and control interface, without... The interface controller of the solid-state drive (SSD) needs to participate in the response, which can avoid the problem that the power-down command cannot be delivered and executed when the SSD is blocked or the interface is unresponsive, thus ensuring the stability and reliability of the power cut-off action. During the test, the time of the power-down trigger signal and the pre-calibrated power cut-off delay are recorded simultaneously. After the SSD is powered on again, the actual time of power failure is calculated based on the two time parameters. The set of logical addresses in the write state within the preset time period before and after that time is locked and consistency verification is performed. Compared with the conventional verification method of full disk scanning, it can accurately correspond to the impact range of a single power failure, improving the accuracy of fault location and the verification efficiency. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only a part of the embodiments of this application, and not all of the embodiments. For those skilled in the art, other drawings obtained from these drawings without creative effort are all within the scope of protection of this application.

[0017] Figure 1A flowchart of a solid-state drive abnormal power loss test method provided in an embodiment of this application.

[0018] Figure 2 This is a flowchart illustrating the generation of a power-down trigger signal in the solid-state drive abnormal power-down test method provided in this application embodiment.

[0019] Figure 3 This is a flowchart illustrating the temperature change process in the solid-state drive abnormal power-down test method provided in this application embodiment.

[0020] Figure 4 A flowchart illustrating the process of obtaining the logical address set in the solid-state drive abnormal power-down test method provided in this application embodiment.

[0021] Figure 5 This is a flowchart illustrating the consistency check performed in the solid-state drive abnormal power failure test method provided in this application embodiment.

[0022] Figure 6 This is a flowchart illustrating the construction of the power-loss erosion index in the solid-state drive abnormal power-loss test method provided in this application embodiment.

[0023] Figure 7 This is a functional block diagram of the solid-state drive abnormal power failure test system provided in an embodiment of this application. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0025] To make the description of this disclosure more detailed and complete, illustrative descriptions of the implementation methods and specific embodiments of this application are provided below; however, this is not the only form of implementing or utilizing the specific embodiments of this application. The implementation methods cover the features of multiple specific embodiments and the method steps and their order for constructing and operating these specific embodiments. However, other specific embodiments can also be used to achieve the same or equivalent functions and step sequences. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein.

[0027] In the description of the embodiments of this application, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The word "and / or" in the text is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of this application, "multiple" means two or more. Other quantifiers should be understood similarly. The preferred embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. Furthermore, the embodiments of this application and the features in the embodiments can be combined with each other without conflict.

[0028] Solid-state drives (SSDs) have been widely used in various computing devices due to their advantages such as high-speed read / write speeds and low power consumption. However, in real-world use, abnormal power loss is a significant factor threatening the reliability of SSDs, potentially leading to data loss, file system corruption, or even device boot failure. Therefore, abnormal power loss testing has become an indispensable reliability verification step before SSDs leave the factory and during the research and development phase.

[0029] Current abnormal power-down tests mostly use preset timings and fixed periods to trigger power outages, and then verify the data integrity after power is restored. They cannot specifically implement power-downs during periods of high internal load processing. Furthermore, when executing a power-down action, the SSD relies on its own data transmission or control interface to transmit the power-down command to the power supply. When the SSD experiences internal blockage due to high load, the data transmission and control interfaces may fail to respond properly to external signals, resulting in unreliable delivery and execution of the power-down command. This leads to insufficient stability and repeatability of the test.

[0030] In view of this, please refer to Figures 1-7 This application proposes a method and system for testing abnormal power loss of solid-state drives (SSDs), which can reliably implement abnormal power loss when the SSD is under high load processing, improve the stability and repeatability of power loss testing, and enhance verification efficiency while improving fault location accuracy.

[0031] Please refer to Figure 1 This is a flowchart of a solid-state drive (SSD) abnormal power-loss testing method provided in this application embodiment. The SSD abnormal power-loss testing method includes the following steps: Step S1: Send an I / O command to the solid-state drive under test to trigger a power failure detection; In this embodiment of the application, the test host establishes a standard data transmission interface connection with the solid-state drive under test, and sends IO (Input / Output) commands to the solid-state drive under test through the data transmission interface to trigger power failure determination.

[0032] Furthermore, the act of sending I / O commands to the SSD under test is continuous throughout the load operation phase of the entire test process, not just once at the start of the test. During the test, I / O commands are continuously generated and sent to the SSD under test through the aforementioned data transmission interface to ensure that the SSD under test remains in an active working state throughout the entire test cycle.

[0033] As an optional implementation, the IO commands include at least file system log update commands, inode modification commands, and partition table operation commands.

[0034] In an optional embodiment, the IO commands include at least file system log update commands, inode modification commands, and partition table operation commands.

[0035] Among them, the file system log update command refers to the IO command generated by the test host when writing or committing to the file system log, which involves modifying the file system log structure; the inode modification command refers to the IO command generated by the test host when creating, deleting, or renaming files or directories, which involves updating the file system inode data structure; and the partition table operation command refers to the IO command generated by the test host when changing the logical partition layout information of the storage device.

[0036] It is understandable that the three IO commands in the above examples directly affect the core metadata structure of the file system. If an abnormal power outage occurs during the execution of these commands, it may lead to failures such as corrupted file system logs, inconsistent inodes, or corrupted partition tables. The recovery difficulty of these failures is usually higher than that of ordinary user data loss. Therefore, this application preferably uses the above-mentioned file system log update commands, inode modification commands, and partition table operation commands as IO commands to trigger power outage detection, so that power outage testing can cover potential failures at the file system level.

[0037] It should be noted that in practical applications, other types of IO commands can also be selected as IO commands to trigger power failure detection according to specific testing requirements, as long as the execution of such commands can reflect whether the solid-state drive is in a state that is easily damaged by power failure. This application does not impose too many restrictions on this.

[0038] Step S2: Record the sending time of each IO command, and obtain the response time of each IO command from the sending time to the current time in real time; In this embodiment, the test host records the sending time of each IO command sent to the solid-state drive under test through the data transmission interface. The sending time refers to the moment when the test host writes the IO command into the sending buffer of the data transmission interface. This moment can be obtained through the system clock of the test host, with an accuracy of microseconds or higher.

[0039] Furthermore, while recording the sending time, the test host calculates the response time of the IO command in real time. The response time refers to the time elapsed from the sending time of the IO command to the current time. Moreover, the test host obtains the response time of the IO command from the sending time to the current time in real time, rather than performing the calculation only once at a specific moment.

[0040] By acquiring response time in real time, the test host can dynamically monitor the response time of each IO command from its issuance to the current moment, thus providing a basis for subsequent judgment on whether a power failure trigger signal needs to be generated.

[0041] It is understandable that the response time of an I / O command directly reflects the processing progress and internal load status of the tested SSD for the current command. In this embodiment, the sending time and response time of each I / O command are mutually corresponding; one I / O command corresponds to one sending time and one real-time updated response time. When the test host sends multiple I / O commands simultaneously to trigger power failure detection, the sending time and response time of each I / O command are recorded and calculated separately without interference.

[0042] Step S3: When the response time of any IO command exceeds a preset timeout threshold and the completion confirmation signal of the IO command has not been received, a power failure trigger signal is generated. In this embodiment, the test host continuously monitors the response time of each IO command acquired in real time in step S2. When it is detected that the response time of any IO command exceeds a preset timeout threshold, and the completion confirmation signal of the IO command has not yet been received by the test host, the test host generates a power-down trigger signal.

[0043] It is understood that the above-mentioned preset timeout threshold is a time length parameter, which can be pre-configured according to the model of the solid-state drive under test, the requirements of the test scenario, and the actual usage environment. This application does not limit the specific duration of the timeout threshold.

[0044] Furthermore, a completion confirmation signal refers to a response signal returned by the SSD under test to the test host through the data transmission interface after completing the operation requested by an I / O command, indicating that the I / O command has been executed. If the response time of an I / O command has exceeded the timeout threshold, and the test host has not yet received a completion confirmation signal for the I / O command, it indicates that the SSD under test has spent more than the normal time processing the I / O command internally, and may be in a busy, blocked, or some kind of abnormal processing state. In this case, powering down the SSD under test can target periods of high processing pressure.

[0045] Furthermore, as long as the response time of any IO command exceeds the preset timeout threshold and the completion confirmation signal has not been received, a power-down trigger signal will be generated immediately without waiting for all IO commands to meet the conditions. This allows for a faster response to abnormal changes in the internal state of the tested SSD, reduces latency caused by waiting, and improves the accuracy of the power-down trigger timing.

[0046] As an optional implementation method, please refer to Figure 2 This is a flowchart illustrating the generation of a power-down trigger signal in the solid-state drive abnormal power-down test method provided in this application embodiment. The generation of the power-down trigger signal includes: Step S30: Construct a state feature vector based on the multi-source operating state characteristics of the tested solid-state drive; the multi-source operating state characteristics include at least the response time of each IO command, the temperature change rate, and the change rate of the operating state parameters of the tested solid-state drive; Step S31: Input the state feature vector into the pre-trained state evaluation model to obtain the confidence level of the tested solid-state drive entering a high-risk working state; Step S32: When the confidence level exceeds a preset threshold, and the response time exceeds a preset timeout threshold and the completion confirmation signal has not been received, the power-down trigger signal is generated.

[0047] In an optional embodiment, the generation of the power-down trigger signal is not based solely on a single response time, but rather on a comprehensive judgment combining multiple source operating state characteristics of the SSD under test. The test host collects the multiple source operating state characteristics of the SSD under test and constructs a state feature vector based on these characteristics.

[0048] Specifically, the multi-source operating status characteristics include at least the response time of each IO command, the temperature change rate, and the change rate of the operating status parameters of the tested solid-state drive; among them, the response time of each IO command refers to the response time of each IO command from the time of sending to the current time, which is calculated in real time in S2; the temperature change rate refers to the change of temperature of the environment in which the tested solid-state drive is located per unit time, which can be obtained by temperature sensor.

[0049] Furthermore, operational status parameters refer to various parameters that reflect the internal working status of the solid-state drive under test, read from its monitoring logs via standard protocols, such as the number of bad blocks, the number of abnormal power outages, and the power-on recovery time. The rate of change of operational status parameters refers to the ratio of the change in these parameters between two consecutive samples to the sampling interval. This application combines the above-mentioned multi-source operational status features to form a multi-dimensional status feature vector, so as to describe the current operational status of the solid-state drive under test from multiple dimensions.

[0050] Based on this, the constructed state feature vector is input into a pre-trained state assessment model. This state assessment model is an offline-trained machine learning model, whose training data comes from multi-source operating state feature samples and corresponding state labels collected from solid-state drives of the same model or type under known operating conditions. After processing the input state feature vector, the state assessment model outputs a confidence score, which represents the probability that the tested solid-state drive is currently in a high-risk operating state. The confidence score typically ranges from 0 to 1, with higher values ​​indicating a greater probability that the tested solid-state drive is in a high-risk operating state.

[0051] It should be noted that the specific training method of the above-mentioned state assessment model belongs to the existing technology in the field of model training. Those skilled in the art can train the model by combining the collected sample data with existing model training frameworks, such as gradient boosting trees, support vector machines or neural networks. Therefore, this application will not describe the specific training process of the state assessment model in detail.

[0052] Specifically, when the confidence level output by the state assessment model exceeds a preset threshold, and the response time exceeds a preset timeout threshold and the completion confirmation signal has not been received, the test host will generate a power failure trigger signal.

[0053] Compared to using response time alone, the method of superimposing confidence judgment introduces additional state dimensions such as temperature change rate and change rate of operating status parameters. It can further confirm whether the overall internal state of the tested solid-state drive is indeed in a high-risk range based on abnormal IO command response time, thereby reducing false triggers caused by occasional IO latency fluctuations and improving the accuracy of power-down triggers.

[0054] As an optional implementation, when the power-down trigger signal is generated, the power-down trigger signal is output with a pre-calibrated delay time in advance, so that the actual power-down time is aligned with the target high-risk window; The target high-risk window is a time period of preset duration, starting from the moment when the response time exceeds the preset timeout threshold and the completion confirmation signal has not yet been received.

[0055] In this embodiment of the application, when a power failure trigger signal is generated, the test host does not immediately output the power failure trigger signal, but outputs it after a pre-defined delay period.

[0056] Specifically, the aforementioned advance output refers to sending the signal a certain amount of time before the power-down trigger signal is generated. The pre-calibrated delay time is the time interval between sending the power-down trigger signal and the actual disconnection of the power supply to the solid-state drive under test. This time interval is obtained in advance through the calibration process before the test begins.

[0057] In an optional embodiment, before the formal test begins, the test host sends a test power-down trigger signal to the physical control channel. At the same time, the waveform of the power-down trigger signal at the time of its transmission and the voltage drop waveform on the power supply pin of the solid-state drive under test are acquired simultaneously using a measuring device such as an oscilloscope or logic analyzer. The time difference between the transition edges of the two waveforms is measured and used as the pre-calibrated delay duration.

[0058] Furthermore, this calibration process is part of the test preparation and does not depend on the response of the data transfer interface or control interface of the solid-state drive under test. Once the latency duration is obtained in advance using the above method, it can be directly read and used during subsequent testing, without needing to remeasure it each time a power outage triggers. Of course, other methods for pre-calibrating latency duration are also feasible, and this application does not impose any restrictions on them.

[0059] Thus, by outputting the power-down trigger signal in advance, this application can offset the delay caused by the subsequent physical control channel and power cut-off action, so that the moment when the power supply to the tested solid-state drive is actually cut off is as close as possible to the target high-risk window corresponding to when the power-down trigger signal is generated.

[0060] In this embodiment, the target high-risk window is a time period. This time period begins when the response time exceeds a preset timeout threshold and a completion confirmation signal has not yet been received, and continues for a preset duration from this starting point. The preset duration can be configured according to the response characteristics of the SSD under test and the testing requirements. When the power supply to the SSD under test is actually cut off within this time period, it indicates that the power outage occurred precisely during a period when the SSD under test is in a high-risk state, which helps ensure the accuracy of the power outage test in identifying potential faults.

[0061] Step S4: Output the power-down trigger signal through a physical control channel that is independent of the data transmission interface and control interface of the solid-state drive under test, so as to cut off the power supply to the solid-state drive under test; In this embodiment of the application, after the test host generates a power-down trigger signal in step S3, it does not transmit the power-down trigger signal through the data transmission interface that previously interacted with the solid-state drive under test for IO command communication, nor does it transmit the power-down trigger signal through the control interface of the solid-state drive under test. Instead, it outputs the power-down trigger signal to the power supply control circuit through a physical control channel that is independent of the above two interfaces.

[0062] Specifically, the aforementioned data transmission interface refers to the standard communication interface used between the test host and the solid-state drive under test for transmitting I / O commands and data, such as the NVMe (Non-Volatile Memory Express) protocol interface or the SATA (Serial Advanced Technology Attachment) protocol interface. The aforementioned control interface refers to the interface through which the test host sends management commands to the solid-state drive under test, such as interfaces used for sending reset commands and querying device status.

[0063] It's understandable that when the SSD under test enters a high-risk operating state, its data transmission and control interfaces are likely already busy, blocked, or even suspended, unable to receive and respond to commands from the test host. If a power-down command is still sent to the SSD under test through the data transmission or control interfaces at this time, the SSD may not be able to receive or process the command at all, causing the power-down action to fail.

[0064] The physical control channel is a signal path that is physically independent of the data transmission and control interfaces of the SSD under test. Its signal transmission does not depend on whether the SSD under test is in a normal response state. Therefore, even if the data transmission and control interfaces of the SSD under test are no longer working properly, the power-down trigger signal can still be successfully transmitted to the power supply control circuit through the physical control channel, ensuring the reliable execution of the power-down action.

[0065] Upon receiving a power-down trigger signal, the power supply control circuit will cut off the power supply to the solid-state drive under test. Cutting off the power supply means disconnecting the power voltage input to the solid-state drive under test, causing it to stop working.

[0066] In an alternative embodiment, the power supply control circuit may be composed of high-speed switching devices, such as MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) switches, to achieve fast and reliable power supply cut-off.

[0067] As an optional implementation, the physical control channel is any one of a GPIO channel, a standalone USB channel, or an Ethernet control channel.

[0068] Optionally, the physical control channel can be implemented as any one of a GPIO (General Purpose Input / Output) channel, a standalone USB (Universal Serial Bus) channel, or an Ethernet control channel.

[0069] Among them, the GPIO channel refers to the general-purpose input / output pins on the test host motherboard, which transmit power-down trigger signals through level changes. Its advantages include low transmission latency and simple implementation. The dedicated USB channel is a USB connection line dedicated to transmitting the power-down trigger signal; this USB channel is not shared with the data transmission interface of the SSD under test. The Ethernet control channel sends power-down commands to network-controlled power devices via a network interface, suitable for scenarios where there is a network connection between the test host and the power supply unit of the SSD under test. All three channels are physically independent of the data transmission and control interfaces of the SSD under test, ensuring that the power-down trigger signal can still be transmitted normally when the SSD's interface is suspended.

[0070] As an optional implementation method, please refer to Figure 3 This is a flowchart illustrating the temperature change process in the solid-state drive abnormal power-loss testing method provided in this application embodiment. After cutting off the power supply to the solid-state drive under test, the method further includes: Step S40: Control the temperature of the environment where the solid-state drive under test is located to change according to a preset temperature change process, and control the solid-state drive under test to be in a power-off and static state during the temperature change process; Step S41: After the temperature change process is completed, perform the step of powering the solid-state drive back on.

[0071] In an optional embodiment, a temperature control step can be performed after the power supply to the solid-state drive under test is cut off and before it is powered on again to simulate the impact of temperature changes in the storage environment after a power outage on the solid-state drive's data retention capability.

[0072] Specifically, the temperature of the environment in which the tested solid-state drive is located is controlled to change according to a preset temperature change process. The preset temperature change process refers to a pre-configured set of parameters for temperature changes over time. For example, the device can be kept at a high temperature for a period of time, and then cooled down to room temperature at a certain rate to simulate temperature change scenarios that the device may experience after power failure, such as day-night temperature differences and cooling down after being exposed to high temperatures. During the execution of the temperature change process, the solid-state drive under test remains in a power-off and static state, that is, it is not powered on or any I / O commands are sent to it.

[0073] After the preset temperature change process is completed, the SSD under test can be allowed to rest for a while before being powered on again. This is followed by the subsequent fault verification process. By performing the above temperature control and power-off resting steps, the SSD under test undergoes a temperature change similar to the actual storage environment after power failure. This ensures that the fault verification results obtained after power-on can reflect the impact of temperature changes on data retention capabilities after power failure.

[0074] Step S5: Record the time when the power failure trigger signal is issued, and obtain the pre-calibrated delay duration, which is the time interval from the issuance of the power failure trigger signal to the actual cut-off of the power supply to the solid-state drive; In this embodiment, after the power-down trigger signal is generated in step S3, and while the test host outputs the power-down trigger signal through the physical control channel in step S4, it simultaneously records the time at which the power-down trigger signal is emitted. The emission time here refers to the moment when the power-down trigger signal is output from the test host to the physical control channel, which can be obtained through the test host's system clock.

[0075] Simultaneously, the test host acquires a pre-calibrated delay duration. This delay duration is the same parameter as the delay duration used for advance output in step S3, both referring to the time interval between the issuance of the power-down trigger signal and the actual cutting off of power to the solid-state drive under test.

[0076] Specifically, in an optional implementation of step S3, the delay duration is used for pre-compensation, that is, the delay duration is output in advance after the power-down trigger signal is generated to offset the transmission and action delay of the hardware link; while in step S5, the delay duration is used for post-calculation, that is, the actual power-down time is deduced by combining the time when the power-down trigger signal is issued, providing a basis for locking the logical address set in subsequent steps.

[0077] It is understood that the delay durations used in steps S3 and S5 both originate from the same pre-calibration and have the same value. This application will not elaborate further on the pre-calibration method for implementing the delay duration.

[0078] It's important to note that there is inevitably a time interval between the issuance of the power-down trigger signal and the actual disconnection of power to the SSD under test. This is because the transmission of the power-down trigger signal in the physical control channel, the operation of switching devices in the power supply control circuit, and the discharge of capacitors in the SSD's power supply circuit all require time to complete. If this time interval is ignored and the issuance of the power-down trigger signal is directly taken as the actual power-down occurrence, a discrepancy will arise between the logical address set subsequently locked based on the actual power-down occurrence and the logical address range where write operations were being performed at the time of the power-down, affecting the accuracy of fault verification.

[0079] Step S6: After the solid-state drive is powered on again, the actual time of power failure of the solid-state drive is calculated based on the time of the power failure trigger signal and the delay time, and the set of logical addresses in the writing state within a preset time period before and after the actual time of power failure is locked. In this embodiment, after the power supply to the solid-state drive under test is cut off in step S4 and the required rest period is completed, the solid-state drive under test is powered on again. After power-on, the test host needs to determine the specific moment when the power failure actually occurred in order to subsequently lock the logical address range in which the write operation was being performed at the moment of power failure.

[0080] Since the power-down trigger signal in step S4 is transmitted to the power supply control circuit through a physical control channel independent of the data transmission interface and control interface, the time from when the test host outputs the power-down trigger signal to when the power supply control circuit actually cuts off the power supply to the SSD under test involves signal transmission through the physical control channel, the operation of switching devices in the power supply control circuit, and capacitor discharge in the power supply circuit of the SSD under test. These processes inevitably consume a certain amount of time. Therefore, the actual time when the power-down occurs is not the same as the time when the power-down trigger signal is issued, but rather occurs after the aforementioned delay.

[0081] For the reasons mentioned above, the test host uses the power-down trigger signal's emission time recorded in step S5 and the pre-calibrated delay duration to add the delay duration to the emission time and calculate the actual power-down time. This calculation method takes into account the unavoidable physical delay in the hardware link, making the calculation result closer to the actual moment when the power supply to the tested solid-state drive is cut off.

[0082] Furthermore, after calculating the actual power outage time, the test host locks onto the set of logical addresses in write state within a preset time period before and after the actual power outage time. The preset time period before and after refers to a time window formed by extending a preset time forward and backward from the actual power outage time.

[0083] Specifically, the length of the preset time periods before and after the power outage can be pre-configured according to the testing requirements, for example, set to 100 milliseconds before and after the actual power outage. The set of logical addresses in the write state refers to the set of logical addresses of the SSD under test that are performing write operations within this time window, thereby limiting the scope of subsequent consistency checks to the logical addresses of write operations directly related to the power outage event.

[0084] As an optional implementation method, please refer to Figure 4This is a flowchart illustrating the process of obtaining a set of logical addresses in a solid-state drive abnormal power-loss testing method provided in this application embodiment. The step of locking the set of logical addresses in a write state within a preset time period before and after the actual power-loss event includes: Step S60: Record the sending time, starting logical address and address length of each write operation in real time through a circular buffer; Step S61: Search the ring buffer according to the calculated actual power failure time; Step S62: Obtain all logical address ranges in write state within a preset time period before and after the actual power failure time to obtain the logical address set.

[0085] In an alternative embodiment, the process of locking the set of logical addresses can be implemented using a ring buffer mechanism.

[0086] During the test, the test host uses a circular buffer to record the sending time, starting logical address, and address length of each write operation in real time. A circular buffer is a fixed-size memory area that is used cyclically. When the buffer is full, new records overwrite the oldest records, thus continuously storing write operation records within a limited memory space.

[0087] Specifically, a write operation refers to the I / O command issued by the test host to the SSD under test for writing data. Each time a write operation is sent to the SSD under test, the test host records the sending time, starting logical address, and address length of the write operation in a circular buffer. The starting logical address refers to the starting position of the write operation in the logical address space, and the address length refers to the size of the logical address range covered by the write operation.

[0088] Furthermore, once the test host calculates the actual time of the power outage, it searches the circular buffer based on that time. Since the records in the circular buffer are arranged in chronological order of transmission time, the test host can find the record at the corresponding time position in the circular buffer based on the actual time of the power outage.

[0089] During the retrieval process, the test host extracts write operation records from the circular buffer whose transmission times fall within a preset time period before and after the actual power outage. For these write operation records, the starting logical address and address length of each record are extracted to obtain the corresponding logical address ranges. These logical address ranges are then merged to form a logical address set, which covers all logical address ranges in a write state within the preset time period before and after the actual power outage. Subsequent steps will perform consistency checks on the data within this set.

[0090] Step S7: Perform a consistency check on the data within the logical address set to obtain the fault check result.

[0091] In this embodiment of the application, after the test host locks the logical address set in step S6, it will perform a consistency check on the data within the logical address set.

[0092] Specifically, consistency verification involves comparing the current data within a logical address set with the original data written to that logical address set before the power outage to determine whether the power outage caused data corruption or loss. Since the logical address set covers areas that are in a write state within a preset time period before and after the actual power outage, the data in these areas is being modified at the time of the power outage and is most susceptible to its impact. Therefore, performing consistency verification on the data within this logical address set can effectively detect the specific impact of the power outage on the data being written.

[0093] Furthermore, after the test host performs the consistency check, it will obtain the corresponding fault check result. The fault check result can include indication information of whether the check passed or failed, and can also include detailed information such as the specific location of the logical address of the failed check and the type of data inconsistency, so as to facilitate subsequent analysis and evaluation of the power loss recovery capability of the tested solid-state drive.

[0094] In one specific embodiment, the fault verification result includes indications of whether the data in the logical address set matches or does not match. When all the data in the logical address set is consistent with the original data written before the power failure, the fault verification result indicates that the power failure did not damage the data being written, and the power failure recovery capability of the tested solid-state drive is normal.

[0095] When the data at one or more logical addresses in the logical address set is inconsistent with the original data written before the power failure, the fault verification result indicates that the power failure has damaged the data being written. The test host can further record the location of the logical address where the data inconsistency occurred, the length of the inconsistent data, and the type of inconsistency, providing a basis for subsequent analysis of the power failure mode of the tested solid-state drive.

[0096] As an optional implementation method, please refer to Figure 5 This is a flowchart illustrating the consistency check process in the solid-state drive abnormal power-loss testing method provided in this application embodiment. The consistency check process for the data within the logical address set includes: Step S70: Perform the first check, the second check, and the third check sequentially on the data within the logical address set; The first verification includes checking the integrity of the file system logs on the tested solid-state drive and whether the directory structure is continuous. The second verification includes comparing the current data in the logical address set with the preset feature code written before the power failure, and judging whether the flash memory translation layer mapping relationship is abnormal based on the comparison result; The third verification includes reading the monitoring logs of the tested solid-state drive through a standard protocol and statistically analyzing the changes in operating status parameters before and after a power outage.

[0097] In an optional embodiment, consistency checks can be performed on the data within the logical address set sequentially through a first check, a second check, and a third check, so as to evaluate the power-loss recovery of the tested solid-state drive from different dimensions.

[0098] In this embodiment, the first verification is a file system-level verification. The test host checks the integrity of the file system log and the continuity of the directory structure on the tested solid-state drive. The file system log is a data structure used by the file system to record metadata change operations. If the writing of the file system log is not yet complete when a power outage occurs, the log may be broken or incomplete, thus affecting the file system's recovery capability after a power outage. The continuity of the directory structure reflects whether the file system's directory organization information has been damaged during a power outage. The first verification can detect the impact of power outages on the metadata structure at the file system level.

[0099] The second verification is at the logical address level. The test host compares the current data within the logical address set with the preset signature code written before the power failure. The preset signature code is specific identification information pre-embedded in the written data when the test host writes data to the SSD under test before the power failure. For example, it may include the write serial number, checksum, or specific data pattern. Its purpose is to ensure that the data read back after the power failure can be accurately compared with the expected value at the time of writing.

[0100] Furthermore, if the current data matches the preset signature, it indicates that the data at that logical address was not affected by the power outage; if the current data does not match the preset signature, it indicates that the data at that logical address was damaged or lost during the power outage. Based on the comparison results, the test host can indirectly determine whether the flash memory translation layer mapping relationship of the tested solid-state drive is abnormal.

[0101] It is understandable that the flash translation layer is a module inside the solid-state drive used to map logical addresses to physical storage locations. If the flash translation layer is updating the mapping table when a power failure occurs, it may cause the logical address to point to the wrong physical location, thus reading incorrect data. Therefore, by comparing the correctness of the data in the logical address set, it is possible to indirectly infer whether the mapping relationship of the flash translation layer has been damaged during a power failure.

[0102] Furthermore, the third verification is at the device parameter level. The test host reads the monitoring logs of the SSD under test through standard protocols and analyzes the changes in operating status parameters before and after power failure. Standard protocols refer to the interface protocols commonly used in the SSD industry, such as the NVMe or SATA protocols. The internal monitoring logs of the SSD under test can be obtained through the standard commands in these protocols.

[0103] Optionally, operating status parameters refer to various indicators recorded in the monitoring log that reflect the internal working status and health of the solid-state drive, such as the number of bad blocks, the number of abnormal power outages, and the power-on recovery time. The test host compares the operating status parameters read before the power outage with the operating status parameters read after the power outage and power-on, and counts the changes in each parameter.

[0104] Furthermore, the changes in operating status parameters can reflect the extent to which power loss affects the internal physical state and firmware operation of the tested solid-state drive. For example, a sudden increase in the number of bad blocks may indicate that the power loss occurred during programming or erasure operations, and an increase in the number of abnormal power outages directly corresponds to this power outage event. In this way, the damage caused by power loss to the tested solid-state drive can be quantified at the device level through third verification.

[0105] As an optional implementation method, please refer to Figure 6 This is a flowchart illustrating the construction of a power-loss erosion index in the solid-state drive abnormal power-loss testing method provided in this application embodiment. After obtaining the fault verification result, the method further includes: Step S71: Obtain the degradation characteristics of the tested solid-state drive after this power outage, the degradation characteristics including at least the bad block count growth rate and the change in operating status parameters; Step S72: Calculate the first-order and second-order rates of change of the degradation characteristics to construct the power-loss erosion index; wherein the power-loss erosion index is a multi-dimensional vector composed of the first-order and second-order rates of change; Step S73: Compare the values ​​of each dimension in the power loss erosion index with the values ​​of the corresponding dimensions in the preset benchmark vector. When the value of any dimension exceeds the corresponding threshold in the preset benchmark vector, terminate the test on the solid-state drive under test.

[0106] In an optional embodiment, after obtaining the fault verification result in step S7, the cumulative damage level of the tested solid-state drive can be further evaluated based on the fault verification result of this power-down test, and a decision can be made on whether to continue the subsequent power-down test cycle based on the evaluation result.

[0107] Specifically, the test host first acquires the degradation characteristics of the tested SSD after the power outage. These degradation characteristics refer to quantitative indicators that reflect the degree of performance degradation or deterioration of the tested SSD after a power outage, including at least the growth rate of bad blocks and changes in operating parameters.

[0108] The bad block count growth rate refers to the ratio of the number of newly added bad blocks after the power outage to the total number of bad blocks before the power outage. This indicator reflects the degree of damage to the physical storage units of the solid-state drive caused by the power outage. The change in operating status parameters refers to the change in operating status parameters before and after the power outage obtained from the third verification in step S7, such as the increase in the number of abnormal power outages and the change in power-on recovery time. These degradation characteristics are all general parameters that can be obtained through standard protocols.

[0109] After obtaining the degradation characteristics, the test host calculates the first-order and second-order rates of change of these characteristics to construct a power-loss erosion index. The first-order rate of change refers to the rate at which the degradation characteristics change during the current power loss relative to the previous power loss, reflecting the extent of damage caused to the tested SSD by a single power loss. The second-order rate of change refers to the rate of change of the first-order rate of change itself, reflecting whether the extent of damage is accelerating.

[0110] In the embodiments of this application, when the first-order rate of change remains stable, it indicates that the damage caused to the tested solid-state drive by each power outage is roughly the same; when the second-order rate of change increases significantly, it indicates that nonlinear damage accumulation has begun to occur inside the tested solid-state drive, that is, the damage caused by each power outage is increasing, which is usually a precursor to irreversible damage to the solid-state drive.

[0111] Furthermore, the power loss erosion index is composed of first-order and second-order rates of change, and its form is a multi-dimensional vector. Each dimension of the vector corresponds to a first-order or second-order rate of change of a degradation characteristic, thus more comprehensively reflecting the internal health status of the tested solid-state drive.

[0112] After obtaining the power loss erosion index, the test host compares the values ​​of each dimension of the index with the corresponding values ​​of the preset benchmark vector. The preset benchmark vector is a pre-defined reference vector whose dimensions correspond one-to-one with the dimensions of the power loss erosion index, with each dimension corresponding to a threshold. These thresholds can be set based on historical test data or engineering experience of the same model of SSD, representing the upper limit of damage that the tested SSD can safely withstand.

[0113] When the value of any dimension in the power-loss erosion index exceeds the threshold of the corresponding dimension in the preset baseline vector, it indicates that the damage to the tested SSD in that dimension has exceeded the safe range, and continuing to perform the power-loss test may lead to irreversible damage. At this point, the test host terminates the test on the tested SSD to avoid complete damage to the tested SSD and to conserve test resources.

[0114] For example, the following section will use an abnormal power loss test of an automotive solid-state drive as an example to fully explain the technical solution of this application.

[0115] Understandably, in actual use, automotive solid-state drives may face complex conditions such as intensive system writing during vehicle startup, continuous video recording and storage during driving, and sudden power outages, which place high demands on power-off reliability.

[0116] Before the test begins, the test host establishes a connection with the solid-state drive under test through a standard data transfer interface, which is an NVMe (Non-Volatile Memory Express) protocol interface.

[0117] The test host is configured with the following test parameters: the preset timeout threshold is set to 200 milliseconds, the preset time intervals before and after are set to 100 milliseconds, and the preset temperature change process is set to first maintain a constant temperature of 85°C for 2 hours after power failure, then cool down to 25°C at a rate of 0.5°C per minute, and finally maintain a constant temperature of 25°C for 12 hours.

[0118] Furthermore, the test host completes the acquisition of the pre-calibrated delay duration. Specifically, under no-load conditions, a test power-down trigger signal is sent to the physical control channel. The waveform at the moment the power-down trigger signal is sent and the voltage drop waveform on the power supply pin of the solid-state drive under test are simultaneously acquired by an oscilloscope. The time difference between the transition edges of the two waveforms is measured to be 120 microseconds, and this 120 microseconds is used as the pre-calibrated delay duration.

[0119] In addition, the test host is also responsible for initializing the test partitions and file system of the SSD under test before each round of testing. This includes reformatting the test partitions of the SSD under test, rebuilding the file system, and writing the baseline characteristic data required for this round of testing to ensure that the initial environment of each round of testing is consistent. Here, the baseline characteristic data refers to test data embedded with preset characteristic codes. The preset characteristic codes include the write sequence number and checksum, which are used for comparison during subsequent consistency checks.

[0120] Specifically, the test host continuously sends I / O commands to the SSD under test to trigger a power failure detection. In this embodiment, the I / O commands used to trigger the power failure detection include file system log update commands, inode modification commands, and partition table operation commands. These commands are sent throughout the entire load operation phase of the test, not just once at the start of the test.

[0121] For each sent I / O command, the test host records its sending time and calculates the response time from the sending time to the current time in real time. Each I / O command corresponds to an independent sending time and a real-time updated response time, and the I / O commands do not interfere with each other.

[0122] Furthermore, the test host continuously monitors the response time of each IO command. When the response time of an IO command exceeds the preset 200-millisecond timeout threshold, and the test host has not yet received the completion confirmation signal for the IO command, the test host generates a power-down trigger signal.

[0123] After the test host generates a power-down trigger signal, it does not transmit the signal through the NVMe data transfer interface that previously interacted with the SSD under test for IO commands, nor does it transmit the signal through the control interface of the SSD under test. Instead, it outputs the power-down trigger signal through a physical control channel that is independent of the above two interfaces.

[0124] In this embodiment, the physical control channel uses a GPIO channel. The power-down trigger signal is transmitted through the GPIO channel to the power supply control circuit, which is composed of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) switches. After receiving the power-down trigger signal, the power supply control circuit cuts off the power supply to the solid-state drive under test.

[0125] While outputting the power-down trigger signal, the test host records the moment the power-down trigger signal is emitted and reads the pre-calibrated delay duration of 120 microseconds during the test initialization phase.

[0126] After disconnecting the power supply to the SSD under test, the test host controlled the temperature of the environment surrounding the SSD according to a preset temperature change process: first, the temperature was raised to 85°C and held for 2 hours; then, it was lowered to 25°C at a rate of 0.5°C per minute; finally, it was held at 25°C for 12 hours. Throughout the entire temperature change process, the SSD under test remained in a power-off, static state. After the above temperature change process was completed, the SSD under test was powered on again.

[0127] After power is restored, the test host uses the recorded time of the power failure trigger signal and the pre-calibrated delay of 120 microseconds to add 120 microseconds to the time of the signal to calculate the actual time of the power failure.

[0128] During testing, the test host maintains a circular buffer that records the sending time, starting logical address, and address length of each write operation in real time. Based on the calculated actual power outage time, the test host retrieves the circular buffer, extracting write operation records whose sending times fall within 100 milliseconds before and after the actual power outage time. The starting logical address and address length of these records are then extracted to obtain the corresponding logical address ranges. These logical address ranges are then merged to form a logical address set.

[0129] The test host performs a consistency check on the data within the logical address set. The check method involves comparing the current data within the logical address set with the original data written to the logical address set before the power outage. In this embodiment, all data within the logical address set is consistent with the original data written before the power outage, and the fault verification result indicates that the power outage did not damage the data being written.

[0130] Before conducting the next round of testing, the test host acquires the degradation characteristics of the tested SSD after the current power outage. These degradation characteristics include the rate of increase in the number of bad blocks and the changes in operating status parameters. The first-order and second-order rates of change of these degradation characteristics are calculated to construct a power outage erosion index. The values ​​of each dimension of the power outage erosion index are then compared with the corresponding values ​​in a preset benchmark vector.

[0131] In this embodiment, after the power failure, the values ​​of each dimension did not exceed the corresponding thresholds. The test host determined that the tested solid-state drive was still in a safe state and entered the next test cycle, repeating the complete process of the above load operation to risk assessment.

[0132] After each round of fault verification is completed, if the test termination condition is not triggered, the test host will reinitialize the test partition and file system of the tested solid-state drive, write new baseline characteristic data, and then enter the next round of load operation to ensure that the initial environment of each round of testing is consistent.

[0133] After a certain round of testing, if the second-order rate of change of the bad block number growth rate in the power-loss erosion index exceeds the corresponding one percent threshold in the preset benchmark vector, it indicates that the damage inside the tested solid-state drive has begun to accumulate non-linearly at an accelerated pace. At this point, the test host terminates the subsequent testing of the tested solid-state drive to prevent it from suffering irreversible damage.

[0134] After the test is completed, the test host finally obtains the total number of power-loss test rounds that the tested solid-state drive underwent within the safety boundary, the fault verification results of each round of power-loss test, and the specific values ​​of each dimension of the power-loss erosion index of the tested solid-state drive when the test is terminated, thus providing data support for firmware optimization and design improvement of solid-state drives.

[0135] It should be noted that the numerical values ​​and specific implementation scenarios described in the above embodiments are merely illustrative examples of the technical solutions of this application and are not intended to limit the scope of protection of this application in any way. In practical applications, the above parameters can be adaptively adjusted according to the model of the solid-state drive under test, the specific requirements of the test scenario, and engineering experience, as should be known by those skilled in the art.

[0136] Based on the above-mentioned SSD abnormal power loss test method, please refer to Figure 7 This is a functional block diagram of the solid-state drive abnormal power loss testing system provided in the embodiments of this application. This application also provides a solid-state drive abnormal power loss testing system, including: The sending unit is used to send IO commands to the solid-state drive under test to trigger power failure detection; The acquisition unit is used to record the sending time of each IO command and to acquire the response time of each IO command from the sending time to the current time in real time; The generation unit is used to generate a power-down trigger signal when the response time of any IO command exceeds a preset timeout threshold and the completion confirmation signal of the IO command has not yet been received. An execution unit is configured to output the power-down trigger signal through a physical control channel independent of the data transmission interface and control interface of the solid-state drive under test, so as to cut off the power supply to the solid-state drive under test. The acquisition unit is used to record the time when the power failure trigger signal is issued and to obtain a pre-calibrated delay duration, wherein the delay duration is the time interval from the issuance of the power failure trigger signal to the actual cut-off of the power supply to the solid-state drive; The locking unit is used to calculate the actual power failure time of the solid-state drive based on the time of the power failure trigger signal and the delay time after the solid-state drive is powered on again, and lock the set of logical addresses in the write state within a preset time period before and after the actual power failure time. The verification unit is used to perform consistency verification on the data within the logical address set and obtain the fault verification result.

[0137] For other details regarding the implementation of the above-mentioned solid-state drive abnormal power failure test system, please refer to the description of the solid-state drive abnormal power failure test method provided in the above-mentioned application embodiments, which will not be repeated here.

[0138] This application provides a method and system for testing abnormal power loss of a solid-state drive (SSD). The method sends I / O commands to the SSD under test to trigger a power loss determination, synchronously records the sending time of each I / O command, and calculates the response time from the sending time in real time. When the response time of any I / O command exceeds a preset threshold and no completion confirmation is received, a power loss trigger signal is generated. Compared to the conventional method of fixed-time triggering, this method ensures that the power loss action occurs during the high-load processing phase of the SSD, more closely reflecting the actual sudden power loss conditions in operation. The power loss trigger signal is output through a physical control channel independent of the SSD's data transmission interface and control interface, without... The interface controller of the solid-state drive (SSD) needs to participate in the response, which can avoid the problem that the power-down command cannot be delivered and executed when the SSD is blocked or the interface is unresponsive, thus ensuring the stability and reliability of the power cut-off action. During the test, the time of the power-down trigger signal and the pre-calibrated power cut-off delay are recorded simultaneously. After the SSD is powered on again, the actual time of power failure is calculated based on the two time parameters. The set of logical addresses in the write state within the preset time period before and after that time is locked and consistency verification is performed. Compared with the conventional verification method of full disk scanning, it can accurately correspond to the impact range of a single power failure, improving the accuracy of fault location and the verification efficiency.

[0139] It should be noted that, in the several embodiments provided in this application, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed between each other can be through some interfaces, or indirect coupling or communication connection between devices or units, and can be electrical, mechanical, or other forms.

[0140] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0141] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for testing an abnormal power-off of a solid state drive, characterized in that, Includes the following steps: Send an I / O command to the solid-state drive under test to trigger a power failure detection; Record the sending time of each IO command and obtain the response time of each IO command from the sending time to the current time in real time; When the response time of any IO command exceeds a preset timeout threshold and the completion confirmation signal of the IO command has not been received, a power failure trigger signal is generated. The power-down trigger signal is output through a physical control channel that is independent of the data transmission interface and control interface of the solid-state drive under test, so as to cut off the power supply to the solid-state drive under test. Record the time when the power failure trigger signal is issued, and obtain the pre-calibrated delay duration, which is the time interval from the issuance of the power failure trigger signal to the actual cut-off of the power supply to the solid-state drive; After the solid-state drive is powered on again, the actual time of power failure of the solid-state drive is calculated based on the time of the power failure trigger signal and the delay time, and the set of logical addresses in the writing state within a preset time period before and after the actual time of power failure is locked. Perform a consistency check on the data within the logical address set to obtain the fault check result. 2.The solid state drive abnormal power-off test method of claim 1, wherein, The IO commands include at least file system log update commands, inode modification commands, and partition table operation commands. 3.The solid state hard disk abnormal power-off test method of claim 1, wherein, The generation of the power-down trigger signal includes: A state feature vector is constructed based on the multi-source operating state characteristics of the tested solid-state drive; the multi-source operating state characteristics include at least the response time of each IO command, the temperature change rate, and the change rate of the operating state parameters of the tested solid-state drive; The state feature vector is input into a pre-trained state assessment model to obtain the confidence level that the tested solid-state drive has entered a high-risk working state. When the confidence level exceeds a preset threshold, and the response time exceeds a preset timeout threshold and the completion confirmation signal has not been received, the power failure trigger signal is generated. 4.The solid state hard disk abnormal power-off test method of claim 3, wherein, When the power failure trigger signal is generated, the power failure trigger signal is output with a pre-calibrated delay time in advance so that the actual power failure time is aligned with the target high-risk window; The target high-risk window is a time period of preset duration, starting from the moment when the response time exceeds the preset timeout threshold and the completion confirmation signal has not yet been received. 5.The solid state hard disk abnormal power-off test method of claim 1, wherein, The physical control channel is any one of the following: GPIO channel, independent USB channel, or Ethernet control channel.

6. The solid-state drive abnormal power loss test method as described in claim 1, characterized in that, After cutting off the power supply to the tested solid-state drive, the process also includes: The temperature of the environment in which the solid-state drive under test is located is controlled to change according to a preset temperature change process, and the solid-state drive under test is controlled to be in a power-off and static state during the temperature change process. After the temperature change process is completed, the solid-state drive is powered on again.

7. The solid-state drive abnormal power loss test method as described in claim 1, characterized in that, The set of logical addresses in write state within a preset time period before and after the actual power failure time includes: The sending time, starting logical address, and address length of each write operation are recorded in real time through a circular buffer. The circular buffer is retrieved based on the calculated actual power outage time. Obtain all logical address ranges in write state within a preset time period before and after the actual power failure time to obtain the logical address set.

8. The solid-state drive abnormal power loss test method as described in claim 1, characterized in that, The process of performing consistency verification on the data within the logical address set includes: The data within the logical address set are subjected to a first check, a second check, and a third check in sequence; The first verification includes checking the integrity of the file system logs on the tested solid-state drive and whether the directory structure is continuous. The second verification includes comparing the current data in the logical address set with the preset feature code written before the power failure, and judging whether the flash memory translation layer mapping relationship is abnormal based on the comparison result; The third verification includes reading the monitoring logs of the tested solid-state drive through a standard protocol and statistically analyzing the changes in operating status parameters before and after a power outage.

9. The solid-state drive abnormal power loss test method as described in claim 8, characterized in that, After obtaining the fault verification result, the process also includes: The degradation characteristics of the tested solid-state drive after the power outage are obtained, and the degradation characteristics include at least the growth rate of the number of bad blocks and the changes in the operating status parameters. The first-order and second-order rates of change of the degradation characteristics are calculated to construct a power-loss erosion index; wherein the power-loss erosion index is a multi-dimensional vector composed of the first-order and second-order rates of change; The values ​​of each dimension in the power loss erosion index are compared with the values ​​of the corresponding dimensions in the preset benchmark vector. When the value of any dimension exceeds the corresponding threshold in the preset benchmark vector, the test on the solid-state drive under test is terminated.

10. A solid-state drive abnormal power failure testing system, characterized in that, include: The sending unit is used to send IO commands to the solid-state drive under test to trigger power failure detection; The acquisition unit is used to record the sending time of each IO command and to acquire the response time of each IO command from the sending time to the current time in real time; The generation unit is used to generate a power-down trigger signal when the response time of any IO command exceeds a preset timeout threshold and the completion confirmation signal of the IO command has not yet been received. An execution unit is configured to output the power-down trigger signal through a physical control channel independent of the data transmission interface and control interface of the solid-state drive under test, so as to cut off the power supply to the solid-state drive under test. The acquisition unit is used to record the time when the power failure trigger signal is issued and to obtain a pre-calibrated delay duration, wherein the delay duration is the time interval from the issuance of the power failure trigger signal to the actual cut-off of the power supply to the solid-state drive; The locking unit is used to calculate the actual power failure time of the solid-state drive based on the time of the power failure trigger signal and the delay time after the solid-state drive is powered on again, and lock the set of logical addresses in the write state within a preset time period before and after the actual power failure time. The verification unit is used to perform consistency verification on the data within the logical address set and obtain the fault verification result.

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