Solid state disk reliability test method, device, equipment and storage medium

Abstract

The application discloses a kind of reliability test method, device, equipment and storage medium of solid state disk.It is determined whether the solid state disk to be tested meets the preset interrupt condition based on the degradation rate of flash memory medium calculated, if it meets, then the interrupt processing is triggered to the solid state disk to be tested;Data integrity check is carried out to the solid state disk to be tested after triggering interrupt processing, and it is determined whether the solid state disk to be tested fails.The application effectively improves the accuracy of solid state disk reliability test.

Description

Technical Field

[0001] This invention relates to the field of solid-state drive (SSD) technology, and more specifically to a method, apparatus, device, and storage medium for reliable testing of SSDs. Background Technology

[0002] Solid-state drives (SSDs) are critical storage devices in modern computer systems, and their performance and reliability are essential for the overall system operation. Effective reliability screening of SSDs during the manufacturing process is a key step in ensuring product quality. Existing SSD testing methods typically employ full-disk scans to assess read / write capabilities and the health of storage units, primarily relying on sequential and random read / write tests to simulate real-world application scenarios.

[0003] However, in terms of testing strategies, existing methods apply uniform test duration and intensity to flash memory chips of different quality levels. This results in lower-quality chips consuming a large amount of testing resources, while higher-quality chips may fail to expose potential defects due to insufficient testing intensity. Regarding monitoring methods, existing methods typically read the SSD's health monitoring information at the beginning and end of the test, lacking dynamic monitoring of bad block growth trends and making it difficult to capture charge leakage or transistor aging phenomena in critical states. As for the excitation source, existing methods rely solely on constant-temperature aging tests, which cannot effectively induce voltage-sensitive defects, and the judgment criteria usually only determine whether read / write errors occur, lacking verification of data retention capabilities.

[0004] Therefore, improving the accuracy of solid-state drive reliability testing is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] This invention provides a method, apparatus, device, and storage medium for reliability testing of solid-state drives (SSDs), which addresses the technical problem of low accuracy in existing SSD reliability testing.

[0006] In a first aspect, the present invention provides a reliability testing method for a solid-state drive, comprising: Obtain the initial health information of the solid-state drive under test, and perform initialization processing on the solid-state drive under test; Based on the initial health information of the solid-state drive under test, the solid-state drive under test after initialization is initially screened. Composite environmental stress is applied to the solid-state drive under test that passes the initial screening, and the number of error correction bits of the solid-state drive under test is dynamically collected during the application of composite environmental stress. Based on the sampling points with multiple error correction bits collected within the sliding window, the degradation rate of the flash memory medium is calculated using a linear regression algorithm. The test solid-state drive (SSD) is determined based on the calculated flash memory media degradation rate to determine whether it meets the preset interrupt conditions. If it does, an interrupt is triggered for the SSD. Perform data integrity verification on the SSD under test after the interrupt is triggered to determine whether the SSD under test has failed.

[0007] Optionally, obtaining the initial health information of the solid-state drive under test and performing initialization processing on the solid-state drive under test includes: Perform a secure erase procedure on the solid-state drive under test, and remove the flash translation layer mapping table and residual charge from the solid-state drive under test; The system employs a full-disk sequential write mode to write a preset boundary flip pattern to the solid-state drive under test and places the storage cells of the solid-state drive under test in a preset charge distribution state. The initial health information of the solid-state drive under test is read through the communication bus, and the initial number of erase / write cycles and the initial number of uncorrectable errors are recorded.

[0008] Optionally, the initial screening of the SSDs under test based on their initial health information, the application of composite environmental stress to the SSDs that pass the initial screening, and the dynamic acquisition of the error correction bits of the SSDs under test during the application of composite environmental stress include: A preset initial uncorrectable error threshold is established, and the initial uncorrectable error count is compared with the initial uncorrectable error threshold. If the initial uncorrectable error count is greater than or equal to the initial uncorrectable error threshold, the solid-state drive under test is determined to have failed the initial screening, and the reliability test of the solid-state drive under test is terminated. If the initial uncorrectable error count is less than the initial uncorrectable error threshold, the solid-state drive under test is determined to have passed the initial screening, and a composite environmental stress is applied to the solid-state drive under test that has passed the initial screening. During the application of composite environmental stress, the health information of the solid-state drive under test is polled at a preset sampling period, and the number of error correction bits corresponding to the original read error rate of the solid-state drive under test is collected.

[0009] Optionally, the step of calculating the flash memory media degradation rate using a linear regression algorithm based on the sampling points of multiple error correction bits collected within a sliding window includes: The monitoring sampling interval and sliding window size are preset, and the number of continuous sampling points m contained in the sliding window is determined. Obtain the sampling time corresponding to each sampling point within the sliding window and the cumulative number of error correction bits at the sampling time; The least squares linear regression is performed on the m sampling points within the sliding window, and the regression slope obtained is used as the degradation rate of the flash memory medium.

[0010] Optionally, the step of determining whether the solid-state drive under test meets a preset interrupt condition based on the calculated flash memory media degradation rate, and if so, triggering an interrupt process for the solid-state drive under test, includes: The system presets a stable threshold and an interrupt threshold for the flash memory media degradation rate, and compares the calculated flash memory media degradation rate with the preset stable threshold and interrupt threshold. If the calculated flash memory media degradation rate is less than or equal to the stability threshold, then the composite environmental stress is applied to the solid-state drive under test with the current test parameters. If the calculated flash memory media degradation rate is greater than the stability threshold and less than the interruption threshold, then the load intensity of the composite environmental stress is increased, and the composite environmental stress is applied to the solid-state drive under test with the test parameters after the load intensity is increased. If the calculated flash memory media degradation rate is greater than or equal to the interrupt threshold, the interrupt condition is determined to be met, and an interrupt process is triggered for the solid-state drive under test.

[0011] Optionally, the step of performing data integrity verification on the solid-state drive under test after triggering the interrupt processing to determine whether the solid-state drive under test has failed includes: Stop writing operations to the solid-state drive under test and abort garbage collection operations on the flash memory conversion layer of the solid-state drive under test; While the garbage collection operation is suspended, a continuous read operation is performed on a preset physical block of the solid-state drive under test. After completing the continuous read operation, the main controller power supply of the solid-state drive under test is cut off, the flash memory chip of the solid-state drive under test is placed in a high-temperature environment for a preset time, and the solid-state drive under test is powered on again after the resting period is over. Read all the data of the solid-state drive under test, and compare and verify the read data with the initial data written by the solid-state drive under test during the initialization process. If a new, uncorrectable error occurs, the solid-state drive under test is determined to be faulty; otherwise, the solid-state drive under test is determined to have passed the test.

[0012] Optionally, after performing data integrity verification on the solid-state drive under test after triggering the interrupt processing to determine whether the solid-state drive under test has failed, the method further includes: For the solid-state drive under test that is determined to pass the test, the composite environmental stress is applied until the cumulative test time reaches the preset standard time, and the consistency of all data on the solid-state drive under test is verified. Collect the cumulative number of erase / write cycles, average temperature, and flash memory degradation rate sequence of the solid-state drive under test during the test period, and input them into the preset reliability distribution model. Use the maximum likelihood estimation method to solve the parameters of the reliability distribution model. Based on the reliability distribution model after solving the parameters, the instantaneous failure rate of the solid-state drive under test under the current operating conditions is calculated, and the expected remaining life of the solid-state drive under test is calculated based on the instantaneous failure rate.

[0013] Secondly, the present invention provides a reliability testing apparatus for a solid-state drive, comprising: The acquisition module is used to acquire the initial health information of the solid-state drive under test and to perform initialization processing on the solid-state drive under test. The screening module is used to perform initial screening of the SSD under test after initialization based on the initial health information of the SSD under test, apply composite environmental stress to the SSD under test that pass the initial screening, and dynamically collect the number of error correction bits of the SSD under test during the application of composite environmental stress. The calculation module is used to calculate the flash memory media degradation rate based on the sampling points of multiple error correction bits collected within the sliding window using a linear regression algorithm. The judgment module is used to determine whether the solid-state drive under test meets the preset interrupt conditions based on the calculated flash memory media degradation rate. If it does, an interrupt process is triggered for the solid-state drive under test. The verification module is used to perform data integrity verification on the solid-state drive under test after the interrupt is triggered, and to determine whether the solid-state drive under test has failed.

[0014] Thirdly, the present invention provides a computer device, the device including a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus; Memory, used to store computer programs; When the processor executes a program stored in the memory, it implements the steps of the reliability testing method for the solid-state drive described in any one of the first aspects above.

[0015] Fourthly, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the reliability testing method for a solid-state drive as described in any one of the first aspects above.

[0016] Compared with existing technologies, this invention provides a reliability testing method, apparatus, device, and storage medium for solid-state drives (SSDs). Based on sampling points with multiple error-correcting bits collected within a sliding window, it calculates the flash memory media degradation rate using a linear regression algorithm. This effectively filters out random noise interference from single sampling, enabling more accurate capture of the degradation trend of the SSD's flash memory media in a critical state. Early abnormal changes in the media can be detected before uncorrectable errors actually occur, providing a reliable and sensitive quantitative basis for subsequent adaptive decision-making. Simultaneously, the flash memory media degradation rate is compared with preset interruption conditions. For SSDs under test that meet the conditions, an automatic interruption is triggered, terminating the regular test and transitioning to data integrity verification. This changes the traditional testing method's strategy of executing the entire test process regardless of sample quality. It can stop the test in the early stages of accelerated failure of high-risk samples, avoiding the continuous consumption of test resources on samples destined to fail, and effectively improving the accuracy of SSD reliability testing. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and not all embodiments. For those skilled in the art, other drawings obtained from these drawings without creative effort are all within the scope of protection of this application.

[0018] Figure 1 This is a flowchart of a reliability testing method for a solid-state drive provided in an embodiment of the present invention.

[0019] Figure 2 This is a flowchart of applying composite environmental stress to a solid-state drive under test, provided by an embodiment of the present invention.

[0020] Figure 3 This is a flowchart of calculating the degradation rate of flash memory media provided in an embodiment of the present invention.

[0021] Figure 4 This is a flowchart provided by an embodiment of the present invention for determining whether a solid-state drive under test meets preset interrupt conditions.

[0022] Figure 5 This is a flowchart provided by an embodiment of the present invention for determining the data integrity of a solid-state drive under test.

[0023] Figure 6 This is a flowchart for predicting the remaining lifespan of a solid-state drive under test, provided by an embodiment of the present invention.

[0024] Figure 7This is a reliability testing device for solid-state drives provided in an embodiment of the present invention.

[0025] Figure 8 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention.

[0026] Figure 9 This is a schematic diagram of the structure of a computer-readable storage medium provided in an embodiment of the present invention. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0028] To make the description of this disclosure more detailed and complete, illustrative descriptions of embodiments and specific examples of the present invention are provided below; however, these are not the only forms of implementing or utilizing the specific embodiments of the present invention. The embodiments cover features of multiple specific embodiments and the methods, steps, and their order for constructing and operating these specific embodiments. However, other specific embodiments may also be used to achieve the same or equivalent functions and step sequences. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application.

[0029] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in sequences other than those illustrated or described herein.

[0030] In the description of the embodiments of the present invention, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The word "and / or" in the text is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of this application, "multiple" means two or more. Other quantifiers should be understood similarly. The preferred embodiments described herein are only used to illustrate and explain the present invention and are not intended to limit the present invention. Furthermore, the embodiments and features in the embodiments of this application can be combined with each other without conflict.

[0031] To address the technical problem of low accuracy in reliability testing of existing solid-state drives (SSDs), this invention provides a reliability testing method for SSDs, such as... Figure 1 The flowchart described above illustrates a reliability testing method for a solid-state drive provided in an embodiment of the present invention, which includes the following steps.

[0032] S10: Obtain the initial health information of the solid-state drive under test and perform initialization processing on the solid-state drive under test. Specifically, in this embodiment of the invention, the solid-state drive under test is initialized, its storage units are restored to a uniform preset state, and the initial health information of the solid-state drive under test is read as the health baseline for subsequent tests. Through initialization processing, it is ensured that all samples under test are under the same starting conditions, thereby ensuring the comparability and accuracy of subsequent test results.

[0033] S20: Based on the initial health information of the SSD under test, an initial screening is performed on the initialized SSDs. A composite environmental stress is applied to the SSDs that pass the initial screening, and the number of error correction bits of the SSDs is dynamically collected during the application of the composite environmental stress. Specifically, in this embodiment of the invention, an initial screening is performed on the SSDs under test to identify and process samples with obvious defects in advance. For the SSDs that pass the initial screening, a composite environmental stress composed of multiple environmental factors is applied, and the number of error correction bits of the SSDs is continuously collected during the stress application process to monitor their health status in real time. Initial screening quickly eliminates unqualified samples, avoiding the investment of subsequent testing resources; at the same time, the application of composite environmental stress can more comprehensively stimulate different types of potential defects, improving the effectiveness of the test.

[0034] S30: Based on sampling points with multiple error correction bits collected within a sliding window, the degradation rate of the flash memory medium is calculated using a linear regression algorithm. Specifically, in this embodiment of the invention, calculating the degradation rate using a sliding window and linear regression can filter out accidental fluctuations from a single sampling, more accurately reflect the true degradation trend of the flash memory medium, and provide a reliable quantitative basis for subsequent decision-making.

[0035] S40: Based on the calculated flash memory media degradation rate, determine whether the solid-state drive under test meets the preset interruption condition. If it does, trigger interrupt processing for the solid-state drive under test. Specifically, in this embodiment of the invention, the calculated media degradation rate is compared with the preset interruption condition. If the interruption condition is met, it indicates that the degradation degree of the solid-state drive under test has exceeded the acceptable range, triggering interrupt processing, stopping the regular test, and proceeding to the subsequent verification stage. This invention, by comparing the media degradation rate with the interruption condition, achieves timely identification and rapid response to high-risk samples, avoids continuing to invest testing time in samples that are about to fail, and improves the utilization efficiency of testing resources.

[0036] S50: Perform data integrity verification on the solid-state drive under test after triggering the interrupt processing to determine whether the solid-state drive under test has failed. Specifically, in this embodiment of the invention, by performing a final data integrity verification on the solid-state drive under test under preset conditions, its reliability under extreme operating conditions can be effectively verified, enabling in-depth screening of potential defects and reducing the risk of defective products leaving the factory.

[0037] As an optional implementation, step S10, which involves acquiring the initial health information of the solid-state drive under test and performing initialization processing on the solid-state drive under test, includes: S11: Perform a secure erase operation on the solid-state drive (SSD) under test, clearing the flash memory translation layer (FMT) mapping table and residual charge. Specifically, in this embodiment, a secure erase command is first sent to the SSD under test, and the SSD controller executes the secure erase operation. During the secure erase process, the controller traverses all flash memory cells, clears the mapping table between logical and physical addresses in the FMT, and performs an erase operation on each memory cell, releasing any residual charge. In previous use or process testing, different memory cells may be in different programming or erase states, resulting in differences in the distribution of residual charge. This difference can affect the consistency of subsequent tests. Secure erasure restores all memory cells to their initial electrical state, providing a unified physical starting point for subsequent tests.

[0038] S12: Using a full-disk sequential write mode, a preset boundary flip pattern is written to the solid-state drive under test (SSD), placing the SSD's storage cells in a preset charge distribution state. Specifically, in this embodiment, after a secure erase, a full-disk sequential write mode is used, starting from the SSD's initial logical address, to continuously write the preset boundary flip pattern across the entire disk. The boundary flip pattern uses a data pattern where the level states of adjacent storage cells alternately flip, such as the hexadecimal "55AA" pattern. This pattern physically places adjacent storage cells in alternating boundary states of charging and uncharging. In NAND flash memory, charge coupling between adjacent storage cells is a significant factor leading to data errors. The boundary flip pattern maximizes the difference in charge states between adjacent cells, placing the storage cells in a sensitive state most susceptible to charge coupling effects. By writing this pattern, the storage cells are actively placed in a critical charge distribution state, making potential charge coupling defects more easily triggered and exposed in subsequent tests. This invention provides a unified and sensitive initial data state for subsequent stress testing, improving the test's sensitivity to charge coupling defects.

[0039] S13: Read the initial health information of the solid-state drive under test (SSD) via the communication bus, and record the initial write / erase cycles and the initial uncorrectable error count. Specifically, in this embodiment of the invention, after completing the pattern writing, a health information query command is sent to the SSD under test via the communication bus to read the initial health information recorded by the internal health monitoring module of the SSD. This initial health information includes at least the initial write / erase cycles and the initial uncorrectable error count. The initial write / erase cycles reflect the total number of programming / erase cycles the SSD under test has undergone before this test, and the initial uncorrectable error count reflects the number of unrepairable storage errors existing in the SSD under test after initialization. This invention establishes a quantitative initial health baseline, providing data support for subsequent initial screening, making the screening judgment based on evidence, and avoiding the waste of resources caused by blind testing.

[0040] As an optional implementation method, such as Figure 2 The above, Figure 2 This is a flowchart of applying composite environmental stress to a solid-state drive (SSD) under test according to an embodiment of the present invention. In step S20, the SSD under test is initially screened based on its initial health information after initialization. Composite environmental stress is applied to the SSDs that pass the initial screening, and the number of error correction bits of the SSD under test is dynamically collected during the application of composite environmental stress. This includes: S21: A preset initial uncorrectable error threshold is established, and the initial uncorrectable error count is compared with the initial uncorrectable error threshold. Specifically, in this embodiment of the invention, after recording the initial uncorrectable error count, a preset initial uncorrectable error threshold is obtained, and the count is compared with the threshold value. This threshold can be predetermined according to the flash memory chip process and type used in the solid-state drive, for example, set to 1. The initial uncorrectable error count reflects the number of storage cell defects that already exist in the solid-state drive under test after initialization but before entering formal stress testing, while the threshold represents the minimum acceptable standard for product quality. By quantitatively comparing the measured value with the threshold, an objective basis for screening decisions can be provided. This invention replaces manual experience judgment with automatic threshold judgment and comparison, standardizing the initial screening process and improving the consistency and reliability of the screening results.

[0041] S22: If the initial uncorrectable error count is greater than or equal to the initial uncorrectable error threshold, the solid-state drive under test is determined to have failed the initial screening, and the reliability test of the solid-state drive under test is terminated. Specifically, in this embodiment of the invention, if an uncorrectable error occurs immediately after the initialization process, it indicates that the flash memory chips of the solid-state drive have serious original defects. Even without any accelerated stress, the charge retention capability or read / write function of its storage cells has failed. Such samples are likely to deteriorate rapidly in subsequent stress tests, and continuing to invest testing resources will not yield effective reliability assessment results. This invention quickly identifies and removes samples with serious original defects at the very beginning of the testing process, avoiding the investment in subsequent time-consuming testing stages such as high-temperature aging and composite stress, effectively saving testing resources and improving the overall testing throughput of the production line.

[0042] S23: If the initial uncorrectable error count is less than the initial uncorrectable error threshold, the solid-state drive under test is determined to have passed the initial screening, and a composite environmental stress is applied to the solid-state drive under test that has passed the initial screening. Specifically, in this embodiment of the invention, when the comparison result shows that the initial uncorrectable error count is less than the threshold, the solid-state drive under test is determined to have passed the initial screening and belongs to the normal sample. For the sample that has passed the screening, a composite environmental stress is applied, which integrates three excitation sources: high temperature environment, mixed read / write load, and dynamic voltage disturbance. A single environmental stress can only excite specific types of defects. For example, high temperature mainly accelerates charge leakage, read / write load mainly tests the main controller scheduling and flash memory wear, while voltage disturbance targets power supply ripple-sensitive defects. Applying the three stresses in combination can excite multiple failure modes simultaneously in the same test cycle, allowing different types of potential defects to be exposed in parallel, improving the comprehensiveness of the test. This invention achieves a multi-dimensional comprehensive test of the solid-state drive through composite stress, making up for the limited coverage of traditional single stress tests and improving the detection rate of complex potential defects.

[0043] S24: During the application of composite environmental stress, the health information of the solid-state drive under test (SSD) is polled at a preset sampling period to collect the number of error correction bits corresponding to the original read error rate of the SSD. Specifically, in this embodiment of the invention, during the continuous application of composite environmental stress, a health information query command is sent to the SSD under test at preset sampling periods to read the error correction bit count value related to the read error rate in the health information. This number of error correction bits reflects the total number of error bits successfully corrected by the SSD controller through the error correction code engine when reading data. Each collected data is recorded together with the corresponding sampling time to form a time-varying error correction bit count sampling sequence. The growth trend of the error correction bit count directly reflects the degradation process of the charge state in the flash memory storage cell. Compared with only focusing on whether uncorrectable errors are eventually generated, monitoring the dynamic changes of the error correction bit count can capture the intermediate transition stage between the storage cell and the critical failure, and detect degradation signs before bad blocks are actually generated. This invention achieves early perception of the degradation process of flash memory media, providing a continuous and fine-grained data foundation for subsequent degradation rate calculation and trend analysis.

[0044] As an optional implementation method, such as Figure 3 The above, Figure 3 This is a flowchart of a method for calculating the degradation rate of flash memory media provided in an embodiment of the present invention. In step S30, the calculation of the flash memory media degradation rate based on sampling points with multiple error correction bits collected within a sliding window using a linear regression algorithm includes: S31: Preset the monitoring sampling interval and sliding window size, and determine the number m of continuous sampling points contained in the sliding window. Specifically, in this embodiment of the invention, based on the number of error correction bits continuously collected step by step, the monitoring sampling interval is preset. The sliding window size W is used as the ratio of the window size to the sampling interval to determine the number of consecutive sampling points m contained within the sliding window, where m is an integer greater than or equal to 2. The sliding window size determines the data span involved in the calculation; a larger window allows for more data points to participate in the fitting, resulting in more stable calculation results, but may reduce the response speed. By reasonably configuring the sampling interval and window size, a balance can be achieved between computational sensitivity and stability.

[0045] S32: Obtain the sampling time corresponding to each sampling point within the sliding window and the cumulative error correction bits at that sampling time. Specifically, in this embodiment of the invention, after each sliding window update, the sampling time corresponding to each sampling point within the window and the cumulative error correction bits collected at that time are extracted to form m sets of data pairs consisting of sampling time and cumulative error correction bits. Each data pair reflects the cumulative degradation degree of the solid-state drive flash memory medium at a sampling time. The cumulative error correction bits are a monotonically increasing cumulative amount, continuously increasing as the test time progresses. A single sampling point only reflects the cumulative value at the current time and cannot individually characterize the rate of degradation. Only by jointly analyzing the times and cumulative values ​​of multiple sampling points can degradation rate information be extracted from the distribution trend of the data pairs. This invention transforms the original health monitoring data into structured time-series data pairs, providing a standardized input data format for subsequent linear regression fitting, ensuring the consistency and accuracy of the calculation process.

[0046] S33: Perform least-squares linear regression fitting on the m sampling points within the sliding window, and use the regression slope obtained as the flash memory media degradation rate. Perform least-squares linear regression fitting on the m sets of data obtained in step S32, with the sampling time as the independent variable and the cumulative number of error correction bits as the dependent variable, solve for the slope of the regression line, and use this slope as the flash memory media degradation rate at the current time. The degradation rate of the flash memory medium. The calculation formula is: in, The number of sampling points within the sliding window. For the first in the window The sampling time corresponding to each sampling point For the first in the window The cumulative error correction bits corresponding to each sampling point.

[0047] In this embodiment of the invention, the least squares method determines the best-fitting line by minimizing the sum of squared distances from each data point to the fitted line, effectively mitigating the impact of random fluctuations at individual sampling points on slope calculation. Compared to calculating the instantaneous rate using only the difference between two adjacent samples, linear regression based on multiple sampling points within a sliding window more robustly reflects the overall degradation trend over the window period. This invention transforms discrete sampling data into a continuous degradation rate index using statistical methods, providing a reliable and stable quantitative basis for subsequent adaptive decision-making.

[0048] As an optional implementation method, such as Figure 4 The above, Figure 4This is a flowchart provided by an embodiment of the present invention for determining whether a solid-state drive under test meets a preset interrupt condition. In step S40, the determination of whether the solid-state drive under test meets the preset interrupt condition based on the calculated flash memory media degradation rate, and if it does, triggering an interrupt process for the solid-state drive under test, includes: S41: Preset stable thresholds and interruption thresholds for flash memory media degradation rate, and compare the calculated flash memory media degradation rate with the preset stable thresholds and interruption thresholds. Specifically, in this embodiment of the invention, after calculating the media degradation rate, obtain preset stable thresholds K1 and K2, and compare the current media degradation rate with both stable thresholds K1 and K2 to determine its threshold range. The stable threshold K1 defines the upper limit of the media degradation rate within the normal fluctuation range, and the interruption threshold K2 defines the critical value at which the media degradation rate enters the accelerated failure stage. The stable threshold K1 is less than the interruption threshold K2. By setting two hierarchical thresholds, stable threshold K1 and interruption threshold K2, the health status of the solid-state drive under test can be divided into three ranges: stable, slightly degraded, and accelerated failure, providing a judgment benchmark for subsequent graded responses.

[0049] S42: If the calculated flash memory media degradation rate is less than or equal to the stability threshold, then the composite environmental stress is applied to the solid-state drive under test using the current test parameters. Specifically, in this embodiment of the invention, when the comparison result shows that the media degradation rate is less than or equal to the stability threshold K1, it is determined that the flash memory media of the solid-state drive under test is in a stable state and the degradation trend is normal. The current test parameters are kept unchanged, and the composite environmental stress is applied to the solid-state drive under test using the original high-temperature environment setting, mixed read / write load ratio, and voltage disturbance parameters.

[0050] S43: If the calculated flash memory media degradation rate is greater than the stability threshold and less than the interruption threshold, the load intensity of the composite environmental stress is increased to apply composite environmental stress to the solid-state drive under test using the test parameters after increasing the load intensity. Specifically, in this embodiment of the invention, when the comparison result shows that the media degradation rate exceeds the stability threshold K1 but has not yet reached the interruption threshold K2, it is determined that the flash memory media of the solid-state drive under test shows slight degradation signs. Keeping the high temperature environment and voltage disturbance parameters unchanged, the intensity of the mixed read / write load is increased, for example, by increasing the queue depth to increase the number of concurrent read / write requests, or by adjusting the ratio of random writes to sequential writes to exacerbate the write amplification effect, to continue applying composite environmental stress using the test parameters after increasing the load intensity.

[0051] S44: If the calculated flash memory media degradation rate is greater than or equal to the interrupt threshold, the interrupt condition is determined to be met, and an interrupt process is triggered for the solid-state drive under test. Specifically, in this embodiment of the invention, when the comparison result shows that the flash memory media degradation rate is greater than or equal to the interrupt threshold K2, it is determined that the flash memory media of the solid-state drive under test has entered the accelerated failure period, satisfying the preset interrupt condition. At this time, the conventional composite environmental stress test of the solid-state drive under test is immediately stopped, the interrupt process is triggered, and the sample is diverted from the current test process and transferred to the data integrity verification stage for final judgment. This invention realizes the immediate identification and rapid removal of high-risk samples, avoids wasting subsequent testing time on samples that are destined to fail, and significantly improves the overall efficiency of solid-state drive testing.

[0052] As an optional implementation method, such as Figure 5 The above, Figure 5 This is a flowchart of a process for verifying the data integrity of a solid-state drive (SSD) under test, provided by an embodiment of the present invention. Step S50, which involves verifying the data integrity of the SSD under test after triggering an interrupt, and determining whether the SSD under test has failed, includes: S51: Stop the write operation on the solid-state drive under test (SSD) and abort the garbage collection operation of the flash conversion layer of the SSD. Specifically, in this embodiment of the invention, after triggering the interrupt handling, a stop write command is sent to the SSD under test to terminate all ongoing and pending write tasks, ensuring that the data state stored in the current user data area remains unchanged. Simultaneously, a configuration command is sent to the SSD controller to abort the garbage collection operation of the flash conversion layer. Garbage collection is a background task within the SSD, where the controller actively migrates valid data from old physical blocks to new physical blocks during idle periods and erases the old blocks for subsequent writing. This invention preserves the true data state of the SSD under test after accelerated degradation testing to the greatest extent possible, avoiding interference from external writing and internal data migration on the test results, and providing a reliable and tamper-proof comparison basis for subsequent data integrity verification.

[0053] S52: While the garbage collection operation is suspended, a continuous read operation is performed on a preset physical block of the solid-state drive under test. Specifically, in this embodiment of the invention, after confirming that the garbage collection operation has been suspended and the data state is frozen, a preset physical block on the solid-state drive under test is selected as the target area for read interference. Without performing an erase operation, multiple consecutive read operations are initiated on the preset physical block, for example, performing 100,000 consecutive read cycles. Each read operation applies a read voltage to the corresponding physical block to detect the current data state stored in each storage unit within that block. This invention, through controlled high-intensity read interference operations, can actively stimulate storage units with insufficient charge retention capacity in a critical state, fully exposing potential read interference-sensitive defects during the testing phase, thereby effectively identifying unreliable products that may gradually develop data errors under normal usage scenarios.

[0054] S53: After completing the continuous read operation, the main controller power supply of the solid-state drive under test is cut off, and the flash memory chip of the solid-state drive under test is placed in a high-temperature environment for a preset time. After the settling period, the solid-state drive under test is powered on again. Specifically, in this embodiment of the invention, after the continuous read operation is completed, the power supply to the main controller and interface circuit of the solid-state drive under test is cut off by a programmable power supply, so that the main controller stops running, leaving only the flash memory chip in a power-off physical environment. The solid-state drive under test, including the flash memory chip, is then placed in a high-temperature environment test chamber and left to stand in a power-off state for a preset time, such as 48 hours. During the settling period, the storage cells of the flash memory chip do not interact with any external circuits and rely entirely on their own stored charge to retain data. After the settling period, the full power supply to the solid-state drive under test is restored by a programmable power supply. This invention, through the combination of high-temperature accelerated charge leakage and power-off settling, constitutes the most stringent test of data retention capability, which can effectively screen out products that perform normally in short-term tests but cannot guarantee long-term data storage reliability, making up for the shortcomings of conventional testing methods in verifying data retention capability.

[0055] S54: Read the full disk data of the solid-state drive under test (SSD), and compare and verify the read full disk data with the initial data written by the SSD during the initialization process. Specifically, in this embodiment of the invention, after power-on and completion of main controller initialization, a full disk data read operation is performed on the SSD under test. Starting from the initial logical address, all user data areas are traversed to obtain the full disk data content currently stored in the flash memory chip. At the same time, a copy of the initial data written and retained during the initialization process is retrieved. The read current full disk data is compared with the initial data segment by segment using a preset verification unit to detect whether there is any data inconsistency. During the comparison and verification process, the change in the uncorrectable error count in the health information of the SSD is monitored synchronously. The initial data is the known correct data written by the SSD under test at the starting point of the test. After undergoing multiple tests such as combined environmental stress, read interference, and high temperature power-off rest, the final read data is compared with the initial data bit by bit or unit by unit, which can accurately identify data bits that have been flipped or lost during the test. The increase in the uncorrectable error count further indicates that the data errors have exceeded the repair capabilities of the solid-state drive's internal error correction engine.

[0056] S55: If a new uncorrectable error is found, the solid-state drive under test is determined to be faulty; otherwise, it is determined to have passed the test. Specifically, in this embodiment of the invention, after completing the full disk data comparison and verification, a final determination is made for the solid-state drive under test based on the verification results. If a new uncorrectable error is found during the comparison process, i.e., there is a data difference between the initial data and the currently read data that cannot be repaired by the internal error correction mechanism, the solid-state drive under test is determined to have failed the reliability test, is marked as a defective product, and is removed from the qualified product line. If the full disk data comparison is completely consistent and no new uncorrectable errors are found, the solid-state drive under test is determined to have passed the reliability test and is marked as a qualified product.

[0057] As an optional implementation method, such as Figure 6 The above, Figure 6 This is a flowchart of a method for predicting the remaining lifespan of a solid-state drive (SSD) under test, provided by an embodiment of the present invention. After performing data integrity verification on the SSD under test after triggering an interrupt to determine whether the SSD under test has failed, the method further includes: S61: For the solid-state drive under test (SSD) that has passed the test, apply the composite environmental stress until the cumulative test time reaches a preset standard time, and perform a consistency check on all data on the SSD. Specifically, in this embodiment of the invention, after determining that the SSD has passed the extreme data integrity check, the sample is placed back in the composite environmental stress test environment, and the composite environmental stress consisting of high temperature, mixed read / write load, and dynamic voltage disturbance is applied to it again. The stress is continuously applied until the cumulative test time of the SSD since entering the test process reaches the preset standard time. After the cumulative test time is reached, the stress application is stopped, and a complete data consistency check is performed on the entire storage space of the SSD.

[0058] S62: Collect the cumulative write / erase cycles, average temperature, and flash memory degradation rate sequence of the solid-state drive under test (SSD) during the test cycle, and input them into a preset reliability distribution model. The parameters of the reliability distribution model are solved using the maximum likelihood estimation method. Specifically, in this embodiment of the invention, after the entire test cycle is completed, the full-cycle operating data of the SSD under test is collected from the test records. The collected data includes at least: the total number of cumulative write / erase cycles during the test, which reflects the total wear experienced by the SSD under test during the entire test process; the average temperature of the operating environment of the SSD under test during the test, which reflects the thermal level of the test stress; and a flash memory degradation rate sequence composed of the flash memory degradation rate values ​​recorded in each sliding window calculation, arranged in chronological order. This sequence records the dynamic evolution of flash memory degradation of the SSD under test throughout the entire test cycle. The collected data is used as input features and imported into a preset reliability distribution model. This reliability distribution model is a statistical distribution model that can describe the failure rate variation law of electronic products during the wear period, such as the two-parameter Weibull distribution model. The maximum likelihood estimation method is used to solve for the model parameters, and the optimal parameter estimates are obtained through statistical analysis of the collected data. This invention transforms discrete test data into a continuous reliability mathematical model and extracts essential parameters reflecting the product failure patterns through statistical inference methods.

[0059] S63: Based on the reliability distribution model after solving the parameters, calculate the instantaneous failure rate of the solid-state drive under test (SSD) under the current operating conditions, and calculate the expected remaining lifespan of the SSD based on the instantaneous failure rate. Specifically, in this embodiment of the invention, after obtaining the reliability distribution model parameters, the current operating conditions and the accumulated running time of the SSD under test are substituted into the reliability distribution model after solving the parameters to calculate the instantaneous failure rate of the SSD under test at the current moment. Based on the calculated instantaneous failure rate, combined with the design life target of the SSD under test and the currently accumulated running time, its expected remaining lifespan is further calculated. The expected remaining lifespan represents the remaining length of time that the SSD under test is expected to continue to work normally under the current operating conditions and health status. This invention elevates the test results from a binary judgment of pass / fail to a multi-dimensional reliability assessment that includes lifespan prediction, which can provide a refined quality level classification basis for production line sorting. For example, products with lower instantaneous failure rates and longer expected remaining lifespans can be classified as high-level, while products with instantaneous failure rates that, although not exceeding the standard, have increased can be classified as low-level, meeting the differentiated reliability requirements of SSDs in different application scenarios.

[0060] In this embodiment of the invention, based on sampling points with multiple error-correcting bits collected within a sliding window, the flash memory media degradation rate is calculated using a linear regression algorithm. This effectively filters out random noise interference from single sampling, enabling more accurate capture of the degradation trend of the flash memory media in a critical state. Early abnormal changes in the media can be detected before uncorrectable errors actually occur, providing a reliable and sensitive quantitative basis for subsequent adaptive decision-making. Simultaneously, the flash memory media degradation rate is compared with preset interruption conditions. For SSDs under test that meet the conditions, an automatic interruption is triggered, terminating the regular test and transitioning to data integrity verification. This departs from the traditional testing method's strategy of executing the entire test process regardless of sample quality. It can immediately stop the test in the early stages of accelerated failure of high-risk samples, avoiding the continuous consumption of test resources on samples destined to fail, and effectively improving the accuracy of SSD reliability testing.

[0061] Based on the above-described reliability testing method for solid-state drives (SSDs), this invention provides a reliability testing apparatus for SSDs, such as... Figure 7As shown in Figure 7, the structural schematic diagram of this solid-state drive (SSD) reliability testing device includes: an acquisition module 71, used to acquire the initial health information of the SSD under test and perform initialization processing on the SSD under test; a screening module 72, used to perform initial screening on the SSD under test after initialization based on the initial health information of the SSD under test, apply composite environmental stress to the SSD under test that passes the initial screening, and dynamically collect the number of error correction bits of the SSD under test during the application of composite environmental stress; a calculation module 73, used to calculate the flash memory media degradation rate based on the sampling points of multiple error correction bits collected within a sliding window using a linear regression algorithm; a judgment module 74, used to determine whether the SSD under test meets the preset interruption conditions based on the calculated flash memory media degradation rate, and if so, to trigger interrupt processing on the SSD under test; and a verification module 75, used to perform data integrity verification on the SSD under test after triggering interrupt processing to determine whether the SSD under test has failed.

[0062] For further details regarding the implementation of the above technical solution by each module in the above solid-state drive reliability testing device, please refer to the description in the solid-state drive reliability testing method provided in the above-mentioned embodiments of the invention, which will not be repeated here.

[0063] Please refer to Figure 8This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. The device includes a processor 801, which can be implemented using a general-purpose central processing unit (CPU), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application; and a memory 802, which can be implemented using a read-only memory (ROM), static storage device, dynamic storage device, or random access memory (RAM), etc. The memory 802 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program code is stored in the memory 802 and is called and executed by the processor 801. The input / output interface 803 is used to realize information input and output. The communication interface 804 is used to realize communication interaction between this device and other devices. Communication can be realized by wired means (e.g., USB, network cable, etc.) or by wireless means (e.g., mobile network, WIFI, Bluetooth, etc.). The bus 805 transmits information between the various components of the device (e.g., processor 801, memory 802, input / output interface 803 and communication interface 804). The processor 801, memory 802, input / output interface 803 and communication interface 804 realize communication connection between each other within the device through the bus 805.

[0064] Please refer to Figure 9 This is a schematic diagram of a computer-readable storage medium structure according to an embodiment of the present invention. The storage medium 90 of this embodiment stores program instructions 91 capable of implementing the aforementioned reliability testing method for a solid-state drive. These program instructions 91 can be stored in the storage medium in the form of a software product, including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks, or terminal devices such as computers, servers, mobile phones, and tablets.

[0065] In the several embodiments provided by this invention, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0066] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated units described above can be implemented in hardware or as software functional units. The above are merely embodiments of the present invention and do not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

[0067] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A reliability testing method for a solid-state drive, characterized in that, include: Obtain the initial health information of the solid-state drive under test, and perform initialization processing on the solid-state drive under test; Based on the initial health information of the solid-state drive under test, the solid-state drive under test after initialization is initially screened. Composite environmental stress is applied to the solid-state drive under test that passes the initial screening, and the number of error correction bits of the solid-state drive under test is dynamically collected during the application of composite environmental stress. Based on sampling points with multiple error-correction bits acquired within a sliding window, the flash memory media degradation rate is calculated using a linear regression algorithm, including: The monitoring sampling interval and sliding window size are preset, and the number of continuous sampling points m contained in the sliding window is determined. Obtain the sampling time corresponding to each sampling point within the sliding window and the cumulative number of error correction bits at the sampling time; The least squares linear regression is performed on the m sampling points within the sliding window, and the regression slope obtained is used as the flash memory medium degradation rate. Based on the calculated flash memory media degradation rate, it is determined whether the solid-state drive under test meets the preset interrupt conditions. If it does, an interrupt process is triggered for the solid-state drive under test, including: The system presets a stable threshold and an interrupt threshold for the flash memory media degradation rate, and compares the calculated flash memory media degradation rate with the preset stable threshold and interrupt threshold. If the calculated flash memory media degradation rate is less than or equal to the stability threshold, then the composite environmental stress is applied to the solid-state drive under test with the current test parameters. If the calculated flash memory media degradation rate is greater than the stability threshold and less than the interruption threshold, then the load intensity of the composite environmental stress is increased, and the composite environmental stress is applied to the solid-state drive under test with the test parameters after the load intensity is increased. If the calculated flash memory media degradation rate is greater than or equal to the interrupt threshold, the interrupt condition is determined to be met, and an interrupt process is triggered for the solid-state drive under test. Perform data integrity verification on the SSD under test after the interrupt is triggered to determine whether the SSD under test has failed.

2. The reliability testing method for a solid-state drive according to claim 1, characterized in that, The process of acquiring the initial health information of the solid-state drive under test and performing initialization processing on the solid-state drive under test includes: Perform a secure erase procedure on the solid-state drive under test, and remove the flash translation layer mapping table and residual charge from the solid-state drive under test; The system employs a full-disk sequential write mode to write a preset boundary flip pattern to the solid-state drive under test and places the storage cells of the solid-state drive under test in a preset charge distribution state. The initial health information of the solid-state drive under test is read through the communication bus, and the initial number of erase / write cycles and the initial number of uncorrectable errors are recorded.

3. The reliability testing method for a solid-state drive according to claim 2, characterized in that, The process involves initial screening of the SSDs after initialization based on their initial health information, applying composite environmental stress to the SSDs that pass the initial screening, and dynamically collecting the number of error correction bits of the SSDs during the application of composite environmental stress. This includes: A preset initial uncorrectable error threshold is established, and the initial uncorrectable error count is compared with the initial uncorrectable error threshold. If the initial uncorrectable error count is greater than or equal to the initial uncorrectable error threshold, the solid-state drive under test is determined to have failed the initial screening, and the reliability test of the solid-state drive under test is terminated. If the initial uncorrectable error count is less than the initial uncorrectable error threshold, the solid-state drive under test is determined to have passed the initial screening, and a composite environmental stress is applied to the solid-state drive under test that has passed the initial screening. During the application of composite environmental stress, the health information of the solid-state drive under test is polled at a preset sampling period, and the number of error correction bits corresponding to the original read error rate of the solid-state drive under test is collected.

4. The reliability testing method for a solid-state drive according to claim 1, characterized in that, The step of performing data integrity verification on the SSD under test after triggering the interrupt to determine whether the SSD under test has failed includes: Stop writing operations to the solid-state drive under test and abort garbage collection operations on the flash memory conversion layer of the solid-state drive under test; While the garbage collection operation is suspended, a continuous read operation is performed on a preset physical block of the solid-state drive under test. After completing the continuous read operation, the main controller power supply of the solid-state drive under test is cut off, the flash memory chip of the solid-state drive under test is placed in a high-temperature environment for a preset time, and the solid-state drive under test is powered on again after the resting period is over. Read all the data of the solid-state drive under test, and compare and verify the read data with the initial data written by the solid-state drive under test during the initialization process. If a new, uncorrectable error occurs, the solid-state drive under test is determined to be faulty; otherwise, the solid-state drive under test is determined to have passed the test.

5. The reliability testing method for a solid-state drive according to claim 1, characterized in that, After performing data integrity verification on the SSD under test after triggering the interrupt to determine whether the SSD under test has failed, the method further includes: For the solid-state drive under test that is determined to pass the test, the composite environmental stress is applied until the cumulative test time reaches the preset standard time, and the consistency of all data on the solid-state drive under test is verified. Collect the cumulative number of erase / write cycles, average temperature, and flash memory degradation rate sequence of the solid-state drive under test during the test period, and input them into the preset reliability distribution model. Use the maximum likelihood estimation method to solve the parameters of the reliability distribution model. Based on the reliability distribution model after solving the parameters, the instantaneous failure rate of the solid-state drive under test under the current operating conditions is calculated, and the expected remaining life of the solid-state drive under test is calculated based on the instantaneous failure rate.

6. A reliability testing device for solid-state drives, characterized in that, The apparatus is used to implement the steps of the reliability testing method for a solid-state drive as described in any one of claims 1-5, including: The acquisition module is used to acquire the initial health information of the solid-state drive under test and to perform initialization processing on the solid-state drive under test. The screening module is used to perform initial screening of the SSD under test after initialization based on the initial health information of the SSD under test, apply composite environmental stress to the SSD under test that pass the initial screening, and dynamically collect the number of error correction bits of the SSD under test during the application of composite environmental stress. The calculation module is used to calculate the flash memory media degradation rate based on the sampling points of multiple error correction bits collected within the sliding window using a linear regression algorithm. The judgment module is used to determine whether the solid-state drive under test meets the preset interrupt conditions based on the calculated flash memory media degradation rate. If it does, an interrupt process is triggered for the solid-state drive under test. The verification module is used to perform data integrity verification on the solid-state drive under test after the interrupt is triggered, and to determine whether the solid-state drive under test has failed.

7. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the reliability testing method for a solid-state drive as described in any one of claims 1 to 5.

8. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the reliability testing method for solid-state drives as described in any one of claims 1 to 5.

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