A ussd double-interface residual response tin paste compensation verification method

Abstract

The application discloses a USSD double-interface residual response tin paste compensation verification method. The method comprises the following steps: acquiring tin paste detection data of a USSD corresponding PCB; performing double-interface equivalent testing in reverse order, acquiring target test stage response characteristics and correcting; determining standardized residual difference parameters based on reference USSD interface reference differences; determining abnormal areas in combination with circuit connection relationships and tin paste detection data, screening double-pad devices, and establishing candidate compensation parameter templates according to repeated tin paste appearances; selecting an appearance matching PCB as a reference PCB and a compensation PCB, performing tin paste compensation on the compensation PCB; testing double-interface residual responses after reflow, verifying effectiveness in combination with process quality and functional results, and determining whether target abnormal response characteristics are improved. The application establishes candidate associations through double-interface responses, circuit connection relationships and repeated tin paste appearances, reduces the influence of test order, test path and interface inherent differences, improves tin paste compensation parameter verification reliability, and reduces the risk of blind process adjustment.

Description

Technical Field

[0001] This application relates to the field of storage product manufacturing process technology, specifically to a method for verifying solder paste compensation for residual response of USSD dual-interface. Background Technology

[0002] With the increasing application of solid-state storage products in data storage devices, USSDs (Dual-Head SSDs) are gradually being used in various application scenarios. USSDs have a first interface and a second interface, and their manufacturing process typically involves solder paste printing, component mounting, reflow soldering, and subsequent testing. Manufacturing fluctuations can affect the product's electrical response, soldering quality, and functional stability.

[0003] In existing manufacturing processes, the manufacturing quality of USSDs is typically controlled through methods such as solder paste inspection, visual inspection, soldering quality inspection, and finished product functional testing. When abnormal test responses or fluctuations in soldering quality are detected, printing parameters, mounting parameters, or other process parameters are usually adjusted based on the test results to improve the manufacturing quality of subsequent products.

[0004] However, existing methods often struggle to distinguish between normal response differences, test condition variations, and abnormal response changes caused by manufacturing factors between different USSD interfaces. They also find it difficult to accurately determine the correlation between local solder paste condition and abnormal interface response based on pre-reflow inspection information. After compensating for local solder paste condition, existing methods typically lack effective verification mechanisms, making it difficult to confirm whether the compensation actually improves the target abnormal response or introduces new soldering quality issues or functional testing risks. Therefore, how to effectively verify the solder paste compensation parameters of USSDs has become a pressing technical problem. Summary of the Invention

[0005] The purpose of this application is to provide a method for verifying solder paste compensation for residual response of USSD dual interface, in order to solve the technical problems of existing methods that make it difficult to distinguish between normal differences in the response of USSD dual interface and abnormal changes caused by manufacturing factors, make it difficult to determine candidate compensation objects related to abnormal response based on solder paste detection information before reflow, and make it difficult to confirm whether solder paste compensation improves the target abnormal response or introduces process quality or functional test risks.

[0006] This application provides a method for verifying solder paste compensation for residual response of a USSD dual-interface, applied to a USSD manufacturing process that sequentially includes solder paste printing, solder paste inspection, component mounting, and reflow soldering. The USSD includes a PCB, a first interface, and a second interface. The PCB has interface circuit areas corresponding to the first and second interfaces, respectively. The first and second interfaces are at least partially connected to a power supply network and / or a ground network on the PCB. The method includes: The solder paste inspection data of the PCB corresponding to multiple USSDs that have completed component placement and reflow soldering is obtained during the solder paste inspection stage. The equivalent test sequence including multiple test stages is executed on the multiple USSDs according to the first test order of passing through the first interface first and then the second interface and the second test order of passing through the second interface first and then the first interface. The target test stage is selected from the equivalent test sequence to obtain the response characteristics of the corresponding interface in the target test stage. The response characteristics are corrected based on the test path correction parameters of the corresponding interface. Based on the corrected response characteristics and the reference response differences of the first and second interfaces of multiple reference USSDs of the same model and meeting the preset reference screening conditions during the target test phase, the standardized residual differential parameters of multiple USSDs are determined. Based on standardized residual differential parameters, the circuit connection relationship between the interface circuit area and the power supply network and / or grounding network, and solder paste detection data, candidate abnormal circuit areas are identified. Candidate dual-pad devices are screened within the candidate abnormal circuit region, and the response characteristics corresponding to the candidate abnormal circuit region that deviate from the reference state of the reference USSD are determined as the target abnormal response characteristics. Candidate compensation parameter templates are established based on the solder paste morphology conditions that repeatedly appear in multiple USSDs with target abnormal response characteristics of candidate dual-pad devices. In the USSD manufacturing process, PCBs that have completed solder paste printing and solder paste inspection but have not completed component mounting, and whose initial solder paste morphology conditions match the candidate compensation parameter template, are selected as the reference PCB and the compensation PCB, respectively. Solder paste compensation is performed on the dual pads corresponding to the candidate dual pad devices in the compensation PCB, but not on the reference PCB. After component mounting and reflow soldering are completed on the reference PCB and the compensation PCB to form the USSD, dual-interface residual response tests are performed to obtain the target abnormal response characteristics of the USSD formed by the reference PCB and the USSD formed by the compensation PCB. When the target abnormal response characteristics of the USSD formed by the compensation PCB are closer to the corresponding reference state of the reference USSD than those formed by the base PCB, and the preset process quality and functional test conditions are met, the solder paste compensation parameters corresponding to the candidate compensation parameter template are determined to be valid.

[0007] The USSD dual-interface residual response solder paste compensation verification method provided in this application first performs equivalent test sequences, including multiple test stages, on multiple USSDs that have completed component mounting and reflow soldering, according to a first test sequence and a second test sequence. A target test stage is selected from the equivalent test sequence, and the response characteristics are corrected based on the test path correction parameters of the corresponding interface. Then, standardized residual differential parameters are determined by combining the reference response differences between the first and second interfaces of the reference USSD in the target test stage. Next, candidate abnormal circuit regions are determined based on the standardized residual differential parameters, the circuit connection relationship between the interface circuit region and the power supply network and / or ground network, and solder paste detection data. Candidate dual-pad devices are screened within the candidate abnormal circuit regions, and a candidate compensation parameter template is established based on the recurring solder paste morphology conditions in multiple USSDs with target abnormal response characteristics. Further, for PCBs whose initial solder paste morphology conditions match the candidate compensation parameter template, a reference PCB and a compensation PCB are set up respectively. Solder paste compensation is performed on the compensation PCB, while no solder paste compensation is performed on the reference PCB. After component mounting and reflow soldering are completed, dual-interface residual response tests are performed on the USSDs formed by the two PCBs respectively.

[0008] Therefore, this application does not directly identify abnormal responses as the root cause of an anomaly in a specific pad or device. Instead, it establishes candidate correlations through dual-interface response analysis, circuit connection relationships, and repeated solder paste morphology conditions. Two opposite test sequences are used to reduce the impact of test order on interface responses, while test path correction parameters and reference response differences are used to reduce the impact of test path differences and inherent interface response differences on anomaly judgment. This solves the problems of existing methods in identifying candidate compensation targets related to abnormal responses and confirming the actual effect of solder paste compensation. Furthermore, by conducting reflow comparison tests between the compensated PCB and the reference PCB, and verifying the results in conjunction with process quality and functional test conditions, it is possible to confirm whether the solder paste compensation parameters improve the target abnormal response and whether they introduce new manufacturing risks. This improves the reliability of solder paste compensation parameter verification and reduces the risk of blindly adjusting process parameters.

[0009] These or other aspects of this application will become more apparent in the following description of the embodiments. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1A flowchart of the USSD dual-interface residual response solder paste compensation verification method provided in an embodiment of this application is shown. Detailed Implementation

[0012] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are all within the scope of protection of this application.

[0013] It should be noted that, unless the context explicitly specifies otherwise, the relational terms such as "first" and "second" used in this document are only used to distinguish one entity, operation, interface, region, or parameter from another entity, operation, interface, region, or parameter, and are not used to specify differences in their importance. For "first test order" and "second test order" that explicitly define the test order, they should be understood according to the chronological relationship described in the corresponding steps.

[0014] The terms "comprising," "including," and any variations thereof are intended to cover non-exclusive inclusion, such that a process, method, apparatus, device, or system that comprises a list of elements may include not only the elements expressly listed, but also other elements not expressly listed, or elements inherent to the process, method, apparatus, device, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, apparatus, device, or system that includes that element.

[0015] In this article, "multiple" refers to two or more; "at least one" refers to one or more.

[0016] It should be noted that in this article, "and / or" means that the related objects can exist individually or simultaneously. For example, A and / or B means that A exists alone, B exists alone, or A and B exist simultaneously. The character " / " indicates an "or" relationship between the preceding and following related objects unless otherwise specified.

[0017] In this article, "connection" or "connection relationship" can be understood as an electrical connection relationship. The connection between two electrical components, interfaces, circuit areas, power supply networks, or grounding networks can be a direct connection or an indirect connection formed through wires, pads, devices, traces, or other electrical components.

[0018] The USSD dual-interface residual response solder paste compensation verification method provided in this application is applicable to the USSD manufacturing process. The USSD is a Dual-Head SSD, i.e., a dual-head solid-state storage product. The USSD includes a PCB, a first interface, and a second interface. The PCB has interface circuit areas corresponding to the first and second interfaces, respectively. The first and second interfaces are at least partially connected to a power supply network and / or ground network on the PCB. It should be understood that the USSD may also include other functional components and circuit structures for its normal operation. This application mainly describes the PCB, first interface, second interface, interface circuit areas, and power supply network and / or ground network related to dual-interface residual response analysis and solder paste compensation verification.

[0019] During the USSD manufacturing process, the PCB sequentially undergoes solder paste printing, solder paste inspection, component placement, and reflow soldering. After component placement and reflow soldering, the USSD can undergo interface testing via the first and second interfaces; the solder paste inspection data generated during the solder paste inspection stage can be used for subsequent analysis. For PCBs produced later, when solder paste printing and inspection are complete but component placement is not yet finished, selection can be made based on their initial solder paste morphology conditions to serve as the target for subsequent solder paste compensation verification.

[0020] Figure 1 A flowchart of the USSD dual-interface residual response solder paste compensation verification method provided in this application embodiment is shown, as follows: Figure 1 As shown, the USSD dual-interface residual response solder paste compensation verification method provided in this application embodiment includes: S100: Obtain solder paste inspection data of multiple USSDs corresponding to PCBs that have completed component placement and reflow soldering during the solder paste inspection stage. Perform an equivalent test sequence including multiple test stages on multiple USSDs according to a first test order of passing through the first interface first and then the second interface, and a second test order of passing through the second interface first and then the first interface. Select the target test stage from the equivalent test sequence, obtain the response characteristics of the corresponding interface in the target test stage, and correct the response characteristics based on the test path correction parameters of the corresponding interface.

[0021] Optionally, in this step, the multiple USSDs that have completed component mounting and reflow soldering are historical products or current batch products used for anomaly analysis. A product identification association is pre-established between each USSD and its corresponding PCB, ensuring that the solder paste inspection data generated during the solder paste inspection stage corresponds to the interface test results after reflow soldering. The solder paste inspection data may include data such as solder paste volume, height, area, center of gravity, outline, spacing with adjacent pads, and inspection time for each pad or pad area on the PCB. The solder paste inspection data is not directly used in this step to determine a specific pad as the root cause of the anomaly; rather, it serves as a source of process data for subsequent candidate correlation analysis based on interface response and circuit connection relationships. The first test sequence is used to execute an equivalent test sequence by first passing the first interface and then the second interface; the second test sequence is used to execute an equivalent test sequence by first passing the second interface and then the first interface. The test objects, test content, and test conditions of the two test sequences are the same or comparable; the difference lies in the order of testing the first and second interfaces. The equivalent test sequence includes multiple test phases, and the target test phase is at least one test phase selected from the equivalent test sequence to be analyzed. The target test phase is used to obtain the response characteristics corresponding to the first interface and the second interface, and serves as the analysis object for subsequently determining the standardized residual difference parameters.

[0022] In some embodiments, the equivalent test sequence includes at least two test phases: standby, read / write, and recovery. The target test phase is at least one test phase selected from the multiple test phases included in the equivalent test sequence. The standby test phase is used to obtain the response characteristics of the USSD in standby mode, such as current response, power supply response, or settling time response during standby. The read / write test phase is used to obtain the response characteristics of the USSD when performing read and / or write operations, such as peak response, average response, fluctuation response, or response change trend during read / write operations. The recovery test phase is used to obtain the response characteristics of the USSD during the process of entering a stable state after read / write operations, such as response decay during recovery, settling time, or standby response after recovery. The target test phase may include only the standby test phase, or only the read / write test phase or the recovery test phase; multiple test phases may also be selected simultaneously as the target test phase. Obtaining response characteristics for different test phases avoids judging interface anomalies based solely on a single operating state.

[0023] When executing the equivalent test sequence, in both the first and second test sequences, the power input voltages of the first and second interfaces are kept within the same target voltage range. Furthermore, the test data volume, logical address range, read / write mode, maximum speed limit, and ambient temperature are kept the same or within a preset allowable error range. Specifically, the test data volume limits the scale of data processed in the read / write test; the logical address range limits the logical address intervals involved in the read / write test; the read / write mode limits the operation mode of reading, writing, or a combination of reading and writing; the maximum speed limit limits the maximum transmission rate during the test; and the ambient temperature limits the environmental conditions during the test. By keeping the aforementioned test conditions the same or within a preset allowable error range, the first and second interfaces undergo the same or equivalent test loads in both test sequences, thus making the obtained response characteristics comparable. Here, "equivalent" does not require the response values ​​of the two interfaces to be completely identical, but rather that the two interface tests meet the basic requirements for comparison in terms of test tasks, workload, and environmental conditions.

[0024] At any given test moment, only the external power supply positive path and data path corresponding to the currently tested interface are in a valid test connection state; untested interfaces are not connected to external power supply positive paths and data paths. Specifically, when testing is performed through the first interface, the external power supply positive path and data path of the first interface are in a valid test connection state, while the second interface is not connected to external power supply positive paths and data paths; when testing is performed through the second interface, the external power supply positive path and data path of the second interface are in a valid test connection state, while the first interface is not connected to external power supply positive paths and data paths. This reduces the impact on the current interface response caused by the external power supply positive path or data path of untested interfaces being in a valid connection state. It should be understood that the first and second interfaces may still form a common connection relationship within the PCB through the power supply network and / or ground network, and this common connection relationship is the basis for subsequent analysis to determine the common connection area.

[0025] Further, in step S100, the response characteristics are corrected based on the test path correction parameters of the corresponding interface, including: Based on a standard reference load, standard reference board, or reference USSD, test path correction parameters are obtained. These parameters include at least one of the following: supply voltage drop deviation, current acquisition deviation, contact state reference value, and test channel recovery time. Specifically, when the test path is in a stable state, reference response data corresponding to the test path can be obtained through a standard reference load, standard reference board, or reference USSD. Test path correction parameters are then formed based on the difference between the obtained reference response data and the expected response data. Specifically, the supply voltage drop deviation characterizes the voltage change generated by the power supply path from the external power supply terminal to the interface power supply input terminal; the current acquisition deviation characterizes the acquisition differences caused by the current acquisition path, sampling device, or sampling position; the contact state reference value characterizes the reference response range corresponding to the test connection being in a normal contact state; and the test channel recovery time characterizes the time required for the test path to recover to meet the conditions for the next test after the previous test.

[0026] Optionally, different correction methods can be adopted depending on the type of response characteristic. For example, for response characteristics mainly affected by the supply voltage drop deviation, corresponding corrections can be made based on the supply voltage drop deviation; for response characteristics mainly affected by the current acquisition deviation, corresponding corrections can be made based on the current acquisition deviation; test results where the contact state does not meet the reference requirements can be excluded as valid input for subsequent residual analysis. After correction based on the test path correction parameters, the corrected response characteristics are obtained. The corrected response characteristics are used for subsequent comparison with the interface reference response of the reference USSD to reduce the impact of response deviations caused by the test path itself on anomaly detection.

[0027] In some embodiments, a state recovery process is further included between the execution of the first test sequence and the second test sequence. The state recovery process includes at least one of the following: idle waiting, file system synchronization or secure unmounting, power-on after a power outage, standby current recovery to a preset stable range, successful interface re-enumeration, recovery to the same test partition state, use of the same logical address range, and execution of the same preset write preprocessing. The recovery test phase in the equivalent test sequence and the state recovery process have different functions. The recovery test phase is used to obtain the recovery response characteristics of the USSD after read / write operations, and is the test phase available for analysis in the equivalent test sequence; the state recovery process is used to restore the internal state of the USSD to the same or equivalent state as much as possible between the two test sequences, so as to ensure that the response characteristics under the forward and reverse test sequences have a basis for comparison.

[0028] Specifically, idle waiting allows the USSD to enter a relatively stable state after the previous round of testing; file system synchronization or safe unmounting can reduce the impact of file system caching, incomplete write operations, or mounted states on the subsequent round of testing; power failure and power-on allows the USSD to re-enter the initialization state; standby current returning to a preset stable range can serve as a criterion for stabilizing the internal working state; successful interface re-enumeration can serve as a criterion for making the interface available again. Restoring to the same test partition state, using the same logical address range, and performing the same preset write preprocessing are used to control the data access location and preprocessing state under the two test sequences, avoiding incomparable differences in interface response due to different logical address ranges, different test partition states, or different write histories.

[0029] As one implementation, when the same USSD cannot be restored to the same or equivalent internal state in both the first and second test sequences to make the response characteristics comparable under the forward and reverse test sequences, at least two USSDs of the same model, material batch, and initialization state are selected. One USSD performs the first test sequence, and the other USSD performs the second test sequence. In this implementation, the two USSDs meet the same or comparable product model, material batch, and initialization state conditions. One USSD is used to obtain the response characteristics under the first test sequence, and the other USSD is used to obtain the response characteristics under the second test sequence. This allows for obtaining response data under both test sequences through multiple matching USSDs when the same USSD cannot be restored to a comparable internal state.

[0030] The corrected response features, corresponding test sequence information, and target test stage information obtained in the aforementioned steps are used as input data for step S200.

[0031] S200: Based on the corrected response characteristics and the reference response differences of the first and second interfaces of multiple reference USSDs of the same model and meeting the preset reference screening conditions during the target test phase, the standardized residual differential parameters of multiple USSDs are determined.

[0032] Optionally, in this step, the reference USSD is a USSD of the same model as the USSD to be analyzed and that meets the preset reference screening conditions. It is used to provide the reference response differences and corresponding reference states of the first and second interfaces during the target testing phase. The reference USSD is not used to simply distinguish between qualified and unqualified products, but rather to establish a benchmark for the response difference between the two interfaces of the same model under normal reference conditions. Even when the first and second interfaces are in normal conditions, differences in interface layout, local power supply paths, local grounding paths, interface circuit area structures, or test paths may result in differences in normal response. Therefore, the judgment of anomalies is not based directly on "the response characteristics of the two interfaces being completely identical," but rather on comparing the reference response differences of the first and second interfaces in the reference USSD under the same target testing phase. After obtaining the corrected response characteristics of the first and second interfaces of the USSD to be analyzed, the actual response difference between the two interfaces is first determined; then, the actual response difference is compared with the reference response difference of the reference USSD; finally, the standardized residual difference parameters are obtained based on the dispersion of the interface differential response in the reference USSD. The standardized residual difference parameters are used to characterize the degree of deviation of the interface differential response of the USSD to be analyzed from the reference state. This parameter reflects both the relative difference between the first and second interfaces and whether that relative difference exceeds the normal discrete range of the reference USSD.

[0033] In some embodiments, in step S200, based on the corrected response characteristics and the reference response differences between the first and second interfaces of multiple reference USSDs of the same model and meeting preset reference screening conditions during the target testing phase, the standardized residual difference parameters of the multiple USSDs are determined, including: For response features where a decrease in value indicates an increased risk of anomaly, the corrected response features are reversed so that an increase in the value of the reversed response feature indicates an increased risk of anomaly. Different types of response features may exhibit different anomaly trends. For example, an increase in the value of some response features may indicate an increased risk of anomaly, while a decrease in the value of others may indicate an increased risk of anomaly. By reversing the direction of response features where a decrease in value indicates an increased risk of anomaly, all response features involved in subsequent analysis are made to conform to the unified trend that "an increase in value indicates an increased risk of anomaly."

[0034] For the response characteristics after the k-th test phase, the j-th direction change, and the p-th interface, the response values ​​are balanced in the following order: in, For the sequential balanced response value of the p-th interface, This refers to the j-th corrected response feature of the p-th interface in the k-th test phase, obtained according to the first test order. The corrected response feature of the p-th interface in the k-th test phase is obtained according to the second test order, where p=1 represents the first interface and p=2 represents the second interface.

[0035] Sequentially balanced response values ​​reduce the impact of state drift, hot state changes, cache state changes, or other sequential effects caused by the order of testing on interface response characteristics by combining response characteristics obtained from two opposite test orders.

[0036] When using different USSDs to execute the first test sequence and the second test sequence respectively and These represent the mean or median of the response characteristics obtained by USSDs meeting the same matching conditions under the corresponding test order. Using the mean reflects the average response level of multiple matched USSDs under the corresponding test order; using the median reduces the impact of individual outliers on the order balancing result. The selection of the mean or median can be determined based on the number of reference samples and the degree of data dispersion.

[0037] The interface differential response value is determined according to the following formula: The standardized residual difference parameters are determined according to the following formula: in, For the k-th test phase and the j-th response feature, the interface differential response value is used to reflect the relative difference between the first interface and the second interface in the same test phase and the same response feature within the same USSD or a group of USSDs that meet the same matching conditions. For the standardized residual difference parameter of the j-th response feature in the k-th test phase, To reference the average differential response of the USSD interface, To reference the interface differential response dispersion of the USSD, The preset minimum dispersion is greater than zero. Used to characterize the center level of the differential response of the reference USSD interface Used to characterize the natural fluctuation of the interface differential response in the reference USSD. This is used to prevent the interface differential response of the reference USSD from being too small, which would cause the calculation denominator to be too small and thus cause the normalized residual differential parameters to lose stability.

[0038] The standardized residual difference parameters obtained in the aforementioned steps are used as the basis for determining the candidate abnormal circuit region in step S300.

[0039] S300: Based on standardized residual differential parameters, the circuit connection relationship between the interface circuit area and the power supply network and / or grounding network, and solder paste detection data, determine the candidate abnormal circuit area.

[0040] Optionally, in this step, the standardized residual differential parameter is used to reflect the deviation of the interface response from the reference state; the circuit connection relationship between the interface circuit area and the power supply network and / or ground network is used to reflect the correlation between different circuit areas and the first interface and the second interface; and the solder paste detection data is used to reflect the solder paste state of the corresponding PCB before reflow soldering.

[0041] Specifically, based on the PCB circuit design relationships and the connection relationships of the power supply network and grounding network, the dedicated area for the first interface, the dedicated area for the second interface, and the area where the first and second interfaces are jointly connected can be determined. Then, by combining the interface deviation status reflected by the standardized residual differential parameters, it can be determined whether the current anomaly is more likely related to a single-sided interface area or more likely to the shared connection area.

[0042] The candidate abnormal circuit region is used to narrow down the analysis scope for subsequent screening of candidate dual-pad devices. It does not mean that the abnormal response has been directly identified as a single pad, device, or solder paste morphology within this region as the sole root cause of the abnormality.

[0043] In some embodiments, the candidate abnormal circuit region includes a first interface-specific region, a second interface-specific region, and a common connection region.

[0044] The first interface-specific area is the interface circuit area corresponding to the first interface and located before the common connection point of the power supply network and / or ground network. The second interface-specific area is the interface circuit area corresponding to the second interface and located before the common connection point of the power supply network and / or ground network. The common connection area is the power supply network and / or ground network and its corresponding device area that are jointly connected to the first and second interfaces. Specifically, the first interface-specific area may include a local interface circuit area from the first interface to the common connection point of the power supply network and / or ground network; the second interface-specific area may include a local interface circuit area from the second interface to the common connection point; the common connection area may include the power supply network and ground network shared by the two interfaces, as well as the device area associated with the power supply network and ground network.

[0045] In step S300, candidate abnormal circuit regions are determined based on standardized residual differential parameters, the circuit connection relationship between the interface circuit region and the power supply network and / or grounding network, and solder paste detection data, including: When the response characteristics of the first interface deviate from its reference range, and the corresponding response characteristics of the second interface are within its reference range, and the following conditions are met: When the first interface-specific region is identified as a candidate abnormal circuit region, and the response characteristics of the first interface deviate from the reference range while the corresponding response characteristics of the second interface are within the reference range, it indicates that the abnormality is mainly manifested as a deviation of the first interface relative to the second interface. This indicates that the deviation exceeds the residual threshold for the corresponding test phase and response characteristics. Therefore, the area specific to the first interface can be considered as the focus of subsequent analysis.

[0046] When the response characteristics of the second interface deviate from its reference range, and the corresponding response characteristics of the first interface are within its reference range, and the following conditions are met: When the response characteristics of the second interface deviate from the reference range while the corresponding response characteristics of the first interface are within the reference range, it indicates that the anomaly is mainly manifested as a deviation of the second interface relative to the first interface. This indicates that the direction and degree of deviation meet the determination conditions of the second interface-specific region.

[0047] When both the first interface and the second interface deviate from their respective reference ranges and the anomaly direction is consistent during the same testing phase, and the following conditions are met: When both interfaces deviate from their respective reference ranges and the abnormal directions are consistent, it indicates that both interfaces are experiencing anomalies in the same direction; simultaneously, the interface differential response does not show a significant deviation on one side of the interface. In this case, the anomaly may be related to the power supply network, grounding network, or corresponding device area shared by the two interfaces, therefore the common connection area is identified as a candidate abnormal circuit region.

[0048] This is the residual threshold corresponding to the j-th response feature in the k-th test stage, where the value is greater than zero. Different residual thresholds can correspond to different test stages and different response features to accommodate the normal dispersion of different test stages and different response features.

[0049] The aforementioned candidate abnormal circuit region will be used as the region range for screening candidate dual-pad devices in step S400.

[0050] S400: Select candidate dual-pad devices within the candidate abnormal circuit region, and determine the response characteristics of the candidate abnormal circuit region that deviate from the reference state corresponding to the reference USSD as the target abnormal response characteristics.

[0051] Optionally, in this step, candidate dual-pad devices are screened within the candidate anomalous circuit region. These candidate dual-pad devices serve as candidates for subsequent solder paste morphology analysis and solder paste compensation. The target anomalous response characteristic is the response characteristic corresponding to the candidate anomalous circuit region and deviating from the reference state corresponding to the reference USSD. The target anomalous response characteristic is used to limit the interface response objects that need improvement in subsequent solder paste compensation verification.

[0052] The candidate dual-pad devices and the target abnormal response characteristics are not directly equivalent to a root cause relationship. Candidate dual-pad devices are merely candidate compensation objects located within the candidate abnormal circuit region and possessing value for subsequent analysis. Further research is needed to establish a statistical correlation between the solder paste state of candidate dual-pad devices and the target abnormal response characteristics, taking into account the recurring solder paste morphology conditions in multiple USSDs.

[0053] In some embodiments, screening candidate dual-pad devices includes: selecting devices having a first pad and a second pad from the interface power supply path, ground return path, or input filter region within the candidate abnormal circuit region. Specifically, candidate dual-pad devices in the interface power supply path may be devices related to interface power supply input, local power supply transmission, or local power supply stability; candidate dual-pad devices in the ground return path may be devices related to interface ground return; and candidate dual-pad devices in the input filter region may be devices related to interface input filtering.

[0054] The first and second pads are two pads corresponding to the same device. Using dual-pad devices as the object of subsequent analysis and compensation allows for the establishment of finer-grained compensation conditions based on the relative solder paste state between the two pads, rather than judging solely based on the absolute solder paste state of a single pad.

[0055] The candidate dual-pad devices and target abnormal response characteristics obtained from the aforementioned screening are used as input information for step S500 to establish a candidate compensation parameter template.

[0056] S500: Establish candidate compensation parameter templates based on the solder paste morphology conditions that repeatedly appear in multiple USSDs with target abnormal response characteristics of candidate dual-pad devices.

[0057] Optionally, in this step, for multiple USSDs with target abnormal response characteristics, the solder paste morphology data formed by candidate dual-pad devices on the corresponding PCB during the solder paste inspection stage is obtained. Then, a candidate compensation parameter template is established based on the solder paste morphology conditions that recur in multiple USSDs.

[0058] In some embodiments, the solder paste morphology conditions include one or more of the following: solder paste volume of the first pad and the second pad, solder paste height, solder paste area, solder paste centroid offset, normalized solder paste volume imbalance of the two pads, and minimum spacing between the solder paste and adjacent pads. The solder paste volume characterizes the amount of solder paste on the pad; the solder paste height characterizes the morphology of the solder paste in the height direction; the solder paste area characterizes the coverage area of ​​the solder paste on the pad plane; the solder paste centroid offset characterizes the offset of the solder paste centroid relative to the pad reference position; the normalized solder paste volume imbalance of the two pads characterizes the relative imbalance of the two pads relative to their respective reference solder paste volumes; and the minimum spacing between the solder paste and adjacent pads characterizes the space margin between the solder paste print pattern before compensation and the solder paste print pattern of the adjacent pads.

[0059] In some embodiments, the recurring solder paste morphology condition includes: when the same or similar solder paste morphology conditions repeatedly appear in multiple USSDs with the same device type, the same pad structure, or the same device area, and the proportion of solder paste morphology conditions appearing in the reference USSD is lower than a preset proportion, the solder paste morphology condition is determined to be a recurring solder paste morphology condition. Specifically, the solder paste morphology data corresponding to multiple USSDs can be classified or matched for the same device type, the same pad structure, or the same device area. If the same or similar solder paste morphology states repeatedly appear in multiple USSDs with the same target abnormal response characteristics, and the solder paste morphology states appear less frequently in the reference USSD, then the solder paste morphology states can be used as morphology matching conditions for candidate compensation parameter templates. The "same or similar" condition can be determined based on preset solder paste morphology classification conditions, allowable deviation ranges, or morphology matching rules. This determination is used to identify recurring solder paste states in multiple abnormal samples, without requiring the solder paste morphology data of multiple samples to be completely identical.

[0060] Repeated solder paste morphology conditions are used to establish a statistical correlation between the solder paste state of candidate dual-pad devices and the target abnormal response characteristics, rather than directly identifying the solder paste morphology in any single USSD as the root cause of the anomaly. This avoids directly adjusting process parameters based solely on the local solder paste inspection results of a single product.

[0061] The candidate compensation parameter template includes at least candidate dual-pad devices, corresponding pads, recurring solder paste morphology conditions, target abnormal response characteristics, compensation trigger threshold, and compensation rules. Specifically, candidate dual-pad devices are used to limit the device objects involved in compensation; corresponding pads are used to limit the specific compensation location; recurring solder paste morphology conditions are used to limit the morphology matching conditions of the subsequent PCB; target abnormal response characteristics are used to limit the response objects that need improvement during compensation verification; the compensation trigger threshold is used to determine whether to proceed with solder paste compensation processing; and compensation rules are used to limit the amount of solder paste compensation, the compensation landing point, compensation safety conditions, or compensation priority.

[0062] The aforementioned candidate compensation parameter template serves as the basis for selecting the reference PCB and compensation PCB in step S600, and as the parameter basis for performing solder paste compensation in step S700.

[0063] S600: In the USSD manufacturing process, select PCBs that have completed solder paste printing and solder paste inspection but have not completed component placement, and whose initial solder paste morphology conditions match the candidate compensation parameter template, and use them as the reference PCB and compensation PCB respectively.

[0064] Optionally, the PCB used in this step is the PCB used to form the USSD in subsequent production. This PCB has completed solder paste printing and solder paste inspection, but has not yet completed component placement, so it still meets the conditions for performing solder paste compensation. A PCB whose initial solder paste morphology conditions match the candidate compensation parameter template is selected to ensure comparability between the subsequent verification object and the solder paste morphology state corresponding to the candidate compensation parameter template. The reference PCB and the compensation PCB are used to form a comparison object before and after compensation.

[0065] In some embodiments, in step S600, during the USSD manufacturing process, PCBs that have completed solder paste printing and solder paste inspection but have not completed component mounting, and whose initial solder paste morphology conditions match the candidate compensation parameter template, are selected as the reference PCB and the compensation PCB, respectively, including: The selected PCB is matched based on the product model, material batch, PCB batch, and initial solder paste morphology. Two PCBs with the same matching conditions are formed into a sample pair, and one PCB in the sample pair is used as the reference PCB and the other PCB is used as the compensation PCB. This ensures that the reference PCB and the compensation PCB are identical or within the preset tolerance range in subsequent component mounting conditions, reflow soldering conditions, and testing environment.

[0066] Specifically, the product model is used to control the consistency of the USSD product structure corresponding to the PCB; the material batch is used to control the batch differences of components or raw materials; the PCB batch is used to control the batch differences of PCB manufacturing; and the initial solder paste morphology conditions are used to control the comparability of the solder paste state of two PCBs before compensation.

[0067] Through the aforementioned matching process, the baseline PCB and the compensation PCB in the same sample pair are made as consistent as possible in terms of product structure, material conditions, PCB conditions, and initial solder paste condition. In this way, the differences in the target abnormal response generated in subsequent comparisons can more effectively reflect the impact of solder paste compensation, rather than being caused by differences in product model, material batch, PCB batch, or initial solder paste condition.

[0068] One PCB in the sample pair is used as the reference PCB, and the other as the compensation PCB. The reference PCB does not undergo subsequent solder paste compensation, while the compensation PCB performs solder paste compensation according to the candidate compensation parameter template. After completing subsequent component placement, reflow soldering, and dual-interface residual response testing, the two PCBs form a pair of verification results for comparing the compensation effects.

[0069] The reference PCB and the compensation PCB are identical or within the preset tolerance range in terms of subsequent component placement conditions, reflow soldering conditions, and testing environment. By controlling subsequent manufacturing conditions, the compensation verification results are avoided from being affected by significant differences in placement conditions, reflow soldering conditions, or testing environment.

[0070] The aforementioned sample pairs and the correspondence between the reference PCB and the compensation PCB serve as the basis for step S700 to perform solder paste compensation and step S900 to verify the validity of the solder paste compensation parameters.

[0071] S700: Perform solder paste compensation on the dual pads corresponding to the candidate dual pad devices in the compensation PCB, and do not perform solder paste compensation on the reference PCB.

[0072] Optionally, in this step, the dual pads on the compensation PCB corresponding to the candidate dual-pad devices are used as the solder paste compensation targets. The reference PCB is not subjected to solder paste compensation and is used as a comparison object for subsequent adjustments. After solder paste compensation is performed, the main difference between the compensation PCB and the reference PCB lies in whether solder paste compensation is performed on the dual pads corresponding to the candidate dual-pad devices. After component placement and reflow soldering are completed under the same or comparable manufacturing conditions, the comparison and verification can be performed based on the USSDs formed by both PCBs.

[0073] In some embodiments, step S700, performing solder paste compensation on the dual pads corresponding to the candidate dual-pad devices in the compensation PCB, includes: Solder paste compensation is performed when the solder paste volume of the first pad is lower than the first pad compensation trigger threshold, the solder paste volume of the second pad is lower than the second pad compensation trigger threshold, or the imbalance of the normalized solder paste volume between the two pads exceeds a preset imbalance trigger threshold. The first and second pad compensation trigger thresholds are used to determine whether the solder paste volume of each of the two pads is in a state requiring compensation; the preset imbalance trigger threshold is used to determine whether there is a significant imbalance in the relative solder paste state between the two pads.

[0074] The volume loss of normalized solder paste with dual pads is determined according to the following formula: in, To measure the volume loss of normalized solder paste before compensation for dual pads, and These are the current solder paste volumes for the first and second pads, respectively. and These are the reference solder paste volumes for the first and second pads, respectively. Specifically, Used to characterize the ratio of the current solder paste volume of the first pad to the reference solder paste volume of the first pad. This is used to characterize the ratio of the current solder paste volume of the second pad to the reference solder paste volume of the second pad. The larger the absolute value of the difference between the two ratios, the more significant the imbalance in the relative solder paste state between the two pads. When the preset imbalance trigger threshold is exceeded, solder paste compensation processing can proceed even if the current solder paste volume of the first and second pads is not lower than their respective compensation trigger thresholds. This avoids judging solely based on the absolute solder paste volume of a single pad while ignoring the relative imbalance between the two pads.

[0075] In some embodiments, when the center of gravity of the solder paste on the first or second pad shifts towards the adjacent pad, and the corresponding minimum spacing is lower than a preset topography warning threshold, solder paste compensation is performed only if the minimum spacing after compensation is not less than a safety spacing threshold. Here, the shift of the solder paste center of gravity towards the adjacent pad indicates that the current solder paste pattern has a tendency to move closer to the adjacent pad; the minimum spacing being lower than the preset topography warning threshold indicates that the space margin between the current solder paste pattern and the solder paste pattern of the adjacent pad is small. In this case, even if the current pad meets the compensation triggering conditions for insufficient solder paste volume or solder paste volume imbalance, solder paste compensation cannot be performed directly. Instead, it should first be determined whether the minimum spacing after compensation is still not less than the safety spacing threshold. This avoids excessive closeness of the solder paste patterns between two adjacent pads due to solder paste compensation.

[0076] In some embodiments, step S700, performing solder paste compensation on the dual pads corresponding to the candidate dual-pad devices in the compensation PCB, further includes constructing a compensation feasible region, wherein the compensation feasible region is based on a first pad compensation amount. Second pad compensation amount First pad compensation landing point Second pad compensation landing point Let be a variable, and satisfy: in, and These represent the solder paste compensation amounts for the first and second pads, respectively. and These are the compensation landing points for the first and second pads, respectively. , , and These represent the lower and upper limits of the allowable solder paste volume range for the first and second pads, respectively. and These are the lower and upper limits of the total solder paste volume allowed for dual pads, respectively. To allow for a normalized solder paste volume imbalance threshold, The minimum solder paste pitch after compensation. The safety distance threshold is... and These represent the maximum safe compensation amounts for the first and second pads, respectively. The first and second constraints control the solder paste volume of both pads after compensation to remain within their respective allowable ranges. The third constraint controls the total solder paste volume after compensation to remain within the allowable range. The fourth constraint controls the degree of imbalance in normalized solder paste volume between the two pads after compensation. The fifth constraint controls the minimum solder paste spacing between the compensated pads and adjacent pads. The sixth and seventh constraints control the maximum safe compensation amount for each pad. The eighth constraint ensures that the actual compensation amount is not zero. Specifically, The minimum solder paste pitch is related to the current solder paste morphology, compensation amount, compensation landing point, and the position of adjacent pads for the first and second pads. Different combinations of compensation amounts and compensation landing points may result in different edge positions of the compensated solder paste printed pattern, thus leading to different minimum solder paste pitches.

[0077] When the feasible compensation domain is empty, automatic solder paste compensation is not performed. Alternatively, when the feasible compensation domain is empty, the corresponding PCB can be wiped and reprinted, manually inspected, or process intercepted, instead of directly using compensation amounts that do not meet safety constraints for solder paste compensation. This avoids introducing solder paste bridging between adjacent pads, exceeding the total solder paste volume limit, or other manufacturing risks in order to improve local solder paste insufficiency or imbalance.

[0078] When the feasible region for compensation is not empty, the total compensation amount is selected first. The minimum compensation combination.

[0079] When the total compensation amount is the same, select the compensation amount combination that minimizes the normalized solder paste volume loss after compensation.

[0080] When the normalized solder paste volume loss is the same after compensation, select the compensation amount combination that maximizes the minimum solder paste spacing after compensation.

[0081] Among these options, first selecting the compensation combination with the smallest total compensation amount can avoid over-compensation when the compensation conditions are met; when the total compensation amount is the same, selecting the compensation combination with the smallest normalized solder paste volume loss after compensation can prioritize improving the relative solder paste state between the two pads; when the first two conditions are still the same, selecting the compensation combination with the largest minimum solder paste spacing after compensation can increase the space safety margin between adjacent pads.

[0082] As one implementation method, , , and Candidates can be selected from a set of candidates that are compatible with the solder paste compensation accuracy. The candidate set can be pre-established based on the minimum stable resolution of the solder paste compensation operation, making the compensation amount and compensation landing point feasible. When the compensation feasible region is not empty, candidate combinations that satisfy all constraints can be screened from the candidate set, and specific compensation amount combinations and compensation landing point combinations can be determined according to the aforementioned priority.

[0083] After the aforementioned steps are completed, the reference PCB and the compensation PCB proceed to the subsequent component placement and reflow soldering process.

[0084] S800: After component mounting and reflow soldering are completed on the reference PCB and compensation PCB to form the USSD, dual-interface residual response tests are performed to obtain the target abnormal response characteristics of the USSD formed by the reference PCB and the USSD formed by the compensation PCB.

[0085] Optionally, in this step, the reference PCB and the compensation PCB are formed into USSDs after component mounting and reflow soldering, respectively. For both types of USSDs, dual-interface residual response testing is performed to obtain the target abnormal response characteristics corresponding to the candidate abnormal circuit region. The USSD formed by the reference PCB reflects the target abnormal response state without solder paste compensation; the USSD formed by the compensation PCB reflects the target abnormal response state after solder paste compensation. The response characteristics of the first and second interfaces in the target testing stage can be obtained from both types of USSDs using the same or comparable dual-interface testing logic as the aforementioned analysis process, forming target abnormal response characteristics for subsequent comparison.

[0086] The dual-interface residual response test here does not only determine whether the USSD formed by the reference PCB and the USSD formed by the compensation PCB have passed the functional test, but further compares the changes in the corresponding target abnormal response characteristics of the two relative to the reference state of the reference USSD.

[0087] The target abnormal response characteristics of the USSD formed by the reference PCB and the USSD formed by the compensation PCB obtained in the aforementioned steps are used as the basis for determining the validity of the solder paste compensation parameters in step S900.

[0088] S900: When the target abnormal response characteristics of the USSD formed by the compensation PCB are closer to the corresponding reference state of the reference USSD than the USSD formed by the reference PCB, and the preset process quality and functional test conditions are met, the solder paste compensation parameters corresponding to the candidate compensation parameter template are determined to be valid.

[0089] Optionally, in this step, the dual-interface residual response test results of the USSD formed by the reference PCB and the USSD formed by the compensation PCB are compared and verified. When the target abnormal response characteristics of the USSD formed by the compensation PCB are closer to the corresponding reference state of the reference USSD than those of the USSD formed by the reference PCB, it indicates that the solder paste compensation has an improving trend for the target abnormal response. Here, "closer" does not require that the target abnormal response characteristics of the USSD formed by the compensation PCB are completely equal to the reference state of the reference USSD, but rather that the USSD formed by the compensation PCB converges towards the corresponding reference state compared to the USSD formed by the reference PCB. Based on the determination that the target abnormal response characteristics have been improved, it is also determined whether the process quality results and functional test results of the USSD formed by the compensation PCB meet the preset conditions. Therefore, the effectiveness of the solder paste compensation parameters is not determined solely by a single response characteristic change, but rather by a comprehensive judgment combining the improvement of the target abnormal response, the process quality results after reflow, and the functional test results.

[0090] In some embodiments, in step S900, when the target abnormal response characteristics of the USSD formed by the compensation PCB are closer to the corresponding reference state of the reference USSD than those formed by the reference PCB, and the preset process quality and functional test conditions are met, the solder paste compensation parameters corresponding to the candidate compensation parameter template are determined to be valid, including: For each sample pair, obtain the standardized residual difference parameters of the USSD formed by the baseline PCB. Standardized residual differential parameters of the USSD formed by the compensation PCB The residual improvement amount is determined according to the following formula: in, Let be the residual improvement of the i-th sample pair on the j-th response feature during the k-th test phase.

[0091] Specifically, Used to characterize the degree of deviation of the USSD formed by the reference PCB in the corresponding test stage and corresponding response characteristics; Used to characterize the degree of deviation of the USSD formed by the compensated PCB in the corresponding test stage and corresponding response characteristics. When When the value is greater than zero, it means that the absolute value of the standardized residual difference parameter of the USSD formed by the compensation PCB in the corresponding test stage and response characteristics is less than that of the USSD formed by the reference PCB, that is, the deviation of the USSD formed by the compensation PCB from the reference state is reduced.

[0092] The arithmetic mean of the residual improvements across multiple sample pairs is used as the average residual improvement. This average residual improvement is used to reduce the impact of random fluctuations in a single sample pair on the validation results, ensuring that the assessment of the compensation effect is based on the overall changes across multiple sample pairs.

[0093] When a candidate abnormal circuit region is located in an interface circuit region corresponding only to the first interface or an interface circuit region corresponding only to the second interface, if the average residual improvement is greater than a preset improvement threshold, then the corresponding target abnormal response characteristic is determined to have been improved. Specifically, for the region dedicated to the first interface or the region dedicated to the second interface, the target abnormal response characteristic is mainly manifested as an abnormal deviation of one interface relative to the other interface. By judging the average residual improvement, it is possible to evaluate whether the USSD formed by the compensation PCB is closer to the interface differential reference state in the reference USSD than the USSD formed by the base PCB.

[0094] When the candidate abnormal circuit region is located in the common connection area of ​​the power supply network and / or ground network, if the target abnormal response characteristics of the first and second interfaces of the USSD formed by the compensation PCB both converge towards their respective reference states compared to the USSD formed by the reference PCB, then the corresponding target abnormal response characteristics are determined to be improved. In the common connection area, both the first and second interfaces may be affected by the common power supply network, the common ground network, or the state of the corresponding device region. Therefore, it is not appropriate to judge the compensation effect solely based on the change in the standardized residual differential parameters of one interface; instead, it is necessary to separately determine whether the target abnormal response characteristics of the first and second interfaces both converge towards their respective reference states.

[0095] The solder paste compensation parameters are deemed effective when the target abnormal response characteristics are improved and the reflow process quality results and functional test results of the USSD formed by the compensated PCB meet the preset conditions. The reflow process quality results reflect the manufacturing quality status of the compensated PCB after reflow soldering; the functional test results reflect whether the USSD formed by the compensated PCB meets the preset functional requirements. The process quality results and functional test results can serve as constraints in judging the compensation effect, avoiding the neglect of potential soldering quality or functional risks introduced by compensation simply due to improvements in local interface response.

[0096] Based on the above technical solution, this application first executes an equivalent test sequence including multiple test stages through a first test sequence and a second test sequence, and selects a target test stage to obtain interface response characteristics; then, it corrects the response characteristics through test path correction parameters, and determines standardized residual difference parameters by combining the interface reference response differences with the reference USSD. Thus, the impact of test sequence, test path differences, and inherent interface response differences on anomaly detection can be reduced respectively.

[0097] Furthermore, this application does not directly identify abnormal responses as the root cause of an anomaly in a specific pad or device. Instead, it determines candidate abnormal circuit regions by combining standardized residual differential parameters, the circuit connection relationship between the interface circuit area and the power supply network and / or grounding network, and solder paste inspection data. Candidate compensation parameter templates are then established based on recurring solder paste morphology conditions in multiple USSDs exhibiting target abnormal response characteristics. This allows for the establishment of candidate correlations between abnormal responses and local solder paste states, providing a basis for subsequent selection of candidate compensation targets and reducing the risk of blindly adjusting process parameters based solely on the inspection results of a single product or solder paste.

[0098] Furthermore, this application sets up a reference PCB and a compensation PCB for PCBs with matching morphology, so that the compensation PCB performs solder paste compensation while the reference PCB does not. Dual-interface residual response testing is then performed after component placement and reflow soldering. This allows verification of whether solder paste compensation actually improves the target abnormal response based on the comparison results after reflow; and by combining the process quality results and functional test results after reflow, it can be confirmed whether solder paste compensation introduces new manufacturing risks, thereby improving the reliability of solder paste compensation parameter verification.

[0099] It should be understood that, in specific implementations, the aforementioned solder paste testing data, response characteristics obtained from interface testing, reference response differences, standardized residual differential parameters, candidate compensation parameter templates, and verification results can be acquired, calculated, stored, and output through a process that associates manufacturing data with test data. This implementation method is only used to illustrate the implementation conditions of the method in this application and is not intended to limit the method in this application to adopting a specific hardware structure or software architecture.

[0100] The above description, in conjunction with specific embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications and substitutions should be considered within the scope of protection of this application.

Claims

1. A method for verifying residual response solder paste compensation in a USSD dual-interface assembly, applied to a USSD manufacturing process sequentially including solder paste printing, solder paste inspection, component mounting, and reflow soldering, wherein the USSD includes a PCB, a first interface, and a second interface, the PCB having interface circuit areas corresponding to the first interface and the second interface respectively, the first interface and the second interface being at least partially connected to a power supply network and / or a ground network on the PCB, characterized in that, include: The solder paste inspection data of the PCB corresponding to the multiple USSDs that have completed component placement and reflow soldering is obtained during the solder paste inspection stage. The multiple USSDs are subjected to an equivalent test sequence including multiple test stages according to a first test order of passing through the first interface first and then the second interface and a second test order of passing through the second interface first and then the first interface. The target test stage is selected from the equivalent test sequence to obtain the response characteristics of the corresponding interface in the target test stage. The response characteristics are corrected based on the test path correction parameters of the corresponding interface. Based on the corrected response characteristics and the reference response differences of the first and second interfaces of multiple reference USSDs of the same model and meeting the preset reference screening conditions during the target test phase, the standardized residual difference parameters of the multiple USSDs are determined. Based on the standardized residual differential parameters, the circuit connection relationship between the interface circuit region and the power supply network and / or grounding network, and the solder paste detection data, candidate abnormal circuit regions are determined. Candidate dual-pad devices are screened within the candidate abnormal circuit region, and the response characteristics corresponding to the candidate abnormal circuit region that deviate from the reference state of the reference USSD are determined as target abnormal response characteristics. Based on the solder paste morphology conditions that repeatedly occur in multiple USSDs with the target abnormal response characteristics of the candidate dual-pad device, a candidate compensation parameter template is established. In the USSD manufacturing process, PCBs that have completed the solder paste printing and solder paste inspection but have not completed the component mounting, and whose initial solder paste morphology conditions match the candidate compensation parameter template, are selected as the reference PCB and the compensation PCB, respectively. Solder paste compensation is performed on the dual pads corresponding to the candidate dual pad devices in the compensation PCB, while solder paste compensation is not performed on the reference PCB; After the component mounting and reflow soldering are completed on the reference PCB and the compensation PCB to form the USSD, a dual-interface residual response test is performed to obtain the target abnormal response characteristics of the USSD formed by the reference PCB and the USSD formed by the compensation PCB. When the target abnormal response characteristics of the USSD formed by the compensation PCB are closer to the corresponding reference state of the reference USSD than the USSD formed by the reference PCB, and the preset process quality and functional test conditions are met, the solder paste compensation parameters corresponding to the candidate compensation parameter template are determined to be valid.

2. The USSD dual-interface residual response solder paste compensation verification method according to claim 1, characterized in that, The equivalent test sequence includes at least two test phases in standby, read / write, and recovery, and the target test phase is at least one test phase selected from the plurality of test phases included in the equivalent test sequence. When executing the equivalent test sequence, in the first test sequence and the second test sequence, the power supply input voltage of the first interface and the second interface is kept within the same target voltage range, and the test data volume, logical address range, read / write mode, upper limit of speed and test ambient temperature are kept the same or within a preset allowable error range; wherein, at any test moment, only the external power supply positive path and data path corresponding to the currently tested interface are in a valid test connection state, and the untested interface is not connected to the external power supply positive path and data path; The correction of the response characteristics based on the test path correction parameters of the corresponding interface includes: The test path correction parameters are obtained based on a standard reference load, a standard reference board, or the reference USSD. The test path correction parameters include at least one of the following: supply voltage drop deviation, current acquisition deviation, contact status reference value, and test channel recovery time.

3. The USSD dual-interface residual response solder paste compensation verification method according to claim 2, characterized in that, Between the execution of the first test sequence and the second test sequence, a state recovery process is performed. The state recovery process includes at least one of the following: idle waiting, file system synchronization or safe unloading, power failure and power-on, standby current recovery to a preset stable range, interface re-enumeration success, recovery to the same test partition state, using the same logical address range, and performing the same preset write preprocessing. When the same USSD cannot be restored to the same or equivalent internal state in the first test sequence and the second test sequence so that the response characteristics under the forward and reverse test sequences are comparable, at least two USSDs of the same model, the same material batch and the same initialization state are selected, one USSD performs the first test sequence and the other USSD performs the second test sequence.

4. The USSD dual-interface residual response solder paste compensation verification method according to claim 3, characterized in that, The standardized residual difference parameters of the multiple USSDs are determined based on the corrected response characteristics and the reference response differences of the first and second interfaces of the multiple reference USSDs of the same model and meeting the preset reference screening conditions during the target testing phase. This includes: For response features whose decreasing values ​​indicate an increased risk of anomalies, the corrected response features are reversed so that an increase in the value of the reversed response features indicates an increased risk of anomalies. For the response characteristics after the k-th test phase, the j-th direction change, and the p-th interface, the response values ​​are balanced in the following order: in, For the sequential balanced response value of the p-th interface, The j-th corrected response feature of the p-th interface in the k-th test phase, obtained according to the first test order. The j-th corrected response feature of the p-th interface in the k-th test phase is obtained according to the second test order, where p=1 represents the first interface and p=2 represents the second interface; When the first test sequence and the second test sequence are executed using different USSDs respectively and These are the mean or median of the response characteristics obtained by USSDs that meet the same matching conditions in the corresponding test order; The interface differential response value is determined according to the following formula: The standardized residual difference parameters are determined according to the following formula: in, For the k-th test phase and the j-th response feature, the interface differential response value is... For the standardized residual difference parameter of the j-th response feature in the k-th test phase, The mean of the interface differential response of the reference USSD. The interface differential response dispersion of the reference USSD, The preset minimum dispersion is greater than zero.

5. The USSD dual-interface residual response solder paste compensation verification method according to claim 4, characterized in that, The candidate abnormal circuit region includes a first interface-specific region, a second interface-specific region, and a common connection region; The first interface-specific area is the interface circuit area corresponding to the first interface and located before the common connection point of the power supply network and / or grounding network; The second interface-specific area is the interface circuit area corresponding to the second interface and located before the common connection point of the power supply network and / or grounding network; the common connection area is the power supply network and / or grounding network and its corresponding device area that are commonly connected to the first interface and the second interface. The step of determining candidate abnormal circuit regions based on the standardized residual differential parameters, the circuit connection relationship between the interface circuit region and the power supply network and / or grounding network, and the solder paste detection data includes: When the response characteristics of the first interface deviate from its reference range, and the corresponding response characteristics of the second interface are within its reference range, and the following conditions are met: When this happens, the first interface-specific area is identified as a candidate abnormal circuit area; When the response characteristics of the second interface deviate from its reference range, and the corresponding response characteristics of the first interface are within its reference range, and the following conditions are met: When this occurs, the second interface-specific area is identified as a candidate abnormal circuit area; When both the first interface and the second interface deviate from their respective reference ranges and the anomaly direction is consistent during the same testing phase, and the following conditions are met: When this occurs, the common connection region is identified as a candidate abnormal circuit region; in, The residual threshold is the value greater than zero for the k-th test phase and the j-th response feature.

6. The USSD dual-interface residual response solder paste compensation verification method according to claim 5, characterized in that, The candidate dual-pad devices to be screened include: Devices with a first pad and a second pad are selected from the interface power supply path, ground return path, or input filter area within the candidate abnormal circuit area. The solder paste morphology conditions include one or more of the following: solder paste volume of the first pad and the second pad, solder paste height, solder paste area, solder paste centroid offset, normalized solder paste volume loss of the two pads, and minimum spacing between the first pad and the second pad; The recurring solder paste morphology conditions include: when the same or similar solder paste morphology conditions repeatedly appear in the same device type, the same pad structure, or the same device area in multiple USSDs with the target abnormal response characteristics, and the occurrence ratio of the solder paste morphology conditions in the reference USSD is lower than a preset ratio, the solder paste morphology conditions are determined to be recurring solder paste morphology conditions. The candidate compensation parameter template includes at least the candidate dual-pad device, the corresponding pad, the repeated solder paste morphology conditions, the target abnormal response characteristics, the compensation trigger threshold, and the compensation rules.

7. The USSD dual-interface residual response solder paste compensation verification method according to claim 1, characterized in that, In the USSD manufacturing process, PCBs that have completed solder paste printing and solder paste inspection but have not completed component mounting, and whose initial solder paste morphology conditions match the candidate compensation parameter template, are selected as the reference PCB and the compensation PCB, respectively, including: The selected PCB is matched based on the product model, material batch, PCB batch, and initial solder paste morphology. Two PCBs with the same matching conditions are formed into a sample pair, and one PCB in the sample pair is used as the reference PCB and the other PCB is used as the compensation PCB. The reference PCB and the compensation PCB are made to be identical or within a preset allowable error range in subsequent component mounting conditions, reflow soldering conditions and testing environment.

8. The USSD dual-interface residual response solder paste compensation verification method according to claim 1, characterized in that, The step of performing solder paste compensation on the dual pads corresponding to the candidate dual-pad devices in the compensation PCB includes: Solder paste compensation is performed when the solder paste volume of the first pad is lower than the first pad compensation trigger threshold, the solder paste volume of the second pad is lower than the second pad compensation trigger threshold, or the imbalance of the normalized solder paste volume of both pads exceeds the preset imbalance trigger threshold. The volume loss of the dual-pad normalized solder paste is determined according to the following formula: in, To measure the volume loss of normalized solder paste before compensation for dual pads, and These are the current solder paste volumes for the first and second pads, respectively. and These are the reference solder paste volumes for the first and second pads, respectively. When the center of gravity of the solder paste on the first or second pad shifts toward the adjacent pad and the corresponding minimum spacing is lower than the preset shape warning threshold, solder paste compensation is performed only when the minimum spacing after compensation is not less than the safe spacing threshold.

9. The USSD dual-interface residual response solder paste compensation verification method according to claim 8, characterized in that, The step of performing solder paste compensation on the dual pads corresponding to the candidate dual-pad devices in the compensated PCB further includes constructing a compensation feasible region, wherein the compensation feasible region is based on a first pad compensation amount. Second pad compensation amount First pad compensation landing point Second pad compensation landing point Let be a variable, and satisfy: in, and These represent the solder paste compensation amounts for the first and second pads, respectively. and These are the compensation landing points for the first and second pads, respectively. , , and These represent the lower and upper limits of the allowable solder paste volume range for the first and second pads, respectively. and These are the lower and upper limits of the total solder paste volume allowed for dual pads, respectively. To allow for a normalized solder paste volume imbalance threshold, The minimum solder paste pitch after compensation. The safety distance threshold is... and These are the maximum safety compensation amounts for the first and second pads, respectively. Automatic solder paste compensation is not performed when the compensation feasible field is empty; When the feasible compensation domain is not empty, the total compensation amount is selected first. The minimum combination of compensation amounts; When the total compensation amount is the same, select the compensation amount combination that minimizes the normalized solder paste volume loss after compensation. When the normalized solder paste volume loss is the same after compensation, select the compensation amount combination that maximizes the minimum solder paste spacing after compensation.

10. The USSD dual-interface residual response solder paste compensation verification method according to claim 7, characterized in that, When the target abnormal response characteristics of the USSD formed by the compensated PCB are closer to the corresponding reference state of the reference USSD than those formed by the base PCB, and the preset process quality and functional test conditions are met, the solder paste compensation parameters corresponding to the candidate compensation parameter template are determined to be valid, including: For each sample pair, obtain the standardized residual difference parameters of the USSD formed by the baseline PCB. Standardized residual differential parameters of the USSD formed by the compensation PCB The residual improvement amount is determined according to the following formula: in, Let be the residual improvement of the i-th sample pair on the j-th response feature in the k-th test phase; The arithmetic mean of the residual improvement of multiple sample pairs is taken as the average residual improvement. When the candidate abnormal circuit region is located in the interface circuit region corresponding only to the first interface or the interface circuit region corresponding only to the second interface, if the average residual improvement amount is greater than the preset improvement threshold, it is determined that the corresponding target abnormal response feature has been improved. When the candidate abnormal circuit region is located in the common connection region of the power supply network and / or grounding network, if the target abnormal response characteristics of the first and second interfaces of the USSD formed by the compensation PCB converge to their respective reference states compared with the USSD formed by the reference PCB, it is determined that the corresponding target abnormal response characteristics have been improved. When the target abnormal response characteristics are improved, and the reflow process quality results and functional test results of the USSD formed by the compensated PCB meet the preset conditions, the solder paste compensation parameters are determined to be effective.

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