A memory grain quality screening method and system

Abstract

The application discloses a memory particle quality screening method and system. The method comprises the following steps: placing a to-be-tested memory particle on a standardized test mainboard and reading the type of the to-be-tested memory particle; constructing a stress gradient matrix according to the type, which contains multiple groups of test conditions, each group of test conditions including a frequency parameter, a timing parameter, a voltage parameter and a temperature parameter, determining the comprehensive stress intensity of each group of test conditions by means of weighted summation based on the test conditions, and classifying the multiple groups of test conditions according to the comprehensive stress intensity; under each group of test conditions, the surface temperature of each to-be-tested memory particle is collected, a preset read-write test algorithm is executed on the to-be-tested memory particle and multiple rounds of cycle tests are performed, and test data corresponding to each group of test conditions is obtained; and according to the type classification result of the test conditions, the test data, the surface temperature and a preset judgment rule, the to-be-tested memory particle is classified in quality; the quality grade of the particle can be objectively and finely distinguished.

Description

Technical Field

[0001] This invention relates to the field of semiconductor memory testing technology, and in particular to a method and system for screening the quality of memory chips. Background Technology

[0002] DRAM (Dynamic Random Access Memory) chips, as core components of memory modules, directly determine the quality of end products through their electrical performance and stability. However, current chip screening methods in the industry have significant limitations. For example, original equipment manufacturer (ATE) testing uses automated testing equipment to detect electrical parameters of chips and classify them according to speed bins during the wafer or packaging stage. While efficient, this method suffers from significant differences between the testing environment and actual system loads, covering only physical layer characteristics and failing to expose potential defects in system-level application scenarios such as data retention, crosstalk, and temperature drift. Another example is module-level finished product testing, which involves soldering chips to the PCB and performing functional tests using testing software. While closely mimicking real-world usage scenarios, this approach is severely delayed, only identifying problems at the finished product stage. Furthermore, external factors such as PCB layout differences and uneven heat dissipation design can mask the true capabilities of the chips, leading to defective products being released or high-quality chips being misjudged. Finally, manual screening relies on engineers manually adjusting BIOS frequency, timings, and voltages and subjectively judging chip quality. This method suffers from inconsistent testing conditions, unquantifiable results, and poor repeatability, making it completely unsuitable for large-scale industrial production.

[0003] In summary, the relevant technologies generally suffer from defects such as a disconnect between testing scenarios and actual applications, delayed screening and intervention, single evaluation dimensions, and lack of standardization. This leads to inferior chips flowing into high-end product lines and high-quality chips being underestimated and mismatched, which restricts the refined positioning and cost control of memory products.

[0004] Therefore, it is necessary to provide a new method and system for screening memory chip quality to solve the above problems. Summary of the Invention

[0005] This invention provides a method and system for screening memory chip quality, which can objectively and precisely distinguish the quality grade of the chips.

[0006] To solve the above-mentioned technical problems, one technical solution adopted by the present invention is: to provide a method for screening the quality of memory chips, comprising: The memory chip under test is placed on a standardized test motherboard and its type is read; the memory chip under test is a bare memory chip, which is connected to the test motherboard through a standardized test socket. A stress gradient matrix is ​​constructed according to the type, the stress gradient matrix contains multiple sets of test conditions, each set of test conditions includes frequency parameters, timing parameters, voltage parameters and temperature parameters. Based on the frequency parameters, timing parameters, voltage parameters and temperature parameters, frequency offset, timing tightening degree, voltage offset and temperature offset are calculated. Based on the weighted sum of the frequency offset, timing tightening degree, voltage offset and temperature offset, the comprehensive stress intensity of each set of test conditions is determined. The multiple sets of test conditions are classified according to the comprehensive stress intensity. Under the test conditions of each set of stress gradient matrix, the surface temperature of each memory chip under test is collected, a preset read / write test algorithm is executed on the memory chip under test and multiple rounds of loop tests are performed to obtain the test data corresponding to each set of test conditions. The quality of the memory chip under test is graded based on the type and classification results of the test conditions, the test data, the surface temperature, and the preset judgment rules.

[0007] According to one embodiment of the present invention, the number of test conditions is not less than three sets; the step of classifying the multiple sets of test conditions according to the comprehensive stress intensity includes: Based on the increasing order of the comprehensive stress intensity, the multiple sets of test conditions are divided into three levels: basic stress conditions, medium stress conditions, and maximum stress conditions.

[0008] According to one embodiment of the present invention, the read / write test algorithm includes at least one of March C+, Checkerboard, Random Pattern, and data retention test.

[0009] According to one embodiment of the present invention, the test data includes at least one of the following: number of bit errors, error rate, number of cycles in which the first error occurs, error address distribution, and system-level fault events; the system-level fault events include system crash, blue screen, or ECC uncorrectable error.

[0010] According to one embodiment of the present invention, the step of classifying the quality of the memory chip under test based on the type classification result of the test conditions, the test data, the surface temperature, and a preset judgment rule includes: If the number of bit errors occurring in the tested memory chip is zero after a preset number of consecutive cycles under the highest stress condition, and the surface temperature does not exceed a first preset value, then it is determined to be of the first level. If the number of bit errors occurring in the tested memory chip is zero after a preset number of consecutive cycles under medium stress conditions, and the number of bit errors occurring in the preset number of consecutive cycles under the highest stress conditions is less than a second preset value, or the first error occurs after the Xth cycle, then it is determined to be of the second level. If the number of bit errors in the memory chip under test is zero after a preset number of cycles under the basic stress condition, and the error rate is greater than a third preset value under the medium stress condition, or an error occurs before the Yth cycle under the highest stress condition, then it is determined to be of the third level. If the number of bit errors in the tested memory chip is not zero under the basic stress condition, it is determined to be a defective product. Wherein, X is 50% of the preset number of times, and Y is 10% to 20% of the preset number of times; and Y <X。

[0011] According to one embodiment of the present invention, the number of bit errors is statistically classified according to the type of the read / write test algorithm, including at least one of March C+ type errors, Checkerboard type errors, Random Pattern type errors, and data retention test type errors; the step of classifying the quality of the memory chip under test according to the type classification result of the test conditions, the test data, the surface temperature, and the preset judgment rules further includes: Based on the error address distribution in the test data, the spatial clustering degree of the error addresses is calculated. The spatial clustering degree is the maximum proportion of the number of bit errors in a single bank or a single row to the total number of bit errors in the same group of test conditions. If the spatial aggregation degree is greater than the fourth preset value, it is determined to be a local defect type particle, and the quality classification is downgraded by one level based on the original quality classification. If the spatial clustering degree is greater than the fifth preset value and the test data contains the data retention test error, then it is determined to be a defective product; the fifth preset value is greater than the fourth preset value; If the test data includes the system-level fault event, the product is determined to be non-conforming or downgraded by one level from the original quality grade.

[0012] According to an embodiment of the present invention, the memory chip quality screening method further includes: After each batch of the memory chips under test is completed, the stress gradient matrix configuration of the next batch of the memory chips under test is automatically optimized based on the statistical results of the current batch and historical cumulative data.

[0013] According to an embodiment of the present invention, the memory chip quality screening method further includes: reading the identification information of the memory chip to be tested, binding the identification information of the memory chip to be tested with the quality grading result and writing it into a database; the identification information includes at least one of Lot ID, Die ID and Wafer ID.

[0014] To solve the above-mentioned technical problems, another technical solution adopted by the present invention is: to provide a memory chip quality screening system, comprising: Standardized test motherboard, including standardized test sockets for accommodating memory chips under test; The memory control module is used to configure the frequency parameters and timing parameters of the memory chip under test. The temperature control module is used to configure the temperature parameters of the memory chip under test; A programmable power supply module for configuring the voltage parameters of the memory chip under test; Temperature acquisition module, used to acquire the surface temperature of the memory chip under test; The test control module is used to execute the memory chip quality screening method described above.

[0015] The beneficial effects of this invention are: the memory chip quality screening method is applicable to quality grading and differentiated applications in the incoming inspection stage of memory chips. Through standardized testing environment and multi-dimensional stress coupling testing, the potential defects of the chips under different boundary conditions are fully stimulated, and the evaluation results are closer to real application scenarios. Fine grading is achieved through stress gradient matrix, breaking through the limitations of traditional binary judgment and providing data support for differentiated product positioning. The whole process is automated, does not rely on human experience, and has high testing efficiency. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the architecture of a memory chip quality screening system according to an embodiment of the present invention.

[0017] Figure 2 This is a schematic diagram of a memory chip quality screening method according to an embodiment of the present invention.

[0018] Figure 3 This is a schematic diagram of a memory chip quality screening method according to another embodiment of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0020] The terms "first," "second," and "third" used in this invention are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this invention are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0021] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0022] Figure 1 This is a schematic diagram of the architecture of a memory chip quality screening system according to an embodiment of the present invention. Please refer to [link / reference]. Figure 1 The memory chip quality screening system 100 includes a standardized test motherboard 10, a memory control module 20, a temperature control module 30, a programmable power supply module 40, a temperature acquisition module 50, and a test control module 60.

[0023] The standardized test motherboard 10 includes a standardized test socket for accommodating the memory chip under test. The standardized test motherboard 10 adopts a uniform PCB layout, and the signal trace length, impedance matching and power integrity of the standardized test socket are kept consistent to eliminate the interference of PCB wiring and heat dissipation conditions on the test results.

[0024] The memory control module 20 is used to configure the frequency and timing parameters of the memory chip under test. The memory control module 20 may include a clock source and a timing register.

[0025] The temperature control module 30 is used to configure the temperature parameters of the memory chip under test; the temperature control module 30 includes a temperature control chamber, a heating device, and a heat dissipation device.

[0026] The programmable power supply module 40 is used to configure the voltage parameters of the memory chip under test; the programmable power supply module 40 is equipped with a voltage feedback loop.

[0027] The temperature acquisition module 50 is used to acquire the surface temperature of the memory chip under test; the temperature acquisition module 50 includes a thermocouple or a thermistor.

[0028] The test control module 60 serves as the main control unit, used to execute the memory chip quality screening method, including running the screening algorithm, loading the stress gradient matrix configuration, issuing test commands, collecting test data, performing graded judgment, binding IDs, and writing to the database.

[0029] The specific workflow of the memory chip quality screening system 100 is as follows: The test control module 60 reads the memory chip type and loads the corresponding stress gradient matrix; sends the frequency / timing configuration to the memory control module 20; sends the voltage setting value to the programmable power supply module 40; and sends the target temperature to the temperature control module 30.

[0030] The temperature control module 30 adjusts the ambient temperature to the target temperature, and the temperature acquisition module 50 continuously monitors the surface temperature of the memory chip and feeds it back to the test control module 60 until the temperature stabilizes within ±2°C.

[0031] The memory control module 20 configures the operating parameters of the memory chips; the test control module 60 starts the read / write test algorithm, writes the pattern to the memory chips and reads it back for comparison; the temperature acquisition module 50 collects temperature rise data in real time; all test data are summarized to the test control module 60.

[0032] The test control module presets judgment rules based on the collected test data and outputs the quality level.

[0033] The test control module 60 reads the identification information of the memory chip, binds the identification information with the quality level, and writes it into the database.

[0034] The memory chip quality screening system 100 has clearly defined modules that work together to achieve precise control of four-dimensional stress conditions and automatic acquisition and analysis of test data. The entire process is automated and does not rely on human experience. The modular design facilitates maintenance and upgrades. The four-dimensional stress coupling test fully stimulates the potential defects of the chips, and the evaluation results are close to real applications, while improving the screening accuracy. It can be used for screening in the incoming material stage to prevent defective chips from entering subsequent processes.

[0035] Figure 2 This is a schematic flowchart of a memory chip quality screening method according to an embodiment of the present invention. It should be noted that if substantially the same result is obtained, the method of the present invention does not necessarily require further clarification. Figure 2The illustrated process sequence is limited. For example... Figure 2 As shown, the method includes the following steps: Step S1: Place the memory chip under test on the standardized test motherboard and read the type of the memory chip under test.

[0036] In step S1, the standardized test motherboard includes a test socket for accommodating the memory chip under test. The standardized test motherboard adopts a uniform PCB layout, and the signal trace length, impedance matching, and power integrity of the standardized test socket are consistent to eliminate interference from differences in PCB wiring and heat dissipation conditions on the test results, ensuring good repeatability. The memory chip under test is a bare memory chip, connected to the test motherboard via the standardized test socket. The chip type (such as DDR5-4800, DDR4-3200, etc.) is identified by reading the memory chip's SPD (Serial Presence Detect) information or laser marking, and its JEDEC nominal parameters (such as nominal frequency, nominal timings, nominal voltage, nominal temperature, maximum operating temperature, etc.) are determined.

[0037] Step S2: Construct a stress gradient matrix according to the type. The stress gradient matrix contains multiple sets of test conditions. Each set of test conditions includes frequency parameters, timing parameters, voltage parameters, and temperature parameters. Based on the frequency parameters, timing parameters, voltage parameters, and temperature parameters, determine the comprehensive stress intensity of each set of test conditions by weighted summation. Classify the multiple sets of test conditions according to the comprehensive stress intensity.

[0038] In step S2, the number of test conditions N is no less than 3 sets, i.e., N≥3, preferably N≥5. Each set of test conditions includes parameter values ​​in four dimensions: frequency parameters, timing parameters, voltage parameters, and temperature parameters. Further, the frequency parameters include the test frequency and the reference frequency; the timing parameters include the test timing parameters and the reference timing parameters; the voltage parameters include the test voltage and the reference voltage; and the temperature parameters include the test temperature and the reference temperature. Here, the reference can be understood as the JEDEC nominal parameter. For example, at least one frequency higher than the JEDEC nominal frequency is set as the test frequency to stimulate the signal integrity margin of the memory chip under test under high-frequency conditions. Another example is setting corresponding timing parameters, including but not limited to CL (CAS Latency), tRCD (RAS to CAS Delay), tRP (Row Precharge Time), and tRAS (Row Active Time). During testing, the timing parameters can be actively tightened to evaluate the stability of the memory chip under test under boundary conditions. For example, nominal, boost, and / or buck voltage values ​​can be set to assess the changes in electrical characteristics of the memory chip under test under different power supply conditions. Another example is setting at least two different junction temperature levels using a temperature control module, such as room temperature and high temperature. High-temperature testing can effectively stimulate potential defects in the memory chip under test, such as increased leakage current and shortened data retention time, under thermal stress conditions. The test conditions in the above four dimensions can be combined and configured to construct a stress gradient matrix containing multiple sets of test conditions. For example, a high-stress test condition containing "high frequency + tight timing + nominal voltage + high temperature" and a basic stress test condition containing "nominal frequency + relaxed timing + nominal voltage + room temperature" can be constructed.

[0039] In some feasible implementations, in step S2, to objectively measure the intensity of each set of test conditions, the stress contribution of each dimension is weighted and quantified by the comprehensive stress intensity. Please refer to [link to relevant documentation]. Figure 3 Step S2 also includes: Step S201: Calculate the frequency offset, timing tightening degree, voltage offset, and temperature offset based on the frequency parameters, timing parameters, voltage parameters, and temperature parameters.

[0040] In this step, the frequency offset represents the increase in test frequency relative to the reference frequency, and the calculation formula is as follows: , For testing frequency, The reference frequency is the JEDEC nominal frequency of the memory chip under test. A higher value indicates higher frequency pressure. Timing tightness represents the degree of tightening of the test timing parameters relative to the baseline timing parameters; the calculation formula is... , The timing parameters to be tested are (any representative value or weighted average of CL, tRCD, and tRP). These are benchmark timing parameters, such as the JEDEC nominal timings of the memory chip under test. The smaller the timing value, the more stringent the constraints. A higher value indicates higher timing stress. Voltage offset represents the deviation of the test voltage from the reference voltage, and is calculated using the following formula: , For testing voltage, The reference voltage is, for example, the JEDEC nominal voltage of the memory chip under test. The larger the value, the further the voltage deviates. Temperature offset represents the increase in test temperature relative to the reference temperature; the calculation formula is... , To test the temperature, As the reference temperature, This is the maximum operating temperature specified by JEDEC. The higher the value, the higher the thermal stress.

[0041] Step S202: Determine the comprehensive stress intensity of each test condition based on the weighted sum of frequency offset, timing tightening degree, voltage offset, and temperature offset.

[0042] In this step, the formula for calculating the Comprehensive Stress Intensity (CSI) is as follows: ,in, This is the frequency offset. For the degree of timing tightening, This is the voltage offset. This is the temperature offset. , , , These are weighting coefficients. The values ​​of each weighting coefficient are determined based on statistical analysis of historical failure data of the memory chips under test. Frequency offset has the most significant impact on chip stability, followed by temperature offset and timing tightening, while voltage offset has a relatively smaller impact. This embodiment can adaptively adjust the above weighting coefficients according to the statistical results of actual failure modes of different chip types (such as DDR4, DDR5, LPDDR), for example... =0.35, =0.25, =0.15, =0.25.

[0043] Step S203: Sort the multiple test conditions in ascending order of comprehensive stress intensity and divide them into three levels: basic stress condition, medium stress condition and highest stress condition.

[0044] In this step, multiple test conditions are sorted by CSI value from smallest to largest and then divided according to the following proportions: Basic stress conditions: the 20% group with the lowest CSI value, for example, when N=5, take group 1; Medium stress conditions: the middle 60% of the CSI values, for example, when N=5, take 3 groups; Maximum stress condition: The 20% group with the highest CSI value, for example, when N=5, take group 1.

[0045] The intensity of each test condition is objectively measured by quantification, avoiding the subjectivity of human experience. In addition, the gradient grading provides a step-by-step evaluation benchmark for subsequent particle quality judgment, improving the consistency of particle quality evaluation.

[0046] Step S3: Under the test conditions of each set of stress gradient matrix, collect the surface temperature of each memory chip under test, execute the preset read and write test algorithm on the memory chip under test and perform multiple rounds of loop test to obtain the test data corresponding to each set of test conditions.

[0047] In step S3, a complete read / write test process is executed under each test condition, with a loop count of no less than 100 times, i.e., the loop count is greater than or equal to 100 times.

[0048] The surface temperature can be a specific temperature value or a temperature rise rate calculated from a specific temperature value. By collecting the surface temperature of each memory chip under test, particle-level temperature monitoring can be achieved, which can accurately locate individual chips with abnormal power consumption or poor heat dissipation.

[0049] The read / write test algorithm includes at least one of March C+, Checkerboard, Random Pattern, and data retention test. As an example, when multiple read / write test algorithms are included, they can be executed sequentially or selectively according to test time requirements. For instance, if the read / write test algorithm includes March C+, Checkerboard, Random Pattern, and data retention test, then March C+ is executed first, followed by Checkerboard, then Random Pattern, and finally the data retention test. Multiple test algorithms can stimulate particle defects from different angles. For example, March C+ detects structural faults, Checkerboard detects coupling interference, Random Pattern detects stability under random data, and the data retention test detects thermally induced charge leakage, achieving comprehensive coverage of various possible failure modes of particles and minimizing the false negative rate.

[0050] The test data includes at least one of the number of bit errors, error rate, the number of cycles at which the first error occurs, error address distribution, and system-level failure events; the system-level failure events include system crash, blue screen, or ECC uncorrectable error. Multi-dimensional data collection provides a sufficient decision basis for subsequent refined classification.

[0051] Step S4: Perform quality classification on the to-be-tested memory die according to the classification result of the test condition type, the test data, the surface temperature, and a preset determination rule.

[0052] In step S4, based on the type classification result, the test data, and the surface temperature, the quality level of the to-be-tested memory die is determined according to the following rules: If the number of bit errors is zero for a preset number of consecutive cycles (e.g., 100) under the highest stress condition for the to-be-tested memory die, and the surface temperature does not exceed a first preset value (e.g., temperature rise rate 2°C / min), it is determined as the first level; If the number of bit errors is zero for a preset number of consecutive cycles (e.g., 100) under the medium stress condition for the to-be-tested memory die, and the number of bit errors is less than a second preset value (e.g., 1e-6) for a preset number of consecutive cycles (e.g., 100) under the highest stress condition, or the first error occurs after the X-th cycle, it is determined as the second level; If the number of bit errors is zero for a preset number of consecutive cycles under the basic stress condition for the to-be-tested memory die, and the error rate under the medium stress condition is greater than a third preset value (e.g., 1e-5), or an error occurs before the Y-th cycle under the highest stress condition, it is determined as the third level; If the number of bit errors is not zero under the basic stress condition for the to-be-tested memory die, it is determined as a non-conforming product; Wherein, X is 50% of the preset number of times, Y is 10%~20% of the preset number of times; and Y<X. For example, if the preset number of times is 100, X is 50, and Y is 10~20.

[0053] The stepwise determination logic makes full use of the information of the stress gradient matrix, and the performance under different stress levels jointly determines the final quality classification, which avoids the contingency of a single test condition; the cycle number dimension is introduced to distinguish "early failure" and "wear-out failure", which improves the accuracy of quality classification.

[0054] Further, the number of bit errors is classified and counted according to the type of read-write test algorithm, including at least one of March C+ type errors, Checkerboard type errors, Random Pattern type errors, and data retention test type errors; the preset determination rules further include: Based on the distribution of error addresses in the test data, the spatial clustering degree of error addresses is calculated. The spatial clustering degree is the maximum proportion of the number of bit errors in a single bank or a single row to the total number of bit errors in the same set of test conditions. Fine-tuning is performed based on the spatial clustering degree and whether there are data-keeping test class errors.

[0055] If the spatial aggregation degree is greater than the fourth preset value, it is determined to be a locally defective particle, and the quality grade is downgraded by one level based on the original quality grade. For example, in step S4, the quality grade is downgraded by one level: first grade → second grade, second grade → third grade, third grade → non-conforming product.

[0056] If the spatial clustering is greater than the fifth preset value and the test data contains data retention test errors, it is judged as a defective product; the fifth preset value is greater than the fourth preset value; for example, the fourth preset value is 50% and the fifth preset value is 80%.

[0057] If the test data includes system-level failure events, the product will be judged as non-conforming or downgraded by one level from its original quality classification.

[0058] This embodiment identifies particles with "few global errors but severe local defects" through spatial error distribution analysis, avoiding the risk of overestimating high-quality particles; the joint determination of data-preserving test errors and spatial clustering further improves the accuracy of defect identification and effectively intercepts potential reliability risks.

[0059] In some feasible implementations, the memory chip quality screening method further includes: After each batch of memory chips is tested, the stress gradient matrix configuration for the next batch of memory chips is automatically optimized based on the statistical results of the current batch and historical cumulative data.

[0060] Specifically, if the error rate of a batch of particles is greater than 30% under medium stress conditions, a transitional condition between basic stress and medium stress will be automatically added to refine the particle size classification. If the pass rate of a batch of particles is greater than 80% under the highest stress conditions, the parameter value of at least one dimension under the highest stress conditions will be automatically increased to fully tap the potential of high-quality particles.

[0061] The adaptive adjustment mechanism of this embodiment enables the testing system to dynamically optimize the testing strategy according to the actual quality distribution of particles from different batches and manufacturers. This avoids both the waste of efficiency caused by over-testing and the missed detection caused by under-testing, thus achieving the optimal allocation of testing resources.

[0062] In some feasible implementations, the memory chip quality screening method further includes: reading the identification information of the memory chip to be tested, binding the identification information of the memory chip to be tested with the quality grading result and writing it into a database.

[0063] The identification information includes at least one of Lot ID, Die ID, and Wafer ID. The binding method can be as follows: package the identification information with the corresponding quality level, test timestamp, test condition configuration, and test data to generate a record, write it to the database, facilitate data traceability, and achieve refined management.

[0064] In memory module manufacturing applications, product lines can be automatically matched based on the quality grade of the chips. For example, first-grade chips are used for e-sports / overclocking product lines, second-grade chips are used for mainstream high-performance product lines, and third-grade chips are used for commercial / entry-level product lines. Defective products are returned to the supplier.

[0065] The memory chip quality screening method of one embodiment of the present invention is applicable to quality grading and differentiated application in the incoming inspection stage of memory chips. Through standardized testing environment and multi-dimensional stress coupling test, the potential defects of the chips under different boundary conditions are fully stimulated, and the evaluation results are closer to the real application scenario. Fine grading is achieved through stress gradient matrix, breaking through the limitations of traditional binary judgment and providing data support for differentiated product positioning. The whole process is automated, does not rely on human experience, and has high testing efficiency.

[0066] The above are merely embodiments of the present invention and do not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A method for screening the quality of memory chips, characterized in that, include: The memory chip under test is placed on a standardized test motherboard and the type of the memory chip under test is read. A stress gradient matrix is ​​constructed according to the type, and the stress gradient matrix contains multiple sets of test conditions. Each set of test conditions includes frequency parameters, timing parameters, voltage parameters, and temperature parameters. Based on the frequency parameters, timing parameters, voltage parameters, and temperature parameters, the comprehensive stress intensity of each set of test conditions is determined by weighted summation. The multiple sets of test conditions are then classified according to the comprehensive stress intensity. Under the test conditions of each set of stress gradient matrix, the surface temperature of each memory chip under test is collected, a preset read / write test algorithm is executed on the memory chip under test and multiple rounds of loop tests are performed to obtain the test data corresponding to each set of test conditions. The quality of the memory chip under test is graded based on the type and classification results of the test conditions, the test data, the surface temperature, and the preset judgment rules. The test data includes at least one of the following: number of bit errors, error rate, number of cycles in which the first error occurs, error address distribution, and system-level fault events; the system-level fault events include system crash, blue screen, or ECC uncorrectable error. The step of classifying the quality of the memory chip under test according to the type classification result of the test conditions, the test data, the surface temperature, and the preset judgment rules includes: If the number of bit errors occurring in the memory chip under test is zero after a preset number of consecutive cycles under the highest stress condition, and the surface temperature does not exceed a first preset value, then it is determined to be of the first level. If the number of bit errors occurring in the tested memory chip after a preset number of consecutive cycles under moderate stress conditions is zero, and the number of bit errors occurring after a preset number of consecutive cycles under the highest stress conditions is less than a second preset value, or the first error occurs after the Xth cycle, then it is determined to be of the second level. If the number of bit errors occurs zero in the preset number of consecutive cycles under basic stress conditions, and the error rate is greater than a third preset value under medium stress conditions, or an error occurs before the Yth cycle under the highest stress conditions, then it is determined to be at the third level. If the number of bit errors in the memory chip under the test is not zero under the basic stress condition, it is determined to be a defective product. Wherein, X is 50% of the preset number of times, Y is 10% to 20% of the preset number of times; and Y < X.

2. The memory chip quality screening method according to claim 1, characterized in that, The number of test conditions is no less than three sets; the comprehensive stress intensity of each set of test conditions is determined by weighted summation based on the frequency parameter, the timing parameter, the voltage parameter, and the temperature parameter; and the multiple sets of test conditions are classified according to the comprehensive stress intensity, including: Based on the frequency parameters, timing parameters, voltage parameters, and temperature parameters, the corresponding frequency offset, timing tightening degree, voltage offset, and temperature offset are calculated. The comprehensive stress intensity of each set of test conditions is determined by a weighted sum of the frequency offset, the timing tightening degree, the voltage offset, and the temperature offset. Based on the increasing order of the comprehensive stress intensity, the multiple sets of test conditions are divided into three levels: basic stress conditions, medium stress conditions, and maximum stress conditions.

3. The memory chip quality screening method according to claim 1, characterized in that, The read / write test algorithm includes at least one of March C+, Checkerboard, Random Pattern, and data retention test.

4. The memory chip quality screening method according to claim 1, characterized in that, The number of bit errors is statistically classified according to the read / write test algorithm type, including at least one of March C+ type errors, Checkerboard type errors, RandomPattern type errors, and data retention test type errors; the step of classifying the quality of the memory chip under test according to the type classification results of the test conditions, the test data, the surface temperature, and the preset judgment rules further includes: Based on the error address distribution in the test data, the spatial clustering degree of the error addresses is calculated. The spatial clustering degree is the maximum proportion of the number of bit errors in a single bank or a single row to the total number of bit errors in the same group of test conditions. If the spatial aggregation degree is greater than the fourth preset value, it is determined to be a local defect type particle, and the quality classification is downgraded by one level based on the original quality classification. If the spatial clustering degree is greater than the fifth preset value and the test data contains the data retention test error, then it is determined to be a defective product; the fifth preset value is greater than the fourth preset value; If the test data includes the system-level fault event, the product is determined to be non-conforming or downgraded by one level from the original quality grade.

5. The memory chip quality screening method according to claim 1, characterized in that, The memory chip quality screening method further includes: After each batch of the memory chips under test is completed, the stress gradient matrix configuration of the next batch of the memory chips under test is automatically optimized based on the statistical results of the current batch and historical cumulative data.

6. The memory chip quality screening method according to claim 1, characterized in that, The memory chip quality screening method further includes: reading the identification information of the memory chip to be tested, binding the identification information of the memory chip to be tested with the quality grading result and writing it into the database; the identification information includes at least one of Lot ID, Die ID and Wafer ID.

7. The memory chip quality screening method according to claim 1, characterized in that, The memory chip under test is a bare memory chip, which is connected to the test motherboard via a standardized test socket.

8. A memory chip quality screening system, characterized in that, include: Standardized test motherboard, including test sockets for accommodating the memory chips under test; The memory control module is used to configure the frequency parameters and timing parameters of the memory chip under test; The temperature control module is used to configure the temperature parameters of the memory chip under test; A programmable power supply module for configuring the voltage parameters of the memory chip under test; Temperature acquisition module, used to acquire the surface temperature of the memory chip under test; A test control module is used to execute the memory chip quality screening method according to any one of claims 1 to 7.

Images