A compatibility test system and method for a mobile phone terminal external PSSD

Abstract

The application relates to the field of computer storage device verification and testing, and discloses a compatibility test system and method for a mobile phone terminal external PSSD, which comprises a smart test fixture, an upper computer and an analysis server; the smart test fixture is provided with a first connecting end connected to the PSSD to be tested, and comprises a power supply output module, an impedance adjusting module and a first control unit; the power supply output module outputs a non-standard power supply waveform with predetermined VBUS power-on parameters based on the instruction of a second control module, so as to simulate the power supply behavior of a target mobile phone; the impedance adjusting module is connected in series in a power supply circuit and is used for adjusting the equivalent series impedance. By simulating the real mobile phone power supply electrical personality and realizing the time alignment of the physical layer and the protocol layer events, the test is improved from the binary PASS / FAIL to quantitative boundary diagnosis, quantitative improvement basis such as critical impedance is provided for PSSD manufacturers, and the technical problems that the existing test cannot reproduce the occasional disk drop fault and the fault cause positioning is inaccurate are solved.

Description

Technical Field

[0001] This invention belongs to the field of computer storage device verification and testing technology, specifically relating to a compatibility testing system and method for external PSSDs in mobile terminals. Background Technology

[0002] The compatibility issues between portable solid-state drives (PSSDs) and smartphones are becoming increasingly prominent. Existing compatibility testing methods primarily rely on manual testing or general-purpose USB interface testers, but these solutions have significant shortcomings. Manual testing is inefficient and struggles to cover underlying protocol errors; general-purpose USB interface testers only focus on PD protocol compliance, while the real cause of PSSD failures is often the transient power supply characteristics of the phone acting as a USB host, such as the VBUS voltage rise slope and non-standard parameters like dynamic IRDrop. Existing testers cannot simulate the electrical "personality" of a real phone, resulting in test results that cannot reproduce intermittent failures, and they lack cross-domain causal correlation analysis capabilities, meaning they cannot effectively align physical layer electrical waveforms with protocol layer events, thus failing to accurately pinpoint the root cause of the failure—for example, they cannot distinguish between "insufficient power supply," "protocol deadlock," or "file system error." Furthermore, existing test results often only output binary "PASS / FAIL" values, lacking diagnostic value and failing to provide R&D personnel with quantitative rectification criteria such as critical impedance or critical current. Therefore, there is an urgent need for a compatibility testing system and method for external PSSDs in mobile terminals that can simulate real mobile phone power supply fingerprints, achieve cross-domain alignment of electrical and protocol events, and provide quantitative boundary diagnostics. Summary of the Invention

[0003] The main purpose of this application is to provide a compatibility testing system and method for external PSSDs in mobile terminals, so as to solve the technical problems in the prior art such as misalignment of PSSD and smartphone compatibility testing objectives, lack of cross-domain causal correlation, and binarization of test results without diagnostic value. It achieves the technical effect of simulating real mobile phone power supply behavior, accurately locating the root cause of faults and providing quantitative rectification basis.

[0004] To achieve the above objectives, this invention provides a compatibility testing system for external PSSDs in mobile terminals, comprising: an intelligent testing fixture, a mobile terminal acting as a host computer, and an analysis server. Wherein: The intelligent test fixture has a first connection terminal for connecting the PSSD under test, and the intelligent test fixture includes a power supply output module, an impedance adjustment module, a first control unit, and a second control module; The second control module is communicatively connected to the external analysis server or the mobile terminal, and is used to receive and parse the target mobile phone power supply fingerprint parameters distributed by the analysis server, and send digital control commands to the lower-level modules. The power supply output module has its input terminal electrically connected to the second control module and its output terminal electrically connected to the first connection terminal via the impedance adjustment module. It is used to output a non-standard power supply waveform with predetermined VBUS power-on parameters based on the instructions of the second control module to simulate the power supply behavior of the target mobile phone. The impedance adjustment module is connected in series in the power supply circuit between the output terminal of the power supply output module and the first connection terminal, and is used to receive the command of the second control module and dynamically adjust the equivalent series impedance of the power supply circuit. The first control unit, whose input terminal is electrically connected to the first connection terminal and whose output terminal is electrically connected to the mobile terminal, is used to monitor electrical abnormal events in the power supply circuit, and when a predetermined abnormality is detected, to send a hardware synchronization signal to the mobile terminal through a specific unused data pin or dedicated data channel in the Type-C interface; The mobile terminal is equipped with a deep testing application, which is used to run tests to collect protocol layer and system layer event logs of the PSSD under test, and to trigger hardware interrupts by capturing the hardware synchronization signal, and record the hardware interrupt trigger time as the time reference zero point for cross-domain analysis. The analysis server is used to receive and store test data from the smart test fixture and the mobile terminal, and to perform aligned cross-domain correlation analysis and fault diagnosis based on the zero point of the time reference.

[0005] To achieve the above objectives, the present invention also provides a compatibility testing method for an external PSSD on a mobile terminal, comprising the following steps: The second control module receives the target mobile phone power supply fingerprint parameters distributed from an external analysis server or mobile terminal, and controls the power supply output module and impedance adjustment module of the intelligent test fixture to output a non-standard power supply waveform simulating the target mobile phone power supply fingerprint parameters to the PSSD under test. During the test, the first control unit monitors electrical abnormal events in the power supply circuit, and when a predetermined abnormality is detected, it sends a hardware synchronization signal to the mobile terminal through a specific unused data pin or dedicated data channel in the Type-C interface. The mobile terminal receives the hardware synchronization signal and captures the hardware interrupt, records the hardware interrupt trigger time as the zero point of the time reference for cross-domain analysis, and timestamps the collected event logs of the protocol layer and system layer based on the zero point of the time reference. The data of the electrical anomaly event marked with a timestamp, along with the event log data, are transmitted to the analysis server; The analysis server performs time-series alignment of the data from the intelligent test fixture and the mobile terminal based on the zero point of the time base. The fingerprint analysis module and the fault diagnosis module perform cross-domain correlation analysis and fault causal chain diagnosis, and generate a diagnostic report containing quantitative electrical parameter boundaries and clear fault root causes based on the analysis and diagnosis results of cross-domain correlation analysis and fault causal chain diagnosis.

[0006] In the compatibility testing system and method for external PSSDs in mobile terminals described in this invention, the power output module and impedance adjustment module of the intelligent test fixture can accurately synthesize non-standard power supply waveforms based on the power supply fingerprint parameters of the target mobile phone (such as VBUS power-on slope and equivalent loop impedance), thereby simulating the electrical "personality" of a real mobile phone. This overcomes the blind spot of existing testers that only focus on PD protocol compliance, and can reproduce intermittent disk drop faults that existing instruments cannot capture, improving the comprehensiveness and accuracy of the test. When the first control unit detects an abnormality in the power supply circuit, it sends a hardware synchronization signal to the host computer. The host computer records this signal as the zero point of time and aligns the protocol layer and system layer event logs it collects to this time reference, realizing cross-domain correlation between physical layer electrical waveforms and protocol layer events. Based on the aligned timestamp data, the analysis server can analyze the causal chain of the fault occurrence—for example, when a voltage drop event occurs before a USB reset event, it is determined to be a power supply fault; when VBUS is stable but the LTSSM state machine is stuck, it is determined to be a protocol fault. This solves the industry pain point that traditional tests cannot distinguish between electrical problems and protocol problems, and achieves accurate fault location. Furthermore, by using boundary search control logic to iteratively search for critical loop impedance and critical current ramp-up time windows using a binary search method, the ambiguous "incompatibility" is transformed into specific electrical parameter margins. This directly provides PSSD manufacturers with a quantitative basis for optimizing power management strategies (PMIC configuration) and firmware code. In addition, the system supports automated parallel testing, significantly improving testing efficiency and covering full-stack verification from the physical layer to the file system, reducing manual intervention and improving the consistency and reliability of test results. Attached Figure Description

[0007] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1 This is an overall structural block diagram of a compatibility testing system for an external PSSD on a mobile terminal, provided in an embodiment of the present invention.

[0009] Figure 2This is a flowchart illustrating a compatibility testing method for an external PSSD connected to a mobile terminal according to an embodiment of the present invention.

[0010] Reference numerals: 100, Intelligent test fixture; 110, First connection terminal; 120, Power output module; 121, Second control module; 130, Impedance adjustment module; 140, First control unit; 200, Host computer; 300, Analysis server. Detailed Implementation

[0011] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0012] The system and method provided by this invention are mainly used to solve the industry problem of difficult-to-reproduce, difficult-to-locate, and difficult-to-rectify compatibility failures caused by the non-standard or different power supply characteristics of mobile phones when PSSDs (portable solid-state drives) are connected to various smartphones (as USB hosts). The system provides an efficient and accurate testing method for PSSD R&D and compatibility verification by accurately simulating the power supply behavior of real mobile phones and performing cross-domain data analysis.

[0013] Before proceeding with the detailed description, several terms used in this application will be explained: Power output module: refers to a circuit unit that can output a specific voltage waveform (VBUS voltage) according to instructions, and its output characteristics (rise slope) can be parameterized.

[0014] Impedance adjustment module: refers to a module that can controllably change its ohmic resistance value in a circuit, used to simulate losses in a circuit, such as cable impedance.

[0015] First control unit: refers to the hardware circuit unit responsible for monitoring specific signals and sending synchronization signals to the outside world when conditions are met.

[0016] Host computer: In this application, it specifically refers to a smartphone device that has a deep testing application installed and serves as a test data acquisition terminal.

[0017] Deep testing application: refers to software installed on the smartphone that can acquire and record the underlying event logs of the smartphone's operating system.

[0018] Hardware synchronization signal: refers to the electrical signal generated by the instantaneous level change of the hardware physical contact, used to physically mark a precise point in time.

[0019] Analysis server: refers to a computing device that can receive, store, and process multi-source test data.

[0020] Zero point in time: refers to a reference starting point in cross-domain analysis that is mutually agreed upon by all parties.

[0021] Critical loop impedance R_critical: refers to the maximum allowable value of the equivalent series impedance of the power supply circuit that would cause a power supply insufficiency fault in the PSSD under test.

[0022] Critical current ramp-up time window T_min: refers to the minimum allowable time window during which the PSSD under test needs to ramp up from the VBUS steady state to the normal operating current in order to avoid protocol response timeout faults.

[0023] Figure 1 This illustration shows a schematic diagram of the structure of a compatibility testing system for an external PSSD on a mobile terminal, as provided in an embodiment of this application. Figure 1 As shown, the compatibility testing system for an external PSSD in a mobile terminal includes: an intelligent test fixture 100, a host computer 200, and an analysis server 300. The intelligent test fixture 100 has a first connection terminal 110 for connecting the PSSD under test, which includes a power output module 120, an impedance adjustment module 130, and a first control unit 140. The power output module 120 is electrically connected to a second control module 121, and its output terminal is electrically connected to the first connection terminal 110 via the impedance adjustment module 130. Based on the instructions of the second control module 121, it outputs a non-standard power supply waveform with predetermined VBUS power-up parameters to simulate the power supply behavior of the target mobile phone. The impedance adjustment module 130 is connected in series in the power supply loop between the output terminal of the power output module 120 and the first connection terminal 110, and is used to receive instructions from the second control module 121 and adjust the power supply loop. The equivalent series impedance of the circuit; the input terminal of the first control unit 140 is electrically connected to the first connection terminal 110, and its output terminal is electrically connected to the host computer 200, for monitoring electrical events in the power supply circuit, and sending a hardware synchronization signal to the host computer 200 when a predetermined abnormality is detected; the host computer 200 has a data port for connecting to the PSSD under test and a signal port for connecting to the first control unit 140, and is equipped with a deep test application for running tests to collect protocol layer and system layer event logs of the PSSD under test, and receiving the hardware synchronization signal as a time reference for cross-domain analysis; the analysis server 300 is communicatively connected to the intelligent test fixture 100 and the host computer 200 via a network, for receiving and storing test data from the intelligent test fixture and the mobile terminal, and performing cross-domain correlation analysis and fault diagnosis based on timestamp alignment.

[0024] Specifically, the intelligent test fixture 100 of the present invention integrates control, playback, and high-frequency sampling into one unit. In the control circuit, the second control module 121 inside the fixture uses a high-frequency microcontroller to establish bidirectional communication feedback with the cloud analysis server 300. The second control module 121 retrieves the power supply fingerprint parameters of the target mobile phone model specified by the user from the server side and converts them into control sequences for the power supply output module 120 and the impedance adjustment module 130.

[0025] The parameterized power stage of the power output module 120 adopts a Buck voltage regulator circuit based on MOSFET chips, coupled with a high-resolution digital driver chip (DRV chip). It can adjust the rise rate, power-on slope, and overshoot peak of the VBUS voltage in real time through multi-stage stepping, with an adjustment accuracy of up to 0.01V / ms. This allows for high-fidelity reproduction of the power-on voltage spike caused by uneven transient response of the PMIC in the target model. The impedance adjustment module 130 is implemented as a programmable impedance network, which consists of a binary weighted parallel array of multiple sets of precision low ESR (equivalent series resistance) power resistors and high-speed solid-state electronic switches (MOSFET switches). It can controllably simulate the DC voltage drop characteristics of cables in the range of 0.05Ω to 5Ω.

[0026] According to the present invention, the system instructs the power supply output module 120 to generate an electrical signal with the characteristics of the target mobile phone through the second control module 121, and instructs the impedance adjustment module 130 to adjust the power supply circuit impedance to the equivalent source impedance level of the target mobile phone, such as adjusting the power supply circuit impedance to a specific VBUS power-on slope, thereby accurately reproducing (replaying) the power supply fingerprint of the real mobile phone on the PSSD port under test. During the test, the first control unit 140 continuously monitors the electrical state of the power supply circuit. When it detects a predetermined abnormality, it immediately sends a hardware synchronization signal to the mobile phone system layer of the host computer 200. This signal is captured by the deep test application on the mobile phone and recorded as a time zero point. The mobile phone simultaneously records protocol layer and system layer events such as USB enumeration, device connection disconnection, and kernel error, and marks the time offset with this zero point as a reference. Finally, the analysis server 300 aligns the electrical waveform data recorded by the fixture with the event log reported by the mobile phone, which includes the time offset, thereby establishing a strict temporal causal relationship between physical layer electrical events such as voltage transients and glitches and protocol layer logical events such as connection, disconnection, and reset. This enables the system to accurately distinguish whether the current test failure is caused by insufficient power supply, protocol mismatch or software driver problem, solves the test blind spot problem, and provides a data foundation for subsequent quantization boundary search.

[0027] In one embodiment, the aforementioned power output module 120 specifically includes a parameterized power stage. This parameterized power stage is electrically connected to the second control module 121, and its output is electrically connected to the impedance adjustment module 130. It receives digital control commands from the second control module 121, synthesizes and outputs a non-standard power supply waveform with a preset VBUS power-up slope and overshoot amplitude. Furthermore, this structure allows for precise control of the VBUS output voltage rise rate, such as simulating the ramp-up effect in mobile phone fast charging protocols. By setting the overshoot amplitude, it reproduces voltage spikes caused by loop compensation differences in different mobile phone power management ICs (PMICs), thereby more realistically reproducing the power supply impact on the PSSD of a specific model. As a specific implementation, the parameterized power stage can be implemented using a MOSFET-based circuit, coupled with a 16-bit resolution DAC (digital-to-analog converter) to generate precise control voltage, achieving VBUS slope adjustment at the 0.01V / ms level.

[0028] In one embodiment, the parameterized power stage mentioned above specifically includes a Buck converter circuit and a DRV chip. The input of the Buck converter circuit is connected to an external DC power supply, and its output is electrically connected to the impedance adjustment module 130. The DRV chip is controlled by the second control module 121 and is electrically connected to the gate of the power switch in the Buck converter circuit, used to drive the power switch to turn on and off to adjust the output voltage waveform. Furthermore, this structure enables precise digital control of the output voltage waveform. The DRV chip, according to instructions sent by the second control module 121, such as a PWM duty cycle sequence, rapidly switches the switching state of the power switch, thereby regulating the inductor's energy storage release in real time and accurately shaping the target VBUS waveform, including the aforementioned rise slope, steady-state voltage value, and overshoot peak value. As a specific implementation, the DRV chip can use a dedicated gate driver IC, whose input is an SPI or I2C digital command from the second control module 121, and whose output drive current can reach several amperes, enabling rapid driving of the MOSFET and ensuring high fidelity of the voltage waveform.

[0029] In one embodiment, the aforementioned first control unit 140 specifically includes a hardware timestamp unit. The input stage of this hardware timestamp unit is electrically connected to the first connection terminal 110, and its output stage is electrically connected to the signal port of the host computer 200. It is used to perform high-speed sampling and comparison of the voltage in the power supply circuit, and when a voltage drop exceeding a preset threshold or an abnormal CC line signal is detected, it generates and outputs a hardware synchronization signal to the host computer via a GPIO pin or a CC pin. Furthermore, this structure enables a rapid response at the nanosecond to microsecond level. When the VBUS voltage dynamically drops due to load changes or other reasons, or when an abnormal level occurs in the CC signal used for protocol negotiation, the unit can immediately capture this event and send a precise synchronization pulse. This allows the event log on the mobile device to be "aligned" with physical layer transient events on the timeline, ensuring the accuracy of cross-domain analysis. As a specific implementation, this hardware timestamp unit can be implemented using a circuit based on an STM32 series microcontroller. It samples the interface voltage at high speed via its internal ADC (analog-to-digital converter) and compares it with a preset threshold. Once triggered, a rising edge pulse is immediately generated through a GPIO port. The preset threshold can be configured via software, for example, to prevent the voltage from dropping more than 5% of its steady-state value.

[0030] In the hardware design for cross-domain timestamp alignment, this invention completely eliminates the conflicting approach of forcibly injecting synchronization level pulses onto the CC (Configuration Channel) line. Because in the standard USB Type-C architecture, the CC line is responsible for transmitting high-frequency USB PD handshake data packets or maintaining specific voltage states (such as Rp / Rd), any external level pulse will cause the PD controller to misjudge and trigger a physical reset, resulting in test interruption. Furthermore, commercial smartphones do not expose any GPIO flying wire pins on their casings.

[0031] To this end, this invention innovatively utilizes specific auxiliary pins in the Type-C physical interface that are idle or unassigned in standard data communication mode—the SBU1 / SBU2 (Sideband Use) pins. The first control unit 140 on the fixture side includes a high-speed sampling circuit and a physical pulse generator, with a sampling frequency of not less than 1kHz. When an electrical abnormality event such as a VBUS voltage drop exceeding 5% or a transient current overload is detected in real time, the physical pulse generator immediately transmits a nanosecond-level narrow-level pulse through the SBU pin as a hardware synchronization signal (HW_IRQ). After the physical pin of the mobile terminal captures this pulse, it directly reaches the underlying operating system, triggering the highest priority hardware interrupt. The arrival time of this hardware interrupt signal is recorded as the first system time (i.e., the time base zero point), thereby ensuring that the alignment error between the hardware and software ends is controlled within ±500μs without completely disrupting USB PD and high-frequency high-speed data line communication.

[0032] In one embodiment, the aforementioned hardware synchronization signal is a logic level pulse, with the rising or falling edge defining the time point as the cross-domain aligned time zero point. This hardware timestamp marker unit sends the hardware synchronization signal to the host computer 200 via the CC pin of the Type-C interface or a dedicated GPIO pin on the smart test fixture 100. Furthermore, using this explicit level transition signal to define the time zero point provides the host computer 200 with a unique and clear time reference marker. Using the Type-C CC pin allows the use of existing USB-C physical connections without additional wiring; while using a dedicated GPIO pin provides greater flexibility, especially suitable for iOS devices using Lightning adapters.

[0033] In one embodiment, the aforementioned host computer 200 specifically includes a smartphone. The smartphone's physical layer connects to the PSSD under test via a USB Type-C or Lightning adapter, and its system layer deploys a deep testing application. This deep testing application includes a kernel event listener and a time alignment module. The kernel event listener is used to capture and filter USB subsystem event logs in the operating system kernel in real time, and the time alignment module is used to capture hardware synchronization signals and record the system time at the arrival of these signals as the time base. Furthermore, using a smartphone as the host computer allows direct access to the most realistic mobile phone system environment and protocol stack behavior. The recorded kernel logs, such as "USB device enumeration successful," "device removed," and "power state change," are direct evidence for determining the PSSD's operating status on the mobile phone. The time alignment module's function of capturing hardware interrupt signals ensures a common time base for electrical events and these log events. As a specific implementation, for Android phones, the kernel event listener can capture logcat kernel logs via ADB (Android Debug Bridge); for iOS phones, USB event information needs to be obtained through a specific driver interface.

[0034] In one embodiment, the aforementioned time alignment module is configured to: record the arrival time of the hardware interrupt signal as the first system time; mark the offset of each protocol event or system event collected by the kernel event listener relative to the first system time; and upload the event log marked with this offset to the analysis server 300. Furthermore, using an offset method instead of absolute time for uploading reduces the risk of errors that may arise from network time synchronization between the mobile phone and the fixture. All uploaded event logs are time-offsets relative to the common reference first system time, with time offsets within ranges such as +5ms or +10.2ms. Thus, during correlation analysis on the server side, only the offset time of the event logs needs to be aligned with the electrical waveform recorded by the fixture that includes the first system time to reconstruct the complete timing chain. This significantly simplifies the data alignment logic and improves the accuracy of the analysis.

[0035] In one embodiment, the impedance adjustment module 130 is implemented as a programmable impedance network, which is connected in series between the output terminal of the power supply output module 120 and the first connection terminal 110. This programmable impedance network is controlled by the second control module 121, and its equivalent series impedance value can be dynamically adjusted to simulate the DC voltage drop characteristics of cables of different qualities or lengths. Furthermore, by using a programmable impedance network, various scenarios, ranging from brand-new high-quality cables to low-quality, aged, or poorly connected cables, can be simulated without replacing the physical cables, thereby testing the operational stability of the PSSD under different cable voltage drops. By parametrically scanning this impedance value, the tolerance boundary of the PSSD to cable impedance can be quantitatively evaluated.

[0036] In one embodiment, the programmable impedance network is specifically composed of a combination of multiple precision power resistors and multiple MOSFET switches. The on or off states of these MOSFET switches are controlled by a second control module 121 to selectively connect or bypass the precision power resistor in the power supply circuit, thereby changing the total impedance value. Furthermore, this parallel-to-series structure allows for fine adjustment of the total impedance by controlling the combination of resistors with different values, such as binary weighting of the total impedance. The precision power resistors ensure the accuracy and stability of the impedance value, while the MOSFET switches provide fast switching capability and low on-resistance, avoiding the introduction of additional nonlinear errors. As a specific implementation, the network can consist of four MOSFETs and precision resistors, with an impedance adjustment range of 1Ω to 100Ω and a step accuracy of 0.01Ω.

[0037] In one embodiment, the aforementioned analysis server 300 specifically includes a data preprocessing module, a fault diagnosis module, and a report generation module. The data processing module standardizes and cleans the received electrical waveform data and event log data; the fault diagnosis module identifies fault types and locates root causes based on timestamp-aligned cross-domain data; and the report generation module generates a compatibility test report containing specific electrical parameter boundaries based on the diagnostic results. Further, the data preprocessing module is responsible for filtering noise, unifying data formats and time units, and preparing a clean and consistent dataset for subsequent analysis; the core task of the fault diagnosis module is to determine whether the fault originates from power supply, protocol, or file system driver by analyzing the aligned time sequence relationship, providing a clear root cause classification; and the report generation module integrates this classification and related measurement parameters into a structured diagnostic report, breaking through the traditional "PASS / FAIL" binary result and providing quantifiable rectification directions.

[0038] In one embodiment, the analysis server 300 further includes a fingerprint analysis module and a fingerprint database. The fingerprint database stores power supply characteristic parameters of various mobile phone models used as USB hosts, including VBUS power-on slope, default current limit value, and equivalent source impedance. The fingerprint analysis module trains a fault diagnosis model based on historical data from the fingerprint database, used for anomaly identification and classification of new test data. Furthermore, by building and continuously updating the fingerprint database, the system can "remember" the typical power supply behavior of different brands and models of mobile phones. When performing a new PSSD test, only the target mobile phone model needs to be selected to call its fingerprint parameters for simulation. The fingerprint analysis module, using a model trained on historical data, can intelligently identify abnormal patterns in voltage waveforms, improving the detection rate and diagnostic accuracy of intermittent and edge faults. As a specific implementation, the fingerprint database can be implemented using a cloud database, supporting the synchronization and updating of power supply fingerprints for the latest mobile phones released via the Internet.

[0039] Specifically, due to the significant differences in the underlying permissions and driver architectures of the Android and iOS operating systems, the mobile terminal of this invention implements deep kernel log capture and relative timestamp binding through different software mechanisms: Example 1: PSSD Compatibility Testing for the iOS Ecosystem In the closed environment of iPhone series mobile phones, the application layer cannot directly capture Kernel Log. In this embodiment, the deep testing application of the mobile terminal develops a USB communication monitoring module based on the official DriverKit and IOKit.framework framework. Due to iOS's restrictions on physical interrupts, the hardware synchronization signal of the fixture is transmitted through the dedicated control channel of a specific MFi certified adapter. When the time alignment module captures this physical synchronization event, it obtains the system's high-precision monotonic clock time (mach_absolute_time()) through the sysctl() system call as the first system time, which is the zero point of the time base. Subsequently, all software layer interaction events captured by the kernel event listener do not use absolute time, which is prone to network drift, but instead mark the relative time offset (Offset) of their occurrence time relative to the first system time, and package the logs with the offset and upload them to the server.

[0040] Example 2: PSSD Compatibility Testing for the Android Ecosystem In the Android system environment, the deep testing application is compiled as a system-pre-installed application (SystemApp), and explicit permissions to read kernel logs are granted by statically modifying the SELinux policy in the system firmware (specifically, the policy configuration is: allow system_app kmsg_device:chr_file rw_file_perms;). The kernel event listener reads the / dev / kmsg device node in real time, focusing on filtering and parsing the LTSSM (Link Training State Machine) low-level logic change logs output by USB controller drivers such as Synopsys DWC3. The time alignment module receives and binds hardware interrupts triggered by SBU pins through low-level system calls. The test benchmarks for the two embodiments are shown in Table 1 below: Table 1: Test Benchmark Table for Two Examples In one embodiment, the fault diagnosis model described above is a random forest model; the feature vector of the test data input to this model includes at least the VBUS voltage rise time, steady-state voltage value, and voltage response characteristics under dynamic load. Furthermore, employing the random forest ensemble learning model effectively handles multi-feature, nonlinear classification problems, exhibits strong resistance to overfitting, and is particularly suitable for processing complex local features in electrical waveform data. Selecting the voltage rise time can determine whether the charging protocol is compatible in the initial stage; the steady-state voltage value reflects the adequacy of the power supply; the voltage response under dynamic load (such as voltage sag depth and recovery speed) reflects the power supply load regulation rate and transient response capability, all of which are key features for evaluating power supply quality and relating to compatibility faults.

[0041] In one embodiment, the test system further includes boundary search control logic. When the fault diagnosis module initially determines that a compatibility fault has occurred, the boundary search control logic is triggered, controlling the second control module 121 to iteratively adjust the impedance value of the programmable impedance network or the current ramp-up time window after the VBUS of the power supply output module 120 stabilizes using a binary search method, automatically searching for the critical electrical parameter values ​​that cause the PSSD under test to malfunction. Furthermore, the boundary search control logic automates and efficiently searches for fault turnaround points. When the initial test fails, the system does not simply report the failure but automatically enters "exploration mode," rapidly approximating the impedance or time boundary causing the fault using a binary search method. This replaces the tedious process of repeated manual attempts, greatly improving test analysis efficiency and enabling the acquisition of accurate critical parameter values.

[0042] Specifically, after the analysis server 300 receives the aligned dataset, the data preprocessing module performs standardization and cleaning, and the fingerprint analysis module is responsible for evaluating physical feature deviations. The fault diagnosis module integrates a machine learning-based fault classification and identification model. The model's feature vector includes at least the VBUS voltage rise time, steady-state voltage value, and voltage response area and drop slope under dynamic load. The model outputs a multi-dimensional fault probability distribution, accurately identifying the root cause. For example, when the "voltage drop event" recorded by hardware sampling occurs before the "USB bus reset event" in the phone's kernel log on the timeline, it is determined to be a physical power supply insufficiency fault; when the VBUS voltage waveform is stable throughout but the LTSSM log shows it stuck in the Polling.Active state, it is determined to be a logic layer protocol handshake mismatch fault.

[0043] When the fault diagnosis module initially determines that a compatibility fault has occurred, the system immediately activates the server's boundary search control logic via the reverse communication link. This logic uses a binary search closed-loop iteration mechanism to generate high-frequency linkage with the second control module 121 of the fixture. Taking the search for the critical loop impedance R_critical as an example, the power-on slope and other parameters are first fixed, and the impedance is amplified by binary search from the initial impedance. After each impedance adjustment, the system automatically restarts the test, and the fault diagnosis module outputs in real time whether the current adjustment result is PASS or FAIL and immediately feeds it back to the boundary search logic. If it is determined to be PASS, the search logic sends an instruction to the impedance network to continue increasing the impedance; if it is determined to be FAIL, the impedance is reduced by binary search in the next iteration. Through this closed-loop test iteration, the system adaptively and quickly converges until the precise and quantitative critical incompatible impedance boundary and critical current boundary are located. An example of its automated boundary search test is shown in Table 2 below: Table 2: Automated Boundary Search Test Table for System Activation Server Finally, the report generation module extracts the convergence boundary value, such as the critical incompatible loop impedance R_critical = 0.95Ω, and automatically assembles a test report rich in quantitative rectification value. This report guides PSSD manufacturers to accurately adjust the undervoltage lockout (UVLO) protection threshold in their internal firmware or optimize the inrush current capacitor configuration of their power management ICs. The entire system achieves fully automated closed-loop testing while ensuring extremely high hardware feasibility.

[0044] In one embodiment, the critical electrical parameters searched specifically include: a critical loop impedance R_critical, which causes the PSSD under test to experience a power supply insufficiency-related disk drop fault when the equivalent series impedance of the power supply loop exceeds this value; and a critical current ramp-up time window T_min, which causes the PSSD under test to experience a connection failure due to protocol response timeout when the allowable current ramp-up time after VBUS stabilization is less than this value. Further, R_critical represents the maximum tolerance of the PSSD to cable and contact impedance, directly guiding cable selection or the design of the PSSD's internal undervoltage lockout threshold; T_min represents the "power-on ready time" of the PSSD's internal power management or startup logic, guiding firmware optimization of startup timing. Both are key quantitative rectification bases, transforming the vague "incompatibility" into specific electrical margin indicators.

[0045] In one embodiment, the intelligent test fixture 100 further includes a housing. The power output module 120, impedance adjustment module 130, first control unit 140, and second control module 121 are all installed within the housing, and the first connection terminal 110 is disposed on the housing. Furthermore, by using a housing, all core electrical modules are integrated and encapsulated, improving the portability, stability, and safety of the device. The housing provides physical protection for the internal circuitry, preventing interference and potential damage from the external environment. The first connection terminal 110 is exposed on the housing, facilitating insertion and removal of the PSSD under test.

[0046] It should be noted that the specific implementation of the present invention can be further clarified in some optional embodiments. As a specific implementation, the preset range of the VBUS power-on slope can be 0.1V / ms to 2.0V / ms to cover scenarios ranging from slow charging to various proprietary fast charging protocols. The deep testing application's permission to obtain kernel logs can be achieved by obtaining root access on the Android system, using ADB debugging authorization, or for the iOS system by jailbreaking or using the officially provided DriverKit / SWIF framework. The pulse width of the hardware synchronization signal can be set between 1μs and 10ms to ensure reliable capture by the host computer. The impedance adjustment range of the programmable impedance network can be set to 0.05Ω to 2Ω or extended to over 5Ω, where 0.05Ω to 2Ω is used to simulate ordinary cables, and over 5Ω is used to simulate severe aging or poor contact conditions. The random forest model in the analysis server 300 can be trained using Python's scikit-learn library, and the feature vector can also include derived features such as voltage drop area and voltage recovery time. The bisection iterative convergence criterion of the boundary search control logic can be set to the condition that the parameter difference between two adjacent searches is less than a preset tolerance. The preset threshold in the first control unit 140 can be dynamically adaptive, for example, set as a percentage of the current steady-state voltage.

[0047] This application also provides a compatibility testing method for external PSSDs on mobile terminals. This method uses the compatibility testing system for external PSSDs on mobile terminals as described in any of the preceding embodiments. The method includes: S1. The second control module receives the target mobile phone power supply fingerprint parameters distributed from an external analysis server or mobile terminal, and controls the power supply output module and impedance adjustment module of the intelligent test fixture to output a non-standard power supply waveform simulating the target mobile phone power supply fingerprint parameters to the PSSD under test. S2. During the test, the first control unit monitors electrical abnormal events in the power supply circuit, and when a predetermined abnormality is detected, it sends a hardware synchronization signal to the mobile terminal through a specific unused data pin or dedicated data channel in the Type-C interface. S3. The mobile terminal receives the hardware synchronization signal and captures the hardware interrupt, records the hardware interrupt trigger time as the zero point of the time reference for cross-domain analysis, and timestamps the collected event logs of the protocol layer and system layer based on the zero point of the time reference. S4. Transmit the data of the electrical anomaly event marked with a timestamp and the event log data to the analysis server; S5. The analysis server performs time-series alignment of the data of the intelligent test fixture and the mobile terminal based on the zero point of the time reference. The fingerprint analysis module and the fault diagnosis module perform cross-domain correlation analysis and fault causal chain diagnosis, and generate a diagnostic report containing quantitative electrical parameter boundaries and clear fault root causes based on the analysis and diagnosis results of cross-domain correlation analysis and fault causal chain diagnosis.

[0048] It should be noted that, in some optional implementations, to further improve testing efficiency and coverage, the system of this invention can support multiple intelligent test fixtures working in parallel, each receiving different test tasks distributed by the analysis server through an independent second control module. These tasks can be arranged based on a combination of the PSSD model under test and the target mobile phone. Furthermore, in the power supply fingerprint replay step, in addition to preset parameters, small random perturbations can be added to simulate real-world uncertainties for robustness testing. In the cross-domain alignment step, the time alignment module inside the host computer can also record the CPU timer TSC value when receiving the hardware synchronization signal to improve the resolution of the zero point. In addition to timing correlation analysis, the fault diagnosis module of the analysis server can further analyze the packets captured by the USB protocol analyzer when a protocol-related fault is determined to be present, to locate the specific erroneous command or timeout waiting state. As a specific implementation, during boundary search, the system automatically records the complete test sequence and related data transitioning from the "PASS" state to the "FAIL" state, forming a test history archive that can be traced and analyzed.

[0049] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A compatibility testing system for external PSSDs in mobile terminals, characterized in that, include: Intelligent test fixtures, mobile terminals serving as host computers, and analysis servers; The intelligent test fixture has a first connection terminal for connecting the PSSD under test, and the intelligent test fixture includes a power supply output module, an impedance adjustment module, a first control unit, and a second control module; The second control module is communicatively connected to the external analysis server or the mobile terminal, and is used to receive and parse the target mobile phone power supply fingerprint parameters distributed by the analysis server or the mobile terminal, and send digital control commands to the lower-level modules. The power supply output module has its input terminal electrically connected to the second control module and its output terminal electrically connected to the first connection terminal via the impedance adjustment module. It is used to output a non-standard power supply waveform with predetermined VBUS power-on parameters based on the instructions of the second control module to simulate the power supply behavior of the target mobile phone. The impedance adjustment module is connected in series in the power supply circuit between the output terminal of the power supply output module and the first connection terminal, and is used to receive the command of the second control module and dynamically adjust the equivalent series impedance of the power supply circuit. The first control unit, whose input terminal is electrically connected to the first connection terminal and whose output terminal is electrically connected to the mobile terminal, is used to monitor electrical abnormal events in the power supply circuit, and when a predetermined abnormality is detected, to send a hardware synchronization signal to the mobile terminal through a specific unused data pin or dedicated data channel in the Type-C interface; The mobile terminal is equipped with a deep testing application, which is used to run tests to collect protocol layer and system layer event logs of the PSSD under test, and to trigger hardware interrupts by capturing the hardware synchronization signal, and record the hardware interrupt trigger time as the time reference zero point for cross-domain analysis. The analysis server is used to receive and store test data from the smart test fixture and the mobile terminal, and to perform aligned cross-domain correlation analysis and fault diagnosis based on the zero point of the time reference.

2. The compatibility testing system for external PSSD in mobile terminals according to claim 1, characterized in that, The power supply output module includes a parameterized power stage, which includes a Buck converter circuit and a DRV chip for driving power switching transistors. The DRV chip is electrically connected to the second control module and is used to receive the digital control commands to adjust the rise rate, power-on slope and overshoot peak of the VBUS voltage.

3. The compatibility testing system for external PSSD in mobile terminals according to claim 2, characterized in that, The DRV chip adjusts the overshoot peak value in a multi-step manner according to the digital control instructions to reproduce the specific power supply fingerprint waveform of the target mobile terminal under different power levels and system loads.

4. The compatibility testing system for external PSSD in mobile terminals according to claim 1, characterized in that, The first control unit includes a high-speed voltage and current sampling circuit and a physical pulse generator. The high-speed voltage and current sampling circuit is used to monitor the waveform of the power supply circuit in real time. When the voltage drop exceeds a preset threshold or the transient current is overloaded, it is determined to be an electrical abnormal event, and the physical pulse generator is triggered to output a level pulse signal as the hardware synchronization signal.

5. The compatibility testing system for external PSSD in mobile terminals according to claim 4, characterized in that, The first control unit is electrically connected to the mobile terminal via the SBU1 / SBU2 auxiliary pins in the Type-C interface. The level pulse signal is directly transmitted to the physical pins of the mobile terminal through the SBU1 / SBU2 auxiliary pins to trigger the underlying hardware interrupt.

6. The compatibility testing system for external PSSD in mobile terminals according to claim 1, characterized in that, The impedance adjustment module includes a programmable impedance network, which comprises a parallel array of multiple low ESR resistors with different resistance values ​​and solid-state electronic switches. The second control module adjusts the equivalent series impedance of the circuit by controlling the conduction combination of the solid-state electronic switches.

7. The compatibility testing system for external PSSD in mobile terminals according to claim 1, characterized in that, The deep testing application deployed on the mobile terminal includes a kernel event listener, which is used to capture in real time the kernel logs of the underlying operating system such as USB driver mounting failure, device reset, and I / O timeout, and together with the message interaction logs of the protocol layer, constitutes the event log.

8. The compatibility testing system for external PSSD in mobile terminals according to claim 1, characterized in that, The intelligent test fixture also includes a data pass-through module, which is connected between the data port of the mobile terminal and the first connection end. The data pass-through module is used to isolate and protect the physical layer signal quality in the data link while maintaining high-speed data communication between the mobile terminal and the PSSD under test.

9. The compatibility testing system for external PSSD in mobile terminals according to claim 1, characterized in that, The intelligent test fixture also includes a fully enclosed shielded housing. The power output module, the impedance adjustment module, the first control unit, and the second control module are all integrated and installed inside the shielded housing to isolate the influence of external electromagnetic interference on high-frequency sampling and power supply fingerprint simulation.

10. A compatibility testing method for an external PSSD on a mobile terminal based on the system described in any one of claims 1 to 9, characterized in that, Includes the following steps: The second control module receives the target mobile phone power supply fingerprint parameters distributed from an external analysis server or mobile terminal, and controls the power supply output module and impedance adjustment module of the intelligent test fixture to output a non-standard power supply waveform simulating the target mobile phone power supply fingerprint parameters to the PSSD under test. During the test, the first control unit monitors electrical abnormal events in the power supply circuit, and when a predetermined abnormality is detected, it sends a hardware synchronization signal to the mobile terminal through a specific unused data pin or dedicated data channel in the Type-C interface. The mobile terminal receives the hardware synchronization signal and captures the hardware interrupt, records the hardware interrupt trigger time as the zero point of the time reference for cross-domain analysis, and timestamps the collected event logs of the protocol layer and system layer based on the zero point of the time reference. The data of the electrical anomaly event marked with a timestamp, along with the event log data, are transmitted to the analysis server; The analysis server performs time-series alignment of the data from the intelligent test fixture and the mobile terminal based on the zero point of the time base. The fingerprint analysis module and the fault diagnosis module perform cross-domain correlation analysis and fault causal chain diagnosis, and generate a diagnostic report containing quantitative electrical parameter boundaries and clear fault root causes based on the analysis and diagnosis results of cross-domain correlation analysis and fault causal chain diagnosis.

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