Power converter integrated circuit with connection fault detection functionality

Abstract

An integrated circuit for a power conversion circuit is disclosed, including an input terminal, an output terminal, a reference ground terminal, a switching terminal, and an abnormal connection event detection circuit. The input terminal is configured to receive an input voltage. The output terminal is configured to provide an output voltage. The reference ground terminal is configured to be coupled to a reference ground voltage. The switching terminal is configured to be coupled to a common connection node of a high-side switch and a low-side switch. The high-side switch and the low-side switch are coupled in series between the output terminal and the reference ground terminal. The abnormal connection event detection circuit is configured to detect an abnormal connection event in the power conversion circuit before startup of the power conversion circuit, and generate an abnormal connection warning signal indicating the abnormal connection event based on detecting the abnormal connection event.

Description

Technical Field

[0001] This application relates to power converters, and more specifically to fault self-detection circuits and techniques for protecting circuit components from abnormal connections. Background Technology

[0002] Power conversion circuits typically utilize the characteristics of energy storage components such as capacitors and inductors. Through control signals (e.g., pulse width modulation (PWM) signals), they operate controllable power switches (e.g., metal-oxide-semiconductor field-effect transistors, MOSFETs) at high frequencies, causing the energy storage components to alternately store and release electrical energy. Through this energy flow process, the power converter can transform the input voltage into another stable voltage to power various application devices.

[0003] In the soldering process of a power management system, which includes power conversion circuitry, ensuring the accurate soldering of relevant power devices (e.g., power switches and power inductors) within the power converter is crucial. Therefore, an effective fault detection scheme is needed to detect abnormal connections such as short circuits or poor soldering in power devices, thereby guaranteeing the performance and reliability of the power management system. Summary of the Invention

[0004] To address the aforementioned problems, this invention proposes an integrated circuit for a power conversion circuit, comprising: an input terminal, an output terminal, a reference ground terminal, a switching terminal, and an abnormal connection event detection circuit. The input terminal is configured to receive an input voltage. The output terminal is configured to provide an output voltage. The reference ground terminal is configured to be coupled to a reference ground voltage. The switching terminal is configured to be coupled to a common connection node of a high-side switch and a low-side switch. The high-side switch and the low-side switch are connected in series between the output terminal and the reference ground terminal. The abnormal connection event detection circuit is configured to detect abnormal connection events in the power conversion circuit before startup and generate an abnormal connection warning signal indicating the abnormal connection event based on the detected abnormal connection event. Attached Figure Description

[0005] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0006] Figure 1 This is a block diagram illustrating a power management system 100 according to an embodiment of the present invention.

[0007] Figure 2 It shows Figure 1 An exemplary circuit diagram of the power stage of the power converter in the power management system shown.

[0008] Figure 3 A flowchart of a method 300 for detecting abnormal connection events according to an embodiment of the present invention is shown.

[0009] Figure 4 An exemplary circuit diagram of a sensing circuit according to an embodiment of the present invention is shown.

[0010] Figure 5 A circuit diagram is shown for determining whether an L open-circuit event or an LS short-circuit event has occurred in method 300.

[0011] Figure 6 A circuit diagram is shown for determining whether an HS short-circuit event has occurred in method 300.

[0012] Figure 7 A circuit diagram is shown for determining whether an HS open-circuit event has occurred in method 300.

[0013] Figure 8 A flowchart of a method 800 for detecting abnormal connection events according to an embodiment of the present invention is shown.

[0014] Figure 9 A circuit diagram is shown for determining whether an HS open-circuit event, an LS short-circuit event, or an L open-circuit event has occurred in method 800. Detailed Implementation

[0015] Various embodiments of the invention will now be described. In the following description, specific details, such as example circuits and example values ​​for these circuit components, are included to provide a thorough understanding of the embodiments. However, those skilled in the art will recognize that this disclosure may be practiced without one or more specific details, or using other methods, components, materials, etc. In other instances, well-known structures, materials, processes, or operations have not been shown or described in detail to avoid obscuring aspects of this disclosure.

[0016] Throughout the specification and claims, the phrases “in one embodiment,” “in some embodiments,” “in one implementation,” and “in some implementations” encompass combinations and sub-combinations of the various features described herein, as well as variations and modifications thereof. These phrases used herein do not necessarily refer to the same embodiment, although they may. Those skilled in the art will understand that the meaning of the foregoing terms is not intended to limit the terminology, but merely to provide illustrative examples. Note that when a component is “connected to” or “coupled to” another component, this means that the component is directly connected to or coupled to the other component, or indirectly connected to or coupled to the other component via another component. Specific features, structures, or characteristics may be included in integrated circuits, electronic circuits, combinational logic circuits, or other suitable components that provide the said functionality. Furthermore, it should be understood that the accompanying drawings provided herein are for explanation to those skilled in the art and are not necessarily drawn to scale.

[0017] Figure 1 This is a block diagram illustrating a power management system 100 according to an embodiment of the present invention. (See reference...) Figure 1 The power management system 100 includes a power converter 120 and a main controller 110.

[0018] like Figure 1 As shown, the power converter 120 includes a power switch 121, a switch controller 122, and an abnormal connection event detection circuit 123. In addition, the power converter 120 also includes connection terminals such as input terminal IN, output terminal OUT, switching terminal SW, enable terminal EN, communication terminal UART, and reference ground terminal PGND. For simplicity, other unrelated circuit components and terminals are omitted in this document.

[0019] The switching terminal SW is configured to be coupled to one end of the power inductor L, and the input terminal IN is configured to be coupled to the other end of the power inductor L. The switching element in power switch 121 is configured to turn on or off under the control of a drive signal (e.g., shown in the figure as a pair of signals with opposite logic states, HDRV and LDRV) to increase or decrease the inductor current flowing through the power inductor L, thereby converting the input voltage Vin to the output voltage Vout. The output terminal OUT is used to provide the output voltage Vout. The output capacitor Co is coupled between the output terminal OUT and the reference ground terminal PGND to filter and smooth the output voltage Vout. Hereinafter, power switch 121, the power inductor, and the output capacitor Co will be referred to as the power stage.

[0020] The switch controller 122 can generate a switch drive signal based on a feedback signal characterizing the output voltage Vout of the power converter 120. For example, in embodiments of PWM control methods such as voltage control and current control, the switch controller 122 can amplify the difference between the feedback signal and a reference signal, and then compare the amplified difference signal with a ramp signal to generate the switch drive signal. It should be understood that the switch controller 122 can be implemented using any suitable control mode and circuit structure, as long as it can achieve control of the power stage. This application does not limit the topology and control mode of the switch controller 122.

[0021] In one embodiment, the abnormal connection event detection circuit 123 may be embedded in a power management integrated circuit (PMIC) along with the switch controller 122 and the power switch circuit 121. It should be understood that the present invention does not limit the package form of the power converter 120. For example, in another embodiment, the power switch circuit 121 may be placed outside the PMIC.

[0022] In one embodiment, the abnormal connection event detection circuit 123 is configured to be enabled in response to the PMIC being powered on (e.g., receiving an input voltage Vin) and to determine whether an abnormal connection event has occurred in the power stage based on a power stage signal received from the power stage, thereby generating an abnormal connection warning signal OS_FLAG. For example, the power stage signal here may include the voltage Vsw at the common connection node of the switching transistors in the power switching circuit 121-1 or the output voltage Vout at the output terminal OUT.

[0023] As shown in the figure, the abnormal connection event detection circuit 123 includes a sensing circuit 123-1 for detecting power stage signals and a control logic circuit 123-2 for controlling the abnormal connection event detection process. Additionally, the abnormal connection event detection circuit 123 may also include a register dedicated to recording abnormal connection events. When an abnormal connection event is determined to have occurred, the bit value of this register can be set to a first value (e.g., 1).

[0024] In one embodiment, the power converter 120 may further include a communication module 124 for sending an abnormal connection warning signal OS_FLAG (e.g., via a communication terminal UART) to an external master controller 110 in response to a bit value in the abnormal connection event register being set to a first value. The communication module 124 may support communication protocols including, but not limited to, UART (Universal Asynchronous Receiver-Transmitter) protocol, SPI protocol, and I2C protocol; this invention does not limit the specific protocols supported.

[0025] In response to an abnormal connection warning signal OS_FLAG not received from the power converter 120 (i.e., indicating that the abnormal connection event detection circuit 123 has not detected an abnormal connection event), the main controller 110 generates a corresponding enable signal Ven (e.g., a signal in an enable logic state (logic high)) and sends it to the enable terminal EN to enable the PMIC when no abnormal connection event is detected, thereby initiating the PMIC startup process (e.g., soft start). Thus, through an internally configured fault self-detection function, a connection fault can be detected in time before the PMIC starts (i.e., before the PMIC receives the enable signal Ven through the enable terminal EN), and the faulty PMIC can be disabled to prevent improper operation of the faulty PMIC from damaging downstream application devices.

[0026] In one embodiment, the main controller 110 may be an Electronic Control Unit (ECU) or a host computer including the ECU. In another embodiment, the main controller 110 may be a Micro Control Unit (MCU) or a host computer including the MCU. The invention is not limited thereto. The main controller 110 may also be embedded in a separate PMIC or in the same PMIC as the power converter 120.

[0027] Figure 2 An exemplary circuit diagram of power stage 200 is shown. (Reference) Figure 2 The power stage 200 includes a high-side switch (also known as the first switch) HS, a low-side switch (also known as the second switch) LS, a power inductor L, and an output capacitor Co. Figure 2 In this embodiment, power stage 200 employs a boost converter circuit structure. Those skilled in the art will understand that in another embodiment, power stage 200 may also employ other switching circuit conversion structures, such as buck converter circuit structures, buck-boost converter circuit structures, etc. This invention does not limit this approach.

[0028] refer to Figure 2The power inductor L has a first terminal and a second terminal, the first terminal of which is coupled to the input terminal IN to receive the input voltage Vin. The high-side switch HS includes a first terminal, a second terminal, and a control terminal. Additionally, the high-side switch HS also includes a body diode D1. The first terminal of the high-side switch HS is coupled to the second terminal of the power inductor L, and the second terminal of the high-side switch HS is coupled to the output terminal OUT to provide the output voltage Vout. The control terminal of the high-side switch HS is used to receive a first drive signal HDRV from the switch controller 150. The high-side switch HS can be turned on and off under the control of the first drive signal HDRV. The low-side switch LS includes a first terminal, a second terminal, and a control terminal. Additionally, the low-side switch also includes a body diode D2. The first terminal of the low-side switch LS is coupled to the second terminal of the power inductor L, and the second terminal of the low-side switch LS is coupled to the reference ground terminal PGND. The control terminal of the low-side switch LS is used to receive a second drive signal LDRV from the switch controller 150. The low-side switch LS can be turned on and off under the control of the second drive signal LDRV. The second terminal of the high-side switch HS is coupled to the first terminal of the low-side switch LS to form a common connection node, and the switching terminal SW is configured to be coupled to this common connection node. One end of the output capacitor Co is coupled to the output terminal OUT, and the other end is coupled to the reference ground terminal PGND.

[0029] In one embodiment, both the high-side switch HS and the low-side switch LS include a controllable transistor. For example, Figure 2 An exemplary example is a metal-oxide-semiconductor field-effect transistor (MOSFET). In Figure 2 In the illustrated embodiment, the high-side switch HS and the low-side switch LS are NMOS transistors. In this example, the power converter may also include a voltage boosting circuit (e.g., a bootstrap capacitor Cb and a bootstrap diode Db coupled between the bootstrap supply input voltage Vb and the switching terminal SW) to ensure accurate turn-on of the high-side switch HS. It should be understood that the invention is not limited thereto. For example, the high-side switch HS may be a PMOS transistor, and the low-side switch LS may be an NMOS transistor. The following description uses the example of both the high-side switch HS and the low-side switch LS being NMOS transistors.

[0030] In one embodiment, such as Figure 2 As shown, the power stage may also include a protection switch PS, configured to be coupled between the output terminal OUT and the high-side switch HS. In one embodiment, the protection switch PS also includes a controllable transistor, such as a MOSFET. Figure 2In the illustrated embodiment, the protection switch PS is a PMOS. In one embodiment, the connection between the protection switch PS and the high-side switch HS is configured such that their body diodes (e.g., body diodes D2 and D3) are connected back-to-back, thereby disconnecting the electrical connection between the output terminal OUT and the switching terminal SW when both the high-side switch HS and the protection switch PS are off. The protection switch PS has a first terminal, a second terminal, and a control terminal, the control terminal of which receives a protection control signal PDRV. During the connection fault detection phase or soft-start phase, when the high-side switch HS is on, the protection control signal PDRV can control the protection switch PS to operate in the variable resistance region to control the current flowing through the high-side switch HS. During normal boost operation, the protection control signal PDRV can control the protection switch PS to be in the on state (e.g., operating in the saturation region).

[0031] Furthermore, the power stage 200 may also include a forced discharge circuit coupled to the output terminal OUT and the switching terminal SW, configured to discharge the output terminal OUT and the switching terminal SW when enabled. In one embodiment, the forced discharge circuit includes a first forced discharge module coupled between the output terminal OUT and the reference ground terminal PGND, and a second forced discharge module coupled between the switching terminal SW and the reference ground terminal PGND. In one embodiment, as shown, the first forced discharge module includes a switching element S1 and a resistor Rdis1 connected in series, and the second forced discharge module includes a switching element S2 and a resistor Rdis2 connected in series. The switching elements S1 and S2 may be, for example, MOSFETs, each having a first terminal, a second terminal, and a control terminal. The control terminals of the switching elements S1 and S2 are respectively used to receive a discharge enable signal V. en_dis1 and V en_dis2 They are turned on under the control of the corresponding discharge enable signals, thereby pulling down the voltages of the switching terminal SW and the output terminal OUT to the reference ground voltage when they are turned on.

[0032] like Figure 2As shown, common abnormal connection events in the power stage can include situations such as the switching terminal SW being shorted to the output terminal OUT (also known as HS short circuit), the switching terminal SW being shorted to the reference ground terminal PGND (also known as LS short circuit), the power inductor L being disconnected from the switching terminal SW or the power inductor being disconnected from the input terminal IN (also known as L open circuit), the high-side switch HS being disconnected from the output terminal OUT or the high-side switch HS being disconnected from the switching terminal SW (also known as HS open circuit), and the low-side switch LS being disconnected from the reference ground terminal PGND or the low-side switch LS being disconnected from the switching terminal SW (also known as LS open circuit), etc. When one or more of these situations occur, the power converter 120 will generate an abnormal connection warning signal (e.g., OS_FLAG) and send it to the main controller 110, and the main controller 110 will respond by disabling the power converter 120.

[0033] During normal boost operation, and assuming no abnormal connection events occur, the protection switch PS remains on. The high-side switch HS and the low-side switch LS are turned on and off under the control of the first drive signal HDRV and the second drive signal LDRV, respectively. This causes the energy storage element (e.g., power inductor L) to alternately store and release electrical energy, thereby converting the input voltage Vin into the output voltage Vout. Specifically, the switch controller 150 can provide the first drive signal HDRV and the second drive signal LDRV to the control terminals of the high-side switch HS and the low-side switch LS, respectively. The first drive signal HDRV has a set logic state (e.g., logic high) for turning on the high-side switch HS and a reset logic state (e.g., logic low) for turning off the high-side switch HS. The second drive signal LDRV has a set logic state (e.g., logic high) for turning on the low-side switch LS and a reset logic state (e.g., logic low) for turning off the low-side switch LS. When the first drive signal HDRV is logic low and the second drive signal LDRV is logic high, the high-side switch HS is turned off and the low-side switch LS is turned on. Current flows from the input terminal VIN through the power inductor L, the switching terminal SW, and the low-side switch LS to charge the power inductor L. When the first drive signal HDRV is logic high and the second drive signal LDRV is logic low, the high-side switch HS is turned on and the low-side switch LS is turned off. Current flows from the input terminal IN through the power inductor L, the switching terminal SW, and the high-side switch HS to the output terminal OUT and the output capacitor Co.

[0034] Figure 1The power converter shown can determine whether an abnormal connection event has occurred before the PMIC starts up and begins operation through an abnormal connection event detection circuit built into the PMIC, and disable the faulty PMIC in advance to prevent the incorrect operation of the faulty chip from causing further damage to the system.

[0035] Figure 3 A flowchart of a method 300 for detecting abnormal connection events according to an embodiment of the present invention is shown. Figure 3 Method 300 will combine Figure 1 , Figure 2 and Figures 4-7 A description will be provided. For explanatory purposes, it will be assumed that the power management system has... Figure 1 As shown in the figure.

[0036] refer to Figure 3 Method 300 includes the following steps 310-390.

[0037] Step 310: Enter the abnormal connection event detection process. For example, the abnormal connection event detection circuit 123 is enabled in response to receiving an input voltage Vin from the input terminal IN, thereby entering the abnormal connection event detection process. In one embodiment, method 300 is performed before the soft start of PMIC 120, at which time the high-side switch HS, low-side switch LS, and protection switch PS are all kept off.

[0038] Step 320: Enable forced discharge function. In one embodiment, the control unit 123-2 in the abnormal event detection circuit 123 can send a first forced discharge enable signal V. en-_dis1 Second forced discharge enable signal V en_dis2 Connect the control terminals of switches S1 and S2 to turn on switches S1 and S2 respectively, and connect the output terminal OUT and the switching terminal SW to the reference ground GND respectively, so as to reduce the output voltage Vout and the switching voltage Vsw on the switching terminal SW to zero volts (or close to zero volts).

[0039] Step 330: Compare the switching voltage Vsw on the switching terminal SW with the reference voltage Vref, and determine whether the switching voltage Vsw is greater than the reference voltage Vref. In one embodiment, this step can be used to determine whether an L open circuit event or an LS short circuit event has occurred.

[0040] In one embodiment, the sensing circuit 123-1 in the abnormal event detection circuit 123 is configured to compare the switching voltage Vsw with the reference voltage Vref and output a sensing signal OS to indicate whether an abnormal connection event has occurred. In one embodiment, the reference voltage Vref can be set to a value close to but less than the input voltage Vin. For example, the reference voltage Vref can be set to 0.8Vin. In another embodiment, the switching voltage Vsw and the reference voltage Vref can be proportionally scaled down before comparison. Figure 4 An exemplary circuit diagram of a sensing circuit 123-1 according to an embodiment of the present invention is shown. Figure 4 In the illustrated embodiment, the proportionally scaled-down reference voltage Vref can be set as the on-threshold RDS(on) of the MOSFET (e.g., RDS(on) = 0.7V). Based on this, the switching voltage Vsw can be scaled down proportionally by adjusting the resistance value of the voltage divider resistor, thereby comparing the scaled-down switching voltage Vsw with 0.7V.

[0041] like Figure 4 As shown, the sensing circuit 123-1 includes MOSFETs S3 and S4, resistors R1-R3, a Schmitt trigger ST, and an inverter INV, with the connections as follows: Figure 4 As shown.

[0042] like Figure 4 As shown, the sensing circuit 123-1 receives the switching voltage Vsw at the input terminal of the switching terminal SW and outputs a sensing signal OS at the output terminal to indicate whether an abnormal connection event has occurred. When MOSFET S1 is turned on, resistors R1 and R2 divide the switching voltage Vsw, generating a voltage divider signal Sdiv = Vsw * R2 / (R1 + R2) across resistor R2 to control MOSFET S2. When the voltage divider signal Sdiv is greater than the turn-on threshold RDS(on) of MOSFET S2 (e.g., RDS(on) = 0.7V), MOSFET S2 is turned on. Based on actual comparison requirements, S can be used as the output of a Schmitt trigger ST or an inverter INV as the sensing signal OS to indicate whether an abnormal connection event has occurred. For example, in step 330, Figure 4 The sensing circuit 123-1 shown can output the output of the Schmitt trigger ST as the sensing signal OS.

[0043] It should be understood that Figure 4 The circuit diagram of sensing circuit 123-1 in the figure is presented merely as an example. Those skilled in the art can design any suitable circuit to compare the switching voltage Vsw with the reference voltage Vref.

[0044] Figure 5A circuit diagram is shown for determining whether an L open-circuit event or an LS short-circuit event has occurred in method 300.

[0045] like Figure 5 As shown in sub-figure (a), under the condition that no L open-circuit event or LS short circuit occurs (i.e., normal condition), the switching terminal SW is coupled to the input terminal IN through the power inductor L. The switching voltage Vsw on the switching terminal SW is equal to the input voltage Vin and greater than the reference voltage Vref, that is, Vsw > Vref. The sensing circuit 123 outputs OS = 0, indicating that no related abnormal connection event has occurred.

[0046] like Figure 5 As shown in sub-figure (b), if an L open circuit event occurs (for example, as shown, the inductor L is disconnected from the input terminal IN), since the forced discharge function remains on, the switching voltage Vsw = 0, which is less than the reference voltage Vref, i.e., Vsw < Vref. The sensing circuit 123 outputs OS = 1, indicating that an abnormal connection event has occurred, such as an L open circuit event.

[0047] like Figure 5 As shown in sub-diagram (c), if an LS short-circuit event occurs (for example, as shown, the switching terminal SW is short-circuited to the reference ground terminal PGND), the switching terminal SW is coupled to the reference ground terminal PGND through the short-circuit path. At this time, the switching voltage is close to zero volts and less than the reference voltage Vref, that is, Vsw < Vref. The sensing circuit 123 outputs OS = 1, indicating that an abnormal connection event has occurred, such as an LS short-circuit event.

[0048] Continue to refer to Figure 3 When it is determined that the switching voltage Vsw is greater than the reference voltage Vref (330 = YES), it indicates that no LS short circuit event or L open circuit event has occurred, and the method proceeds to step 340 to continue judging other types of abnormal connection events. Otherwise (330 = NO), it indicates that an LS short circuit event or L open circuit event has occurred, and the method proceeds to step 390.

[0049] Step 340: Compare the voltage Vout on the output terminal OUT with the reference voltage Vref, and determine whether the output voltage Vout is greater than the reference voltage Vref. In one embodiment, this step can be used to determine whether an HS short-circuit event has occurred.

[0050] For example, in step 340, the sensing circuit 123-1 in the abnormal event detection circuit 123 can be based on Figure 4 The sensing circuit 123-1 shown compares the voltage Vout with the reference voltage Vref, and Figure 4 The sensing circuit 123-1 shown can output the output of the inverter INV as the sensing signal OS.

[0051] Figure 6 A circuit diagram is shown for determining whether an HS short-circuit event has occurred in method 300.

[0052] like Figure 6 As shown in sub-figure (a), in the absence of an HS short circuit event, since the forced discharge function remains on, the output port is connected to the reference ground via switch S2 and resistor Rdis2. At this time, the output voltage Vout is close to zero volts and less than the reference voltage Vref, that is, Vout < Vref. The sensing circuit 123 outputs OS = 0, indicating that no HS short circuit event has occurred.

[0053] like Figure 6 As shown in sub-diagram (b), if an HS short circuit event occurs, the output terminal OUT is coupled to the input terminal IN through the short circuit path, so that the voltage on the output terminal OUT is greater than the reference voltage Vref, that is, Vout>Vref. The sensing circuit 123 outputs OS=1, indicating that an abnormal connection event has occurred, such as an HS short circuit event.

[0054] Return to reference Figure 3 If step 340 determines that the output voltage Vout is less than the reference voltage Vref (340 = NO), indicating that no HS short-circuit event has occurred, the method proceeds to step 350 to continue judging other types of abnormal connection events. Otherwise (340 = YES), the method proceeds to step 390.

[0055] Step 350: Disable the forced discharge function and turn on the high-side switch HS. In this step, current will flow from the input terminal IN to the output terminal OUT. In one embodiment, the control logic circuit 123-2 in the abnormal connection event detection circuit 123 can control the magnitude of the protection control signal PDRV provided to the protection switch PS, thereby making the protection switch PS operate in the variable resistance region and controlling the magnitude of the current flowing through the high-side switch HS.

[0056] Step 360: Compare the voltage Vout on the output terminal OUT with the reference voltage Vref, and determine whether the output voltage Vout is greater than the reference voltage Vref. In one embodiment, this step can be used to determine whether an HS open-circuit event has occurred.

[0057] For example, in step 360, the sensing circuit 123-1 in the abnormal event detection circuit 123 can be based on Figure 4 The sensing circuit 123-1 shown compares the voltage Vout with the reference voltage Vref, and Figure 4 The sensing circuit 123-1 shown can output the output of the Schmitt trigger ST as the sensing signal OS.

[0058] Figure 7 A circuit diagram is shown for determining whether an HS open-circuit event has occurred in method 300.

[0059] like Figure 7 As shown in sub-figure (a), in the absence of an open-circuit event at HS, due to the forced discharge function being turned off (as shown, S1 and S2 are turned off) and the high-side switch HS and protection switch BS being turned on, current will flow from the input terminal IN to the output terminal OUT, charging the output capacitor Co. After a predetermined time, the output voltage Vout will become greater than the reference voltage Vref, and the sensing circuit 123 will output OS = 0.

[0060] like Figure 7 As shown in sub-figure (b), if an HS open circuit event occurs (for example, as shown, the high-side switch HS is disconnected from the output terminal OUT), the output terminal OUT will be disconnected from the input terminal IN. Since the output terminal OUT was discharged in the previous step, the voltage Vout on the output terminal OUT is 0, which is less than the reference voltage Vref, i.e., Vout < Vref. The sensing circuit 123 outputs OS = 1, indicating that an abnormal connection event has occurred, such as an HS open circuit event.

[0061] Return to reference Figure 3 If step 360 determines that the output voltage Vout is greater than the reference voltage Vref (360 = YES), it indicates that no HS open circuit event has occurred, and the method proceeds to step 370. Otherwise (360 = NO), the method proceeds to step 390.

[0062] According to one embodiment of the present invention, after step 360, method 300 may further include step 370 for detecting whether the switching terminal SW is disconnected from the reference ground terminal PGND (e.g., an LS open-circuit event). In this step, the low-side switch LS is turned on, and it is detected whether current flows through the low-side switch LS. If no current is detected flowing through the low-side switch LS, a sensing signal OS = 1 is output, indicating that an abnormal connection event, such as an LS open-circuit event, has occurred. In this embodiment, the abnormal connection event detection circuit 123 may further include a current sensing circuit for detecting whether current flows through the low-side switch LS.

[0063] Step 380: Normal startup (e.g., soft boot) of PMIC.

[0064] Step 390: Set the bit value of the exception event register to a first value (e.g., 1). For example, the control unit 123-2 in the exception event detection circuit 123 can set the bit value of the exception event register to the first value based on the signal OS = 1. Further, the communication module 124 can generate an abnormal connection warning signal OS_FLAG in response to the bit value being set to the first value and send it to the external master controller 110 via the communication terminal UART. The master controller 110 will then disable the faulty PMIC.

[0065] Figure 8 A flowchart of a method 800 for detecting abnormal connection events according to another embodiment of the present invention is shown. Figure 8 Method 800 will combine Figure 1 , Figure 2 and Figure 9 A description will be provided. For explanatory purposes, it will be assumed that the power management system has... Figure 1 As shown in the figure.

[0066] refer to Figure 8 Method 800 is as follows: steps 810-880.

[0067] Step 810: Enter the abnormal connection event detection process. For example, the abnormal connection event detection circuit 123 is enabled in response to receiving an input voltage Vin from the input terminal IN, thereby entering the abnormal connection event detection process. In one embodiment, method 800 is performed before the soft start of PMIC 120, at which time the high-side switch HS, low-side switch LS, and protection switch PS are all kept off.

[0068] Step 820: Enable forced discharge function. In one embodiment, the control unit 123-2 in the abnormal event detection circuit 123 can send a first forced discharge enable signal V. en-_dis1 Second forced discharge enable signal V en_dis2 Connect the control terminals of switches S1 and S2 to turn on switches S1 and S2 respectively, and connect the output terminal OUT and the switching terminal SW to the reference ground GND respectively, so as to reduce the output voltage Vout and the switching voltage Vsw on the switching terminal SW to zero volts (or close to zero volts).

[0069] Step 830: Compare the output voltage Vout at the output terminal OUT with the reference voltage Vref, and determine whether the output voltage Vout is greater than the reference voltage Vref. In one embodiment, this step can be used to determine whether an HS short-circuit event has occurred.

[0070] For example, in step 830, the sensing circuit 123-1 in the abnormal event detection circuit 123 can be based on Figure 4The sensing circuit 123-1 shown compares the voltage Vout with the reference voltage Vref, and Figure 4 The sensing circuit 123-1 shown can output the output of the inverter INV as the sensing signal OS.

[0071] The circuit diagram used in step 830 to determine whether an HS short-circuit event has occurred can be found in [reference]. Figure 6 To understand this, I will not elaborate further.

[0072] When step 830 determines that the output voltage Vout is less than the reference voltage Vref (830 = NO), indicating that no HS short-circuit event has occurred, the method proceeds to step 840 to further determine whether other types of abnormal connection events have occurred. Otherwise (830 = YES), the method proceeds to step 880.

[0073] Step 840: Disable the forced discharge function and turn on the high-side switch HS. In this step, current will flow from the input terminal IN to the output terminal OUT. In one embodiment, the control logic circuit 123-2 in the abnormal connection event detection circuit 123 can control the magnitude of the protection control signal PDRV provided to the protection switch PS, thereby making the protection switch PS operate in the variable resistance region and controlling the magnitude of the current flowing through the high-side switch HS.

[0074] Step 850: Compare the voltage Vout on the output terminal OUT with the reference voltage Vref, and determine whether the output voltage Vout is greater than the reference voltage Vref. In one embodiment, this step can be used to determine whether an HS open-circuit event, an LS short-circuit event, or an L open-circuit event has occurred.

[0075] For example, in step 850, the sensing circuit 123-1 in the abnormal event detection circuit 123 can be based on Figure 4 The sensing circuit 123-1 shown compares the voltage Vout with the reference voltage Vref, and Figure 4 The sensing circuit 123-1 shown can output the output of the Schmitt trigger ST as the sensing signal OS.

[0076] Figure 9 A circuit diagram is shown for determining whether an HS open-circuit event, an LS short-circuit event, or an L open-circuit event has occurred in method 800.

[0077] like Figure 9As shown in sub-figure (a), in the absence of the aforementioned event, since the forced discharge function is turned off (as shown, S1 and S2 are turned off) and the high-side switch HS and protection switch BS are turned on, current will flow from the input terminal IN through the high-side switch HS and protection switch PS to the output terminal OUT, charging the output capacitor Co. After a predetermined time, the output voltage Vout will become greater than the reference voltage Vref, and the sensing circuit 123 will output OS = 0.

[0078] like Figure 9 As shown in sub-figure (b), if an HS open circuit event occurs (for example, as shown, the output terminal OUT is disconnected from the input terminal IN), since the output terminal OUT was discharged in the previous step, the voltage Vout on the output terminal OUT is 0, which is less than the reference voltage, i.e., Vout < Vref. The sensing circuit 123 outputs OS = 1, indicating that an abnormal connection event has occurred, such as an HS open circuit event.

[0079] like Figure 9 As shown in sub-diagram (c), if an LS short-circuit event occurs (for example, as shown, the switching terminal SW is coupled to the reference ground terminal PGND through a short-circuit path), the output terminal OUT is connected to the reference ground terminal PGND through the protection switch PS, the high-side switch HS, and the short-circuit path between the switching terminal SW and the reference ground terminal PGND, causing the output voltage to be less than the reference voltage, i.e., Vout < Vref. The sensing circuit 123 outputs OS = 1, indicating that an abnormal connection event has occurred, such as an LS short-circuit event.

[0080] like Figure 9 As shown in sub-diagram (d), if an L open-circuit event occurs, the output terminal OUT is in a floating state because the forced discharge function is turned off. At this time, the output voltage Vout is less than the reference voltage Vref, that is, the output voltage Vout < Vref. The sensing circuit 123 outputs OS = 1, indicating that an abnormal connection event has occurred, such as an L open-circuit event.

[0081] Return to reference Figure 8 If step 850 determines that the output voltage Vout is greater than the reference voltage (850 = YES), indicating that the above event has not occurred, the method proceeds to step 860. Otherwise (850 = NO), the method proceeds to step 880.

[0082] According to one embodiment of the present invention, after step 850, method 800 may further include step 860 for detecting whether the switching terminal SW is disconnected from the reference ground terminal PGND (e.g., an LS open-circuit event). In step 860, the low-side switch LS is turned on, and it is detected whether current flows through the low-side switch LS. If no current is detected flowing through the low-side switch LS, a sensing signal OS = 1 is output, indicating that an abnormal connection event, such as an LS open-circuit event, has occurred. In this embodiment, the abnormal connection event detection circuit 123 may further include a current sensing circuit for detecting whether current flows through the low-side switch LS.

[0083] Return to reference Figure 8 If step 860 determines that current flows through the low-side switch LS (860 = YES), indicating that no LS open-circuit event has occurred, the method proceeds to step 870. Otherwise (860 = NO), the method proceeds to step 880.

[0084] Step 870: Normal startup (e.g., soft boot) of PMIC.

[0085] Step 880: Set the bit value of the exception event register to a first value (e.g., 1). For example, the control unit 123-2 in the exception event detection circuit 123 can set the bit value of the exception event register to the first value based on the signal OS = 1. Further, the communication module 124 can generate an abnormal connection warning signal OS_FLAG in response to the bit value being set to the first value and send it to the external master controller 110 via the communication terminal UART. The master controller 110 will then disable the faulty PMIC.

[0086] although Figure 3 and Figure 8 The sequence of actions is shown. It will be apparent to those skilled in the art that these actions can be performed in any suitable order, and that only a portion of them may be performed; the invention does not impose any limitation on this.

[0087] Therefore, this application proposes a fault self-detection circuit and corresponding method for protecting PMIC circuit components from short-circuit events, open-circuit events, or other problems. It can detect abnormal connection events in a timely manner before the PMIC is officially started and disable faulty chips to prevent further damage caused by incorrect operation of the faulty chips, thereby improving the reliability of the PMIC.

[0088] Those skilled in the art will understand that this disclosure is not limited to what has been specifically shown and described above. Rather, the scope of this disclosure is defined by the claims and includes combinations and sub-combinations of the various features described above, as well as variations and modifications that would occur to those skilled in the art upon reading the foregoing description and that are not found in the prior art.

Claims

1. An integrated circuit for a power conversion circuit, comprising: The input terminal is configured to receive input voltage. The output terminal is configured to provide an output voltage. The reference ground terminal is configured to be coupled to the reference ground voltage. A switching terminal is configured to be coupled to a common connection node of a high-side switch and a low-side switch, wherein the high-side switch and the low-side switch are connected in series between the output terminal and the reference ground terminal. An abnormal connection event detection circuit is configured to detect abnormal connection events in the power conversion circuit before the power conversion circuit is started, and to generate an abnormal connection warning signal to indicate the abnormal connection event based on the detection of the abnormal connection event.

2. The integrated circuit of claim 1 further includes an enable terminal configured to receive an enable signal, wherein prior to startup refers to the integrated circuit not receiving an enable signal through the enable terminal.

3. The integrated circuit according to claim 2, wherein when no abnormal connection event occurs in the power conversion circuit, the integrated circuit receives the enable signal through the enable terminal.

4. The integrated circuit according to claim 1, wherein, The abnormal connection event includes one or more of the following: the switching terminal is shorted to the output terminal, the switching terminal is shorted to the reference ground terminal, the high-side switch is disconnected from the output terminal, the high-side switch is disconnected from the switching terminal, the low-side switch is disconnected from the reference ground terminal, and the low-side switch is disconnected from the switching terminal.

5. The integrated circuit according to claim 4, wherein, The switching terminal is configured to be coupled to one end of the power inductor, the input terminal is configured to be coupled to the other end of the power inductor, the high-side switch and the low-side switch are configured to be turned on or off under the control of a control signal to increase or decrease the inductor current flowing through the power inductor, thereby converting the input voltage into the output voltage, and wherein the abnormal connection event further includes: the switching terminal being disconnected from the power inductor, and the power inductor being disconnected from the input terminal.

6. The integrated circuit according to claim 1 further includes a communication terminal for providing the abnormal connection warning signal to the main controller.

7. The integrated circuit according to claim 1, wherein, The abnormal connection event detection circuit includes: A sensing circuit is configured to compare a switching voltage at the switching terminal or an output voltage at the output terminal with a reference voltage, and generate a sensing signal based on the comparison result; and The control logic circuit is configured to generate the abnormal connection warning signal in response to the sensing signal having a set logic state.

8. The integrated circuit of claim 7 further includes a forced discharge circuit coupled to the output terminal and the switching terminal, configured to discharge the output terminal and the switching terminal when enabled.

9. The integrated circuit according to claim 8, wherein the forced discharge circuit includes a first forced discharge circuit and a second forced discharge circuit, the first forced discharge circuit and the second forced discharge circuit being configured to discharge the output terminal and the switching terminal respectively when enabled.

10. The integrated circuit according to claim 9, wherein, The first forced discharge circuit includes a first switching element and a first discharge resistor connected in series between the output terminal and the reference ground terminal, and the second forced discharge circuit includes a second switching element and a second discharge resistor connected in series between the output terminal and the reference ground terminal, wherein the first switching element and the second switching element are configured to be turned on in response to a discharge enable signal from the control logic circuit, thereby connecting the switching terminal and the output terminal to the reference ground terminal, respectively.

11. The integrated circuit according to claim 7, wherein, The control logic circuit further includes a register for recording the abnormal connection event, wherein the control logic circuit is configured to set the bit value of the register to a first value in response to the sensing signal having a set logic state.

12. The integrated circuit according to claim 8, wherein, The abnormal event detection circuit is configured to be enabled in response to the input voltage, thereby entering the abnormal connection event detection process.

13. The integrated circuit according to claim 12, wherein, During the abnormal connection event detection process, the control logic circuit is configured to perform one or more of the following steps: Enable the forced discharge circuit to discharge the output terminal and the switching terminal. The sensing circuit is controlled to compare the switching voltage on the switching terminal with the reference voltage. If the switching voltage is less than the reference voltage, the sensing circuit outputs a sensing signal with a set logic state; if the switching voltage is greater than the reference voltage, the sensing circuit outputs a sensing signal with a reset logic state. If the switching voltage is greater than the reference voltage, the output voltage is compared with the reference voltage, and it is determined whether the output voltage is greater than the reference voltage. If the output voltage is greater than the reference voltage, the sensing circuit outputs a sensing signal with a set logic state. If the output voltage is less than the reference voltage, the sensing circuit outputs a sensing signal with a reset logic state. If the output voltage is determined to be less than the reference voltage, the discharge circuit is disabled and the high-side switch is turned on. Then, it is determined whether the output voltage is greater than the reference voltage. If the output voltage is greater than the reference voltage, the sensing circuit outputs a sensing signal with a reset logic state. If the output voltage is less than the reference voltage, the sensing circuit outputs a sensing signal with a set logic state.

14. The integrated circuit according to claim 12, wherein, During the abnormal connection event detection process, the control logic circuit is configured to perform one or more of the following steps: Enable the forced discharge circuit to discharge the output terminal. The sensing circuit is controlled to compare the output voltage with the reference voltage. If the output voltage is greater than the reference voltage, the sensing circuit outputs a sensing signal with a set logic state; if the output voltage is less than the reference voltage, the sensing circuit outputs a sensing signal with a reset logic state. If the output voltage is determined to be less than the reference voltage, the discharge circuit is disabled and the high-side switch is turned on. Then, it is determined whether the output voltage is greater than the reference voltage. If the output voltage is greater than the reference voltage, the sensing circuit outputs a sensing signal with a reset logic state. If the output voltage is less than the reference voltage, the sensing circuit outputs a sensing signal with a set logic state.

15. The integrated circuit according to claim 13 or 14, further comprising a protection switch coupled between the high-side switch and the output terminal, wherein, The protection switch and the high-side switch are connected such that the body diode in the high-side switch and the body diode in the protection switch are connected in series back-to-back.

16. The integrated circuit according to claim 15, wherein, When the discharge circuit is disabled and the high-side switch is turned on, the protection switch is configured to operate in the variable resistance region, thereby controlling the magnitude of the current flowing through the high-side switch.

17. The integrated circuit according to claim 13 or 14 further includes a current sensing circuit, wherein, The control logic circuit is further configured to: Turn off the high-side switch and turn on the low-side switch, and The current sensing circuit is controlled to detect whether current flows through the low-side switch. If current is detected flowing through the low-side switch, the current sensing circuit outputs a sensing signal with reset logic; if no current is detected flowing through the low-side switch, the current sensing circuit outputs a sensing signal with set logic.

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