A dynamic swing control method, control circuit and switching power supply converter

Abstract

A kind of dynamic swing rate control method, control circuit and switching power supply converter, using analog circuit to control the opening and closing speed of the power switch tube of switching power supply converter, high side switch tube and low side switch tube are configured high side drive unit and low side drive unit respectively, including opening drive tube group and closing drive tube group in drive unit, the transistors in two drive tube groups are configured step by step according to size ratio, so that drive current increases step by step, the switching node voltage LX of switching power supply converter is detected in real time, according to the voltage variation level of LX, the transistor in drive tube group is gradually turned on, to realize the dynamic adaptive control of the switching speed of high side switch tube and low side switch tube.The circuit of the present application is simple and easy to realize, and is conducive to large-scale low-cost production.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology and relates to power management, specifically a dynamic slew rate control method, control circuit, and switching power supply converter. Background Technology

[0002] In switching power supply converters, especially synchronous buck DC / DC converters, two power transistors are typically used as switches to achieve voltage conversion. To turn on the power transistor, the driver provides current to the gate capacitance to charge it; to turn off the power transistor, the driver provides a discharge current path to discharge the gate capacitance. For gate switches, if the gate driver is too strong, extremely rapid current changes flowing through the parasitic inductance can generate extremely high induced voltage spikes, which may cause overshoot and ringing at the switching node, potentially damaging the transistor over time. If the gate driver slowly turns the transistor on and off, it increases switching losses in the transistor. To address this, a slew rate control scheme, also known as "slew rate control," is developed. Slew rate control controls the rate of voltage or current change when the power switch is turned on and off, balancing the overshoot and ringing problems caused by excessively fast switching speeds with the losses caused by excessively slow switching speeds. This effectively reduces electromagnetic interference (EMI) generated by the switching power supply while maintaining a certain level of efficiency.

[0003] During operation, the switching power supply converter circuit is affected by various load, temperature, and voltage conditions, and the slew rate control needs to adapt to changes in the switching speed. Figure 1 and Figure 2The scheme disclosed in US patent application US20250373144A1 discloses an adaptive slew rate control scheme. The adaptive slew rate control circuit 210 controls the slew rate based on resistor Rext1 and the voltage generated by the bandgap voltage reference circuit. It uses an ADC circuit to control digital logic, and logic circuit 380 controls the pmos and nmos transistors of the multiplexer to control the drive strength, thereby dynamically controlling the switching speed of the high-side transistor HS and the low-side transistor LS. The logic circuit requires a clock signal CLK to scan periodically. In the scheme of US20250373144A1, the ADC circuit controls the digital logic to set the drive strength, and the adaptive slew rate control circuit periodically (e.g., once per minute) performs a calibration process on the switching rate to achieve adaptive control of the switching speed. However, the digital logic and circuit system controlled by the ADC are complex, which increases the internal complexity of the chip. Furthermore, the adaptive conversion rate control circuit needs to perform a calibration procedure periodically, meaning that the adjustment of the switching speed is periodic rather than real-time. When the ADC samples and converts, and the logic circuit decodes and processes, a certain delay is introduced, which increases the response time of the entire control loop. It cannot adapt to the circuit conditions in real time and cannot be used in fields that require fast response, especially high-frequency switching circuits.

[0004] Other existing technologies also employ digital control circuits, such as Figure 3 The traditional pure digital control slew rate method uses a shift register to control the sequential activation of the output drive module. This scheme uses a fixed time to control the activation speed of the power transistor, which cannot reflect the real-time status of the circuit and cannot meet the need for fast response. Summary of the Invention

[0005] The technical problem to be solved by the present invention is that the existing technology for adaptive control of slew rate in switching power converters relies on periodically calibrated ADC digital logic control, which is complex, cannot monitor the circuit status in real time, and cannot meet the fast response requirements of switching power converters.

[0006] The technical solution of this invention is as follows: a dynamic slew rate control method, which uses analog circuits to control the turn-on and turn-off speeds of the power switching transistors of a switching power converter. High-side and low-side switching transistors are respectively configured with high-side drive units and low-side drive units. Each drive unit includes a turn-on drive transistor group and a turn-off drive transistor group. The transistors in the two drive transistor groups are arranged progressively according to their size ratio, causing the drive current to increase progressively.

[0007] The switching node voltage LX of a switching power converter is detected in real time. For a high-side switching tube, LX is compared with Vref1=VDD-0.1V and Vref2=VDD-0.3V; for a low-side switching tube, LX is compared with Vref3=-0.1V and Vref4=-0.3V. The change level of LX is monitored in real time, and transistors in a driving tube group are conducted step by step according to the voltage change level of LX, so as to realize dynamic adaptive control of the switching speeds of the high-side switching tube and the low-side switching tube.

[0008] Further, the two driving tube groups comprise three-stage transistors, and the transistor ratio is 1:2:4,

[0009] When the high-side switching tube is turned on, the LX voltage rises. In a turn-on driving tube group of a high-side driving unit, when LX < (VDD-0.3), a first-stage transistor is conducted to charge the gate of the high-side switching tube alone; when (VDD-0.3) < LX < (VDD-0.1), the first-stage transistor and a second-stage transistor are conducted to charge the gate of the high-side switching tube together; when LX > (VDD-0.1), all three-stage transistors are conducted to charge the gate of the high-side switching tube together;

[0010] When the low-side switching tube is turned on, the LX voltage drops. In a turn-on driving tube group of a low-side driving unit, when LX < -0.3, a first-stage transistor is conducted to charge the gate of the low-side switching tube alone; when -0.3 < LX < -0.1, the first-stage transistor and a second-stage transistor are conducted to charge the gate of the low-side switching tube together; when LX > -0.1, all three-stage transistors are conducted to charge the gate of the low-side switching tube together;

[0011] With the step-by-step conduction of the transistors, the driving current is amplified in a step-by-step accelerated manner, so as to control the turn-on speed of the high-side switching tube.

[0012] Further, according to control signals HI and LI of the switching power converter, HI is a switching signal of the high-side switching tube, and LI is a switching signal of the low-side switching tube; when HI is at a high level, the gate capacitance of the high-side switching tube is charged, and as the LX voltage rises, the high-side switching tube is completely turned on from slow to fast; when HI is at a low level, the high-side switching tube is turned off, and the control of LI on the low-side switching tube is the same.

[0013] The present invention also provides a dynamic slew rate control circuit, including a high-side switch Ppower, a low-side switch Npower, a high-side LX detection circuit, a low-side LX detection circuit, a high-side drive unit, and a low-side drive unit. In the high-side LX detection circuit, comparators comp1 and comp2 compare the switching node voltage LX of the switching power converter with Vref1=VDD-0.1V and Vref2=VDD-0.3V, respectively. In the low-side LX detection circuit, comparators comp3 and comp4 compare the switching node voltage LX with Vref3=-0.1V and Vref4=-0.3V, respectively. The high-side drive unit and the low-side drive unit each include an on-drive transistor group and an off-drive transistor group. The transistors in the two drive transistor groups are arranged in a size ratio of 1:2:4. Under the on-off signals of Ppower and Npower, the transistors in the two drive transistor groups are turned on step by step according to the change in LX voltage, so that the drive current increases step by step, thereby controlling the on-time of the high-side switch and the low-side switch.

[0014] Furthermore, the high-side drive unit includes PMOS transistors P1~P3 for the turn-on drive transistor group and NMOS transistors N1~N3 for the turn-off drive transistor group, and the low-side drive unit includes PMOS transistors P4~P6 for the turn-on drive transistor group and NMOS transistors N4~N6 for the turn-off drive transistor group. It is also equipped with inverters inv1~inv8, NOR gates nor1~nor4, and NAND gates nand1~nand4.

[0015] In the high-side drive unit, the sources and bodies of P1, P2, P3, and Ppower are connected and connected to VDD. The sources and bodies of N1, N2, and N3 are connected and connected to VSS. The drains of P1, P2, and P3 are connected together and connected to the drains of N1, N2, and N3, and output to the gate PG of Ppower. The switching signal HI of the high-side switch is connected to the gates of P1 and N1 respectively. The output of comp1 and the switching signal HI are connected to the gate of P2 after passing through nor1 and inv1. The output of comp2 and the switching signal HI are connected to the gate of P3 after passing through nor2 and inv2. The output of comp2 and the switching signal HI are connected to the gate of N2 after passing through nand1 and inv3. The output of comp1 and the switching signal HI are connected to the gate of N3 after passing through nand2 and inv4.

[0016] In the low-side drive unit, the sources and bodies of P4, P5, and P6 are connected and connected to VDD. The sources and bodies of N4, N5, N6, and Npower are connected and connected to VSS. The drains of P4, P5, and P6 are connected together and connected to the drains of N4, N5, and N6, and output to the gate NG of Npower. The switching signals LI of the low-side switching transistors are connected to the gates of P4 and N4 respectively. The output of comp4 and the switching signal LI are connected to the gate of P5 after passing through nor3 and inv5. The output of comp3 and the switching signal LI are connected to the gate of P6 after passing through nor4 and inv6. The output of comp3 and the switching signal LI are connected to the gate of N5 after passing through nand3 and inv7. The output of comp4 and the switching signal LI are connected to the gate of N3 after passing through nand4 and inv8.

[0017] Furthermore, the high-side LX detection circuit includes PMOS transistors PR1, PR2, PR3, P1A, P2A, P3A, P1B, P2B, and P3B; NMOS transistors N0A, N1A, N2A, N3A, N4A, N1B, N2B, N3B, and N4B; N0A, PR1, PR2, and PR3 form the Vref1 and Vref2 reference circuits; P1A, P2A, P3A, N1A, N2A, N3A, and N4A form comparator comp1; and P1B, P2B, P3B, N1B, N2B, N3B, and N4B form comparator comp2. The specific connections are as follows:

[0018] The sources and bodies of PR1, P1A, P2A, P3A, P1B, P2B, and P3B are connected to VDD. The bodies of PR2 and PR3 are connected to VDD. The sources and bodies of N0A, N3A, N4A, N3B, and N4B are connected to VSS. The gates of PR1, PR2, and PR3 are connected to the gate voltage PG of Ppower. The drain of PR1 is connected to the source of PR2. The output signal (VDD-0.1) is connected to the gate of N1A. The drain of PR2 is connected to the source of PR3. The output signal (VDD-0.3) is connected to the gate of N1B. The drain of PR3 is connected to the drain of N0A. The gates of N0A, N3A, N4A, N3B, and N4B are connected to VSS. The gate of P1A is connected to the drain of P1A and is connected to the gate of P2A and the drain of N1A. The source and body of N1A are connected to the source and body of N2A and are connected to the drain of N3A. The drains of P2A and N2A are connected to the gate of P3A. The gates of N2A and N2B are connected to LX. The drain of P3A is connected to the drain of N4A, serving as the output of comp1. The gate of P1B is connected to the drain of P1B and is connected to the gate of P2B and the drain of N1B. The source and body of N1B are connected to the source and body of N2B and the drain of N3B. The drains of P2B and N2B are connected to the gate of P3B. The drain of P3B is connected to the drain of N4B, serving as the output of comp2.

[0019] Furthermore, the low-side LX detection circuit includes PMOS transistors PC0, PC1, PC2, PC3, PC4, PD1, PD2, PD3, PD4, and NMOS transistors NR1, NR2, NR3, NR4, NR5, NR6, NC1, NC2, NC3, ND1, ND2, ND3. PC0, NR6, NR5, NR4, NR3, NR2, and NR1 form the reference voltage Vref3 and Vref4 generation circuit. PC1, PC2, PC3, PC4, NC1, NC2, and NC3 form comparator comp4. PD1, PD2, PD3, PD4, ND1, ND2, and ND3 form comparator comp3. The comparison of Vref3 and Vref4 with LX is achieved by comparing LX+0.1V, LX+0.3V with ground 0V, realizing the comparison of LX with -0.1V and -0.3V. The specific connection is as follows:

[0020] The sources and bodies of PC0, PC1, PC2, PC3, PC4, PD1, PD2, PD3, and PD4 are connected to VDD. The sources and bodies of NR1, NC1, NC2, NC3, ND1, ND2, and ND3 are connected to VSS. The gates of PC0, PC1, PC2, PD1, and PD2 are connected to B+. The gates of NR1, NR2, NR3, NR4, NR5, and NR6 are connected to the gate voltage NG signal of Npower. The drain of PC0 is connected to the drain and body of NR6. The source of NR6 is connected to the drain of NR5. The source and body of NR5 are connected and then connected to the drain and body of NR4. The (LX+0.3) signal is output to the gate of PC3. The source of NR4 is connected to the drain of NR3. The source and body of NR3 are connected and then connected to the drain and body of NR2. The (LX+0.1) signal is output to the gate of PD3. The source of NR2 is connected to the drain of NR1. The source and body of NR1 are connected to the LX signal. The drain of PC1 is connected to the source and body of PC3 and the source and body of PC4. The drain of PC3 is connected to the drain and gate of NC1 and the gate of NC2. The gate of PC4 is connected to the VSS potential. The drain of PC4 is connected to the drain of NC2 and the gate of NC3. The drain of PC2 is connected to the drain of NC3 as the output of comp4. The drain of PD1 is connected to the source and body of PD3 and the source and body of PD4. The drain of PD3 is connected to the drain and gate of ND1 and the gate of ND2. The gate of PD4 is connected to the VSS potential. The drain of PD4 is connected to the drain of ND2 and the gate of ND3. The drain of PD2 is connected to the drain of ND3 as the output of comp3.

[0021] The present invention also provides a switching power supply converter, which is equipped with the above-mentioned dynamic slew rate control circuit to dynamically control the switching speed of the high-side switching transistor and the low-side switching transistor.

[0022] In the circuit of this invention, P1~P3 are used to turn off Ppower; N1-N3 are used to turn on Ppower. When Ppower is turned on, NMOS discharge is used to pull its gate voltage low from VIN to GND. VDD charges the inductor through Ppower, and the LX voltage rises. It successively passes through the thresholds of (VDD-0.3) and (VDD-0.1), and N2 and N3 are turned on respectively to achieve two increases in the turn-on current, accelerating the drop of PG to turn on Ppower. That is, this invention can increase the discharge current from 1 times to 3 times to 7 times by detecting the VDS voltage of Ppower and comparing it with two different voltage thresholds, and gradually turn on N1, N2, and N3. This can improve the turn-on speed of Ppower from 1 times to 3 times to 7 times. When Ppower is turned off, Npower is turned on at the same time, and the LX voltage begins to drop. When Ppower is turned off, the initial LX voltage is close to VDD. Due to dead time control, Npower is kept off. At this time, the inductor freewheels through the parasitic body diode D1 of the Npower transistor, and the LX voltage is about -0.6V. As Npower is turned on, it is charged using PMOS, which pulls its gate voltage from GND to VIN high. The LX voltage starts to rise from -0.6V, passing through -0.3V and -0.1V respectively, turning on P5 and P6 twice to increase the turn-on current and accelerate the rise of NG to turn on Npower. By gradually turning on P4, P5, and P6, the charging current can be increased from 1 to 3 to 7 times, thereby increasing the Npower turn-on speed from 1 to 3 to 7 times. This allows control over the turn-on speed of the power transistor, achieving dynamic slew rate control.

[0023] This invention investigates a more reliable dynamic slew rate control method that controls the slew rate by real-time detection of the MOSFET drain-source voltage (VDS). This slew rate control method compares the MOSFET's VDS with two different voltage thresholds to turn the MOSFET on and off, thus achieving rapid turn-off with minimal delay.

[0024] This invention employs real-time detection analog control technology. During the power transistor's turn-on and turn-off processes, the LX voltage is detected. The LX voltage reflects the VDS voltage of the high-side switch and the low-side switch. These voltages are compared with two reference voltage points to control the gate turn-on speed of the high-side switch and the low-side switch, respectively. The turn-on speed is slow at the moment of startup and accelerates during the process. Furthermore, the turn-on speed of the power transistor is controlled according to the operating state of the circuit devices themselves, i.e., the change in the LX voltage, thus achieving adaptive dynamic slew rate control. The circuit is simple and easy to implement, which is conducive to large-scale low-cost production.

[0025] Meanwhile, the circuit of this invention features adaptive multi-level MOSFET gate control, achieving multi-level 1:3:7 turn-on speed control to ensure an optimized balance between power consumption and electromagnetic compatibility (EMC). This avoids ringing caused by power-on overshoot and reduces switching losses. Attached Figure Description

[0026] Figure 1 A schematic diagram of the adaptive slewing rate actuator disclosed in US patent application US20250373144A1.

[0027] Figure 2 A circuit diagram of the adaptive conversion rate control circuit in US patent application US20250373144A1.

[0028] Figure 3 This is a schematic diagram of a traditional slew rate control actuator.

[0029] Figure 4 This is a schematic diagram of the dynamic control circuit for the synchronous rectification buck circuit of the present invention.

[0030] Figure 5 This is a circuit diagram of comp1 and comp2, as well as Vref1 and Vref2 circuits in this invention.

[0031] Figure 6 This is a circuit diagram of comp3 and comp4, as well as Vref3 and Vref4 circuits in this invention. Detailed Implementation

[0032] This invention proposes a dynamic slew rate control method. It employs analog circuitry to control the turn-on and turn-off speeds of the power switches in a switching power converter. High-side and low-side switches are configured with high-side and low-side drive units, respectively. Each drive unit includes a turn-on drive transistor group and a turn-off drive transistor group. The transistors in the two drive transistor groups are arranged in a proportional order to increase the drive current step by step. The switching node voltage LX of the switching power converter is monitored in real time. For the high-side switch, LX is compared with Vref1 = VDD - 0.1V and Vref2 = VDD - 0.3V; for the low-side switch, LX is compared with Vref3 = -0.1V and Vref4 = -0.3V. The changes in LX are monitored in real time, and the transistors in the drive transistor groups are turned on step by step according to the voltage change levels of LX, achieving dynamic adaptive control of the switching speeds of the high-side and low-side switches.

[0033] The circuit implementation of this invention is described in detail below.

[0034] The dynamic control circuit information for the synchronous rectification buck circuit of the present invention is as follows:

[0035] Figure 4The connection relationship of the dynamic control circuit for synchronous rectification buck converter of the present invention is shown.

[0036] VDD is high level, VSS is low level. inv1, inv2, inv3, inv4, inv5, inv6, inv7, and inv8 are inverters; nor1, nor2, nor3, and nor4 are NOR gates; nand1, nand2, nand3, and nand4 are NAND gates. comp1, comp2, comp3, and comp4 are comparators. Vref1, Vref2, Vref3, and Vref4 are reference voltages. Ppower and Npower are the output synchronous rectifier power transistors, with PG and NG being their gate voltages. D1 is the parasitic diode of Npower. LX is the port connecting the output synchronous rectifier transistor to the inductor, i.e., the switching node voltage. P1, P2, P3, P4, P5, and P6 are PMOS transistors, and N1, N2, N3, N4, N5, and N6 are NMOS transistors. Their dimensions are as follows:

[0037] P1:P2:P3= P4:P5:P6= N1:N2:N3=N4:N5:N6=1:2:4.

[0038] HI is the switching signal for controlling Ppower; LI is the switching signal for controlling Npower.

[0039] LX is input to the positive input terminals of comp1 and comp2. Vref1 = VDD - 0.1V is input to the negative input terminal of comp1, and Vref2 = VDD - 0.3V is input to the negative input terminal of comp2. HI is connected to the gates of P1 and N1, as well as one end of nor1, nor2, nand1, and nand2.

[0040] The output of comp1 is connected to the other end of nor1 and nand2; the output of comp2 is connected to the other end of nor2 and nand1. The sources and bodies of P1, P2, P3, and Ppower are connected together to VDD. The sources and bodies of N1, N2, and N3 are connected together to VSS. The drains of P1, P2, and P3 are connected together, connected to the drains of N1, N2, and N3, and output to the gate PG of Ppower. The output of nor1 is connected to the input of inv1, and the output of inv1 is connected to the gate of P2. The output of Nor2 is connected to the input of inv2, and the output of inv2 is connected to the gate of P3. The output of Nand1 is connected to the input of inv3, and the output of inv3 is connected to the gate of N2. The output of Nand2 is connected to the input of inv4, and the output of inv4 is connected to the gate of N3.

[0041] LX is input to the negative input terminals of comp3 and comp4, Vref3=-0.1V is input to the positive input terminal of comp3, and Vref4=-0.3V is input to the positive input terminal of comp4. LI is connected to the gates of P4 and N4, as well as one end of nor3, nor4, nand3, and nand4.

[0042] The output of comp3 is connected to the other end of nor4 and nand3; the output of comp4 is connected to the other end of nor3 and nand4. The sources and bodies of P4, P5, and P6 are connected together to VDD. The sources and bodies of N4, N5, N6, and Npower are connected together to VSS. The drains of P4, P5, and P6 are connected together, connected to the drains of N4, N5, and N6, and output to the gate NG of Npower. The output of nor3 is connected to the input of inv5, and the output of inv5 is connected to the gate of P5. The output of nor4 is connected to the input of inv6, and the output of inv6 is connected to the gate of P6. The output of Nand3 is connected to the input of inv7, and the output of inv7 is connected to the gate of N5. The output of Nand4 is connected to the input of inv8, and the output of inv8 is connected to the gate of N6.

[0043] The drains of Ppower and Npower are connected to LX, with an external inductor providing the output Vout. D1 is located between the source and drain of the Npower transistor.

[0044] The principle analysis of the dynamic slew rate control circuit of this invention is as follows.

[0045] Ppower is the high-side switch connected to VDD, and Npower is the low-side switch connected to VSS. They intersect at point LX and are connected to the inductor. When Ppower is turned on, VDD charges the inductor through it, and the LX voltage rises. When Ppower is turned off, due to dead-time control, Npower has not yet turned on. First, the body diode of Npower freewheels, maintaining the inductor current to discharge to the output, and the LX voltage begins to drop. Then, Npower is gradually turned on, and the inductor discharges through Npower.

[0046] The gate of Ppower is controlled by P1, P2, P3 and N1, N2, N3, where P1, P2, P3 control Ppower to turn off, and N1, N2, N3 control Ppower to turn on. The gate of Npower is controlled by P4, P5, P6 and N4, N5, N6, where P4, P5, P6 control Npower to turn on, and N4, N5, N6 control Npower to turn off. Due to the size ratio...

[0047] P1:P2:P3= P4:P5:P6= N1:N2:N3=N4:N5:N6=1:2:4. The Ppower tube is turned on step by step by using NMOS to discharge and pulling its gate voltage down from VIN to GND. By detecting the VDS voltage of Ppower and comparing it with two different voltage thresholds, and gradually turning on N1, N2 and N3, the discharge current can be increased from 1 time to 3 times and then to 7 times, thereby increasing the turn-on speed of Ppower from 1 time to 3 times and then to 7 times; similarly, the Npower tube is turned on step by step by using PMOS to charge and pulling its gate voltage up from GND to VIN. By detecting the VDS voltage of Npower and comparing it with two different thresholds, and gradually turning on P4, P5 and P6, the charging current can be increased from 1 time to 3 times and then to 7 times, thereby increasing the turn-on speed of Npower from 1 time to 3 times and then to 7 times. In this way, the turn-on speed of the power tube can be controlled, that is, dynamic slew rate control of the power tube is realized.

[0048] HI and LI are general control signals for DC / DC. HI is the control signal for the high-side switch Ppower: when HI=VDD, Ppower is turned on; when HI=VSS, Ppower is turned off. LI is the control signal for the low-side switch: when LI=VDD, Npower is turned off; when LI=VSS, Npower is turned on.

[0049] During the rising process of LX, the voltage starts to rise from VSS to VDD: when LX<(VDD-0.3), comp1 and comp2 output low level VSS; when (VDD-0.3)<LX<(VDD-0.1), comp1 outputs low level and comp2 outputs high level; when LX>(VDD-0.1), comp1 and comp2 output high level VDD.

[0050] The LX voltage starts to rise from about -0.6V, because -0.6V is the voltage divided by the body diode of the inductor when the inductor flows freewheeling current through the low-side switch tube. When LX<-0.3, comp3 and comp4 output high level VDD; when -0.3<LX<-0.1, comp4 outputs low level VSS and comp3 outputs high level; when LX>-0.1, comp3 and comp4 output low level VSS.

[0051] Turn on Ppower to charge the inductor, and at this time, the initial voltage of LX is close to VSS. Controlled by the dead time, first LI=VDD and HI=VSS, that is, P1 is turned on, the Ppower tube is kept off, N4 is turned on and Npower is turned off at the same time. Then, HI switches to VDD, P1 is turned off and N1 is turned on, pulling the gate PG of the Ppower tube low to turn on Ppower, and LX starts to rise from VSS to VDD as Ppower is turned on. Meanwhile, since HI=VDD, nor1 and nor2 output low levels, turning off P2 and P3 through inv1 and inv2 respectively. When LX<(VDD-0.3), comp1 and comp2 output low level VSS, nand1 and nand2 output high level, turning off N2 and N3 through inv3 and inv4 respectively, that is, only N1 is conducted at this time. Limited by the size of N1 being N1×1 time, the gate discharge current of the Ppower tube is small, that is, the Ppower turn-on speed is the slowest. When (VDD-0.3)<LX<(VDD-0.1), comp1 outputs low level, comp2 outputs high level, nand1 outputs low level, nand2 keeps high level, N2 is turned on through inv3, and N3 keeps off at the same time. At this time, the sum of the sizes of (N1+N2) is N1×3 times, and the Ppower turn-on speed is increased. When LX> (VDD-0.1), comp1 and comp2 output high level VDD, nand1 and nand2 output low level, turning on N2 and N3 through inv3 and inv4 respectively. At this time, the sum of the sizes of (N1+N2+N3) is N1×7 times, reaching the maximum charging current, that is, the fastest turn-on speed of the Ppower tube.

[0052] Similarly, when Ppower is turned off, the HI signal changes from VDD to VSS, and N1 is turned off immediately. Since the outputs of nand1 and nand2 flip to high level, inv3 and inv4 output low level and turn off N2 and N3. At the same time, P1 is turned on immediately, and starts to pull up the gate voltage PG of Ppower to turn off Ppower. As Ppower is turned off, the LX voltage VDD starts to decrease. When LX > VDD-0.1V, comp1 and comp2 output high level, nor1 and nor2 output low level, inv1 and inv2 output high level, and turn off P2 and P3. That is, only P1 is conductive at this time, limited by that the size of P1 is P1x1 times, the gate discharge current of the Ppower transistor is small, that is, the turn-on speed of Power is the slowest. When (VDD-0.3) < LX < (VDD-0.1V), comp1 outputs low level, comp2 outputs high level, nor1 outputs low level, nor2 keeps high level, P2 is turned on through inv1, while P3 keeps off. At this time, the sum of the sizes of (P1+P2) is P1x3 times, and the turn-on speed of Ppower is increased. When LX < (VDD-0.3), comp1 and comp2 output low level VSS, nor1 and nor2 output high level, P2 and P3 are turned on through inv1 and inv2 respectively. At this time, the sum of the sizes of (P1+P2+P3) is P1x7 times, reaching the maximum charging current, that is, the fastest turn-off speed of the Ppower transistor.

[0053] In the turn-on / turn-off process of Ppower, the invention has slow turn-on / turn-off instant speed and accelerates step by step during the process. The turn-on / turn-off speed increases gradually with the change of LX, which realizes real-time dynamic adaptation to the actual working condition of the circuit, and can effectively avoid the ringing caused by rapid power-on overshoot at the switching instant. Meanwhile, the subsequent acceleration process can speed up charging and reduce switching loss caused by incomplete turn-on, so as to ensure the optimal balance between power consumption and electromagnetic compatibility (EMC).

[0054] For turning on and off Npower, Ppower is turned off, Npower is turned on at the same time to discharge the inductor, and the initial voltage of LX is close to VDD. Due to dead time control, first HI=VSS, that is, P1 is turned on, the Ppower tube is kept off; meanwhile LI=VDD, N4 is kept on, and Npower is kept off during the dead time. At this time, the inductor freewheels through the parasitic body diode D1 of the Npower tube, and the LX voltage is approximately -0.6V. Then LI is switched to VSS, N4 is turned off, P4 is turned on, the gate NG of the Npower tube is pulled high, and Npower is turned on. As Npower gradually conducts, LX starts to rise from -0.6V to VSS. Meanwhile, since LI=VSS, nand3 and nand4 output high levels, turning off N5 and N6 through inv7 and inv8 respectively. When LX < -0.3, comp3 and comp4 output the high level VDD, nor3 and nor4 output low levels, and turn off P5 and P6 through inv5 and inv6 respectively. That is, only P4 is conductive at this time. Limited by the size of P4 which is 1×P4, the gate charging current of the Npower tube is small, which means the turning-on speed of Npower is the slowest. When -0.3 < LX < -0.1, comp4 outputs a low level, comp3 outputs a high level, nor3 outputs a high level, nor4 remains at a high level, P5 is turned on through inv5, and P6 is kept off at the same time. At this time, the sum of the sizes of (P4+P5) is 3×P4, and the turning-on speed of Npower is increased. When LX > -0.1, comp3 and comp4 output the low level VSS, nor3 and nor4 output high levels, and turn on P5 and P6 through inv5 and inv6 respectively. At this time, the sum of the sizes of (P4+P5+P6) is 7×P4, which reaches the maximum charging current, that is, the fastest charging speed of the Npower tube.

[0055] Similarly, when Npower is turned off, the LI signal changes from VSS to VDD, and P4 is turned off immediately. Since the outputs of nor3 and nor4 flip to low, inv5 and inv6 output high level, turning off P5 and P6. Meanwhile, N4 is turned on immediately, and starts to pull down the gate voltage NG of Npower, thus turning off Npower. As Npower is turned off, the LX voltage starts to decrease from VSS. When LX > -0.1V, comp3 and comp4 output low level VSS, nand3 and nand4 output high level, and turn off N5 and N6 through inv7 and inv8 respectively. At this time, only N4 is conducting. Limited by the size of N4 which is N4×1, the gate discharge current of the Npower transistor is small, that is, the turning-off speed of Npower is the slowest. When -0.3 < LX < -0.1, comp4 outputs low level, comp3 outputs high level, nand3 outputs low level, nand4 keeps high level, N5 is turned on through inv7, and N6 keeps turned off. At this time, the sum of the sizes of (N5+N6) is N4×3, and the turning-off speed of Npower increases. When LX > -0.1, comp3 and comp4 output low level VSS, nand3 and nand4 output high level, and turn on N5 and N6 through inv7 and inv8 respectively. At this time, the sum of the sizes of (N4+N5+N6) is N4×7, reaching the maximum discharge current, that is, the fastest turning-off speed of the Npower transistor.

[0056] Since during the turn-on / turn-off process of the Npower transistor, the turn-on / turn-off speed is slow at the initial moment and accelerated during the process, that is, the turn-on / turn-off speed increases gradually. Therefore, ringing caused by overshoot during rapid power-on at the switching moment can be effectively avoided, an optimized balance between power consumption and electromagnetic compatibility (EMC) is ensured, and meanwhile, the subsequent acceleration process can speed up charging and reduce switching loss caused by incomplete turn-on.

[0057] Further, the generation mode of the reference voltage is special, especially the negative voltages of -0.3V and -0.1V. In order to generate the reference voltages Vref1 to Vref4 and facilitate circuit integration, the present invention designs a detection circuit for the LX voltage.

[0058] Figure 5 shows the circuit connection relationship of comp1, comp2, Vref1 and Vref2 of the present invention: PR1, PR2, PR3, P1A, P2A, P3A, P1B, P2B, P3B are PMOS transistors, and N0A, N1A, N2A, N3A, N4A, N1B, N2B, N3B, N4B are NMOS transistors.

[0059] VDD-0.1 is Vref1, VDD-0.3 is Vref2, LX is the interface signal between the inductor and power transistor of the switching power supply circuit, i.e., the switching node voltage, PG is the gate voltage of the Ppower power transistor, and B- is the bias voltage of the NMOS transistor.

[0060] The sources and bodies of PR1, P1A, P2A, P3A, P1B, P2B, and P3B are connected together with the bodies of PR2 and PR3, and then connected to VDD. The sources and bodies of N0A, N3A, N4A, N3B, and N4B are connected to VSS. The gates of PR1, PR2, and PR3 are connected to PG. The drain of PR1 is connected to the source of PR2, and the output signal (VDD-0.1) is connected to the gate of N1A. The drain of PR2 is connected to the source of PR3, and the output signal (VDD-0.3) is connected to the gate of N1B. The drain of PR3 is connected to the drain of N0A. The gates of N0A, N3A, N4A, N3B, and N4B are connected to the B- signal. The gate of P1A is connected to its drain and is also connected to the gate of P2A and the drain of N1A. The source and body of N1A are connected to the source and body of N2A and the drain of N3A. The drain of P2A and the drain of N2A are connected to the gate of P3A. The gates of N2A and N2B are connected to LX. The drain of P3A is connected to the drain of N4A, and the output signal of comparator comp1 is comp1-out. The gate of P1B is connected to its drain, the gate of P2B, and the drain of N1B. The source and body of N1B are connected to the source and body of N2B and the drain of N3B. The drains of P2B and N2B are connected to the gate of P3B. The drain of P3B is connected to the drain of N4B, and the output signal of comparator comp2 is comp2-out.

[0061] For Vref1 and Vref2, the negative voltages -0.1V and -0.3V are formed by a voltage divider through resistors PR1-PR3. When PMOS is fully turned on, it acts as a resistor, and a constant bias current flows through it, creating a constant voltage divider that produces VDD-0.1V and VDD-0.3V respectively. N0A, PR1, PR2, and PR3 form the reference circuits for Vref1 and Vref2. N0A is connected to the B-bias voltage, generating a bias current. When PG is low (i.e., when the high-side power transistor Ppower is on), PR1, PR2, and PR3 are on, acting as linear resistors. By adjusting the dimensions of N0A, PR1, PR2, and PR3, a 0.1V voltage divider can be achieved for PR1, and a 0.2V voltage divider can be achieved for PR1, resulting in an output voltage of (VDD-0.1V) for PR1 and an output voltage of (VDD-0.3V) for PR2.

[0062] Comparator comp1 is composed of P1A, P2A, P3A, N1A, N2A, N3A, and N4A, and comparator comp2 is composed of P1B, P2B, P3B, N1B, N2B, N3B, and N4B. Comp1 detects LX and (VDD-0.1). When LX < (VDD-0.1), the output of comp1 flips, and comp1-out = 0. Comp2 detects LX and (VDD-0.3). When LX < (VDD-0.3), the output of comp2 flips, and comp2-out = 0. The unique feature of this comparator lies in the pairing of the input transistors and the reference. Since VDD-0.1 and VDD-0.3 are high voltages, an NMOS input differential pair is used; conversely, since LX is low voltage, a PMOS input differential pair is used.

[0063] Figure 6 This is a schematic diagram showing the circuit connection relationship between comp3 and comp4, and Vref3 and Vref4 of the present invention.

[0064] PC0, PC1, PC2, PC3, PC4, PD1, PD2, PD3, and PD4 are PMOS transistors, and NR1, NR2, NR3, NR4, NR5, NR6, NC1, NC2, NC3, ND1, ND2, and ND3 are NMOS transistors. Since the circuit cannot directly generate a negative voltage reference, LX+0.1, LX+0.3, and ground (0) are used to compare LX with -0.1V and -0.3V, respectively. In other words, during circuit design, LX+0.1 is used as Vref3, LX+0.3 as Vref4, NG is the gate voltage of the Npower transistor, and B+ is the bias voltage of the PMOS transistor.

[0065] The sources and bodies of PC0, PC1, PC2, PC3, PC4, PD1, PD2, PD3, and PD4 are connected to VDD. The sources and bodies of NR1, NC1, NC2, NC3, ND1, ND2, and ND3 are connected to VSS. The gates of PC0, PC1, PC2, PD1, and PD2 are connected to B+. The gates of NR1, NR2, NR3, NR4, NR5, and NR6 are connected to the NG signal. The drain of PC0 is connected to the drain and body of NR6, and the source of NR6 is connected to the drain of NR5. The source and body of NR5 are connected to the drain and body of NR4, outputting a (LX+0.3) signal to the gate of PC3. The source of NR4 is connected to the drain of NR3. The source and body of NR3 are connected to the drain and body of NR2, outputting a (LX+0.1) signal to the gate of PD3. The source of NR2 is connected to the drain of NR1. The source and body of NR1 are connected to the LX signal. The drain of PC1 is connected to the source and body of PC3 and PC4. The drain of PC3 is connected to the drain and gate of NC1 and the gate of NC2. The gate of PC4 is connected to VSS potential, and the drain of PC4 is connected to the drain of NC2 and the gate of NC3. The drain of PC2 is connected to the drain of NC3, outputting the output signal comp4_out of comp4. The drain of PD1 is connected to the source and body of PD3 and PD4. The drain of PD3 is connected to the drain and gate of ND1 and the gate of ND2. The gate of PD4 is connected to VSS potential, and the drain of PD4 is connected to the drain of ND2 and the gate of ND3. The drain of PD2 is connected to the drain of ND3, outputting the output signal comp3_out of comparator comp3.

[0066] PC1, PC2, PC3, PC4, NC1, NC2, and NC3 form comparator comp4, and PD1, PD2, PD3, PD4, ND1, ND2, and ND3 form comparator comp3.

[0067] PC0, NR6, NR5, NR4, NR3, NR2, and NR1 form the circuit for generating reference voltages Vref3 and Vref4. When the NG signal is high, the low-side N-power transistor is turned on, and NR6, NR5, NR4, NR3, NR2, and NR1 are all turned on, forming a linear resistor. PC0 acts as a reference current source, and the reference current flowing through NR6, NR5, NR4, NR3, NR2, and NR1 forms a resistive voltage divider. In this invention, by designing the dimensions of PC0 and NR6, NR5, NR4, NR3, NR2, and NR1, a 0.1V voltage divider is formed on NR1 and NR2, and a 0.3V voltage divider is formed on NR1, NR2, NR3, and NR4. After superimposing the voltage of the LX signal, reference voltages of (LX+0.1) and (LX+0.3) are generated.

[0068] Comp4 compares (LX+0.3) with the VSS signal (ground), and the toggle point is when LX+0.3=0, i.e., LX=-0.3V. This achieves the effect of comparing LX with -0.3V, allowing control when the inductor voltage LX flips to a negative voltage, solving the problem of not being able to generate a negative voltage reference in positive voltage circuits. Similarly, comp3 compares (LX+0.1) with the VSS signal (ground), and the toggle point is when LX+0.1=0, i.e., LX=-0.1V. This achieves the effect of comparing LX with -0.1V.

[0069] This invention employs real-time detection analog control technology. During the power-on and power-off processes, the LX voltage is detected and compared with two reference voltage points to control the gate turn-on speed of the high-side and low-side switches, respectively. This provides adaptive detection, and the circuit is simple and easy to implement, facilitating large-scale, low-cost production. Simultaneously, the circuit of this invention features adaptive multi-stage MOSFET gate control, ensuring an optimized balance between power consumption and electromagnetic compatibility (EMC). It avoids ringing caused by power-on overshoot and reduces switching losses. The startup is slow initially, but accelerates during the process.

Claims

1. A dynamic pendulum rate control method, characterized in that: An analog circuit is used to control the turn-on and turn-off speed of the power switch tube of the switching power converter. A high-side driving unit and a low-side driving unit are respectively configured for the high-side switch tube and the low-side switch tube. The driving units include a turn-on driving tube group and a turn-off driving tube group. The transistors in the two driving tube groups are arranged step by step according to the size ratio, so that the driving current increases step by step. The switching node voltage LX of the switching power converter is detected in real time. For the high-side switch tube, LX is compared with Vref1=VDD-0.1V and Vref2=VDD-0.3V; for the low-side switch tube, LX is compared with Vref3=-0.1V and Vref4=-0.3V, wherein VDD is a high level, and Vref1, Vref2, Vref3, and Vref4 are reference voltages respectively. The change level of LX is monitored in real time, and the transistors in the driving tube groups are conducted step by step according to the voltage change level of LX, so as to realize dynamic adaptive control of the switching speed of the high-side switch tube and the low-side switch tube; When the high-side switch tube is turned on, the LX voltage rises. In the turn-on driving tube group of the high-side driving unit, when LX<(VDD-0.3V), the first-stage transistor is conducted to charge the gate of the high-side switch tube alone; when (VDD-0.3V)<LX<(VDD-0.1V), the first-stage and second-stage transistors are conducted to charge the gate of the high-side switch tube together; when LX>(VDD-0.1V), all three-stage transistors are conducted to charge the gate of the high-side switch tube together; When the low-side switch tube is turned on, the LX voltage drops. In the turn-on driving tube group of the low-side driving unit, when LX<-0.3V, the first-stage transistor is conducted to charge the gate of the low-side switch tube alone; when -0.3V<LX<-0.1V, the first-stage and second-stage transistors are conducted to charge the gate of the low-side switch tube together; when LX>-0.1V, all three-stage transistors are conducted to charge the gate of the low-side switch tube together; With the step-by-step conduction of the transistors, the driving current is amplified in an accelerated manner step by step, so as to control the turn-on speed of the high-side switch tube.

2. The dynamic pendulum rate control method according to claim 1, characterized in that: The two driving tube groups comprise three-stage transistors, and the size ratio of the transistors is 1:2:

4.

3. The dynamic pendulum rate control method according to claim 1, characterized in that: According to the control signals HI and LI of the switching power converter, HI is the switching signal of the high-side switch tube, and LI is the switching signal of the low-side switch tube; when HI is at a high level, the gate capacitance of the high-side switch tube is charged, and as the LX voltage rises, the high-side switch tube is fully turned on from slow to fast; when HI is at a low level, the high-side switch tube is turned off, and the control of LI on the low-side switch tube is the same.

4. A dynamic slew rate control circuit, characterized in that... It comprises a high-side switching tube Ppower, a low-side switching tube Npower, a high-side LX detection circuit, a low-side LX detection circuit, a high-side driving unit and a low-side driving unit. In the high-side LX detection circuit, comparators comp1 and comp2 respectively compare the switching node voltage LX of the switching power converter with Vref1=VDD-0.1V and Vref2=VDD-0.3V. In the low-side LX detection circuit, comparators comp3 and comp4 respectively compare the switching node voltage LX with Vref3=-0.1V and Vref4=-0.3V. VDD is a high level, and Vref1, Vref2, Vref3, and Vref4 are reference voltages respectively. The high-side driving unit and the low-side driving unit each comprise a turn-on driving tube set and a turn-off driving tube set. Transistors in the two driving tube sets are configured step by step according to a size ratio, and the size ratio is 1:2:

4. Under turn-on and turn-off signals for Ppower and Npower, transistors in the two driving tube sets are turned on step by step according to the change of LX voltage, so that driving current increases step by step, thereby controlling the turn-on speed of the high-side switching tube and the low-side switching tube; When the high-side switching tube is turned on, the LX voltage rises. In the turn-on driving tube set of the high-side driving unit, when LX<(VDD-0.3V), the first-stage transistor is turned on to charge the gate of the high-side switching tube alone; when (VDD-0.3V)<LX<(VDD-0.1V), the first-stage and second-stage transistors are turned on to charge the gate of the high-side switching tube together; when LX>(VDD-0.1V), all three-stage transistors are turned on to charge the gate of the high-side switching tube together; When the low-side switching tube is turned on, the LX voltage drops. In the turn-on driving tube set of the low-side driving unit, when LX<-0.3V, the first-stage transistor is turned on to charge the gate of the low-side switching tube alone; when -0.3V<LX<-0.1V, the first-stage and second-stage transistors are turned on to charge the gate of the low-side switching tube together; when LX>-0.1V, all three-stage transistors are turned on to charge the gate of the low-side switching tube together; With the step-by-step conduction of the transistors, the driving current is amplified in an accelerated step-by-step manner, thereby controlling the turn-on speed of the high-side switching tube.

5. The dynamic slew rate control circuit according to claim 4, characterized in that the high-side driving unit comprises a turn-on driving tube set of PMOS transistors P1~P3 and a turn-off driving tube set of NMOS transistors N1~N3; the low-side driving unit comprises a turn-on driving tube set of PMOS transistors P4~P6 and a turn-off driving tube set of NMOS transistors N4~N6; the circuit is further provided with inverters inv1~inv8, NOR gates nor1~nor4, and NAND gates nand1~nand4; In the high-side drive unit, the sources and bodies of P1, P2, P3, and Ppower are connected together and connected to VDD. The sources and bodies of N1, N2, and N3 are connected together and connected to VSS. VSS is at a low level. The drains of P1, P2, and P3 are connected together and connected to the drains of N1, N2, and N3, and output to the gate PG of Ppower. The switching signal HI of the high-side switch is connected to the gates of P1 and N1 respectively. The output of comp1 and the switching signal HI are connected to the gate of P2 after passing through nor1 and inv1. The output of comp2 and the switching signal HI are connected to the gate of P3 after passing through nor2 and inv2. The output of comp2 and the switching signal HI are connected to the gate of N2 after passing through nand1 and inv3. The output of comp1 and the switching signal HI are connected to the gate of N3 after passing through nand2 and inv4. In the low-side drive unit, the sources and bodies of P4, P5, and P6 are connected and connected to VDD. The sources and bodies of N4, N5, N6, and Npower are connected and connected to VSS. The drains of P4, P5, and P6 are connected together and connected to the drains of N4, N5, and N6, and output to the gate NG of Npower. The switching signals LI of the low-side switching transistors are connected to the gates of P4 and N4 respectively. The output of comp4 and the switching signal LI are connected to the gate of P5 after passing through nor3 and inv5. The output of comp3 and the switching signal LI are connected to the gate of P6 after passing through nor4 and inv6. The output of comp3 and the switching signal LI are connected to the gate of N5 after passing through nand3 and inv7. The output of comp4 and the switching signal LI are connected to the gate of N3 after passing through nand4 and inv8.

6. The dynamic slew rate control circuit according to claim 4, characterized in that: The high-side LX detection circuit includes PMOS transistors PR1, PR2, PR3, P1A, P2A, P3A, P1B, P2B, and P3B; NMOS transistors N0A, N1A, N2A, N3A, N4A, N1B, N2B, N3B, and N4B; N0A, PR1, PR2, and PR3 form the Vref1 and Vref2 reference circuits; P1A, P2A, P3A, N1A, N2A, N3A, and N4A form comparator comp1; and P1B, P2B, P3B, N1B, N2B, N3B, and N4B form comparator comp2. The specific connections are as follows: The sources and bodies of PR1, P1A, P2A, P3A, P1B, P2B, and P3B are connected to VDD. The bodies of PR2 and PR3 are connected to VDD. The sources and bodies of N0A, N3A, N4A, N3B, and N4B are connected to VSS, which is low. The gates of PR1, PR2, and PR3 are connected to the gate voltage PG of Ppower. The drain of PR1 is connected to the source of PR2. The output signal VDD-0.1V is connected to the gate of N1A. The drain of PR2 is connected to the source of PR3. The output signal VDD-0.3V is connected to the gate of N1B. The drain of PR3 is connected to the drain of N0A. N0A, N3A, N4A, N3B, and N4B are connected to VSS. The gate of B is connected to the bias voltage B-. The gate of P1A is connected to the drain and is connected to the gate of P2A and the drain of N1A. The source and body of N1A are connected to the source and body of N2A and are connected to the drain of N3A. The drains of P2A and N2A are connected to the gate of P3A. The gates of N2A and N2B are connected to LX. The drain of P3A is connected to the drain of N4A, serving as the output of comp1. The gate of P1B is connected to the drain and is connected to the gate of P2B and the drain of N1B. The source and body of N1B are connected to the source and body of N2B and the drain of N3B. The drains of P2B and N2B are connected to the gate of P3B. The drain of P3B is connected to the drain of N4B, serving as the output of comp2.

7. The dynamic slew rate control circuit according to claim 4, characterized in that it has low... The LX detection circuit includes PMOS transistors PC0, PC1, PC2, PC3, PC4, PD1, PD2, PD3, PD4, and NMOS transistors NR1, NR2, NR3, NR4, NR5, NR6, NC1, NC2, NC3, ND1, ND2, ND3. PC0, NR6, NR5, NR4, NR3, NR2, and NR1 form the reference voltage Vref3 and Vref4 generation circuit. PC1, PC2, PC3, PC4, NC1, NC2, and NC3 form comparator comp4. PD1, PD2, PD3, PD4, ND1, ND2, and ND3 form comparator comp3. The comparison of Vref3 and Vref4 with LX is achieved by comparing LX +0.1V, LX +0.3V with ground (0V), thus realizing the comparison of LX with -0.1V and -0.3V. The specific connection is as follows: The sources and bodies of PC0, PC1, PC2, PC3, PC4, PD1, PD2, PD3, and PD4 are connected to VDD. The sources and bodies of NR1, NC1, NC2, NC3, ND1, ND2, and ND3 are connected to VSS. The gates of PC0, PC1, PC2, PD1, and PD2 are connected to B+. The gates of NR1, NR2, NR3, NR4, NR5, and NR6 are connected to the gate voltage NG signal of Npower. The drain of PC0 is connected to the drain and body of NR6. The source of NR6 is connected to the drain of NR5. The source and body of NR5 are connected and then connected to the drain and body of NR4. The LX+0.3V signal is output to the gate of PC3. The source of NR4 is connected to the drain of NR3. The source and body of NR3 are connected and then connected to the drain and body of NR2. The LX+0.1V signal is output to the gate of PD3. The source of NR2 is connected to the drain of NR1. The source and body of NR1 are connected to the LX signal. The drain of PC1 is connected to the source and body of PC3 and the source and body of PC4. The drain of PC3 is connected to the drain and gate of NC1 and the gate of NC2. The gate of PC4 is connected to the VSS potential. The drain of PC4 is connected to the drain of NC2 and the gate of NC3. The drain of PC2 is connected to the drain of NC3, serving as the output of comp4. The drain of PD1 is connected to the source and body of PD3 and the source and body of PD4. The drain of PD3 is connected to the drain and gate of ND1 and the gate of ND2. The gate of PD4 is connected to the VSS potential. The drain of PD4 is connected to the drain of ND2 and the gate of ND3. The drain of PD2 is connected to the drain of ND3, serving as the output of comp3.

8. A switching power supply converter, characterized in that... The device is equipped with the dynamic slew rate control circuit according to any one of claims 4 to 7, which dynamically controls the switching speed of the high-side switch and the low-side switch.

Images