A crosstalk suppression circuit and an electrical apparatus

Abstract

The application discloses a crosstalk suppression circuit and an electric device, the crosstalk suppression circuit comprises at least two MOS transistors connected in series to form a half-bridge circuit, and a driving circuit for driving the MOS transistors to work, and the crosstalk suppression circuit at least comprises a clamping circuit connected between the gate and the source of the MOS transistors, and a driving monitoring unit connected to the output end of the driving circuit; the clamping circuit is configured to clamp the gate-source voltage of the MOS transistors to 0V when in the on state; the driving monitoring unit is configured to provide a control level capable of turning on the clamping circuit when monitoring that the driving circuit provides a driving voltage capable of turning on the MOS transistors. Compared with the prior art, the application realizes active clamping control of the gate-source voltage of the MOS transistors, can prevent the MOS transistors from being mis-conducted or broken down due to crosstalk, and improves the stability and reliability of the system.

Description

Technical Field

[0001] This invention relates to the field of power device control, and in particular to a crosstalk suppression circuit and electrical equipment. Background Technology

[0002] In power electronic systems, SiC MOSFETs, as core devices with high frequency and high power, are widely used in inverters, motor drives, photovoltaic inverters, and other equipment. Due to their fast switching speed and large parasitic inductance, they are prone to gate-source voltage crosstalk in bridge circuits, leading to false conduction or breakdown, which seriously affects the stability and reliability of the system.

[0003] Existing passive drive solutions have the following problems in terms of crosstalk suppression:

[0004] 1. The suppression effect is limited, and precise voltage clamping cannot be achieved;

[0005] 2. Complex structure, many components, and high cost;

[0006] 3. Difficult to adapt to high-frequency, high-power application scenarios;

[0007] 4. It is susceptible to the influence of parasitic parameters and has poor anti-interference ability;

[0008] Therefore, how to design a crosstalk suppression circuit and electrical equipment that can effectively suppress crosstalk between the gate and source voltages of SiC MOSFETs, which could lead to mis-conduction or breakdown, is a technical problem that the industry urgently needs to solve. Summary of the Invention

[0009] To address the problem that existing passive drive solutions have limited crosstalk suppression effects and cannot achieve precise voltage clamping, this invention proposes a crosstalk suppression circuit and electrical equipment.

[0010] The technical solution of the present invention is to propose a crosstalk suppression circuit, including at least two MOS transistors connected in series to form a half-bridge circuit, and a driving circuit for driving the MOS transistors to work. The crosstalk suppression circuit includes at least a clamping circuit connected between the gate and source of the MOS transistors, and a driving monitoring unit connected to the output terminal of the driving circuit.

[0011] The clamping circuit is configured to clamp the gate-source voltage of the MOSFET to 0V when it is in the ON state;

[0012] The drive monitoring unit is configured to provide a control level that enables the clamping circuit to conduct when the drive circuit provides a drive voltage that enables the MOS transistor to conduct.

[0013] The present invention, through the above-described scheme, can accurately monitor the driving voltage of the MOSFET, i.e., the SiC MOSFET, and determine whether the MOSFET is in the off state due to the driving voltage. In conjunction with the clamping circuit, when the MOSFET is in the off state, the gate-source voltage of the MOSFET is actively clamped to 0V, thereby achieving active voltage clamping and fundamentally avoiding the response delay and false triggering problems of traditional passive clamping.

[0014] Furthermore, the crosstalk suppression circuit also includes a discharge circuit connected between the driving circuit and the gate of the MOS transistor, the discharge circuit being used to discharge the transient positive current at the gate of the MOS transistor.

[0015] The present invention, through the above-described scheme, can quickly discharge the transient positive current at the gate of the MOSFET through a discharge circuit, thereby achieving forward crosstalk suppression. It can reduce the peak forward crosstalk voltage from -8.02V in the traditional passive scheme to -3.08V, a reduction of 4.94V, and completely avoid the problem of MOSFET mis-turn-on.

[0016] Furthermore, the MOSFET includes a first MOSFET located on the high-voltage side and a second MOSFET located on the low-voltage side;

[0017] The driving circuit has a first output terminal and a second output terminal, and the first output terminal and the second output terminal are used to provide driving voltages with opposite levels. The first output terminal is connected to the gate of the first MOS transistor, and the second output terminal is connected to the gate of the second MOS transistor.

[0018] The present invention, through the above-described scheme, can form a half-bridge circuit with the first MOSFET and the second MOSFET, thereby achieving a series of advantages such as smooth current output, efficient energy conversion, and reduced power loss. At the same time, by driving the first MOSFET and the second MOSFET through a drive circuit with a push-pull circuit, it has the advantages of low conduction loss, high efficiency, and strong load capacity.

[0019] Furthermore, the clamping circuit includes: Schottky diode D1, Schottky diode D3, PMOS transistor Q1, and PMOS transistor Q3;

[0020] The drain of the first MOSFET is connected to the power supply, the source of the first MOSFET is connected to the drain of the second MOSFET, and the source of the second MOSFET is grounded.

[0021] The negative terminal of the Schottky diode D1 is connected between the first output terminal and the gate of the first MOS transistor, the positive terminal of the Schottky diode D1 is connected to the drain of the PMOS transistor Q1, the source of the PMOS transistor Q1 is connected between the source of the first MOS transistor and the drain of the second MOS transistor, and the gate of the PMOS transistor Q1 is connected to the drive monitoring unit.

[0022] The negative terminal of the Schottky diode D3 is connected between the second output terminal and the gate of the second MOS transistor, the positive terminal of the Schottky diode D3 is connected to the drain of the PMOS transistor Q3, the source of the PMOS transistor Q3 is connected between the source of the second MOS transistor and ground, and the gate of the PMOS transistor Q3 is connected to the drive monitoring unit.

[0023] Through the above-described design, this invention enables the clamping circuit to be turned on by turning on PMOS transistors Q1 and Q3 when the first and second MOS transistors are in the off state. Furthermore, when PMOS transistors Q1 and Q3 are on, the gates and sources of the first and second MOS transistors are connected, clamping the gate-source voltage to 0V, thus avoiding the problem of false turn-on of the first and second MOS transistors. In addition, the gates of both PMOS transistors Q1 and Q3 are connected to a drive monitoring unit, enabling active control of the clamping circuit. Since the drive monitoring unit can detect whether the drive voltage is used to turn on the first and second MOS transistors, this invention can determine whether the first and second MOS transistors are in the off state and achieve active clamping when they are off, thereby fundamentally avoiding the response delay and false triggering problems of traditional passive clamping.

[0024] Furthermore, the drive monitoring unit includes: comparator A1 and comparator A2;

[0025] The non-inverting input of comparator A1 is connected between the first output and the gate of the first MOS transistor, the inverting input of comparator A1 is connected to a reference voltage setting circuit to obtain a first reference voltage, and the output of comparator A1 is connected to the gate of the PMOS transistor Q1.

[0026] The non-inverting input of comparator A2 is connected between the second output and the gate of the second MOS transistor, the inverting input of comparator A2 is connected to a reference voltage setting circuit to obtain a second reference voltage, and the output of comparator A2 is connected to the gate of the PMOS transistor Q3.

[0027] Through the above-described configuration, this invention can compare the driving voltage output by the driving circuit with the first reference voltage and the second reference voltage using comparators A1 and A2, thereby determining whether the driving voltage turns on the first MOSFET and the second MOSFET. Furthermore, comparators A1 and A2 can output different levels based on the comparison results of the driving voltage with the first and second reference voltages, which can be directly used to control the clamping circuit. This enables the process from driving voltage detection to determining that the first and second MOSFETs are off, and finally to active clamping by the clamping circuit.

[0028] Furthermore, the reference voltage setting circuit includes: resistors R3, R4, R7, R8, reference power supply U2, and reference power supply U4;

[0029] The positive terminal of the reference power supply U2 is connected to the resistor R3 and the resistor R4 in series and then grounded. The negative terminal of the reference power supply U2 is connected between the source of the first MOS transistor and the drain of the second MOS transistor. The inverting input terminal of the comparator A1 is connected between the resistor R3 and the resistor R4.

[0030] The positive terminal of the reference power supply U4 is connected to the resistors R7 and R8 in series and then grounded. The negative terminal of the reference power supply U4 is connected between the source of the second MOS transistor and ground. The inverting input terminal of the comparator A2 is connected between the resistors R7 and R8.

[0031] Through the above-described configuration, this invention can provide a first reference voltage and a second reference voltage for comparators A1 and A2, providing a reference voltage basis for determining the drive voltage. At the same time, the configuration of the reference voltage setting circuit can provide a certain control delay time for comparators A1 and A2, which can avoid the large current surge caused by the inconsistency between the timing of clamping the gate-source voltage of the MOSFET to 0V and the timing of the drive circuit issuing the drive voltage for turning off the first and second MOSFETs.

[0032] Furthermore, the crosstalk suppression circuit also includes an overvoltage protection circuit connected to the drive monitoring unit, the overvoltage protection circuit including: Schottky diode D2 and Zener diode D4;

[0033] The negative terminal of the Schottky diode D2 is connected between the first output terminal and the gate of the first MOS transistor, and the positive terminal of the Schottky diode D2 is connected to the non-inverting input terminal of the comparator A1.

[0034] The negative terminal of the Zener diode D4 is connected between the second output terminal and the gate of the second MOS transistor, and the positive terminal of the Zener diode D4 is connected to the non-inverting input terminal of the comparator A2.

[0035] Through the above-described configuration, this invention utilizes Schottky diode D2 to block the positive voltage output from the drive circuit to comparator A1, preventing PMOS transistor Q1 from turning on when the drive circuit outputs a positive voltage, ensuring that PMOS transistor Q1 is in the off state, and guaranteeing the normal control of the clamping circuit. In addition, through the configuration of Zener diode D4, this invention can limit the positive voltage output from the drive circuit to comparator A2, avoiding overvoltage damage to the non-inverting input terminal of comparator A2.

[0036] Furthermore, the crosstalk suppression circuit also includes a delay circuit, which includes: resistor R1, resistor R5, capacitor C1, and capacitor C3.

[0037] One end of the resistor R1 is connected to the positive terminal of the Schottky diode D2, and the other end of the resistor R1 is connected to the capacitor C1. The other end of the capacitor C1 is connected between the source of the first MOSFET and the drain of the second MOSFET. The non-inverting input terminal of the comparator A1 is connected between the resistor R1 and the capacitor C1.

[0038] One end of the resistor R5 is connected to the positive terminal of the Zener diode D4, and the other end of the resistor R4 is connected to the capacitor C3. The other end of the capacitor C3 is connected between the source of the second MOS transistor and ground. The non-inverting input terminal of the comparator A2 is connected between the resistor R5 and the capacitor C3.

[0039] The present invention uses the above-mentioned scheme to form RC delay circuits by resistor R1 and capacitor C1, and resistor R5 and capacitor C3, respectively, thereby avoiding the large current surge that occurs because the timing of clamping the gate-source voltage of the first MOSFET and the second MOSFET to 0V is inconsistent with the timing of the driving circuit issuing the driving voltage to turn off the first MOSFET and the second MOSFET.

[0040] Furthermore, the discharge circuit includes: resistors Rg1, R2, Rg2, R6, capacitors C2 and C4, PNP transistor Q2, and PNP transistor Q4.

[0041] The resistor Rg1 is connected in series between the first output terminal of the driving circuit and the gate of the first MOS transistor. The emitter of the PNP transistor Q2 is connected between the resistor Rg1 and the gate of the first MOS transistor. The base of the PNP transistor Q2 is connected between the resistor Rg1 and the first output terminal. The collector of the PNP transistor Q2 is connected to one end of the resistor R2. The other end of the resistor R2 is connected between the source of the first MOS transistor and the drain of the second MOS transistor. The capacitor C2 is connected in parallel across the resistor R2.

[0042] The resistor Rg2 is connected in series between the second output terminal of the driving circuit and the gate of the second MOS transistor. The emitter of the PNP transistor Q4 is connected between the resistor Rg2 and the gate of the second MOS transistor. The base of the PNP transistor Q4 is connected between the resistor Rg2 and the second output terminal. The collector of the PNP transistor Q4 is connected to one end of the resistor R6. The other end of the resistor R6 is connected between the source of the second MOS transistor and ground. The capacitor C4 is connected in parallel across the resistor R6.

[0043] Through the above-described scheme, this invention utilizes resistor Rg1, resistor R2, capacitor C2, and PNP transistor Q2 to form a low-impedance discharge branch, and simultaneously utilizes resistor Rg2, resistor R6, capacitor C4, and PNP transistor Q4 to form another low-impedance discharge circuit. This allows for the rapid extraction of transient positive currents at the gates of the first and second MOSFETs, achieving forward crosstalk suppression. The peak forward crosstalk voltage can be reduced from -8.02V in the traditional passive scheme to -3.08V, a reduction of 4.94V, completely avoiding the problem of MOSFET mis-conduction.

[0044] Furthermore, the driving circuit includes a first push-pull circuit and a second push-pull circuit. The first push-pull circuit is connected to a positive voltage, and the second push-pull circuit is connected to a negative voltage. The first push-pull circuit and the second push-pull circuit are controlled by the same driving input. The first push-pull circuit has a first output terminal connected to a first MOSFET, and the second push-pull circuit has a second output terminal connected to a second MOSFET.

[0045] The present invention utilizes the above-described scheme to drive the first MOSFET and the second MOSFET respectively using the first push-pull circuit and the second push-pull circuit. It can take advantage of the advantages of push-pull circuits, such as low conduction loss, high efficiency, and strong load capacity, to achieve reliable control of the first MOSFET and the second MOSFET.

[0046] The present invention also proposes an electrical device having the aforementioned crosstalk suppression circuit.

[0047] Furthermore, the aforementioned electrical equipment is an air conditioner.

[0048] Compared with the prior art, the present invention has at least the following beneficial effects:

[0049] 1. By setting up a clamping circuit, this invention can actively clamp the gate-source voltage of the first MOSFET and the second MOSFET to 0V when the first MOSFET and the second MOSFET are turned off, thereby achieving negative crosstalk suppression and completely eliminating the risk of negative voltage breakdown and false turn-on.

[0050] 2. By setting up a discharge circuit, this invention can quickly discharge the transient positive current at the gates of the first and second MOSFETs, thereby suppressing forward crosstalk and reducing the peak forward crosstalk voltage from -8.02V in the traditional passive solution to -3.08V, a reduction of 4.94V, thus completely avoiding the problem of MOSFET mis-conduction.

[0051] 3. The crosstalk suppression circuit provided by this invention has a simple circuit structure, which can reduce hardware costs, facilitate integration and maintenance, enhance the anti-interference capability of the system, and adapt to high-frequency and high-power application environments. Attached Figure Description

[0052] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0053] Figure 1 This is a schematic diagram of the basic framework of the crosstalk suppression circuit in this invention;

[0054] Figure 2 This is a schematic diagram illustrating the working process of the crosstalk suppression circuit in this invention;

[0055] Figure 3 This is a schematic diagram of the crosstalk suppression circuit in the first embodiment of the present invention;

[0056] Figure 4 This is a schematic diagram of the crosstalk suppression circuit in the second embodiment of the present invention;

[0057] Figure 5 This is a schematic diagram of the crosstalk suppression circuit in the third embodiment of the present invention;

[0058] Figure 6 This is a schematic diagram of the crosstalk suppression circuit in the fourth embodiment of the present invention;

[0059] Figure 7 This is a schematic diagram of the crosstalk suppression circuit in the fifth embodiment of the present invention;

[0060] Figure 8 This is a timing coordination table for the crosstalk suppression circuit in this invention when the driving circuit provides different driving voltages;

[0061] Figure 9 This is a schematic diagram showing the output and transfer characteristics of the PMOS transistor in the crosstalk suppression circuit of this invention when the P-channel enhancement mode is used;

[0062] Figure 10This is a schematic diagram showing the output and transfer characteristics of the PMOS transistor in the crosstalk suppression circuit of this invention when the P-channel depletion type is used. Detailed Implementation

[0063] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0064] Therefore, a feature pointed out in this specification is used to describe one feature of one embodiment of the invention, and does not imply that every embodiment of the invention must have the described feature. Furthermore, it should be noted that this specification describes many features. Although certain features may be combined to illustrate possible system designs, these features may also be used in other combinations not explicitly stated. Therefore, unless otherwise stated, the described combinations are not intended to be limiting.

[0065] The principles and structure of the present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0066] SiC MOSFETs, as core devices for high frequency and high power, are widely used in inverters, motor drives, photovoltaic inverters, and other equipment. Due to their fast switching speed and large parasitic inductance, they are prone to gate-source voltage crosstalk in bridge circuits, leading to false turn-on or breakdown, which seriously affects the stability and reliability of the system.

[0067] Existing passive drive solutions have the following problems in terms of crosstalk suppression:

[0068] 1. The suppression effect is limited, and precise voltage clamping cannot be achieved;

[0069] 2. Complex structure, many components, and high cost;

[0070] 3. Difficult to adapt to high-frequency, high-power application scenarios;

[0071] 4. It is susceptible to the influence of parasitic parameters and has poor anti-interference ability;

[0072] To address the aforementioned problems, this invention proposes a crosstalk suppression circuit that suppresses crosstalk from both positive and negative perspectives. The driving circuit in this invention can provide both positive and negative voltages. Positive crosstalk suppression occurs when the driving circuit provides a positive voltage, while negative crosstalk suppression occurs when the driving circuit provides a negative voltage. Based on this principle, the crosstalk suppression circuit proposed in this invention includes at least two MOSFETs connected in series to form a half-bridge circuit, and a driving circuit for driving the MOSFETs. The crosstalk suppression circuit includes at least a clamping circuit connected between the gate and source of the MOSFETs, and a driving monitoring unit connected to the output of the driving circuit.

[0073] The clamping circuit is configured to clamp the gate-source voltage of the MOSFET to 0V when it is in the ON state;

[0074] The drive monitoring unit is configured to provide a control level that enables the clamping circuit to turn on when the drive circuit provides a drive voltage that turns on the MOSFET.

[0075] This section describes the design of negative crosstalk suppression in this invention. Through the drive monitoring unit, it can accurately monitor the drive voltage of the MOSFET (SiC MOSFET) and determine whether the MOSFET is in a turn-off state due to the drive voltage. In conjunction with the clamping circuit, when the MOSFET is in a turn-off state, it actively clamps the gate-source voltage of the MOSFET to 0V, realizing active voltage clamping. This fundamentally avoids the response delay and false triggering problems of traditional passive clamping.

[0076] Furthermore, the crosstalk suppression circuit proposed in this invention also includes a discharge circuit connected between the driving circuit and the gate of the MOS transistor, the discharge circuit being used to discharge the transient positive current at the gate of the MOS transistor.

[0077] This section describes the design of forward crosstalk suppression in this invention. It can quickly discharge the transient positive current at the gate of the MOSFET through a discharge circuit, thereby achieving forward crosstalk suppression. It can reduce the peak forward crosstalk voltage from -8.02V in the traditional passive solution to -3.08V, a reduction of 4.94V, and completely avoid the problem of MOSFET mis-turn-on.

[0078] Please see Figure 3 In the first embodiment of the present invention, the MOS transistor includes a first MOS transistor located on the high voltage side and a second MOS transistor located on the low voltage side;

[0079] The driving circuit has a first output terminal and a second output terminal, and the first output terminal and the second output terminal are used to provide driving voltages with opposite levels. The first output terminal is connected to the gate of the first MOSFET, and the second output terminal is connected to the gate of the second MOSFET.

[0080] Here, the first MOSFET is also known as MOSFET T1, and the second MOSFET is also known as MOSFET T2. Both the first and second MOSFETs are SiC MOSFETs. The first and second MOSFETs are connected in series to form a half-bridge circuit. Since SiC MOSFETs have fast switching speed and large parasitic inductance, they are prone to gate-source voltage crosstalk. The above-mentioned design schemes for positive crosstalk suppression and negative crosstalk suppression in this invention are used to avoid this gate-source voltage crosstalk, which could lead to the first and second MOSFETs being mis-turned on.

[0081] Here, the drain of the first MOSFET is connected to the power supply VCC as the high-voltage side, and the source of the second MOSFET is grounded as the low-voltage side. The drive circuit is used to control the conduction state of the first and second MOSFETs respectively. Specifically, the drive current is composed of two push-pull circuits. The upper end of the first push-pull circuit is connected to a 15V positive voltage, and the end connected to the first MOSFET is the first output terminal. The lower end of the second push-pull circuit is connected to a -5V negative voltage, and the end connected to the second MOSFET is the second output terminal. The two push-pull circuits are controlled by the same drive input.

[0082] When the drive input is high, the upper push-pull circuit outputs a 15V positive voltage as the drive voltage, and the lower push-pull circuit outputs a -5V negative voltage as the drive voltage.

[0083] When the drive input is low, the upper push-pull circuit outputs a -5V negative voltage as the drive voltage, and the lower push-pull circuit outputs a 15V positive voltage as the drive voltage.

[0084] The first MOSFET and the second MOSFET are turned off when the gate receives a negative voltage and turned on when the gate receives a positive voltage, thereby controlling the conduction state of the first MOSFET and the second MOSFET through the above-mentioned driving circuit.

[0085] The present invention, through the above-described scheme, can form a half-bridge circuit with the first MOSFET and the second MOSFET, thereby achieving a series of advantages such as smooth current output, efficient energy conversion, and reduced power loss. At the same time, by driving the first MOSFET and the second MOSFET through a drive circuit with a push-pull circuit, it has the advantages of low conduction loss, high efficiency, and strong load capacity.

[0086] In other embodiments of the present invention, optocouplers or magnetic coupling transformers can also be used to obtain the above-mentioned driving voltage, which can have better electrical isolation and strong anti-common-mode interference capability, but will increase transmission delay and device cost, and lose the ability to directly monitor the amplitude of the driving voltage.

[0087] Please see Figure 3In the first embodiment of the present invention, the clamping circuit includes: Schottky diode D1, Schottky diode D3, PMOS transistor Q1, and PMOS transistor Q3;

[0088] The negative terminal of Schottky diode D1 is connected between the first output terminal and the gate of the first MOS transistor, the positive terminal of Schottky diode D1 is connected to the drain of PMOS transistor Q1, the source of PMOS transistor Q1 is connected between the source of the first MOS transistor and the drain of the second MOS transistor, and the gate of PMOS transistor Q1 is connected to the drive monitoring unit.

[0089] The negative terminal of Schottky diode D3 is connected between the second output terminal and the gate of the second MOS transistor, the positive terminal of Schottky diode D3 is connected to the drain of PMOS transistor Q3, the source of PMOS transistor Q3 is connected between the source of the second MOS transistor and ground, and the gate of PMOS transistor Q3 is connected to the drive monitoring unit.

[0090] Here, the clamping circuit actually consists of two parts. One part is composed of Schottky diode D1 and PMOS transistor Q1, which is used to clamp the gate-source voltage of the first MOS transistor. The other part is composed of Schottky diode D3 and PMOS transistor Q3, which is used to clamp the gate-source voltage of the second MOS transistor. The working principle of the two clamping circuits is the same. Taking Schottky diode D1 and PMOS transistor Q1 as an example, when PMOS transistor Q1 is turned on, it can connect the gate and source of the first MOS transistor, thereby clamping the gate-source voltage to 0V.

[0091] In other words, this invention, through this part of the solution, can achieve conduction control of the clamping circuit by turning on PMOS transistors Q1 and Q3 when the first and second MOS transistors are in the off state. Furthermore, when PMOS transistors Q1 and Q3 are turned on, the gates and sources of the first and second MOS transistors are connected, clamping the gate-source voltage to 0V, thereby avoiding the problem of false turn-on of the first and second MOS transistors. In addition, the gates of both PMOS transistors Q1 and Q3 are connected to the drive monitoring unit, enabling active control of the clamping circuit through the drive monitoring unit. Since the drive monitoring unit can detect whether the drive voltage is used to turn on the first and second MOS transistors, this invention can determine whether the first and second MOS transistors are in the off state and achieve active clamping when they are in the off state, thus fundamentally avoiding the response delay and false triggering problems of traditional passive clamping.

[0092] The above-mentioned clamping circuit design is only a preferred embodiment of the present invention. In other embodiments of the present invention, a bidirectional silicon controlled rectifier (SCR) or a bipolar transistor (BJT) push-pull structure can be used to replace the original PMOS transistors Q1 and Q3.

[0093] Bidirectional thyristors have stronger tolerance to high currents, but are difficult to turn off. Bipolar transistors are cheaper, but have a saturation voltage drop and a slightly slower switching speed, and their high-frequency performance is reduced. The specific choice can be made based on the actual situation of the design.

[0094] Please see Figure 4 The second embodiment of the present invention provides an implementation of a drive monitoring unit, which specifically includes: comparator A1 and comparator A2;

[0095] The non-inverting input of comparator A1 is connected between the first output and the gate of the first MOS transistor, the inverting input of comparator A1 is connected to the reference voltage setting circuit to obtain the first reference voltage, and the output of comparator A1 is connected to the gate of PMOS transistor Q1.

[0096] The non-inverting input of comparator A2 is connected between the second output and the gate of the second MOS transistor. The inverting input of comparator A2 is connected to the reference voltage setting circuit to obtain the second reference voltage. The output of comparator A2 is connected to the gate of PMOS transistor Q3.

[0097] Similarly, the drive monitoring unit here is also divided into two parts. Comparator A1 constitutes one part of the drive monitoring unit and is used to control PMOS transistor Q1. Comparator A2 constitutes the other part of the drive monitoring unit and is used to control PMOS transistor Q3. The working principle of the two parts is the same. The working principle of the drive monitoring unit is explained below using comparator A1:

[0098] When the drive circuit outputs a negative voltage, this voltage can be output to the non-inverting input of comparator A1. At this time, the comparator A1 outputs a negative voltage, which can turn on the PMOS transistor Q1, thereby activating the clamping circuit and realizing negative crosstalk suppression.

[0099] To satisfy the above-mentioned control of PMOS transistors Q1 and Q3, PMOS transistors can be selected as P-channel enhancement-type transistors, so that PMOS transistors Q1 and Q3 are not conducting at 0V and conduct at negative voltage. This allows, in other embodiments of the invention, PMOS transistors Q1 and Q3 to be adjusted to P-channel depletion-type transistors according to actual needs. Figure 9 and Figure 10 The diagrams show the output and transfer characteristics of a PMOS transistor in P-channel enhancement mode and P-channel depletion mode, respectively.

[0100] Through the above-described configuration, this invention can compare the driving voltage output by the driving circuit with the first reference voltage and the second reference voltage using comparators A1 and A2, thereby determining whether the driving voltage turns on the first MOSFET and the second MOSFET. Furthermore, comparators A1 and A2 can output different levels based on the comparison results of the driving voltage with the first and second reference voltages, which can be directly used to control the clamping circuit. This enables the process from driving voltage detection to determining that the first and second MOSFETs are off, and finally to active clamping by the clamping circuit.

[0101] The aforementioned drive monitoring unit is only a preferred embodiment of the present invention. In other embodiments of the present invention, a microcontroller (MCU) combined with an analog-to-digital converter (ADC) or a dedicated drive monitoring chip can be used to replace the design scheme of comparator A1 and comparator A2. Compared with the design scheme of comparator A1 and comparator A2, this scheme is more flexible and the threshold (i.e., reference voltage) can be dynamically adjusted by software. However, the response speed of the microcontroller may exceed 10ns, which cannot achieve the extreme high speed of the design scheme of comparator A1 and comparator A2. On the other hand, the use of a dedicated drive monitoring chip has the problem of slightly higher cost. The specific implementation scheme can be selected according to the actual situation.

[0102] Furthermore, in this second embodiment, the reference voltage setting circuit specifically includes: resistor R3, resistor R4, resistor R7, resistor R8, reference power supply U2, and reference power supply U4;

[0103] The positive terminal of the reference power supply U2 is connected to ground after being connected in series with resistors R3 and R4. The negative terminal of the reference power supply U2 is connected between the source of the first MOSFET and the drain of the second MOSFET. The inverting input terminal of comparator A1 is connected between resistors R3 and R4.

[0104] The positive terminal of the reference power supply U4 is connected to ground via resistors R7 and R8 in series. The negative terminal of the reference power supply U4 is connected between the source of the second MOSFET and ground. The inverting input of comparator A2 is connected between resistors R7 and R8.

[0105] The reference voltage setting circuit here is also divided into two parts. Resistors R3, R4 and reference power supply U2 constitute one part of the reference voltage setting circuit, which is used to provide the reference voltage to the inverting input terminal of comparator A1. Resistors R7, R8 and reference power supply U4 constitute the other part of comparator A2, which is used to provide the reference voltage to the inverting input terminal of comparator A2. The two parts of the reference voltage setting circuit are consistent in principle. The following explanation will focus on resistors R3, R4 and reference power supply U2.

[0106] The reference power supply U2 provides voltage U2, which is divided by resistors R3 and R4. Since the inverting input of comparator A1 is connected between resistors R3 and R4, the reference voltage it provides is actually the voltage divided across resistor R4, and its magnitude is U2*R4 / (R3+R4), which serves as the first reference voltage.

[0107] Similarly, resistors R7 and R8 and the reference power supply U4 can provide a reference voltage of size U4*R8 / (R7+R8) to the inverting input of comparator A2, which serves as the second reference voltage.

[0108] In other words, through this part of the design, the present invention can provide a first reference voltage and a second reference voltage for comparators A1 and A2, providing a reference voltage basis for determining the drive voltage. At the same time, the setting of the reference voltage setting circuit can provide a certain control delay time for comparators A1 and A2, which can avoid the large current surge caused by the inconsistency between the time when the gate-source voltage of the MOS transistor is clamped to 0V and the time when the drive circuit issues the drive voltage for turning off the first MOS transistor and the second MOS transistor.

[0109] Please see Figure 5 In the third embodiment of the present invention, the crosstalk suppression circuit further includes an overvoltage protection circuit connected to the drive monitoring unit, the overvoltage protection circuit including: Schottky diode D2 and Zener diode D4;

[0110] The cathode of Schottky diode D2 is connected between the first output terminal and the gate of the first MOSFET, and the anode of Schottky diode D2 is connected to the non-inverting input terminal of comparator A1.

[0111] The negative terminal of Zener diode D4 is connected between the second output terminal and the gate of the second MOSFET, and the positive terminal of Zener diode D4 is connected to the non-inverting input terminal of comparator A2.

[0112] Here, the overvoltage protection circuit is also divided into two parts. The Schottky diode D2 constitutes one part of the overvoltage protection circuit. It can use the Schottky diode D2 to block the positive voltage output by the drive circuit to the comparator A1, prevent the PMOS transistor Q1 from turning on when the drive circuit outputs a positive voltage, ensure that the PMOS transistor Q1 is in the off state, and ensure the normal control of the clamping circuit.

[0113] Zener diode D4 forms another part of the overvoltage protection circuit, which can limit the positive voltage output by the drive circuit to comparator A2, and prevent overvoltage damage to the non-inverting input of comparator A2.

[0114] The main differences between Zener diodes and Schottky diodes lie in their structure, voltage tolerance, current leakage characteristics, speed and response time, as well as price and availability. Zener diodes have high reverse voltage tolerance, typically between tens and hundreds of volts, while Schottky diodes have lower reverse voltage tolerance, generally between a few and tens of volts. Zener diodes have extremely low reverse current leakage, almost negligible, while Schottky diodes have relatively high reverse current leakage. Zener diodes have larger junction capacitance and more complex structures, and their switching speed and response time are generally slower than those of Schottky diodes. Each has its advantages and disadvantages, and the choice can be made based on the actual situation.

[0115] Please see Figure 6 In the fourth embodiment of the present invention, the crosstalk suppression circuit further includes a delay circuit, which includes: resistor R1, resistor R5, capacitor C1, and capacitor C3.

[0116] One end of resistor R1 is connected to the positive terminal of Schottky diode D2, and the other end of resistor R1 is connected to capacitor C1. The other end of capacitor C1 is connected between the source of the first MOSFET and the drain of the second MOSFET. The non-inverting input of comparator A1 is connected between resistor R1 and capacitor C1.

[0117] One end of resistor R5 is connected to the positive terminal of Zener diode D4, and the other end of resistor R4 is connected to capacitor C3. The other end of capacitor C3 is connected between the source of the second MOSFET and ground. The non-inverting input of comparator A2 is connected between resistor R5 and capacitor C3.

[0118] Here, the delay circuit also consists of two parts. Resistor R1 and capacitor C1 constitute one part of the delay circuit, and resistor R5 and capacitor C3 constitute the other part. The two parts work on the same principle to avoid the large current surge that occurs because the timing of clamping the gate-source voltage of the first MOSFET and the second MOSFET to 0V is inconsistent with the timing of the drive circuit issuing the drive voltage to turn off the first MOSFET and the second MOSFET.

[0119] Please see Figure 7 In the fifth embodiment of the present invention, the crosstalk suppression circuit further includes a discharge circuit, which is used to achieve positive crosstalk suppression, specifically including: resistor Rg1, resistor R2, resistor Rg2, resistor R6, capacitor C2, capacitor C4, PNP transistor Q2, and PNP transistor Q4.

[0120] Resistor Rg1 is connected in series between the first output terminal of the drive circuit and the gate of the first MOS transistor. The emitter of PNP transistor Q2 is connected between resistor Rg1 and the gate of the first MOS transistor. The base of PNP transistor Q2 is connected between resistor Rg1 and the first output terminal. The collector of PNP transistor Q2 is connected to one end of resistor R2. The other end of resistor R2 is connected between the source of the first MOS transistor and the drain of the second MOS transistor. Capacitor C2 is connected in parallel across resistor R2.

[0121] Resistor Rg2 is connected in series between the second output terminal of the drive circuit and the gate of the second MOSFET. The emitter of PNP transistor Q4 is connected between resistor Rg2 and the gate of the second MOSFET. The base of PNP transistor Q4 is connected between resistor Rg2 and the second output terminal. The collector of PNP transistor Q4 is connected to one end of resistor R6. The other end of resistor R6 is connected between the source of the second MOSFET and ground. Capacitor C4 is connected in parallel across resistor R6.

[0122] The discharge circuit is also divided into two parts. One part consists of resistor Rg1, resistor R2, capacitor C2, and PNP transistor Q2 forming a low-impedance discharge branch. The other part consists of resistor Rg2, resistor R6, capacitor C4, and PNP transistor Q4 forming a low-impedance discharge circuit. This circuit can quickly discharge the transient positive current at the gates of the first and second MOSFETs, thereby suppressing forward crosstalk. It can reduce the peak forward crosstalk voltage from -8.02V in the traditional passive solution to -3.08V, a reduction of 4.94V, and completely avoid the problem of MOSFET mis-conduction.

[0123] The above is a design scheme in a preferred embodiment of the present invention. In other embodiments of the present invention, a transient voltage suppressor diode (TVS) can be connected in parallel between the gate and source of the first MOSFET and the second MOSFET to replace the original discharge circuit. Compared with the above discharge circuit design, the circuit structure is simpler. However, the transient voltage suppressor diode (TVS) has leakage current and the clamping voltage cannot be accurate to 0V. The reliability may be degraded after multiple impacts.

[0124] Figure 1 The above is a basic schematic diagram of the crosstalk suppression circuit. It provides a drive input to the push-pull circuit, thereby outputting different drive voltages. This drive voltage is then supplied to the SiC MOSFET through the gate resistors (i.e., resistors Rg1 and Rg2) to control the conduction state of the SiC MOSFET. A clamping circuit is connected in the power supply path of the drive voltage to the SiC MOSFET. This clamping circuit is controlled by the drive monitoring unit to achieve active voltage clamping. At the same time, it is combined with software control to achieve delay control.

[0125] Figure 2The corresponding workflow (described in the section below the crosstalk suppression circuit) is as follows: the drive circuit first outputs the corresponding drive voltage Vcomp, and then obtains the drive voltage Vcomp through the drive monitoring unit. The drive monitoring unit compares the drive voltage Vcomp with the reference voltage. If it is lower than the reference voltage, it means that the drive voltage Vcomp is used to turn off the second MOSFET. At this time, the PMOS transistor Q3 is triggered to turn on, clamping the gate-source voltage of the second MOSFET to 0V. At the same time, the circuit operation status data is recorded, the delay time of the delay circuit is dynamically adjusted, the closed-loop control algorithm is executed, and the circuit status is checked for abnormality. If it is, the protection is activated; otherwise, the closed-loop control is started.

[0126] Taking the second MOSFET as an example, the specific implementation of the crosstalk suppression circuit in this invention includes:

[0127] 1. Clamping circuit settings;

[0128] When the SiC MOSFET (the second MOSFET, also known as MOSFET T2) is off, a clamping circuit consisting of PMOS transistor Q3 and Schottky diode D3 clamps the gate-source voltage to 0V. This clamping circuit is connected between the gate and source of the second MOSFET to ensure that the gate-source voltage remains stable when the second MOSFET is off.

[0129] 2. Control logic design;

[0130] The gate of PMOS transistor Q3 is connected to the output of the drive circuit through comparator A2;

[0131] When the drive circuit outputs the drive voltage to turn off the second MOSFET, the drive circuit outputs a negative voltage. This negative voltage passes through the Zener diode D4 and the RC delay circuit (composed of resistor R5 and capacitor C3) and is then input to the non-inverting input of comparator A2.

[0132] At this time, the voltage at the non-inverting input of comparator A2 is lower than the reference voltage at its inverting input, and comparator A2 outputs a negative voltage, which turns on PMOS transistor Q3 and activates the clamping circuit.

[0133] The clamping circuit (composed of MOSFET Q3 and Schottky diode D3) clamps the gate-source voltage of the second MOSFET to 0V.

[0134] 3. Software control logic

[0135] The software module runs in the embedded controller and is responsible for receiving the output signal of the voltage comparator and determining whether the conduction time of PMOS transistor Q3 needs to be adjusted according to the preset algorithm.

[0136] The software module communicates with the main control chip via the SPI / I2C interface and dynamically adjusts the conduction time of PMOS transistor Q3 to adapt to different load conditions and working environment changes.

[0137] The software module uses PID control algorithm or fuzzy control algorithm to perform closed-loop regulation of the gate-source voltage of the second MOSFET, thereby improving the system response speed and stability.

[0138] When abnormal voltage fluctuations or temperature increases are detected, the software can trigger protection mechanisms, such as quickly shutting down PMOS transistor Q3 or issuing an alarm signal, to enhance system safety.

[0139] The software can also record operating status data (such as voltage, current, temperature, etc.) and supports remote monitoring and debugging.

[0140] 3. Prevent false triggering and current surges

[0141] Since the timing of clamping the gate-source voltage of the SiC MOSFET to zero is inconsistent with the timing of the drive circuit outputting the drive voltage to turn off the SiC MOSFET, an RC delay circuit (composed of resistor R5 and capacitor C3) is connected to the gate of PMOS transistor Q3 to avoid large current surges.

[0142] Comparator A2 itself has a certain delay characteristic, and the delay time can be controlled by adjusting the reference voltage at its inverting input terminal;

[0143] To prevent the PMOS transistor Q1 from turning on when the drive circuit outputs a positive voltage, a Schottky diode D2 is connected in series in the circuit to block the forward voltage and ensure that the PMOS transistor Q1 is in the off state.

[0144] 5. Voltage protection measures

[0145] To prevent overvoltage damage to the input of comparator A2, a Zener diode D4 is added to its non-inverting input to limit the forward voltage;

[0146] An RC circuit (consisting of resistor R5 and capacitor C3) is used to achieve circuit delay and improve system stability.

[0147] 6. Enable signal processing

[0148] When the driving voltage is used to turn on the second MOSFET, the driving circuit outputs a positive voltage to the non-inverting input of comparator A2. At this time, the voltage at the non-inverting input of comparator A2 is higher than that at the inverting input, and the output is 0V.

[0149] At this time, PMOS transistor Q3 gradually turns off, and the second MOS transistor begins to conduct.

[0150] Appendix Figure 8The timing table for providing different drive voltages to the drive circuit (still using the second MOSFET as an example) shows that when the second MOSFET is in standby or off, the drive input signal is logic 0. At this time, the drive circuit outputs a negative voltage of -5V, the input of comparator A2 is low (i.e., negative voltage), and the output of comparator A2 is low (i.e., negative voltage). At this time, PMOS transistor Q3 is turned on, activating the clamping circuit and clamping the gate-source voltage of the second MOSFET to 0V. At this time, the gate voltage of the second MOSFET is stable at 0V.

[0151] At the moment the second MOSFET is turned on, the drive input signal changes from logic 0 to logic 1, and the output of the drive circuit starts to change from -5V negative voltage to +15V positive voltage. The input of comparator A2 is at the rising edge, and the output of comparator A2 becomes high level after a delay, causing PMOS transistor Q3 to be turned off, the clamping circuit is released, and the gate voltage of the second MOSFET rises to 15V positive voltage following the drive voltage.

[0152] When the second MOSFET is turned on, the drive input signal is logic 1, the drive circuit outputs a positive voltage of +15V, the input of comparator A2 is high, the output of comparator A2 is high, the PMOS transistor Q3 is turned off, the clamping circuit is disconnected, the gate voltage of the second MOSFET is a positive voltage of +15V, and it works normally.

[0153] At the instant the second MOSFET is turned off, the drive input signal changes from logic 1 to logic 0, and the output of the drive circuit starts to change from +15 positive voltage to -5V negative voltage. The input of comparator A2 is at the falling edge, and the output of comparator A2 becomes low level (i.e. negative voltage) after a delay. PMOS transistor Q3 is turned on, which activates the clamping circuit and quickly pulls the gate-source voltage of the second MOSFET back to 0V.

[0154] Based on the above-described solution, the present invention has at least the following beneficial effects:

[0155] 1. By setting up a clamping circuit, this invention can actively clamp the gate-source voltage of the first MOSFET and the second MOSFET to 0V when the first MOSFET and the second MOSFET are turned off, thereby achieving negative crosstalk suppression and completely eliminating the risk of negative voltage breakdown and false turn-on.

[0156] 2. By setting up a discharge circuit, this invention can quickly discharge the transient positive current at the gates of the first and second MOSFETs, thereby suppressing forward crosstalk and reducing the peak forward crosstalk voltage from -8.02V in the traditional passive solution to -3.08V, a reduction of 4.94V, thus completely avoiding the problem of MOSFET mis-conduction.

[0157] 3. The crosstalk suppression circuit provided by this invention has a simple circuit structure, which can reduce hardware costs, facilitate integration and maintenance, enhance the anti-interference capability of the system, and adapt to high-frequency and high-power application environments.

[0158] The present invention also proposes an electrical device having the above-mentioned crosstalk suppression circuit, which can be an air conditioner.

[0159] Based on the above settings, this invention is applicable to the core electronics industry within strategic emerging technology industries. Compared with existing technologies, this invention has the following design advantages:

[0160] Prior art document 1 (CN112350702A) discloses an output stage circuit for a high-side power switch. Its core lies in using an output negative voltage clamping module (including a first PMOS transistor MP1, multiple Zener diodes D17–D19, and a fourth depletion-type NMOS transistor MND4) to clamp the negative voltage generated when an inductive load is turned off. This negative voltage triggers the PMOS transistor to turn on, thereby restarting the high-side power transistor MN0, forming a freewheeling path to achieve rapid demagnetization of the inductive load. This solution limits the negative voltage amplitude through a diode series structure and, combined with a gate protection module and a current limiting module, achieves protection of the power transistor's gate oxide layer and overcurrent limitation, effectively improving the reliability of the intelligent power switch under harsh load environments.

[0161] However, the shortcomings of existing technical document 1 are as follows:

[0162] Its clamping mechanism relies on the absolute value of the negative voltage at the load end to trigger, that is, the PMOS transistor MP1 will only turn on when the output voltage VOUT drops below VBB–BV17–BV18–BV19. Its response speed is limited by the breakdown delay of the diode and the rising slope of the inductor current, and it cannot achieve real-time, active and fast clamping of the gate-source voltage.

[0163] Its control logic is passive feedback, which relies entirely on the physical changes of the load voltage. It lacks the ability to sense and coordinate the control of the drive signal status (such as turn-on / turn-off commands). In high-frequency switching or transient interference scenarios, it is prone to response lag or false triggering. It does not involve the voltage status judgment of the drive power supply. When the drive power supply is turned off at a negative voltage (such as -5V), it cannot actively clamp the gate-source voltage to 0V. It cannot effectively suppress the positive gate crosstalk of the lower transistor caused by the rapid turn-on of the upper transistor in the bridge circuit.

[0164] The circuit structure is complex, relying on multiple high-voltage Zener diodes and depletion-type MOSFETs, resulting in a large layout area, high cost, and unsuitability for driving scenarios of high-frequency, low-gate-charge devices represented by SiC MOSFETs.

[0165] Based on the above-described settings, this invention differs from technical document 1 in the following ways:

[0166] This invention adopts a "comparator + PMOS active clamping" structure, which does not rely on the negative voltage trigger of the load voltage. Instead, it monitors the gate-source voltage of the SiC MOSFET in real time through the comparator, and actively controls the PMOS transistor to turn on when the driving circuit switches from positive voltage to negative voltage (or when crosstalk spikes occur), clamping the gate-source voltage to 0V, thus achieving feedforward, active, and low-delay voltage clamping.

[0167] This invention uses the drive circuit state (+15V / -5V) as the control signal source, and achieves synchronization with the drive timing through a delay circuit and a Zener diode. When the drive circuit outputs a negative voltage, the clamp is automatically activated; when the drive circuit outputs a positive voltage, the clamp is automatically deactivated, achieving seamless coordination with the drive logic and fundamentally avoiding the response delay and false triggering problems of traditional passive clamping.

[0168] This invention addresses the characteristics of SiC MOSFETs (extremely fast switching speed, low gate charge, and susceptibility to crosstalk-induced turn-on) by designing a dual-channel suppression structure with both positive and negative channels.

[0169] Forward crosstalk: rapidly discharged by resistor + transistor + capacitor;

[0170] Negative crosstalk: 0V clamping is achieved by a comparator + PMOS transistor + Schottky diode;

[0171] This enables comprehensive suppression of interference between the upper and lower transistors in a bridge circuit.

[0172] This invention is constructed using discrete components, eliminating the need for high-voltage Zener diode arrays or depletion-type MOSFETs. It features a simple structure, low cost, and easy integration, making it particularly suitable for high-density, high-power-density applications such as new energy vehicle electronic control, photovoltaic inverters, and industrial motor drives.

[0173] Based on this difference, the technical effects actually achieved by the present invention include at least the following:

[0174] The gate-source voltage remains stably at 0V when the SiC MOSFET is off, completely eliminating the risk of false turn-on due to negative voltage drift or crosstalk.

[0175] With a response time of less than 10ns, it is much faster than the passive response that relies on diode breakdown in Technical Document 1 (typically >50ns), and is suitable for high-frequency switching systems above 100kHz.

[0176] Without the need to add a drive power supply or complex isolation circuits, the traditional +15V / -5V drive circuit can be directly reused as the control source, reducing system cost by more than 30% and achieving higher integration.

[0177] It supports modular expansion and can be deployed in parallel on multi-channel half-bridge / full-bridge topologies, making it suitable for multi-phase motor drives and high-power inverter systems.

[0178] Prior art document 2 (CN207234647U) discloses a high-speed voltage comparator and its integrated control chip for AC-DC switching power supplies. Its core innovation lies in clamping the internal node voltages of the comparator using a voltage clamping circuit (composed of a first NMOS and a second NMOS), limiting the swing of the first node voltage (vo1) and the second node voltage (vo2) to no more than half of the power supply voltage. This shortens the comparator's response time from the input differential signal to the output switching (measured delay reduced from 53.5ns to 25ns). This solution is applied to a PWM control chip, detecting the inductor current through a sampling resistor and quickly turning off the power transistor when the current reaches a threshold, thus achieving overcurrent protection and constant peak current control. It is suitable for BUCK-type AC-DC power supply systems.

[0179] However, the shortcomings of prior art document 2 are:

[0180] The "clamping" of its voltage comparator is the amplitude limitation of the internal node voltage, which is only used to accelerate the comparator's own response. It does not involve external active control of the gate-source voltage of power devices (such as MOSFETs), and it cannot suppress the gate crosstalk voltage caused by the interaction of the upper and lower transistors in the bridge topology.

[0181] Its application scenario is a single-transistor switching power supply, which only handles the peak control of inductor current. It does not meet the scenario requirements of mutual interference between high-side and low-side devices in half-bridge / full-bridge topologies, and cannot solve the problem of positive mis-conduction or negative voltage breakdown of SiC MOSFETs caused by dv / dt coupling in high-frequency bridge circuits.

[0182] Its control logic is open-loop response type, and it only outputs a turn-off signal based on the comparison result between the sampled voltage and the reference voltage. It does not have the ability to sense and coordinate the driving power supply status (such as 15V / –5V), and cannot achieve intelligent timing control of "clamping to 0V when turning off and automatically releasing when turning on".

[0183] Its circuit structure is an optimized analog circuit within a single chip, relying on complex structures such as high-precision PMOS / NMOS mirror current sources and multi-stage inverters. It is not suitable for discrete, low-cost, modular drive systems, and its "voltage clamping" function is limited to the comparator and cannot be externally connected to the gate of power devices to form a physical clamping path.

[0184] Without considering the negative voltage turn-off scenario, its design assumes that the power transistor gate drive is always positive voltage (such as 0V–12V), which is completely unsuitable for the current mainstream SiC MOSFETs that use a negative voltage drive architecture of -5V turn-off and +15V turn-on, and cannot achieve the key protection mechanism of "0V safety clamp".

[0185] Based on the above-described settings, this invention differs from technical document 2 in the following ways:

[0186] The "comparator" of this invention is not used for current sampling or overcurrent protection, but as an intelligent control unit of the external drive system. Its input signal comes from the drive voltage of the SiC MOSFET, and its output directly drives the PMOS transistor to achieve active clamping of the external gate-source voltage of the power device. It belongs to the system-level protection architecture, rather than single-module response acceleration.

[0187] The present invention features a dual-channel suppression structure with both positive and negative directions:

[0188] Forward crosstalk: rapidly discharged by resistor + transistor + capacitor;

[0189] Negative crosstalk: 0V clamping is achieved by a comparator + PMOS transistor + Schottky diode;

[0190] This invention creatively uses the driving voltage (+15V / –5V) as the control signal source, and "translates" the driving voltage state into the input logic of the comparator through a Zener diode and a delay circuit, so as to achieve precise synchronization between the driving timing and the clamping action. No additional control signal or isolation power supply is required, realizing a minimalist architecture of "controlling the clamp with the drive".

[0191] The clamping circuit of the present invention is physically external (the clamping circuit is connected between the gate and source of the SiC MOSFET), which directly acts on the power device to form a low-impedance discharge path. The response speed can reach <10ns, which is far superior to the 25ns response limited to internal node voltage scaling in technical document 2.

[0192] This invention is aimed at SiC MOSFET high-frequency bridge systems and solves the system-level reliability problem of cross-talk, while technical document 2 solves the problem of single-tube current control accuracy. The two have completely different application scenarios, technical objectives and protection objects.

[0193] Based on this difference, the technical effects actually achieved by the present invention include at least the following:

[0194] The peak forward crosstalk voltage is reduced from -8.02V in the traditional passive solution to -3.08V, a reduction of 4.94V, completely avoiding false turn-on of SiC MOSFETs;

[0195] At the instant the drive voltage switches to negative voltage, the gate-source voltage is clamped to 0V, achieving the industrial-grade safety standard of "turning off and returning to zero".

[0196] With a response time of less than 10ns, it can match the switching frequency of SiC MOSFETs from 100kHz to 1MHz, far exceeding the 25ns response capability of the internal comparator in technical document 2.

[0197] No additional isolation power supply, DC-DC converter, or dedicated IC is required. Existing +15V / –5V drive circuits can be fully reused, reducing hardware costs by more than 40% and circuit area by 60%. It is suitable for high-density, high-reliability scenarios such as new energy vehicle electronic control, photovoltaic inverters, and industrial servo systems.

[0198] It should be noted that the terminology used above is for describing specific embodiments only and is not intended to limit the exemplary embodiments of the present invention. When the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof. The order of execution of actions, steps, etc., in the apparatus and methods described in the specification and drawings can be implemented in any order unless a specific order is expressly specified, and as long as the output of the preceding process is not used in the subsequent process. Similar sequential terms used for ease of description do not imply that such an order must be followed.

[0199] Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as constraints. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters in the following figures denote similar items; therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0200] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A crosstalk suppression circuit, comprising at least two MOSFETs connected in series to form a half-bridge circuit, and a driving circuit for driving the MOSFETs to operate, characterized in that, The crosstalk suppression circuit includes at least a clamping circuit connected between the gate and source of the MOS transistor, and a drive monitoring unit connected to the output of the drive circuit. The clamping circuit is configured to clamp the gate-source voltage of the MOSFET to 0V when it is in the ON state; The drive monitoring unit is configured to provide a control level that enables the clamping circuit to conduct when the drive circuit provides a drive voltage that enables the MOS transistor to conduct.

2. The crosstalk suppression circuit according to claim 1, characterized in that, The crosstalk suppression circuit further includes a discharge circuit connected between the driving circuit and the gate of the MOS transistor, the discharge circuit being used to discharge transient positive current at the gate of the MOS transistor.

3. The crosstalk suppression circuit according to claim 1, characterized in that, The MOSFET includes a first MOSFET located on the high-voltage side and a second MOSFET located on the low-voltage side; The driving circuit has a first output terminal and a second output terminal, and the first output terminal and the second output terminal are used to provide driving voltages with opposite levels. The first output terminal is connected to the gate of the first MOS transistor, and the second output terminal is connected to the gate of the second MOS transistor.

4. The crosstalk suppression circuit according to claim 3, characterized in that, The clamping circuit includes: Schottky diode D1, Schottky diode D3, PMOS transistor Q1, and PMOS transistor Q3; The drain of the first MOSFET is connected to the power supply, the source of the first MOSFET is connected to the drain of the second MOSFET, and the source of the second MOSFET is grounded. The negative terminal of the Schottky diode D1 is connected between the first output terminal and the gate of the first MOS transistor, the positive terminal of the Schottky diode D1 is connected to the drain of the PMOS transistor Q1, the source of the PMOS transistor Q1 is connected between the source of the first MOS transistor and the drain of the second MOS transistor, and the gate of the PMOS transistor Q1 is connected to the drive monitoring unit. The negative terminal of the Schottky diode D3 is connected between the second output terminal and the gate of the second MOS transistor, the positive terminal of the Schottky diode D3 is connected to the drain of the PMOS transistor Q3, the source of the PMOS transistor Q3 is connected between the source of the second MOS transistor and ground, and the gate of the PMOS transistor Q3 is connected to the drive monitoring unit.

5. The crosstalk suppression circuit according to claim 4, characterized in that, The drive monitoring unit includes: comparator A1 and comparator A2; The non-inverting input of comparator A1 is connected between the first output and the gate of the first MOS transistor, the inverting input of comparator A1 is connected to a reference voltage setting circuit to obtain a first reference voltage, and the output of comparator A1 is connected to the gate of the PMOS transistor Q1. The non-inverting input of comparator A2 is connected between the second output and the gate of the second MOS transistor, the inverting input of comparator A2 is connected to a reference voltage setting circuit to obtain a second reference voltage, and the output of comparator A2 is connected to the gate of the PMOS transistor Q3.

6. The crosstalk suppression circuit according to claim 5, characterized in that, The reference voltage setting circuit includes: resistors R3, R4, R7, and R8; reference power supply U2; and reference power supply U4. The positive terminal of the reference power supply U2 is connected to the resistor R3 and the resistor R4 in series and then grounded. The negative terminal of the reference power supply U2 is connected between the source of the first MOS transistor and the drain of the second MOS transistor. The inverting input terminal of the comparator A1 is connected between the resistor R3 and the resistor R4. The positive terminal of the reference power supply U4 is connected to the resistors R7 and R8 in series and then grounded. The negative terminal of the reference power supply U4 is connected between the source of the second MOS transistor and ground. The inverting input terminal of the comparator A2 is connected between the resistors R7 and R8.

7. The crosstalk suppression circuit according to claim 5, characterized in that, The crosstalk suppression circuit also includes an overvoltage protection circuit connected to the drive monitoring unit, the overvoltage protection circuit including: Schottky diode D2 and Zener diode D4; The negative terminal of the Schottky diode D2 is connected between the first output terminal and the gate of the first MOS transistor, and the positive terminal of the Schottky diode D2 is connected to the non-inverting input terminal of the comparator A1. The negative terminal of the Zener diode D4 is connected between the second output terminal and the gate of the second MOS transistor, and the positive terminal of the Zener diode D4 is connected to the non-inverting input terminal of the comparator A2.

8. The crosstalk suppression circuit according to claim 7, characterized in that, The crosstalk suppression circuit further includes a delay circuit, which includes: resistor R1, resistor R5, capacitor C1, and capacitor C3; One end of the resistor R1 is connected to the positive terminal of the Schottky diode D2, and the other end of the resistor R1 is connected to the capacitor C1. The other end of the capacitor C1 is connected between the source of the first MOSFET and the drain of the second MOSFET. The non-inverting input terminal of the comparator A1 is connected between the resistor R1 and the capacitor C1. One end of the resistor R5 is connected to the positive terminal of the Zener diode D4, and the other end of the resistor R4 is connected to the capacitor C3. The other end of the capacitor C3 is connected between the source of the second MOS transistor and ground. The non-inverting input terminal of the comparator A2 is connected between the resistor R5 and the capacitor C3.

9. The crosstalk suppression circuit according to claim 2, characterized in that, The discharge circuit includes: resistors Rg1, R2, Rg2, R6, capacitors C2 and C4, PNP transistor Q2, and PNP transistor Q4. The resistor Rg1 is connected in series between the first output terminal of the driving circuit and the gate of the first MOS transistor. The emitter of the PNP transistor Q2 is connected between the resistor Rg1 and the gate of the first MOS transistor. The base of the PNP transistor Q2 is connected between the resistor Rg1 and the first output terminal. The collector of the PNP transistor Q2 is connected to one end of the resistor R2. The other end of the resistor R2 is connected between the source of the first MOS transistor and the drain of the second MOS transistor. The capacitor C2 is connected in parallel across the resistor R2. The resistor Rg2 is connected in series between the second output terminal of the driving circuit and the gate of the second MOS transistor. The emitter of the PNP transistor Q4 is connected between the resistor Rg2 and the gate of the second MOS transistor. The base of the PNP transistor Q4 is connected between the resistor Rg2 and the second output terminal. The collector of the PNP transistor Q4 is connected to one end of the resistor R6. The other end of the resistor R6 is connected between the source of the second MOS transistor and ground. The capacitor C4 is connected in parallel across the resistor R6.

10. The crosstalk suppression circuit according to claim 1, characterized in that, The driving circuit includes a first push-pull circuit and a second push-pull circuit. The first push-pull circuit is connected to a positive voltage, and the second push-pull circuit is connected to a negative voltage. The first push-pull circuit and the second push-pull circuit are controlled by the same driving input. The first push-pull circuit has a first output terminal connected to a first MOSFET, and the second push-pull circuit has a second output terminal connected to a second MOSFET.

11. An electrical appliance, characterized in that, The electrical equipment has a crosstalk suppression circuit as described in any one of claims 1 to 10.

12. The electrical equipment according to claim 11, characterized in that, The electrical equipment mentioned is an air conditioner.

Images