Multiphase interleaved power factor corrector, power supply and computing device

Abstract

The application provides a multi-phase interleaved power factor corrector, a power supply and a computing device. The multi-phase interleaved power factor corrector generates a first pulse width modulation control signal with a preset frequency and a preset nominal duty cycle through a controller; controls the on-off of two main switch tubes based on the first pulse width modulation control signal; determines an inductor current reference value based on the difference between the output current value of each conversion circuit and the average value of the output currents of the plurality of conversion circuits; generates a second pulse width modulation control signal based on the difference between the inductor current reference value and the inductor current value of the corresponding conversion circuit, and the phase difference of the inductor current of the conversion circuit; controls the on-off of two freewheeling switch tubes based on the second pulse width modulation control signal, so as to realize the current phase difference and balance of the plurality of conversion circuits, and output a bus DC voltage signal of the multi-phase interleaved power factor corrector.

Description

Technical Field

[0001] This application relates to the field of server power supply technology, and in particular to a multiphase interleaved power factor corrector, power supply, and computing device. Background Technology

[0002] In the field of server power supply technology, with the continuous improvement of power density, multiphase interleaved power factor correctors have become the mainstream application solution. To optimize system performance, multiphase interleaved power factor correctors typically require phase-shift control to effectively suppress high-frequency input ripple and improve electromagnetic compatibility characteristics. Simultaneously, current sharing control of the multiphase branches is also necessary to balance the thermal stress distribution of power devices, meet the design requirements of efficient heat dissipation and high reliability, and thus enhance the power supply's output capability.

[0003] However, under the Triple Critical Mode (TCM) control framework, phase-shifting control is subject to rigid constraints, requiring that the negative current reference and the turn-on duration of the main switch in each phase-interleaved branch remain completely consistent. Otherwise, phase-shifting disorder will occur, resulting in the loss of the technical effect of phase-shifting control. On the other hand, the realization of current-sharing control requires actively adjusting the two core variables: the negative current reference or the turn-on duration of the main switch in each phase. This directly conflicts the degree of freedom in adjusting current-sharing control with the constraints of phase-shifting control, resulting in a strict limitation on the variables that can be coordinated. Consequently, the inductance value becomes the main adjustment parameter for achieving current-sharing.

[0004] Even with optimized inductor design and enhanced factory screening to reduce inductor tolerance, an unavoidable tolerance in the inductance value remains. This results in a 20% difference in heat loss between phase inductors and power devices, making effective current sharing control impossible. The imbalance in current across phases subjects power devices to significant thermal stress, easily leading to inductor saturation and directly causing a decrease in the actual output power of the power supply, making it difficult to meet the demands of high power density applications. Summary of the Invention

[0005] This application provides a multiphase interleaved power factor corrector, power supply, and computing device that can meet the hardware timing requirements of multiphase interleaving, effectively suppress input high-frequency ripple, improve electromagnetic compatibility characteristics, achieve current sharing among various conversion circuits, effectively balance the thermal stress of inductors and power balance devices, fundamentally avoid inductor saturation problems, and improve the output capability of the power factor corrector to meet the application requirements of high power density.

[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions: In a first aspect, embodiments of this application provide a multiphase interleaved power factor corrector, including a multiphase interleaved power factor correction circuit and a controller; the multiphase interleaved power factor correction circuit includes an AC input power supply, multiple conversion circuits coupled to and connected in parallel with the AC input power supply, and an output voltage regulating capacitor connected in parallel with the output terminals of the multiple conversion circuits; the conversion circuit includes two main switching transistors and two freewheeling switching transistors; The controller, coupled to the conversion circuit, is used to: generate a first pulse width modulation (PWM) control signal with a preset frequency and a preset nominal duty cycle; wherein the preset frequency is a switching frequency synchronized with the AC input power frequency, and the preset nominal duty cycle is 50%; control the on / off state of two main switching transistors based on the first PWM control signal; determine an inductor current reference value based on the difference between the actual output current value of each conversion circuit and the average actual output current value of multiple conversion circuits; generate a second PWM control signal based on the difference between the inductor current reference value and the actual inductor current value of each conversion circuit, and the actual inductor current phase difference between each conversion circuit; wherein the duty cycle of the second PWM signal is fixed, but the switching frequency is adjustable; control the on / off state of two freewheeling switching transistors based on the second PWM control signal, so that the currents of multiple conversion circuits are out of phase and balanced, and the multiphase interleaved power factor corrector outputs a DC voltage signal from the bus.

[0007] Based on this scheme, the controller controls the on / off state of the main switch transistor using a second pulse width modulation (PWM) control signal with the same frequency as the AC input power supply and a nominal duty cycle of 50%. It determines the inductor current reference value based on the difference between the actual output current value and the average value of the actual output current of each conversion circuit. Then, combining this inductor current reference value with the actual inductor current value, and the second PWM control signal generated by the time phase difference of the inductor current between each conversion circuit, it controls the on / off state of the freewheeling switch transistor. This enables dynamic real-time adjustment of the inductor current, effectively compensating for current deviations caused by inductance tolerance. It fundamentally solves the inherent contradiction between phase-shift control and current-sharing control under the totem-pole TCM control architecture, achieving a balanced current distribution across each conversion circuit. This not only effectively balances the thermal stress of power devices and avoids inductor saturation, but also ensures the output capability of the power factor corrector, adapting to high power density application requirements.

[0008] In some embodiments of this application, the controller is specifically used to perform signal conditioning and conversion processing on the difference between the actual output current value of each conversion circuit and the average value of the actual output current of multiple conversion circuits to obtain an inductor current reference value.

[0009] Based on this scheme, the difference between the actual output current value of each conversion circuit and the average value of the actual output current of multiple conversion circuits can be used to directly locate the current offset of each conversion circuit. Therefore, by performing signal conditioning and conversion processing on this difference, the deviation signal can be reasonably converted into a control signal, thereby obtaining an inductor current reference value that can be directly used for current closed-loop control.

[0010] In some embodiments of this application, the controller is specifically used to perform proportional-integral adjustment on the difference between the actual output current value of each conversion circuit and the average value of the actual output current of multiple conversion circuits to generate an adjusted inductor current reference signal; and to perform digital-to-analog conversion on the adjusted inductor current reference signal to obtain an inductor current reference value.

[0011] Based on this scheme, by performing proportional-integral adjustment on the difference between the actual output current value of each conversion circuit and the average value of the actual output current of the multi-phase interleaved conversion circuit, current deviation fluctuations can be accurately suppressed, static errors and dynamic interference can be eliminated, and a stable and well-fitted adjusted inductor current reference signal can be generated. The adjusted inductor current reference signal is then converted from digital to analog to obtain an inductor current reference value that can be directly compared with the actual inductor current value of the conversion circuit and adapted to the controller's control logic, thus achieving accurate conversion and adaptation of deviation signals to control signals.

[0012] In some embodiments of this application, the controller is specifically used to determine the turn-off time of the second pulse width modulation control signal based on the difference between the reference value of the inductor current of each conversion circuit and the actual inductor current value.

[0013] Based on this solution, the actual inductor current deviation of each conversion circuit can be tracked in real time. By precisely controlling the turn-off time of the second pulse width modulation control signal, the inductor current offset can be dynamically corrected, enhancing the accuracy of current sharing control, effectively compensating for the influence of inductance value tolerance, ensuring current balance in each conversion circuit, achieving thermal stress balance of power devices, and providing reliable control support for the stable output and high power density adaptation of the multiphase interleaved power factor corrector.

[0014] In some embodiments of this application, a conversion circuit is used to convert an AC voltage signal input from an AC input power source into a first DC voltage signal; The output voltage regulator capacitor is coupled to the output terminal of the multiphase interleaved power factor corrector to stabilize the first DC voltage signal as the bus DC voltage signal. The controller is also used to determine the on-time of the second pulse width modulation control signal based on the difference between the bus DC voltage signal and the output voltage reference value, as well as the actual inductor current phase difference between each conversion circuit.

[0015] Based on this scheme, the conversion circuit can effectively convert the AC voltage signal into the first DC voltage signal, providing a foundation for the DC output of the multiphase interleaved power factor corrector. The output voltage stabilizing capacitor can stabilize the first DC voltage signal, suppress voltage fluctuations, and ensure the stability of the output bus DC voltage signal. By combining the difference between the bus DC voltage signal and the output voltage reference value, and the actual inductor current phase difference between each conversion circuit, the controller determines the conduction duration of the second pulse width modulation control signal, which can achieve precise voltage regulation control of the bus DC voltage, while ensuring the phase reversal accuracy and current balance of each conversion circuit.

[0016] In some embodiments of this application, the controller is specifically used to perform proportional-integral adjustment on the difference between the bus DC voltage signal and the output voltage reference value to obtain the adjusted time value; to superimpose the input voltage feedforward amount and the time compensation amount on the adjusted time value to obtain the reference conduction duration of the second pulse width modulation control signal; and to determine the conduction duration of the second pulse width modulation control signal based on the reference conduction duration and the actual inductor current phase difference between each conversion circuit.

[0017] Based on this scheme, the difference between the bus DC voltage signal and the output voltage reference value is adjusted proportionally and integrally, which can accurately eliminate the static error and dynamic fluctuation of the bus DC voltage and realize high-precision voltage regulation control in closed loop. The superposition of the input voltage feedforward can compensate for the interference caused by the input voltage change in advance, and the time compensation can correct the effects of control delay, device characteristic deviation, etc., and improve the timeliness and accuracy of the conduction time determination. The conduction time is further optimized by combining the actual inductor current phase difference between each conversion circuit, which can ensure the phase reversal accuracy and current balance of each conversion circuit.

[0018] In some embodiments of this application, the controller is specifically used to determine the conduction duration adjustment value based on the difference between the inductor current phase difference threshold and the actual inductor current phase difference between each conversion circuit; and to superimpose the conduction duration adjustment value on the reference conduction duration to obtain the conduction duration of the second pulse width modulation control signal.

[0019] Based on this scheme, the conduction duration adjustment value is determined in real time based on the difference between the inductor current phase difference threshold and the actual inductor current phase difference between each conversion circuit. The conduction duration is then dynamically corrected by adjusting the conduction duration value. In this way, it can be ensured that the actual inductor current phase difference of each conversion circuit is stably maintained within the preset phase difference threshold range, thus accurately guaranteeing the phase misalignment accuracy.

[0020] In some embodiments of this application, the controller is specifically used to proportionally adjust the difference between the current phase difference threshold and the actual inductor current phase difference between each conversion circuit to obtain the conduction duration adjustment value.

[0021] Based on this scheme, the offset between the actual inductor current phase difference and the preset threshold of each conversion circuit can be accurately captured. The phase deviation can be linearly and quickly corrected through proportional adjustment, generating an accurate and suitable conduction time adjustment value.

[0022] In some embodiments of this application, the controller is further configured to turn off the second pulse width modulation control signal when the actual inductor current value of each conversion circuit is greater than or equal to the inductor current threshold.

[0023] Based on this scheme, assuming that the inductor current threshold can reflect the maximum allowable limit of the inductor current in the conversion circuit, the controller shuts off the second pulse width modulation control signal when the actual inductor current value of each conversion circuit is greater than or equal to the inductor current threshold. This can quickly cut off the inductor current supply to that conversion circuit, thereby achieving overcurrent protection for the multiphase interleaved power factor corrector. This effectively avoids faults such as inductor saturation and power device damage caused by inductor current overload, further improving the reliability and safety of the entire multiphase interleaved power factor corrector.

[0024] Secondly, embodiments of this application provide a control method for a multiphase interleaved power factor corrector. The multiphase interleaved power factor corrector includes a multiphase interleaved power factor correction circuit and a controller. The multiphase interleaved power factor correction circuit includes an AC input power supply, multiple conversion circuits coupled to and connected in parallel with the AC input power supply, and output voltage regulating capacitors connected in parallel with the output terminals of the multiple conversion circuits. The conversion circuit includes two main switching transistors and two freewheeling switching transistors. The control method includes: Generate a first pulse width modulation control signal with a preset frequency and a preset nominal duty cycle; wherein, the preset frequency is a switching frequency synchronized with the AC input power frequency, and the preset nominal duty cycle is 50%; The on / off state of the two main switching transistors is controlled based on the first pulse width modulation control signal; The inductor current reference value is determined based on the difference between the actual output current value of each conversion circuit and the average actual output current value of multiple conversion circuits. Based on the difference between the reference value and the actual value of the inductor current of each conversion circuit, and the phase difference of the actual inductor current between each conversion circuit, a second pulse width modulation control signal is generated; wherein, the duty cycle of the second pulse width modulation control signal is fixed, but the switching frequency is adjustable. The switching of two freewheeling transistors is controlled by the second pulse width modulation control signal, so that the currents of multiple conversion circuits are out of phase and balanced, and the multiphase interleaved power factor corrector outputs the DC voltage signal of the bus.

[0025] Thirdly, embodiments of this application provide a control device for a multiphase interleaved power factor corrector. The multiphase interleaved power factor corrector includes a multiphase interleaved power factor correction circuit and a controller. The multiphase interleaved power factor correction circuit includes an AC input power supply, multiple conversion circuits coupled to and connected in parallel with the AC input power supply, and output voltage regulating capacitors connected in parallel with the output terminals of the multiple conversion circuits. The conversion circuit includes two main switching transistors and two freewheeling switching transistors. The device includes: The first generation module is used to generate a first pulse width modulation control signal with a preset frequency and a preset nominal duty cycle. The preset frequency is the switching frequency synchronized with the AC input power frequency, and the preset nominal duty cycle is 50%. The first control module is used to control the on / off state of the two main switching transistors based on the first pulse width modulation control signal; The determination module is used to determine the inductor current reference value based on the difference between the actual output current value of each conversion circuit and the average output current value of multiple conversion circuits. The second generation module is used to generate a second pulse width modulation control signal based on the difference between the reference value and the actual inductor current value of each conversion circuit, and the phase difference of the actual inductor current between each conversion circuit; wherein, the duty cycle of the second pulse width modulation control signal is fixed, but the switching frequency is adjustable. The second control module is used to control the on / off state of the two freewheeling switches based on the second pulse width modulation control signal, so that the currents of multiple conversion circuits are out of phase and balanced, and the multiphase interleaved power factor corrector outputs the DC voltage signal of the bus.

[0026] Fourthly, embodiments of this application provide a power supply, including a resonant converter and the multiphase interleaved power factor corrector provided in the first aspect; The resonant converter, whose input is coupled to the output of the multiphase interleaved power factor corrector, is used to perform resonant conversion processing on the bus DC voltage signal output by the multiphase interleaved power factor corrector to output the target DC voltage signal.

[0027] Fifthly, embodiments of this application provide a computing device, which includes a motherboard and a power supply provided in the fourth aspect; the power supply has its output terminal coupled to the power input terminal of the motherboard for supplying power to the motherboard.

[0028] In a sixth aspect, embodiments of this application provide a storage medium storing a computer program for executing the control method of the multiphase interleaved power factor corrector provided in the second aspect above.

[0029] In a seventh aspect, embodiments of this application provide a computer program product that, when instructions in the computer program product are executed by a processor, performs the control method for the multiphase interleaved power factor corrector provided in the second aspect above. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of a multiphase interleaved power factor corrector provided in an embodiment of this application.

[0031] Figure 2 This is a schematic diagram of another multiphase interleaved power factor corrector provided in an embodiment of this application.

[0032] Figure 3A This is a schematic diagram of the structure of a controller provided in an embodiment of this application.

[0033] Figure 3B This is a flowchart illustrating a control method for a multiphase interleaved power factor corrector provided in an embodiment of this application.

[0034] Figure 4 This is a flowchart illustrating another control method for a multiphase interleaved power factor corrector provided in an embodiment of this application.

[0035] Figure 5 This is a flowchart illustrating another control method for a multiphase interleaved power factor corrector provided in an embodiment of this application.

[0036] Figure 6 This is a flowchart illustrating another control method for a multiphase interleaved power factor corrector provided in an embodiment of this application.

[0037] Figure 7 This is a flowchart illustrating another control method for a multiphase interleaved power factor corrector provided in an embodiment of this application.

[0038] Figure 8 This is a schematic diagram of the control device for a multiphase interleaved power factor corrector provided in an embodiment of this application.

[0039] Figure 9 A schematic diagram of the control device for another multiphase interleaved power factor corrector provided in this application embodiment.

[0040] Figure 10 This is a schematic diagram of a power supply provided in an embodiment of this application.

[0041] Figure 11 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application. Detailed Implementation

[0042] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. To facilitate a clear description of the technical solutions of the embodiments of this application, the use of terms such as "first," "second," etc., in the embodiments of this application is for illustrative purposes and to distinguish the objects being described. There is no particular order between them, nor does it indicate a specific limitation on the number of devices in the embodiments of this application, and they do not constitute any limitation on the embodiments of this application.

[0043] The following describes the relevant technical terms used in the embodiments of this application: A computing device is an electronic device used to perform computing tasks. Computing devices can include personal computers, servers, embedded computers, and supercomputers, etc. This application uses a server as an example for illustrative purposes. The server in this application can be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, cloud communication, middleware services, domain name services, security services, content delivery networks (CDNs), and big data and artificial intelligence platforms. When the aforementioned server is a server cluster or distributed system composed of multiple physical servers, the multiple physical servers can form a blockchain, with each physical server being a node on the blockchain. The physical type of the server can include rack servers, cabinet servers, high-density servers, graphics processing unit (GPU) servers, tower servers, blade servers, artificial intelligence (AI) servers, etc. This application does not limit the type of server in its embodiments.

[0044] A multiphase interleaved power factor corrector (PFC) is a power electronic device used for AC-DC conversion. It achieves input current harmonic suppression and power factor correction by connecting two or more PFC converter units in parallel and interleaving the switching transistors of each unit with a phase difference of 360° / n (where n is the number of phases). Its core mechanism lies in utilizing the time-domain cancellation effect of multiphase current ripple to significantly reduce the total current ripple amplitude and increase the equivalent switching frequency. This reduces the size of magnetic components, improves electromagnetic compatibility characteristics, and supports modular power expansion in high-power applications.

[0045] A resonant converter is a switching power supply topology that achieves power conversion based on a resonant network. Its core feature is that it utilizes the resonant characteristics of the resonant element to enable the switching transistor to complete the turn-on or / off action at the moment when the current or voltage crosses zero, thereby significantly reducing switching losses and improving power conversion efficiency.

[0046] A power supply is a power conversion and distribution device that provides stable and reliable power to the entire computing device and its internal core components (such as motherboards, processors, and memory). Its core components include, as mentioned above, a multiphase interleaved power factor corrector and a resonant converter. The multiphase interleaved power factor corrector converts the external AC input power into a stable DC bus voltage signal, improves the input power factor, and reduces current harmonic distortion. The resonant converter performs resonant transformation on the DC bus voltage signal, converting it into a target DC voltage signal that meets the operating requirements of various components of the computing device. It is characterized by high efficiency, energy saving, stability, reliability, and adaptability to high power density, ensuring the stability of power supply to the computing device under long-term high-load operation scenarios and providing core power support for the normal operation of the computing device.

[0047] This application provides a multiphase interleaved power factor corrector, which includes a multiphase interleaved power factor correction circuit and a controller. The multiphase interleaved power factor correction circuit includes an AC input power supply, multiple conversion circuits coupled to and connected in parallel with the AC input power supply, and an output stabilizing capacitor connected in parallel with the output terminals of the multiple conversion circuits. Each conversion circuit includes two main switches and two freewheeling switches. The controller generates a first pulse width modulation signal with a preset frequency and a preset nominal duty cycle, and controls the switching on and off of the two main switches based on the first pulse width modulation control signal. An inductor current reference value is determined based on the difference between the actual output current value of each conversion circuit and the average actual output current value of the multiple conversion circuits. A second pulse width modulation control signal is generated based on the difference between the inductor current reference value and the actual inductor current value of each conversion circuit, as well as the actual inductor current phase difference between the conversion circuits. The switching on and off of the two freewheeling switches is controlled based on the second pulse width modulation control signal, so that the currents of the multiple conversion circuits are out of phase and balanced, and the multiphase interleaved power factor corrector outputs a DC voltage signal from the bus. This enables dynamic real-time adjustment of the inductor current, effectively compensating for current deviations caused by inductance tolerance. It fundamentally resolves the inherent contradiction between phase-shift control and current-sharing control under the totem-pole TCM control architecture, achieving balanced current distribution across all conversion circuits. This not only effectively balances the thermal stress of power devices and avoids inductor saturation, but also ensures the output capability of the power factor corrector, adapting to high power density application requirements.

[0048] Figure 1 This is a schematic diagram of a multiphase interleaved power factor corrector provided in an embodiment of this application. Figure 1As shown, the multiphase interleaved power factor corrector 10 includes a multiphase interleaved power factor correction circuit 101 and a controller 102; the multiphase interleaved power factor correction circuit 101 includes an AC input power supply 1011, a plurality of conversion circuits 1012 coupled to and connected in parallel with the AC input power supply 1011, and an output voltage regulator capacitor 1013 connected in parallel with the output terminals of the plurality of conversion circuits; The converter circuit 1012 includes two main switching transistors and two freewheeling switching transistors; Controller 102, coupled to conversion circuit 1012, is used to: generate a first pulse width modulation (PWM) control signal with a preset frequency and a preset nominal duty cycle; wherein the preset frequency is a switching frequency synchronized with the AC input power supply frequency, and the preset nominal duty cycle is 50%; control the switching on and off of two main switching transistors based on the first PWM control signal; determine an inductor current reference value based on the difference between the actual output current value of each conversion circuit and the average actual output current value of multiple conversion circuits; generate a second PWM control signal based on the difference between the inductor current reference value and the actual inductor current value of each conversion circuit, and the actual inductor current phase difference between each conversion circuit; and control the switching on and off of two freewheeling switching transistors based on the second PWM control signal, so that the currents of multiple conversion circuits are out of phase and balanced, and the multiphase interleaved power factor corrector outputs a DC voltage signal from the bus. The duty cycle of the second PWM control signal is fixed, but the switching frequency is adjustable.

[0049] The controller 102 is the core control unit for controlling the multiphase interleaved power factor correction circuit 101. Its core components may include digital signal processors, microcontrollers, complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), or application-specific integrated circuits (ASICs) with data processing and logic control capabilities. The chip may integrate functional modules such as timers, analog-to-digital converters (ADCs), and pulse width modulation (PWM) generators, providing hardware support for the precise control of the switching transistors in the multiphase interleaved power factor correction circuit. This application embodiment does not limit the specific type of controller 102; this embodiment uses a CPLD as an example for illustrative purposes.

[0050] The controller 102 can be determined comprehensively based on factors such as system performance requirements and development cycle. For example, for applications requiring high control accuracy and response speed, a high-performance digital signal processor can be selected; for cost-sensitive applications, a microcontroller may be a better choice.

[0051] In addition, the controller 102 can be paired with peripheral circuits such as a drive circuit to amplify the generated PWM control signal to meet the driving requirements of the switching transistor, ensuring that the switching transistor can be reliably turned on and off. This drive circuit typically needs to have sufficient output current capability and a fast switching speed to reduce switching losses and improve the efficiency of the entire system.

[0052] The AC input power supply 1011 is a power supply that provides an AC voltage signal of a preset amplitude. In some examples, the AC voltage signal of the preset amplitude may be a 220V power frequency AC voltage signal.

[0053] The conversion circuit 1012 is a conversion unit that converts AC voltage signals to DC voltage signals, and can adopt a totem-pole bridgeless topology. Taking the totem-pole bridgeless topology of the conversion circuit 1012 as an example, the conversion circuit 1012 includes a power frequency half-bridge main switching branch composed of two main switching transistors and a high-frequency freewheeling branch composed of two freewheeling switching transistors. Figure 2 As shown, the two main switching transistors may include Neg and Pos, and the two freewheeling switching transistors may include HSi and LSi. Here, i is any one of 1 to 3.

[0054] Neg, Pos, HSi, and LSi can all be fully controllable voltage or current transistors. This application does not limit the types of Neg, Pos, HSi, and LSi. In some examples, Neg, Pos, HSi, and LSi are all silicon metal-oxide-semiconductor field-effect transistors (SiMOSFETs). In other examples, Neg, Pos, HSi, and LSi are all low-switching-loss, high-voltage insulated-gate bipolar transistors (IGBTs). In still other examples, Neg and Pos are IGBTs, and HSi and LSi are Si MOSFETs. This application provides an illustrative example using Neg and Pos as IGBTs and HSi and LSi as Si MOSFETs.

[0055] Taking an AC input power supply 1011 with a frequency of 50Hz as an example, the first pulse width modulation (PWM) control signal may include two PWM control signals, both with a nominal duty cycle of 50% and a frequency of 50Hz. In some examples, the first PWM control signal may include a first sub-PWM control signal for controlling Neg and a second sub-PWM control signal for controlling Pos.

[0056] The first sub-PWM control signal and the second sub-PWM control signal are complementary in phase and their conduction intervals do not overlap (there is a dead zone). That is, when the first sub-PWM control signal is high, the second sub-PWM control signal is low, and vice versa.

[0057] This application does not limit the implementation method of the controller 102 generating the first pulse width modulation control signal. In some examples, if the controller 102 includes an ASIC, the controller 102 can directly generate the first pulse width modulation control signal through hardware logic circuits based on the built-in 50Hz reference clock module and duty cycle calibration module. In other examples, if the controller 102 includes an FPGA, the controller 102 can first divide the FPGA's 100MHz core clock to a 50Hz reference clock through the built-in clock divider module, and then generate the first pulse width modulation signal by configuring the high and low level durations to be equal (both 10ms) through the built-in duty cycle generation module and signal output module. In yet another example, if the controller 102 is a CPLD, it can generate a 50Hz reference clock and a first pulse width modulation control signal with a 50% duty cycle by constructing a frequency divider and a state machine through internal programmable logic based on the clock provided by an external crystal oscillator.

[0058] Understandably, the control signal output terminal of controller 102 is coupled to the control terminals (e.g., gates) of Neg and Pos to control the on / off states of Neg and Pos. For example, during the positive half-cycle of the AC input power supply 1011, Pos is turned on, Neg is turned off, and the AC input current flows into the subsequent rectifier bridge arm through Pos; during the negative half-cycle of the AC input power supply 1011, Neg is turned on, Pos is turned off, and the AC input current flows into the subsequent rectifier bridge arm through Neg, thereby realizing the rectification function of the power frequency half-bridge.

[0059] The second pulse width modulation signal may include two PWM control signals with variable frequency and fixed duty cycle. In some examples, the second pulse width modulation signal may include a third sub-PWM control signal for controlling HSi and a fourth sub-PWM control signal for controlling LSi.

[0060] The third and fourth sub-PWM control signals are complementary in phase and their conduction intervals do not overlap (there is a dead zone). That is, when the third sub-PWM control signal is high, the fourth sub-PWM control signal is low, and vice versa.

[0061] The actual inductor current value of the conversion circuit 1012 refers to the current value on the inductor of the conversion circuit 1012 acquired in real time; the actual inductor current phase difference between each conversion circuit 1012 refers to the phase deviation of the inductor current waveform of each conversion circuit 1012 detected in real time relative to the same reference, or the phase deviation of the inductor current waveform between two adjacent conversion circuits 1012.

[0062] The controller 102 can collect the actual output current value of each conversion circuit 1012 in real time, calculate the average actual output current of multiple conversion circuits 1012, and calculate the difference between the actual output current value of each conversion circuit 1012 and the average actual current value to obtain the current sharing deviation of each conversion circuit 1012. The controller 102 then processes the current sharing deviation to obtain the inductor current reference value. Simultaneously, the controller collects the actual inductor current value of each conversion circuit 1012 and the actual inductor current phase difference between each conversion circuit in real time. The controller 102 performs comprehensive adjustment calculations on the difference between the inductor current reference value and the actual inductor current value of each conversion circuit, as well as the actual inductor current phase difference between each conversion circuit 1012, to dynamically adjust the frequency of the output pulse and generate a second pulse width modulation control signal with a fixed duty cycle but variable frequency.

[0063] The control output terminal of the controller 102 is also coupled to the control terminals of HSi and LSi to control the conduction and cutoff of HSi and LSi. The conduction and cutoff of HSi and LSi will be dynamically adjusted according to the change of inductor current and control strategy, so that the current of multiple conversion circuits 1012 is out of phase and balanced, and the multiphase interleaved power factor corrector 10 outputs a DC voltage signal.

[0064] It is understood that if the multiphase interleaved power factor correction circuit 101 includes two conversion circuits 1012, then the current phase misalignment of the two conversion circuits 1012 means that the phase of the inductor current of the two conversion circuits 1012 differs from each other by 180°; if the multiphase interleaved power factor correction circuit 101 includes three conversion circuits 1012, then the current phase misalignment of the three conversion circuits 1012 means that the phase of the inductor current of the three conversion circuits 1012 differs from each other by 120°; if the multiphase interleaved power factor correction circuit 101 includes four conversion circuits 1012, then the current phase misalignment of the four conversion circuits 1012 means that the phase of the inductor current of the four conversion circuits 1012 differs from each other by 90°; if the multiphase interleaved power factor correction circuit 101 includes N conversion circuits 1012, then the current phase misalignment of the N conversion circuits 1012 means that the phase of the inductor current of the N conversion circuits 1012 differs from each other by 360° / N, where N is an integer greater than or equal to 1.

[0065] Current balancing of multiple conversion circuits 1012 means that the output current of each conversion circuit 1012 remains consistent.

[0066] The multiphase interleaved power factor corrector provided in this application uses a controller that controls the on / off state of the main switch via a second pulse width modulation (PWM) control signal with a nominal duty cycle of 50% and the same frequency as the AC input power supply. It determines an inductor current reference value based on the difference between the actual output current value and the average actual output current value of each conversion circuit. This reference value, combined with a second PWM control signal generated from the difference between the reference value and the actual inductor current value, controls the on / off state of the freewheeling switch. This enables dynamic real-time adjustment of the inductor current, effectively compensating for current deviations caused by inductance tolerance. It fundamentally solves the inherent contradiction between phase-shift control and current-sharing control under the totem-pole TCM control architecture, achieving a balanced current distribution across the conversion circuits. This not only effectively balances the thermal stress of power devices and avoids inductor saturation, but also ensures the output capability of the power factor corrector, adapting to high power density application requirements.

[0067] Figure 2 This is a schematic diagram of another multiphase interleaved power factor corrector provided in an embodiment of this application. Figure 2 As shown, the AC input power supply 1011 is AC, the output voltage regulator capacitor 1013 is C, and the multiphase interleaved power factor correction circuit 101 includes the first to third conversion circuits 1012, and each conversion circuit 1012 shares the same main switch Pos and Neg. In addition to the main switch Pos and Neg, the i-th conversion circuit 1012 also includes an inductor Li, a switch HSi and a switch LSi. Each switch includes a freewheeling diode and a parasitic output capacitor; i is 1, 2 or 3.

[0068] Continue to refer to Figure 2As shown, Pos and Neg are connected in series to form a first series branch, and HSi and LSi are connected in series to form a second series branch. The first series branch and the second series branch are connected in parallel across the output terminal out of the multiphase interleaved power factor corrector 10 and ground. The drain of Pos and the source of Neg are coupled to form a first common node, and the source of HSi and the drain of LSi are coupled to form a second common node. The sources of Pos and LSi are both grounded, and the drains of Neg and HSi are both coupled to the output terminal out of the multiphase interleaved power factor corrector 10. A third series branch formed by AC and Li is connected in series across the first common node and the second common node. The L terminal of AC is coupled to the first common node, the N terminal of AC is coupled to one end of Li, and the other end of Li is coupled to the corresponding second common node.

[0069] Continue to refer to Figure 2 As shown, a surge protection element SurgeH and a buffer capacitor Cd1 can be connected between the N terminal of AC and the output terminal out of the multiphase interleaved power factor corrector 10. A surge protection element SurgeL and a buffer capacitor Cd2 can also be connected between the N terminal of AC and ground to suppress and absorb the AC measured current input surge at the moment of AC power-on or when instantaneous overvoltage occurs.

[0070] refer to Figure 2 As shown, the operation of the multiphase interleaved power factor corrector 10 during the positive half-cycle of AC (Pos remains on, Neg remains off), i.e., when the N terminal is positive and the L terminal is negative, can include the following: First, when Pos and LSi are both on, the current starts from the N terminal of AC, passes through Li and LSi in sequence, and then flows back to the L terminal of AC through Pos, realizing energy storage in Li; then, LSi is off and HSi is on, and the inductor Li releases energy. The current starts from the N terminal of AC, passes through Li, HSi, and C in sequence, and then flows back to the L terminal of AC through Pos, realizing freewheeling; next, when the energy on the inductor Li is completely released, the current in the inductor Li reverses and the amplitude of the reverse current reaches a preset amplitude threshold, HSi is turned off. The current direction starts from the L terminal of AC, passes through Pos, ground, the parasitic output capacitor of LSi in sequence, and then flows back to the N terminal of AC through Li, so as to release the charge on the parasitic output capacitor of LSi. Finally, after the charge on the parasitic output capacitor of LSi is released, LSi turns on and enters the freewheeling stage. The current starts from the L terminal of AC, passes through Pos, ground, LSi in sequence, and then flows back to the N terminal of AC through Li.

[0071] The operation of the multiphase interleaved power factor corrector 10 during the negative half-cycle of Vac (Neg remains on, Pos remains off), i.e., when the L terminal is positive and the N terminal is negative, can be summarized as follows: First, when Neg and HSi are both on, the current starts from the L terminal of AC, passes through Neg and HSi in sequence, and then flows back to the N terminal of AC through Li, thus storing energy in Li. Then, Neg remains on, HSi is off, and LSi is on. The current starts from the L terminal of AC, passes through Neg, C, and LSi in sequence, and then flows back to the N terminal of AC through Li, thus freewheeling. Next, when the energy on inductor Li is exhausted, and a reverse current occurs in inductor Li and the amplitude of the reverse current reaches a preset amplitude threshold, LSi is turned off. The current starts from the N terminal of AC, passes through the parasitic output capacitors of Li and HSi in sequence, and then flows back to the L terminal of AC through Neg, thus releasing the charge on the parasitic output capacitor of HSi. Finally, when the charge on the parasitic output capacitor of HSi is completely released, HSi turns on and enters the freewheeling stage. The current starts from the N terminal of AC, passes through Li and HSi in sequence, and then flows back to the L terminal of AC through Neg.

[0072] The controller 102 can control the output voltage of the multiphase interleaved power factor corrector 10 to be stabilized at a preset amplitude DC voltage by controlling the on-time and off-time of HSi and LSi, and ensure that the currents of each conversion circuit 1012 are out of phase and balanced.

[0073] Continue to refer to Figure 1 or Figure 2 As shown, the controller 102 is specifically used to perform signal conditioning and conversion processing on the difference between the actual output current value of each conversion circuit 1012 and the average value of the actual output current of multiple conversion circuits 1012, so as to obtain the inductor current reference value Iref.

[0074] like Figure 2 As shown, taking the conversion circuit 1012 including HS1 and LS1 as an example, the actual output current value of the conversion circuit 1012 refers to the current value flowing from HS1 or LS1 to the output terminal out of the multiphase interleaved power factor corrector 10.

[0075] Taking the converter circuit 1012 including Li as an example, the inductor current reference value Iref refers to the reference current when adjusting the inductor current ILi.

[0076] like Figure 3A As shown, the controller 102 can collect the output current value Ioi of the i-th conversion circuit 1012 in real time to obtain Io1, Io2 and Io3, calculate the average value Iavg of Io1, Io2 and Io3, obtain Iavg=(Io1+Io2+Io3) / 3, and Ioi-Iavg, and process Ioi-Iavg through a preset control algorithm to obtain the inductor current reference value Irefi.

[0077] For example, the controller 102 can process the Ioi-Iavg using a proportional-integral adjustment algorithm and perform digital-to-analog conversion on the obtained digital current reference value to generate an analog inductor current reference value Irefi.

[0078] In some examples, the controller 102 can perform proportional-integral adjustment on the difference Ioi between the output current value Ioi of each conversion circuit 1012 and the average output current value Iavg of the multiple conversion circuits 1012, to generate an adjusted inductor current reference signal; and perform digital-to-analog conversion on the adjusted inductor current reference signal to obtain the inductor current reference value Irefi.

[0079] The proportional coefficient Kp and integral coefficient Ki of the proportional-integral control can be determined based on theoretical calculations of the mathematical model, stability requirements, and dynamic performance indicators of the closed-loop control system. For example, the tuning process for the proportional coefficient Kp and integral coefficient Ki may include: (1) Establish the mathematical model of the control system Determine the transfer functions of the current sampling section and the proportional-integral controller, respectively.

[0080] GainSample = 1 / (1 + ... ×s) (1; Where GainSample is the transfer function of the current sampling stage. is the filter coefficient, a fixed time constant determined by the hardware (RC filter); s is a complex variable in the Laplace transform; GainPID=Kp+Ki / s=(Ki+Kp×s) / s=(s+Ki / Kp)×Kp / s (2); GainPID is the transfer function of the current sampling stage.

[0081] Thus, the transfer function for the entire flow equalization coefficient is: Gainall=GainPID×GainSample=(s+Ki / Kp)×Kp / s× 1 / (1+ ×s) (3; (2) Determine the design objectives of the control system To ensure absolute system stability and simplify dynamic characteristics, the entire closed-loop system needs to be downgraded to a single-level system. This means ensuring that the zero point (s=-Ki / Kp) provided by the PI controller exactly cancels out the poles (s=-1 / Kp) of the controlled object (the data acquisition stage). ×s). Therefore, the first constraint is Ki / Kp = .

[0082] To ensure the desired response speed, the open-loop gain crossover frequency of the system needs to be set at BW to control the closed-loop bandwidth. Therefore, the second constraint is Kp / (2π×BW) = 1. Here, BW is the desired current-sharing bandwidth, typically taken as 1kHz-5kHz.

[0083] Therefore, based on the first and second constraints mentioned above, we can solve for Kp = 2 × BW × π and Ki = 2 × BW × π. .

[0084] The multiphase interleaved power factor corrector provided in this application precisely suppresses current deviation fluctuations, eliminates static errors and dynamic interference, and generates a stable, adjusted inductor current reference signal that meets current sharing requirements by proportional-integral adjustment of the difference between the actual output current value of each conversion circuit and the average actual output current of the multiphase interleaved conversion circuit. The adjusted inductor current reference signal is then converted from digital to analog to obtain an inductor current reference value that can be directly compared with the actual inductor current value of the conversion circuit and adapted to the controller's control logic, thus achieving precise conversion and adaptation of the deviation signal to the control signal. Furthermore, since the difference between the actual output current value of each conversion circuit and the average actual output current of multiple conversion circuits can directly locate the current offset of each conversion circuit, signal adjustment and conversion processing of this difference can achieve a reasonable conversion of the deviation signal to the control signal, thereby obtaining an inductor current reference value that can be directly used for current closed-loop control.

[0085] Continue to refer to Figure 3A As shown, in some embodiments of this application, the controller 102 is specifically used to determine the turn-off time (Toff time) of the second pulse width modulation control signal based on the difference between the inductor current reference value Irefi and the actual inductor current value ILi of each conversion circuit 1012, Irefi-ILi.

[0086] In some examples, the controller 102 can set the PWM signal low to turn off HSi and end the energy storage phase of the inductor when the difference between the inductor current reference value Irefi and the actual inductor current value ILi in each conversion circuit 1012 is less than or equal to zero, that is, when the actual inductor current value ILi reaches the inductor current reference value Irefi.

[0087] This application embodiment does not limit the implementation method of the controller 102 setting the PWM signal low. This application embodiment takes the example of setting the PWM signal low by sequentially processing the difference Irefi-ILi through the error amplifier, comparator and flip-flop in the controller 102, and can be referred to as... Figure 3A As shown.

[0088] The multiphase interleaved power factor corrector provided in this application embodiment can track the inductor current deviation of each conversion circuit in real time. By precisely controlling the turn-off time of the second pulse width modulation control signal, it dynamically corrects the inductor current offset, enhances the accuracy of current sharing control, effectively compensates for the influence of inductance value tolerance, ensures current balance in each conversion circuit, realizes thermal stress balance of power devices, and provides reliable control support for the stable output and high power density adaptation of the multiphase interleaved power factor corrector.

[0089] Continue to refer to Figure 1 or Figure 2 As shown, in some embodiments of this application, the conversion circuit 1012 is used to convert the AC voltage signal Vin, which is input from the AC input power supply AC, into a first DC voltage signal Vout. The output voltage regulator capacitor C is coupled to the output terminal out of the multiphase interleaved power factor corrector 10 to stabilize the first DC voltage signal Vout, which serves as the bus DC voltage signal Vbus. The controller 102 is also used to determine the on-time Ton of the second pulse width modulation control signal based on the difference between the bus DC voltage signal Vbus and the output voltage reference value VbusRef, and the phase difference of the inductor current between each conversion circuit 1012.

[0090] For example, the first DC voltage signal Vout and the bus DC voltage signal Vbus are both voltages at the output terminal out of the multiphase interleaved power factor corrector 10.

[0091] The AC voltage signal Vin can be a 220V AC voltage signal output from the AC input power supply 1011. The first DC voltage signal Vout or the bus DC voltage signal Vbus can be a 400V DC voltage signal.

[0092] The output voltage reference value VbusRef refers to the target DC output voltage value that the multiphase interleaved power factor corrector 10 is expected to achieve. It is the reference for voltage closed-loop control and is used to determine the output voltage level of the multiphase interleaved power factor corrector 10.

[0093] refer to Figure 2As shown, the actual inductor current phase difference between each conversion circuit 1012 may include a first phase difference, a second phase difference, and a third phase difference. Specifically, the first phase difference may be the actual inductor current phase difference between the conversion circuit 1012 including L1, HS1, and LS1 and the conversion circuit 1012 including L2, HS2, and LS2; the second phase difference may be the actual inductor current phase difference between the conversion circuit 1012 including L1, HS1, and LS1 and the conversion circuit 1012 including L3, HS3, and LS3; and the third phase difference may be the actual inductor current phase difference between the conversion circuit 1012 including L2, HS2, and LS2 and the conversion circuit 1012 including L3, HS3, and LS3.

[0094] refer to Figure 3A As shown, the controller 102 can first determine the reference conduction time Ton-base of the second pulse width modulation control signal based on the difference between the bus DC voltage signal Vbus and the output voltage reference value VbusRef. Then, it can fine-tune the reference conduction time Ton-base according to the actual inductor current phase difference between each conversion circuit 1012, and finally determine the conduction time Ton of the second pulse width modulation control signal.

[0095] Continue to refer to Figure 1 or Figure 2 As shown, the controller 102 can first process the difference between the bus DC voltage signal Vbus and the output voltage reference value VbusRef through a composite adjustment algorithm to obtain the reference conduction time Ton-base of the second pulse width modulation control signal. Then, based on the actual inductor current phase difference between each conversion circuit 1012, the reference conduction time Ton-base is adjusted to determine the conduction time Ton of the second pulse width modulation control signal.

[0096] Continue to refer to Figure 3A As shown, in some embodiments of this application, the controller 102 is specifically used to perform proportional-integral adjustment on the difference between the bus DC voltage signal Vbus and the output voltage reference value VbusRef to obtain the adjusted time value; to superimpose the input voltage feedforward amount Kff and the time compensation amount ThDi Ton on the adjusted time value to obtain the reference conduction duration Ton-base of the second pulse width modulation control signal; and to determine the conduction duration Ton of the second pulse width modulation control signal based on the phase difference between the reference conduction duration Ton-base and the actual inductor current of each conversion circuit 1012.

[0097] The input voltage feedforward quantity Kff, also known as the input voltage feedforward gain, refers to the proportional coefficient that introduces the detected or calculated value of the input voltage as a feedforward signal into the control loop to compensate for the impact of input voltage fluctuations on the system output in advance.

[0098] Kff=220×220 / (Vinrms×Vinrms) (1); Where 220 is the rated input voltage RMS value, and Vinrms is the actual input voltage RMS value.

[0099] The multiphase interleaved power factor corrector provided in this application performs proportional-integral adjustment on the difference between the bus DC voltage signal and the output voltage reference value, which can accurately eliminate the static error and dynamic fluctuation of the bus DC voltage and realize high-precision voltage regulation control in closed loop. The superposition of the input voltage feedforward can compensate for the interference caused by the input voltage change in advance, and the time compensation can correct the effects of control delay, device characteristic deviation, etc., and improve the timeliness and accuracy of the conduction time determination. The conduction time is further optimized by combining the actual inductor current phase difference between each conversion circuit, which can ensure the phase reversal accuracy and current balance of each conversion circuit.

[0100] like Figure 3A As shown, the controller 102 is specifically used to determine the conduction duration adjustment value Ton-reg based on the difference between the inductor current phase difference threshold and the actual inductor current phase difference between each conversion circuit 1012; and to superimpose the conduction duration adjustment value Ton-reg onto the reference conduction duration Ton-base to obtain the conduction duration Ton of the second pulse width modulation control signal.

[0101] The inductor current phase difference threshold refers to the ideal phase difference between the inductors of each conversion circuit 1012. If the multiphase interleaved power factor correction circuit 101 includes two conversion circuits 1012, the inductor current phase difference threshold of the conversion circuit 1012 is 180°; if the multiphase interleaved power factor correction circuit 101 includes three conversion circuits 1012, the inductor current phase difference threshold of the conversion circuit 1012 is 120°.

[0102] The conduction duration adjustment value refers to the adjustment duration of the baseline conduction duration.

[0103] Continue to refer to Figure 3A As shown, the multiphase interleaved power factor correction circuit 101 includes three conversion circuits 1012 as an example. In some examples, the controller 102 can proportionally adjust the difference between the current phase difference thresholds фref1, фref2, and фref3 (фreffi, i is 1, 2, or 3) between each conversion circuit 1012 and the corresponding actual inductor current phase differences ф1, ф2, and ф3 (фi, i is 1, 2, or 3). This can accurately capture the offset of the actual inductor current phase difference between each conversion circuit 1012 from the preset threshold. Through proportional adjustment, linear and rapid correction of the phase deviation is achieved, generating an accurate and suitable conduction time adjustment value Ton-reg.

[0104] Similar to the proportional coefficient Kp and integral coefficient Ki mentioned above, the proportional coefficient of the proportional control can also be determined based on theoretical calculations of the mathematical model of the closed-loop control system, stability requirements, and dynamic performance indicators. The embodiments in this application will not be elaborated further here.

[0105] The multiphase interleaved power factor corrector provided in this application determines the conduction duration adjustment value in real time based on the difference between the inductor current phase difference threshold and the actual inductor current phase difference between each conversion circuit. It then dynamically corrects the conduction duration using this adjustment value. This ensures that the actual inductor current phase difference between each conversion circuit remains stably within a preset phase difference threshold range, accurately guaranteeing phase reversal accuracy. Furthermore, it enables effective conversion of AC voltage signals to a first DC voltage signal, providing a foundation for the DC output of the multiphase interleaved power factor corrector. The output voltage regulator capacitor stabilizes the first DC voltage signal, suppressing voltage fluctuations and ensuring the stability of the output bus DC voltage signal. By combining the difference between the bus DC voltage signal and the output voltage reference value with the inductor current phase difference of the conversion circuits, the controller determines the conduction duration of the second pulse width modulation control signal, achieving precise voltage regulation control of the bus DC voltage while ensuring the phase reversal accuracy and current balance of each conversion circuit.

[0106] In some embodiments of this application, such as Figure 1 or Figure 2 As shown, the controller 102 is also used to turn off the second pulse width modulation control signal when the actual inductor current value of each conversion circuit 1012 is greater than or equal to the preset inductor current threshold.

[0107] The preset inductor current threshold refers to the maximum allowable limit of the inductor current of the converter circuit 1012. In some instances, the preset current inductor threshold can be set to 1.5 times or higher than the rated inductor current of the converter circuit 1012. This application embodiment does not limit the size of the preset current inductor threshold; this application embodiment uses a preset current inductor threshold of 1.5 times the rated inductor current as an example for illustrative purposes.

[0108] Continue to refer to Figure 3AAs shown, the multiphase interleaved power factor correction circuit 101 includes three conversion circuits 1012 as an example. The analog inductor currents IL1, IL2, and IL3 (such as the current amplified by an amplifier) ​​of each conversion circuit 1012 can be detected by current sensors, and converted into digital inductor currents IL-1, IL-2, and IL-3 respectively by an analog-to-digital converter (ADC). Next, a comparator compares the actual inductor current value of each conversion circuit 1012 with the corresponding preset inductor current threshold. If the actual inductor current value is greater than or equal to the preset inductor current threshold, the output of the second pulse width modulation control signal to the control terminals of the freewheeling switches HSi and LSi in the conversion circuit 1012 is stopped.

[0109] The multiphase interleaved power factor corrector provided in this application embodiment, when the preset inductor current threshold can reflect the maximum allowable limit of the inductor current of the conversion circuit, and the controller shuts off the second pulse width modulation control signal when the actual inductor current value of each conversion circuit is greater than or equal to the preset inductor current threshold, can quickly cut off the inductor current supply of that conversion circuit, realize overcurrent protection for the multiphase interleaved power factor corrector, effectively avoid inductor saturation, power device damage and other faults caused by inductor current overload, and further improve the reliability and safety of the entire multiphase interleaved power factor corrector operation.

[0110] and Figure 1 Corresponding to the multiphase interleaved power factor corrector 10 shown, this application embodiment also provides a control method for the multiphase interleaved power factor corrector, applied to, for example... Figure 1 Or the controller 102 shown in Figure 2, such as Figure 3B As shown, the control method of the multiphase interleaved power factor corrector may include the following steps 301 to 305.

[0111] Step 301: Generate a first pulse width modulation control signal with a preset frequency and a preset nominal duty cycle.

[0112] The preset frequency is the switching frequency synchronized with the AC input power frequency, and the preset nominal duty cycle is 50%. Step 302: Control the on / off state of the two main switching transistors based on the first pulse width modulation control signal.

[0113] Step 303: Determine the reference value of the inductor current based on the difference between the actual output current value of each conversion circuit and the average value of the actual output current of multiple conversion circuits.

[0114] Step 304: Based on the difference between the reference value and the actual value of the inductor current of each conversion circuit, and the phase difference of the actual inductor current between each conversion circuit, generate a second pulse width modulation control signal.

[0115] The duty cycle of the second pulse width modulation control signal is fixed, but the switching frequency is adjustable.

[0116] Step 305: Control the on / off state of the two freewheeling switches based on the second pulse width modulation control signal so that the currents of multiple conversion circuits are out of phase and balanced, and the multiphase interleaved power factor corrector outputs the DC voltage signal of the bus.

[0117] In the above Figure 3B Based on the embodiment shown, step 303 determines the inductor current reference value based on the difference between the actual output current value of each conversion circuit and the average value of the actual output current of multiple conversion circuits, which may include step 3031.

[0118] Step 3031: Perform signal conditioning and conversion processing on the difference between the actual output current value of each conversion circuit and the average value of the actual output current of multiple conversion circuits to obtain the inductor current reference value.

[0119] like Figure 4 As shown, step 3031 performs signal conditioning and conversion processing on the difference between the actual output current value of each conversion circuit and the average value of the actual output current of multiple conversion circuits to obtain the inductor current reference value, which may include the following steps 401 and 402.

[0120] Step 401: Perform proportional-integral adjustment on the difference between the actual output current value of each conversion circuit and the average value of the actual output current of multiple conversion circuits to generate an adjusted inductor current reference signal. Step 402: Perform digital-to-analog conversion on the adjusted inductor current reference signal to obtain the inductor current reference value.

[0121] like Figure 5 As shown above, in the above Figure 3B Based on the embodiment shown, step 304, which generates a second pulse width modulation control signal based on the difference between the reference value and the actual value of the inductor current of each conversion circuit and the phase difference of the actual inductor current between each conversion circuit, may include step 3041.

[0122] Step 3041: Determine the turn-off time of the second pulse width modulation control signal based on the difference between the reference value of the inductor current and the actual inductor current value of each conversion circuit.

[0123] Continue as Figure 5As shown, step 304, which generates a second pulse width modulation control signal based on the difference between the reference value and the actual value of the inductor current of each conversion circuit and the phase difference of the actual inductor current between each conversion circuit, may also include step 3042.

[0124] Step 3042: Based on the difference between the bus DC voltage signal and the output voltage reference value, and the actual inductor current phase difference between each conversion circuit, determine the conduction duration of the second pulse width modulation control signal.

[0125] like Figure 6 As shown above, in the above Figure 5 Based on the embodiment shown, step 3042 determines the conduction duration of the second pulse width modulation control signal based on the difference between the bus DC voltage signal and the output voltage reference value, as well as the actual inductor current phase difference between each conversion circuit, and may include the following steps 601 to 603.

[0126] Step 601: Perform proportional-integral adjustment on the difference between the bus DC voltage signal and the output voltage reference value to obtain the adjusted time value.

[0127] Step 602: Add the input voltage feedforward and time compensation to the adjusted time value to obtain the reference conduction duration of the second pulse width modulation control signal.

[0128] Step 603: Determine the conduction duration of the second pulse width modulation control signal based on the reference conduction duration and the actual inductor current phase difference between each conversion circuit.

[0129] like Figure 7 As shown above, in the above Figure 6 Based on the embodiment shown, step 603 determines the conduction duration of the second pulse width modulation control signal based on the reference conduction duration and the actual inductor current phase difference between each conversion circuit, and may include the following steps 701 and 702.

[0130] Step 701: Determine the conduction duration adjustment value based on the difference between the inductor current phase difference threshold and the actual inductor current phase difference between each conversion circuit.

[0131] Step 702: Add the conduction duration adjustment value to the reference conduction duration to obtain the conduction duration of the second pulse width modulation control signal.

[0132] In some embodiments of this application, step 701 determines the conduction duration adjustment value based on the difference between the inductor current phase difference threshold and the actual inductor current phase difference between each conversion circuit. This may include: proportionally adjusting the difference between the current phase difference threshold and the actual inductor current phase difference between each conversion circuit to obtain the conduction duration adjustment value.

[0133] In some embodiments of this application, the second pulse width modulation control signal is turned off when the actual inductor current value of each conversion circuit is greater than or equal to a preset inductor current threshold.

[0134] In some embodiments of this application, the control method of the multiphase interleaved power factor corrector may further include step 306. Step 306: When the actual inductor current value of each conversion circuit is greater than or equal to a preset inductor current threshold, the second pulse width modulation control signal is turned off.

[0135] The beneficial technical effects corresponding to the exemplary embodiments of the control method of the multiphase interleaved power factor corrector described above can be found in the corresponding beneficial technical effects of the embodiments of the multiphase interleaved power factor corrector described above, and will not be repeated here.

[0136] Corresponding to the aforementioned embodiments of the control method for a multiphase interleaved power factor corrector, this application also provides an embodiment of a control device for a multiphase interleaved power factor corrector. Figure 8 As shown, the control device 80 of the multiphase interleaved power factor corrector may include a generation module 801, a first control module 802, a determination module 803, a second generation module 804, and a second control module 805. The first generation module 801 is used to generate a first pulse width modulation control signal with a preset frequency and a preset nominal duty cycle. The preset frequency is the switching frequency synchronized with the AC input power frequency, and the preset nominal duty cycle is 50%. The first control module 802 is used to control the on / off state of the two main switching transistors based on the first pulse width modulation control signal; The determination module 803 is used to determine the inductor current reference value based on the difference between the actual output current value of each conversion circuit and the average actual output current value of multiple conversion circuits. The second generation module 804 is used to generate a second pulse width modulation control signal based on the difference between the reference value and the actual inductor current value of each conversion circuit, and the phase difference of the actual inductor current between each conversion circuit; wherein, the duty cycle of the second pulse width modulation control signal is fixed, but the switching frequency is adjustable.

[0137] The second control module 805 is used to control the on / off state of the two freewheeling switches based on the second pulse width modulation control signal, so that the currents of multiple conversion circuits are out of phase and balanced, and the multiphase interleaved power factor corrector outputs the DC voltage signal of the bus.

[0138] In some embodiments of this application, the determining module 803 is specifically used to perform signal conditioning and conversion processing on the difference between the actual output current value of each conversion circuit and the average value of the actual output current of multiple conversion circuits to obtain an inductor current reference value.

[0139] In some embodiments of this application, the determining module 803 is specifically used to perform proportional-integral adjustment on the difference between the actual output current value of each conversion circuit and the average value of the actual output current of multiple conversion circuits to generate an adjusted inductor current reference signal; and to perform digital-to-analog conversion on the adjusted inductor current reference signal to obtain an inductor current reference value.

[0140] In some embodiments of this application, the second generation module 804 is specifically used to determine the turn-off time of the second pulse width modulation control signal based on the difference between the reference value of the inductor current of each conversion circuit and the actual inductor current value.

[0141] In some embodiments of this application, the second generation module 804 is further configured to determine the conduction duration of the second pulse width modulation control signal based on the difference between the bus DC voltage signal and the output voltage reference value, as well as the actual inductor current phase difference between each conversion circuit.

[0142] In some embodiments of this application, the second generation module 804 is specifically used to perform proportional-integral adjustment on the difference between the bus DC voltage signal and the output voltage reference value to obtain the adjusted time value; to superimpose the input voltage feedforward amount and the time compensation amount on the adjusted time value to obtain the reference conduction duration of the second pulse width modulation control signal; and to determine the conduction duration of the second pulse width modulation control signal based on the reference conduction duration and the actual inductor current phase difference between each conversion circuit.

[0143] In some embodiments of this application, the second generation module 804 is specifically used to determine the conduction duration adjustment value based on the difference between the inductor current phase difference threshold and the actual inductor current phase difference between each conversion circuit; and to superimpose the conduction duration adjustment value on the reference conduction duration to obtain the conduction duration of the second pulse width modulation control signal.

[0144] In some embodiments of this application, the second generation module 804 is specifically used to proportionally adjust the difference between the current phase difference threshold and the actual inductor current phase difference between each conversion circuit to obtain the conduction duration adjustment value.

[0145] like Figure 9 As shown above, in the above Figure 8 Based on the illustrated embodiment, the control device 80 of the multiphase interleaved power factor corrector may include a shutdown module 805. The shutdown module 805 is used to shut down the second pulse width modulation control signal when the actual inductor current value of each conversion circuit is greater than or equal to a preset inductor current threshold.

[0146] Figure 10 This is a schematic diagram of a power supply structure provided in an embodiment of this application. Figure 10As shown, the power supply 100 includes a resonant converter 101 and, as shown, a resonant converter 101 and a resonant converter 102. Figure 1 or Figure 2 The multiphase interleaved power factor corrector 102 provided in the embodiment.

[0147] The resonant converter 101 has its input terminal coupled to the output terminal of the multiphase interleaved power factor corrector 102. It is used to perform resonant conversion processing on the bus DC voltage signal output by the multiphase interleaved power factor corrector 102 to output the target DC voltage signal.

[0148] Figure 11 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application. Figure 11 As shown, the computing device 110 includes a motherboard 111 and a... Figure 10 The power supply 100 shown is coupled to the power input terminal of the motherboard 111 and is used to supply power to the motherboard 111.

[0149] In addition to the methods and devices described above, embodiments of this application may also provide a computer program product, including computer program instructions, which, when executed by a processor, cause the processor to perform the steps in the control method of the multiphase interleaved power factor corrector of the various embodiments of this application described in the method embodiment section above.

[0150] Computer program products can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments of this application. These programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0151] Furthermore, embodiments of this application may also be computer-readable storage media storing computer program instructions thereon, which, when executed by a processor, cause the processor to perform the steps in the control method of the multiphase interleaved power factor corrector of various embodiments of this application described in the above method embodiment section.

[0152] Computer-readable storage media may take the form of any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may include, but is not limited to, systems, apparatuses, or devices that are electrical, magnetic, optical, electromagnetic, infrared, or semiconductor, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0153] The basic principles of this application have been described above with reference to specific embodiments. However, the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of each embodiment of this application. Furthermore, the specific details of the above embodiments are for illustrative and facilitative purposes only, and are not limitations. These details do not restrict this application from being implemented using the aforementioned specific details.

[0154] Those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

[0155] Furthermore, the embodiments described above are merely specific embodiments of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made based on the technical solution of this application should be included within the scope of protection of this application.

Claims

1. A multiphase interleaved power factor corrector, characterized in that, It includes a multiphase interleaved power factor correction circuit and a controller; the multiphase interleaved power factor correction circuit includes an AC input power supply, multiple conversion circuits coupled to and connected in parallel with the AC input power supply, and an output voltage regulator capacitor connected in parallel with the output terminals of the multiple conversion circuits; The conversion circuit includes two main switching transistors and two freewheeling switching transistors; The controller, coupled to the conversion circuit, is used for: A first pulse width modulation control signal with a preset frequency and a preset nominal duty cycle is generated; wherein, the preset frequency is a switching frequency synchronized with the AC input power supply frequency, and the preset nominal duty cycle is 50%; The on / off state of the two main switching transistors is controlled based on the first pulse width modulation control signal; The inductor current reference value is determined based on the difference between the actual output current value of each of the aforementioned conversion circuits and the average actual output current value of the multiple conversion circuits. Based on the difference between the reference value and the actual value of the inductor current of each of the conversion circuits, and the phase difference of the actual inductor current between the conversion circuits, a second pulse width modulation control signal is generated; wherein, the duty cycle of the second pulse width modulation control signal is fixed, but the switching frequency is adjustable; The two freewheeling switches are controlled by the second pulse width modulation control signal to make the currents of the multiple conversion circuits out of phase and balanced, and the multiphase interleaved power factor corrector outputs the DC voltage signal of the bus.

2. The multiphase interleaved power factor corrector according to claim 1, characterized in that, The controller is specifically used to perform signal conditioning and conversion processing on the difference between the actual output current value of each of the conversion circuits and the average value of the actual output current of the multiple conversion circuits to obtain the inductor current reference value.

3. The multiphase interleaved power factor corrector according to claim 2, characterized in that, The controller is specifically used for: The difference between the actual output current value of each of the aforementioned conversion circuits and the average value of the actual output current of the multiple conversion circuits is proportional-integral adjustment to generate an adjusted inductor current reference signal. The adjusted inductor current reference signal is converted from digital to analog to obtain the inductor current reference value.

4. The multiphase interleaved power factor corrector according to claim 1, characterized in that, The controller is specifically used to determine the turn-off time of the second pulse width modulation control signal based on the difference between the reference value of the inductor current and the actual inductor current value of each of the conversion circuits.

5. The multiphase interleaved power factor corrector according to claim 1, characterized in that, The conversion circuit is used to convert the AC voltage signal input from the AC input power supply into a first DC voltage signal; The output voltage regulator capacitor is coupled to the output terminal of the multiphase interleaved power factor corrector and is used to stabilize the first DC voltage signal as the bus DC voltage signal. The controller is further configured to determine the conduction duration of the second pulse width modulation control signal based on the difference between the bus DC voltage signal and the output voltage reference value, and the actual inductor current phase difference between each of the conversion circuits.

6. The multiphase interleaved power factor corrector according to claim 5, characterized in that, The controller is specifically used for: The difference between the bus DC voltage signal and the output voltage reference value is adjusted proportionally and integrally to obtain the adjusted time value. The input voltage feedforward and time compensation are superimposed on the adjusted time value to obtain the reference on-time of the second pulse width modulation control signal; The conduction duration of the second pulse width modulation control signal is determined based on the reference conduction duration and the actual inductor current phase difference between each of the conversion circuits.

7. The multiphase interleaved power factor corrector according to claim 6, characterized in that, The controller is specifically used for: The conduction duration adjustment value is determined based on the difference between the inductor current phase difference threshold and the actual inductor current phase difference between each of the aforementioned conversion circuits. The conduction duration of the second pulse width modulation control signal is obtained by superimposing the reference conduction duration with the conduction duration adjustment value.

8. The multiphase interleaved power factor corrector according to claim 7, characterized in that, The controller is specifically used for: The conduction duration adjustment value is obtained by proportionally adjusting the difference between the current phase difference threshold and the actual inductor current phase difference between each of the conversion circuits.

9. The multiphase interleaved power factor corrector according to any one of claims 1-8, characterized in that, The controller is further configured to turn off the second pulse width modulation control signal when the actual inductor current value of each of the conversion circuits is greater than or equal to the inductor current threshold.

10. A power supply, characterized in that, Includes a resonant converter and a multiphase interleaved power factor corrector as described in any one of claims 1-9; The resonant converter has its input terminal coupled to the output terminal of the multiphase interleaved power factor corrector, and is used to perform resonant conversion processing on the bus DC voltage signal output by the multiphase interleaved power factor corrector to output the target DC voltage signal.

11. A computing device, characterized in that, Includes the motherboard and the power supply as described in claim 10; The power supply has its output terminal coupled to the power input terminal of the motherboard and is used to supply power to the motherboard.

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