A voltage generating system circuit applied to an analog switch

Abstract

The application relates to a voltage generation system circuit applied to an analog switch. The voltage generation system circuit comprises a band-gap reference voltage generation circuit for outputting a band-gap reference output voltage VBGR with threshold compensation; a charge pump voltage generation circuit for generating non-overlapping clocks CKP~CKN input to a multi-stage charge pump circuit through a clock generation digital circuit, and the peak-peak value of the clock signals of the input non-overlapping clocks CKP~CKN is the voltage domain where a digital clock driving stage is located; and a charge pump output voltage is generated through the multi-stage charge pump circuit and input to an analog negative feedback loop, so that the charge pump output voltage is adjustable and serves as a control voltage of the analog switch. The band-gap reference voltage with threshold compensation solves the problem of large on-resistance variation caused by process corner deviation; the adjustable output voltage of the charge pump solves the problem of the charge pump output voltage being lower than an expected value caused by charge sharing effect, and the design requirement of the analog switch control voltage is met.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to a voltage generation system circuit for analog switches. Background Technology

[0002] Voltage generation system circuits, including bandgap references and charge pumps, are widely used in analog switches, A / D converters, D / A converters, power management chips, and other devices. Their purpose is to provide stable and accurate internal high voltages for core analog circuits. As the core device in the analog signal path, the conduction performance of the switching MOSFET directly depends on the stability and accuracy of the control voltage. If the control voltage drifts due to temperature, process variations, or power supply fluctuations, it will cause significant changes in the on-resistance of the analog switch, and may even degrade the signal transmitted throughout the system. Therefore, a high-performance voltage generation system circuit is crucial for improving the performance of analog switches.

[0003] To meet the demands of high-performance analog switches, researching high-performance voltage generation system circuits is of great significance. In bandgap reference circuit design, traditional op-amp-less bandgap reference voltage generation circuits, such as... Figure 1 As shown, a traditional bandgap reference voltage generation circuit aims to generate a reference voltage independent of conditions such as temperature and supply voltage. Its core design idea is to utilize the positive temperature coefficient current (IPTAT) generated by the bandgap circuit falling across resistor Rm2 to produce a positive temperature coefficient voltage, which is then compared with the base-emitter voltage (Vt) of a bipolar transistor with a negative temperature coefficient. BE They compensate for each other to achieve zero temperature coefficient output voltage.

[0004] The generated IPTAT current is:

[0005] Where V T For thermal voltage, ΔV BE =V BE2 -V BE1 N is the ratio of the emitter areas of bipolar transistors Qm1 and Qm2.

[0006] The generated zero temperature coefficient output voltage:

[0007] Since the formula for the on-resistance of an analog switch in the deep linear region is:

[0008] Where μ n C represents the carrier mobility. ox The gate oxide capacitance per unit area is represented by W / L, which represents the width-to-length ratio of the transistor. TH V represents the threshold voltage of the transistor. sV represents the source voltage of a transistor. G This indicates the gate voltage of the transistor.

[0009] As can be seen from the above equation, the analog switch on-resistance Ron has a threshold voltage V. TH The zero-temperature coefficient output voltage generated by the conventional op-amp-less bandgap reference voltage generation circuit, after being processed by circuits such as a charge pump, is used as the analog switch gate control voltage (i.e., V in the above equation). G The amplified bandgap reference output voltage will exhibit a situation where the core indicator, on-resistance, fluctuates drastically with process angle deviations, therefore it is not suitable for analog switching circuits.

[0010] In the design of charge pump circuits, cross-coupled charge pump circuits are typically used, such as... Figure 2 The diagram shown is a typical circuit diagram of a single-stage cross-coupled charge pump. This circuit uses CP-IN as input and operates under the drive of a differential clock signal. Ideally, V can be obtained at the output CP-OUT terminal. IN +V CK-PP The voltage (peak-to-peak value of the clock signal). The specific working principle is as follows: Initially, assume the voltages at nodes A, B, and CP-OUT are all 0, CKN=0, CKP=VDD, and CP-IN=VDD. At the next moment, when CKN becomes VDD and CKP becomes 0, the voltage at node B becomes VDD, turning on transistor NM0. CP-IN charges node A, and the voltage at node A becomes VDD. At this time, neither of the two P transistors is conducting. At the next moment, when CKN becomes 0 and CKP becomes VDD, the voltage at point A becomes 2VDD, turning on transistor NM1. CP-IN charges node B, and the voltage at node B becomes VDD. At this time, PM0 turns on, and node A shares charge with the output node CP-OUT.

[0011]

[0012] At this point, the voltage at node A also becomes this value. However, in reality, as node A transfers charge to the output node, its voltage gradually decreases. PM0 will cut off at a certain moment, at which point the charge transfer process stops. Overall, the voltage at the output node increases. At the next moment, when CKP becomes 0 and CKN becomes VDD, the voltage at point B becomes 2VDD, turning on NM0. CP-IN charges node A, and the voltage at node A becomes VDD. At this time, PM1 turns on, and node B shares charge with the output node, continuing to transfer charge to the output, increasing the voltage at the output node. This process repeats continuously until the output voltage reaches 2VDD, at which point charge sharing ceases, and the circuit is in a relatively stable state.

[0013] However, this structure has some obvious problems. First, the output voltage of the charge pump cannot be freely controlled; the output voltage can only be the peak-to-peak value of the input voltage plus the clock signal voltage. Second, due to the charge sharing effect, the output voltage of the charge pump is lower than the expected value, thus failing to meet the design requirements of the analog switch control voltage.

[0014] In summary, the existing technology has the following main drawbacks: While traditional bandgap reference voltage generation circuits can output a zero-temperature coefficient voltage, the voltage processed by circuits such as charge pumps, when used as analog switch control voltage, exhibits significant fluctuations in the on-resistance, a key performance indicator, due to process angle variations. Therefore, they are not suitable for analog switch circuits. Traditional cross-coupled charge pumps, although simple in structure and low in power consumption, cannot freely control the output voltage, and the output voltage often falls below the expected value, thus failing to meet the design requirements for analog switch control voltages.

[0015] Therefore, there is an urgent need for this invention to propose a voltage generation system circuit for analog switches to solve the above-mentioned technical problems. Summary of the Invention

[0016] The purpose of this invention is to provide a voltage generation system circuit for analog switches. When the bandgap reference voltage with threshold compensation is processed by the circuit and used as the control voltage of the analog switch, the threshold term in the on-resistance of the analog switch can be compensated, thereby solving the problem of large changes in on-resistance caused by process corner deviation. By adopting a charge pump voltage generation system with analog feedback loop, the output voltage is adjustable, and the problem of the charge pump output voltage being lower than the expected value due to charge sharing effect is solved, thus meeting the design requirements of analog switch control voltage.

[0017] To solve the above-mentioned technical problems, the present invention provides a voltage generation system circuit applied to an analog switch, comprising: A bandgap reference voltage generation circuit is used to output a bandgap reference output voltage VBGR with threshold compensation; a threshold voltage for compensation is provided by adding a diode-connected NMOS transistor to the bandgap reference voltage output branch; the temperature coefficient is balanced by adjusting the resistance value of the resistor in the bandgap reference voltage output branch. The charge pump voltage generation circuit includes an analog negative feedback loop, a clock generation digital circuit, and a multi-stage charge pump circuit. The positive input terminal Y of the analog negative feedback loop is connected to the bandgap reference output voltage VBGR, the negative input terminal X is connected to the feedback terminal, and the output terminal Z outputs an adaptive voltage value as the voltage domain of the digital clock driver stage of the clock generation digital circuit. The clock generation digital circuit generates non-overlapping clocks CKP~CKN, which are input to the multi-stage charge pump circuit, and the peak-to-peak value of the clock signals of the non-overlapping clocks CKP~CKN is the voltage domain of the digital clock driver stage. The multi-stage charge pump circuit generates a charge pump output voltage Vcp and inputs it to the analog negative feedback loop to make the charge pump output voltage Vcp adjustable and serve as the control voltage for the analog switch.

[0018] Preferably, the bandgap reference voltage generation circuit includes: a PTAT current generation branch and a bandgap reference voltage output branch; the PTAT current generation branch is used to generate a PTAT current and mirror the PTAT current to the bandgap reference voltage output branch, so that the bandgap reference voltage output branch generates a bandgap reference output voltage VBGR with threshold compensation.

[0019] Preferably, the PTAT current generating branch includes: PMOS transistors P1~P4, NMOS transistors N1~N4, resistors R1, resistors R3~R4, and PNP transistors Q1~Q2; the sources of PMOS transistors P1~P2 are connected to the power supply VDD, and their gates are connected to the drain of PMOS transistor P3 and one end of resistor R3; the drain of PMOS transistor P1 is connected to the source of PMOS transistor P3; the other end of resistor R3 is connected to the gate of PMOS transistors P3~P4 and the drain of NMOS transistor N3; the source of NMOS transistor N3 is connected to the drain of NMOS transistor N1; the source of NMOS transistor N1 is connected to one end of resistor R1 and forms node X'; the resistor R1... The other end is connected to the emitter of PNP transistor Q1, and the base and collector of PNP transistor Q1 are grounded to GND; the gate of NMOS transistor N1 is connected to the gate of NMOS transistor N2, the drain of NMOS transistor N4, and one end of resistor R4; the source of NMOS transistor N2 is connected to the emitter of PNP transistor Q2 to form node Y'; the base and collector of PNP transistor Q2 are grounded to GND; the drain of NMOS transistor N2 is connected to the source of NMOS transistor N4; the gate of NMOS transistor N4 is connected to the gate of NMOS transistor N3, the drain of PMOS transistor P4, and the other end of resistor R4; the source of PMOS transistor P4 is connected to the drain of PMOS transistor P2.

[0020] Preferably, the bandgap reference voltage output branch includes: PMOS transistors P5~P6, resistor R2, PNP transistor Q3, and NMOS transistor M0; the source of PMOS transistor P5 is connected to power supply VDD, and its gate is connected to the gate of PMOS transistors P1~P2; the drain of PMOS transistor P5 is connected to the source of PMOS transistor P6, and the gate of PMOS transistor P6 is connected to the gate of PMOS transistors P3~P4; the drain of PMOS transistor P6 is connected to one end of resistor R2 and serves as the output terminal to output the bandgap reference output voltage VBGR; the other end of resistor R2 is connected to the emitter of PNP transistor Q3, the base and collector of PNP transistor Q3 are connected to the gate and drain of NMOS transistor M0, and the source of NMOS transistor M0 is grounded to GND.

[0021] Preferably, the simulated negative feedback loop includes: The feedback voltage divider circuit includes: NMOS transistors M1~M3 and a current drain I1; one end of the current drain I1 is grounded to GND, and the other end is connected to the source of NMOS transistor M1; the gate of NMOS transistor M1 is connected to the drain of NMOS transistor M2 and the source of NMOS transistor M3, and the drain of NMOS transistor M1 is connected to the source of NMOS transistor M2 to form node X2; the gate of NMOS transistor M2, and the gate and drain of NMOS transistor M3 are connected to the output voltage Vcp of the charge pump. The operational amplifier circuit OPA has its positive input terminal Y connected to the bandgap reference output voltage VBGR, its negative input terminal X connected to the source of the NMOS transistor M1, and its output terminal Z outputting the adaptive voltage value.

[0022] Preferably, the operational amplifier circuit OPA includes: NMOS transistors N11-N15, PMOS transistors P11-P13, capacitor C0, and current source I2; the sources of the PMOS transistors P11-P13 are connected to the power supply VDD, the gate and drain of the PMOS transistor P11 are connected to the gate of the PMOS transistor P12, and the drain of the NMOS transistor N11; the gate of the NMOS transistor N11 serves as the negative input terminal X of the operational amplifier circuit OPA, the source of the NMOS transistor N11 is connected to the source of the NMOS transistor N12 and the drain of the NMOS transistor N13, and the current source of the NMOS transistor N12... The gate serves as the positive input terminal Y of the operational amplifier circuit OPA; the drain of the NMOS transistor N12 is connected to the drain of the PMOS transistor P12, the gate of the PMOS transistor P13, and one end of the capacitor C0; the drain of the PMOS transistor P13 is connected to the other end of the capacitor C0 and the drain of the NMOS transistor N14, serving as the output terminal Z of the operational amplifier circuit OPA; the gate of the NMOS transistor N14 is connected to the gate of the NMOS transistor N13, the gate and drain of the NMOS transistor N15, and the current source I2 connected to the power supply VDD; the sources of the NMOS transistors N13~N15 are grounded to GND.

[0023] Preferably, the clock generating digital circuit includes: inverters INV1~INV4 and NAND1~NAND2; the input terminal of inverter INV1 is connected to the clock signal CK, and the output terminal is connected to the input terminal of inverter INV2 and the first input terminal of NAND1; the output terminal of inverter INV2 is connected to the first input terminal of NAND2, the output terminal of NAND2 is connected to the second output terminal of NAND1 and the input terminal of inverter INV4; the output terminal of inverter INV4 outputs the non-overlapping clock CKP; the output terminal of NAND1 is connected to the second output terminal of NAND2 and the input terminal of inverter INV3, and the output terminal of inverter INV3 outputs the non-overlapping clock CKN; inverters INV3~INV4 serve as the digital clock driving stage, and their power supply terminals are connected to the output terminal Z of the analog negative feedback loop.

[0024] Preferably, the multi-stage charge pump circuit includes three cascaded charge pump modules CP1 to CP3; the input terminal of charge pump module CP1 is connected to the power supply VDD, the output terminal is connected to the input terminal of charge pump module CP2, the output terminal of charge pump module CP2 is connected to the input terminal of charge pump module CP3, and the output terminal of charge pump module CP3 serves as the output terminal of the multi-stage charge pump circuit, outputting the charge pump output voltage Vcp; the non-overlapping clock terminals of charge pump modules CP1 to CP3 are respectively connected to the non-overlapping clocks CKP to CKN.

[0025] Preferably, the charge pump modules CP1~CP3 all adopt a cross-coupled charge pump structure, including: PMOS transistors P21~P22, NMOS transistors N21~N22, and capacitors C1~C2; the source of the NMOS transistors N21~N22 serves as the input terminal CP_IN of the cross-coupled charge pump structure; the drain of the NMOS transistor N21 is connected to one end of capacitor C1, the drain of PMOS transistor P21, and the gates of PMOS transistors P22 and NMOS transistor N22 to form node A, and the other end of capacitor C1 is connected to a non-overlapping clock CKP; the gate of the NMOS transistor N21 is connected to one end of capacitor C2, the drains of NMOS transistors N22 and PMOS transistor P22, and the gate of PMOS transistor P21 to form node B, and the other end of capacitor C2 is connected to a non-overlapping clock CKN; the source of the PMOS transistors P21~P22 serves as the output terminal CP_OUT of the cross-coupled charge pump structure.

[0026] The present invention also provides an analog switch, employing a voltage generation system circuit for an analog switch as described above.

[0027] Compared with the prior art, the present invention has the following beneficial effects: This invention addresses the problem of on-resistance fluctuations caused by threshold terms in traditional voltage generation systems due to process angle deviations. Firstly, it utilizes a threshold compensation mechanism in a bandgap reference voltage generation circuit with threshold compensation function to simulate the on-resistance of a switching circuit. Secondly, it satisfies the threshold term in the on-resistance by generating a charge pump output voltage based on a feedback voltage divider circuit, thus providing the gate control voltage for the analog switch. Furthermore, by adjusting the current in the feedback voltage divider circuit, the output charge pump voltage can be controlled to meet relevant application requirements. Finally, the presence of the analog feedback loop solves the problem of the charge pump output voltage being lower than expected due to charge sharing effects. Attached Figure Description

[0028] Figure 1 A circuit diagram for generating a conventional bandgap reference voltage, provided for existing technologies.

[0029] Figure 2 A circuit diagram of a conventional single-stage cross-coupled charge pump provided for existing technology.

[0030] Figure 3 The present invention provides a circuit diagram for generating a bandgap reference voltage with threshold compensation function.

[0031] Figure 4 The present invention provides a circuit diagram of a charge pump voltage generation circuit using an analog feedback loop.

[0032] Figure 5The circuit diagram of the operational amplifier provided for this invention.

[0033] Figure 6 The circuit diagram of the single-stage charge pump module provided by the present invention. Detailed Implementation

[0034] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0035] like Figure 3 and Figure 4 As shown, this embodiment of the invention specifically provides a voltage generation system circuit applied to an analog switch, including: A bandgap reference voltage generation circuit is used to output a bandgap reference output voltage VBGR with threshold compensation; a threshold voltage for compensation is provided by adding a diode-connected NMOS transistor to the bandgap reference voltage output branch; the temperature coefficient is balanced by adjusting the resistance value of the resistor in the bandgap reference voltage output branch. The charge pump voltage generation circuit includes an analog negative feedback loop, a clock generation digital circuit, and a multi-stage charge pump circuit. The positive input terminal Y of the analog negative feedback loop is connected to the bandgap reference output voltage VBGR, the negative input terminal X is connected to the feedback terminal, and the output terminal Z outputs an adaptive voltage value as the voltage domain of the digital clock driver stage of the clock generation digital circuit. The clock generation digital circuit generates non-overlapping clocks CKP~CKN, which are input to the multi-stage charge pump circuit, and the peak-to-peak value of the clock signals of the non-overlapping clocks CKP~CKN is the voltage domain of the digital clock driver stage. The multi-stage charge pump circuit generates a charge pump output voltage Vcp and inputs it to the analog negative feedback loop to make the charge pump output voltage Vcp adjustable and serve as the control voltage for the analog switch.

[0036] Continue reading Figure 3As shown, the bandgap reference voltage generation circuit includes a PTAT current generation branch and a bandgap reference voltage output branch. The PTAT current generation branch includes constant voltage PMOS transistors P1, P2, P3, and P4, constant voltage NMOS transistors N1, N2, N3, and N4, resistors R1, R3, and R4, and PNP transistors Q1 and Q2. In the PTAT current generation branch, the sources of the constant-voltage PMOS transistors P1 and P2 are connected to the power supply VDD; the gates of the constant-voltage PMOS transistors P1 and P2 are connected to the upper end of resistor R3; the drain of the constant-voltage PMOS transistor P1 is connected to the source of the constant-voltage PMOS transistor P3; the drain of the constant-voltage PMOS transistor P2 is connected to the source of the constant-voltage PMOS transistor P4; the gates of the constant-voltage PMOS transistors P3 and P4 are connected to the lower end of resistor R3; the drain of the constant-voltage PMOS transistor P3 is connected to the upper end of resistor R3; the drain of the constant-voltage PMOS transistor P4 is connected to the upper end of resistor R4; the drain of the constant-voltage NMOS transistor N3 is connected to the lower end of resistor R3; the drain of the constant-voltage NMOS transistor N4 is connected to the lower end of resistor R4; and the constant-voltage N... The gates of MOSFETs N3 and N4 are connected to the upper end of resistor R4. The source of N3 is connected to the drain of N1. The source of N4 is connected to the drain of N2. The gates of N1 and N2 are connected to the lower end of resistor R4. The source of N1 is connected to the upper end of resistor R1 to form node X'. The source of N2 is connected to the emitter of PNP transistor Q2 to form node Y'. The emitter of PNP transistor Q1 is connected to the lower end of resistor R1. The base and collector of PNP transistor Q1 are connected to GND. The base and collector of PNP transistor Q2 are connected to GND.

[0037] The bandgap reference voltage generation branch includes constant-voltage PMOS transistors P5 and P6, resistor R2, PNP transistor Q3, and constant-voltage NMOS transistor M0. In this branch, the source of constant-voltage PMOS transistor P5 is connected to the power supply VDD; the gate of P5 is connected to the gates of constant-voltage PMOS transistors P1 and P2; the drain of P5 is connected to the source of constant-voltage PMOS transistor P6; the gate of P6 is connected to the gates of constant-voltage PMOS transistors P3 and P4; the drain of P6 is connected to the upper end of resistor R2 and outputs the bandgap reference voltage VBGR; the emitter of PNP transistor Q3 is connected to the lower end of resistor R2; the base and collector of PNP transistor Q3 are connected to the drain and gate of constant-voltage NMOS transistor M0; and the source of NMOS transistor M0 is connected to GND.

[0038] The present invention also includes the following working principle: Compared to traditional bandgap reference voltage generation circuits, this invention adds a diode-connected NMOS transistor M0 to the output voltage branch to provide a threshold voltage for compensation. The temperature coefficient can be balanced by adjusting the value of resistor R2. The specific working principle is as follows: When the dimensions of PMOS transistors P1, P2, and P5, P3, P4, and P6 are the same, and the dimensions of NMOS transistors N3 and N4, as well as NMOS transistors N1 and N2, are the same, a common-source, common-gate current mirror structure is formed by P1, P2, and P5, and P3, P4, and P6. This makes the branch currents I1, I2, and I3 of PNP transistors Q1, Q2, and Q3 equal. Therefore, the voltage values ​​at nodes X' and Y' are the same, and the parallel ratio of PNP transistors Q1 and Q2 is N. When the branch currents I1 and I2 are equal, the voltage drop across resistor R1 is the difference between the base-emitter voltage of PNP transistor Q2 and the base-emitter voltage of PNP transistor Q1. As shown in the following formula:

[0039] Where V T This is thermal voltage.

[0040] Therefore, we can conclude that I1=I2=I3=I PTAT :

[0041] At this time, the bandgap reference output voltage VBGR is:

[0042] Where V OV The overdrive voltage is expressed as follows:

[0043] From the above expression for the bandgap reference output voltage VBGR, it can be concluded that the temperature coefficient-compensated bandgap reference output voltage can be achieved by adjusting the value of resistor R2.

[0044] The bandgap reference output voltage in this invention is applied in analog switching circuits, and the formula for the on-resistance of the analog switch in the deep linear region is:

[0045] As can be seen from the above formula, there is a threshold voltage V for the on-resistance of the analog switch. THBecause process angle deviations can cause drastic fluctuations in the on-resistance, a core indicator in analog switch circuits, the threshold-compensated bandgap reference voltage of this invention, after circuit processing, can be used as the gate voltage of the analog switch. This compensates for the threshold term in the on-resistance of the analog switch, thereby reducing the drastic fluctuations in on-resistance due to process angle variations. The specific formula is as follows:

[0046] The gate control voltage of the analog switch is From the bandgap reference output voltage, we can derive:

[0047] The above derivation shows that the bandgap reference output voltage with threshold compensation can compensate for the threshold term in the on-resistance, but because... The existence of the coefficient does not fully compensate for the loss, and if To achieve the amplification ratio through resistor voltage division, it is also necessary that 1 < <2, if If the coefficient is greater than 2, it will not only fail to achieve the threshold compensation function, but will also further worsen the phenomenon of the on-resistance fluctuating with the process angle deviation. Therefore, the present invention adopts the feedback voltage divider circuit in the analog feedback loop charge pump voltage generation system to solve this problem.

[0048] Continue reading Figure 4 As shown, the simulated negative feedback loop includes a feedback voltage divider circuit and an operational amplifier circuit (OPA). The feedback voltage divider circuit includes constant-voltage NMOS transistors M1, M2, and M3, and a current drain I1. In the feedback voltage divider circuit, the source of the constant-voltage NMOS transistor M1 is connected to the X terminal of the operational amplifier circuit (OPA) and the current drain I1. The gate of the constant-voltage NMOS transistor M1 is connected to the drain of the constant-voltage NMOS transistor M2 and the source of the constant-voltage NMOS transistor M3. The drain of the constant-voltage NMOS transistor M1 is connected to the source of the constant-voltage NMOS transistor M2, forming node X2. The gates of the constant-voltage NMOS transistors M2 and M3, and the drain of the constant-voltage NMOS transistor M3 are connected to the charge pump output voltage Vcp of the three-stage charge pump circuit.

[0049] like Figure 5As shown, the operational amplifier circuit OPA includes constant-voltage NMOS transistors N11, N12, N13, and N14, constant-voltage PMOS transistors P11, P12, and P13, and capacitor C0. In the operational amplifier circuit OPA, the sources of constant-voltage PMOS transistors P11, P12, and P13 are connected to the power supply VDD. The gates of constant-voltage PMOS transistors P11 and P12 are connected to the drain of constant-voltage PMOS transistor P11 and the drain of constant-voltage NMOS transistor N11. The drain of constant-voltage PMOS transistor P12 is connected to the drain of constant-voltage NMOS transistor N12, capacitor C0, and the gate of constant-voltage PMOS transistor P13. The drain of constant-voltage PMOS transistor P13 is connected to capacitor C0... The drain of the constant voltage NMOS transistor N14 is connected to the ground, the gate of the constant voltage NMOS transistor N11 is connected to the X terminal of the feedback voltage divider circuit, the source of the constant voltage NMOS transistors N11 and N12 is connected to the drain of the constant voltage NMOS transistor N13, the gate of the constant voltage NMOS transistor N12 is connected to the external bandgap reference output voltage, the gate of the constant voltage NMOS transistors N13 and N14 is connected to the gate of the external current source circuit, and the source of the constant voltage NMOS transistors N13 and N14 is connected to ground GND.

[0050] The aforementioned external current source circuit includes an NMOS transistor N15 and a current source I2; the gate of the NMOS transistor N14 is connected to the gate of the NMOS transistor N13, the gate and drain of the NMOS transistor N15, and the current source I2 connected to the power supply VDD; the source of the NMOS transistor N15 is grounded to GND.

[0051] Continue reading Figure 4 As shown, the clock generating digital circuit includes: inverters INV1~INV4 and NAND1~NAND2; the input terminal of inverter INV1 is connected to the clock signal CK, and the output terminal is connected to the input terminal of inverter INV2 and the first input terminal of NAND1; the output terminal of inverter INV2 is connected to the first input terminal of NAND2, the output terminal of NAND2 is connected to the second output terminal of NAND1 and the input terminal of inverter INV4; the output terminal of inverter INV4 outputs the non-overlapping clock CKP; the output terminal of NAND1 is connected to the second output terminal of NAND2 and the input terminal of inverter INV3, and the output terminal of inverter INV3 outputs the non-overlapping clock CKN; inverters INV3~INV4 serve as the digital clock driving stage, and their power supply terminals are connected to the output terminal Z of the analog negative feedback loop.

[0052] Continue reading Figure 4 He Ru Figure 6As shown, the three-stage charge pump circuit includes charge pump modules CP1, CP2, and CP3, wherein the charge pump module circuit includes constant voltage NMOS transistors N21 and N22, constant voltage PMOS transistors P21 and P22, and capacitors C1 and C2. In the charge pump module circuit, the sources of constant voltage PMOS transistors P21 and P22 are connected to the charge pump module output CP_OUT. The gate of constant voltage PMOS transistor P21 is connected to the drain of constant voltage PMOS transistor P22, capacitor C2, the drain of constant voltage NMOS transistor N22, and the gate of constant voltage NMOS transistor N21. The drain of constant voltage PMOS transistor P21 is connected to the gate of constant voltage PMOS transistor P22, capacitor C1, the drain of constant voltage NMOS transistor N21, and the gate of constant voltage NMOS transistor N22. Capacitor C1 is connected to the output clock signal CKP of the charge pump clock generation digital circuit. Capacitor C2 is connected to the output clock signal CKN of the charge pump clock generation digital circuit. The drains of constant voltage NMOS transistors N21 and N22 are connected to the charge pump module input CP_IN.

[0053] The present invention also includes the following working principle: Compared to traditional cross-coupled charge pump circuits, the charge pump voltage generation system using an analog feedback loop in this invention provides adjustable output voltage and solves the problem of charge pump output voltage falling below the expected value due to charge sharing effect. The specific working principle is as follows: In the three-stage charge pump circuit, the charge pump module circuit is a single-stage cross-coupled charge pump module. A higher charge pump output voltage is obtained through three-stage cascading. The connection relationship is as follows: the input of charge pump module CP1 is the power supply voltage VDD; the output of charge pump module CP1 is the input of charge pump module CP2; the output of charge pump module CP2 is the input of charge pump module CP3; and the output of charge pump module CP3 is the output of the three-stage charge pump circuit. As can be seen from the above traditional single-stage cross-coupled charge pump, the charge pump output voltage is strongly correlated with the peak-to-peak value of the input clock signal, which is the voltage domain of the digital clock driver stage. This invention processes the externally generated clock signal CK through a clock generation digital circuit and uses it as the input non-overlapping clocks CKP and CKN of the three-stage charge pump circuit. Its peak-to-peak value is the voltage value of the adaptive output of the analog feedback loop. The output voltage of the three-stage charge pump circuit is used as the power supply voltage of the feedback voltage divider circuit. The operational amplifier circuit clamps the potential at the X terminal to the potential at the Y terminal through a negative feedback mechanism, which is the bandgap reference output voltage with threshold compensation. The output of the operational amplifier circuit is used as the power supply voltage of the digital clock driver stage, i.e., the peak-to-peak value of the input clock signal.

[0054] As can be seen from the above, if Figure 4 The feedback voltage divider circuit uses a resistor voltage divider method. The amplification ratio is achieved through resistive voltage division, because The existence of the term coefficient cannot completely compensate for the threshold term in the on-resistance, and if... If the term coefficient is greater than 2, not only will the threshold compensation function not be achieved, but it will also further worsen the phenomenon of on-resistance fluctuation with process angle deviation caused by the threshold term. Therefore, this invention adopts a MOS transistor voltage divider circuit structure as follows: Figure 4 As shown.

[0055] Its working principle is as follows: When M1 and M3 are operating in the saturation region, and M2 is operating in the linear region, for M1 and M3:

[0056]

[0057] For M2:

[0058] Here we can consider V TH1 =V TH2 =V TH3 =V TH And obviously I D1 =I D2 =I D3 .

[0059] To build V DS2 =V GS3 -V TH Then it is necessary to:

[0060] From the above formula, we can derive:

[0061] When V GS1 =V GS3 Then, we can conclude that:

[0062] That is, the drain-source voltage of M1 is the threshold voltage of the NMOS transistor.

[0063] When the aforementioned feedback voltage divider circuit is applied to a charge pump voltage generation system with an analog feedback loop, the operational amplifier circuit (OPA) clamps the potential at the X terminal to the potential at the Y terminal through a negative feedback mechanism, resulting in a bandgap reference output voltage with threshold compensation. This can be seen from the above equation. Figure 4 The voltage at node X2 in the feedback voltage divider circuit is:

[0064] Therefore, it can be concluded that in the feedback voltage divider circuit:

[0065] That is, the output voltage of the charge pump at this time is:

[0066] Since the output of the operational amplifier circuit is used as the clock to generate the power supply voltage of the digital clock drive stage in the digital circuit, the amplitude of the non-overlapping clocks CKP and CKN input to the charge pump can be controlled through the analog feedback loop to satisfy the power supply voltage of the feedback voltage divider circuit mentioned above, i.e., the output voltage of the charge pump.

[0067] By adjusting the current of the feedback voltage divider circuit, the output charge pump voltage can be controlled to meet the relevant application requirements. Furthermore, due to the existence of the analog feedback loop, the problem of the charge pump output voltage being lower than expected due to the charge sharing effect is solved.

[0068] This invention relates to a voltage generation system circuit for analog switches, using the output voltage of this charge pump as the control voltage for the analog switch.

[0069] The above equation shows that the gate control voltage of the analog switch at this point only has a term equal to the threshold voltage, thus resolving the issue mentioned above. The presence of a term coefficient cannot fully compensate for the threshold term in the on-resistance. In this case, the on-resistance value is:

[0070] The above μ n C represents the carrier mobility. ox The gate oxide capacitance per unit area is represented by W / L, which represents the width-to-length ratio of the transistor. TH V represents the threshold voltage of the transistor. GS V represents the gate-source voltage of a transistor. DS V represents the drain-source voltage of a transistor. G V represents the gate voltage of a transistor. S This represents the source voltage of the transistor.

[0071] In summary, the present invention comprises a bandgap reference voltage generation circuit with threshold compensation function and a charge pump voltage generation system using an analog feedback loop, which together form a voltage generation system circuit applied to an analog switch. This provides the gate control voltage for the analog switch and solves the problem of on-resistance fluctuation with process angle deviation caused by the threshold term in traditional voltage generation systems.

[0072] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A voltage generation system circuit for analog switches, characterized in that, include: A bandgap reference voltage generation circuit is used to output a bandgap reference output voltage VBGR with threshold compensation; a threshold voltage for compensation is provided by adding a diode-connected NMOS transistor to the bandgap reference voltage output branch; the temperature coefficient is balanced by adjusting the resistance value of the resistor in the bandgap reference voltage output branch. The charge pump voltage generation circuit includes an analog negative feedback loop, a clock generation digital circuit, and a multi-stage charge pump circuit. The positive input terminal Y of the analog negative feedback loop is connected to the bandgap reference output voltage VBGR, the negative input terminal X is connected to the feedback terminal, and the output terminal Z outputs an adaptive voltage value as the voltage domain of the digital clock driver stage of the clock generation digital circuit. The clock generation digital circuit generates non-overlapping clocks CKP~CKN, which are input to the multi-stage charge pump circuit, and the peak-to-peak value of the clock signals of the non-overlapping clocks CKP~CKN is the voltage domain of the digital clock driver stage. The multi-stage charge pump circuit generates a charge pump output voltage Vcp and inputs it to the analog negative feedback loop to make the charge pump output voltage Vcp adjustable and serve as the control voltage for the analog switch.

2. The voltage generation system circuit for analog switches as described in claim 1, characterized in that, The bandgap reference voltage generation circuit includes a PTAT current generation branch and a bandgap reference voltage output branch. The PTAT current generation branch is used to generate a PTAT current and mirror the PTAT current to the bandgap reference voltage output branch, so that the bandgap reference voltage output branch generates a bandgap reference output voltage VBGR with threshold compensation.

3. The voltage generation system circuit for analog switches as described in claim 2, characterized in that, The PTAT current generation branch includes: PMOS transistors P1~P4, NMOS transistors N1~N4, resistors R1, resistors R3~R4, and PNP transistors Q1~Q2; the sources of PMOS transistors P1~P2 are connected to the power supply VDD, and their gates are connected to the drain of PMOS transistor P3 and one end of resistor R3. The drain of PMOS transistor P1 is connected to the source of PMOS transistor P3. The other end of resistor R3 is connected to the gates of PMOS transistors P3~P4 and the drain of NMOS transistor N3. The source of NMOS transistor N3 is connected to the drain of NMOS transistor N1. The source of NMOS transistor N1 is connected to one end of resistor R1 and forms node X'. The other end of resistor R1... The emitter of PNP transistor Q1 is connected to the PNP transistor, and the base and collector of PNP transistor Q1 are grounded to GND. The gate of NMOS transistor N1 is connected to the gate of NMOS transistor N2, the drain of NMOS transistor N4, and one end of resistor R4. The source of NMOS transistor N2 is connected to the emitter of PNP transistor Q2 to form node Y'. The base and collector of PNP transistor Q2 are grounded to GND. The drain of NMOS transistor N2 is connected to the source of NMOS transistor N4. The gate of NMOS transistor N4 is connected to the gate of NMOS transistor N3, the drain of PMOS transistor P4, and the other end of resistor R4. The source of PMOS transistor P4 is connected to the drain of PMOS transistor P2.

4. The voltage generation system circuit for analog switches as described in claim 3, characterized in that, The bandgap reference voltage output branch includes: PMOS transistors P5~P6, resistor R2, PNP transistor Q3, and NMOS transistor M0; the source of PMOS transistor P5 is connected to power supply VDD, and its gate is connected to the gate of PMOS transistors P1~P2; the drain of PMOS transistor P5 is connected to the source of PMOS transistor P6, and the gate of PMOS transistor P6 is connected to the gate of PMOS transistors P3~P4; the drain of PMOS transistor P6 is connected to one end of resistor R2 and serves as the output terminal to output the bandgap reference output voltage VBGR; the other end of resistor R2 is connected to the emitter of PNP transistor Q3, and the base and collector of PNP transistor Q3 are connected to the gate and drain of NMOS transistor M0, respectively; the source of NMOS transistor M0 is grounded to GND.

5. The voltage generation system circuit for analog switches as described in claim 1, characterized in that, The simulated negative feedback loop includes: The feedback voltage divider circuit includes: NMOS transistors M1~M3 and a current drain I1; one end of the current drain I1 is grounded to GND, and the other end is connected to the source of NMOS transistor M1; the gate of NMOS transistor M1 is connected to the drain of NMOS transistor M2 and the source of NMOS transistor M3, and the drain of NMOS transistor M1 is connected to the source of NMOS transistor M2 to form node X2; the gate of NMOS transistor M2, and the gate and drain of NMOS transistor M3 are connected to the output voltage Vcp of the charge pump. The operational amplifier circuit OPA has its positive input terminal Y connected to the bandgap reference output voltage VBGR, its negative input terminal X connected to the source of the NMOS transistor M1, and its output terminal Z outputting the adaptive voltage value.

6. The voltage generation system circuit for analog switches as described in claim 5, characterized in that, The operational amplifier circuit OPA includes: NMOS transistors N11-N15, PMOS transistors P11-P13, capacitor C0, and current source I2; the sources of PMOS transistors P11-P13 are connected to power supply VDD, and the gate and drain of PMOS transistor P11 are connected to the gate of PMOS transistor P12 and the drain of NMOS transistor N11; the gate of NMOS transistor N11 serves as the negative input terminal X of the operational amplifier circuit OPA, the source of NMOS transistor N11 is connected to the source of NMOS transistor N12 and the drain of NMOS transistor N13, and the gate of NMOS transistor N12... Y is the positive input terminal of the operational amplifier circuit OPA; the drain of NMOS transistor N12 is connected to the drain of PMOS transistor P12, the gate of PMOS transistor P13 and one end of capacitor C0, the drain of PMOS transistor P13 is connected to the other end of capacitor C0 and the drain of NMOS transistor N14 and serves as the output terminal Z of the operational amplifier circuit OPA; the gate of NMOS transistor N14 is connected to the gate of NMOS transistor N13, the gate and drain of NMOS transistor N15 and the current source I2 connected to power supply VDD; the sources of NMOS transistors N13~N15 are grounded to GND.

7. The voltage generation system circuit for analog switches as described in claim 1, characterized in that, The clock generating digital circuit includes: inverters INV1~INV4 and NAND gates NAND1~NAND2; the input of inverter INV1 is connected to the clock signal CK, and the output is connected to the input of inverter INV2 and the first input of NAND gate NAND1; the output of inverter INV2 is connected to the first input of NAND gate NAND2, the output of NAND gate NAND2 is connected to the second output of NAND gate NAND1 and the input of inverter INV4; the output of inverter INV4 outputs the non-overlapping clock CKP; the output of NAND gate NAND1 is connected to the second output of NAND gate NAND2 and the input of inverter INV3, and the output of inverter INV3 outputs the non-overlapping clock CKN; inverters INV3~INV4 serve as the digital clock driving stage, and their power supply is connected to the output Z of the analog negative feedback loop.

8. The voltage generation system circuit for analog switches as described in claim 1, characterized in that, The multi-stage charge pump circuit includes three cascaded charge pump modules CP1 to CP3; the input terminal of charge pump module CP1 is connected to the power supply VDD, the output terminal is connected to the input terminal of charge pump module CP2, the output terminal of charge pump module CP2 is connected to the input terminal of charge pump module CP3, and the output terminal of charge pump module CP3 serves as the output terminal of the multi-stage charge pump circuit, outputting the charge pump output voltage Vcp; the non-overlapping clock terminals of charge pump modules CP1 to CP3 are respectively connected to the non-overlapping clocks CKP to CKN.

9. A voltage generation system circuit for analog switches as described in claim 8, characterized in that, The charge pump modules CP1~CP3 all adopt a cross-coupled charge pump structure, including: PMOS transistors P21~P22, NMOS transistors N21~N22, and capacitors C1~C2; the source of NMOS transistors N21~N22 serves as the input terminal CP_IN of the cross-coupled charge pump structure; the drain of NMOS transistor N21 is connected to one end of capacitor C1, the drain of PMOS transistor P21, and the gates of PMOS transistors P22 and NMOS transistor N22 to form node A, and the other end of capacitor C1 is connected to a non-overlapping clock CKP; the gate of NMOS transistor N21 is connected to one end of capacitor C2, the drains of NMOS transistors N22 and PMOS transistor P22, and the gate of PMOS transistor P21 to form node B, and the other end of capacitor C2 is connected to a non-overlapping clock CKN; the source of PMOS transistors P21~P22 serves as the output terminal CP_OUT of the cross-coupled charge pump structure.

10. An analog switch, characterized in that, The voltage generation system circuit for analog switches as described in any one of claims 1 to 9 is adopted.

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