A DCM implementation method based on a Buck_Boost converter BOOST mode

Abstract

The application discloses a DCM implementation method based on a Buck_Boost converter BOOST mode, and belongs to the technical field of switching power supply control, and comprises the following steps: detecting an inductor current state during Boost mode operation, responding to a first condition that inductor current valley values are all zero-crossed in continuous multiple switching periods, forcibly switching the converter from the Boost mode to the Buck-Boost mode operation, and generating an off signal to hard off the Boost upper tube so that the Boost upper tube is kept off; under the Buck-Boost mode, the timing of each switching period is reconfigured, at least including a first period in which the inductor current is established via the Buck upper tube and the Boost lower tube, and a second period in which the inductor current is freewheeling and descending via the Buck upper tube and the Boost upper tube; the inductor current descending time variation caused by load variation is compensated by adjusting the length of the first period and / or the second period, and the switching frequency is maintained in a target frequency range. The application realizes approximate constant-frequency operation while eliminating light-load circulating current loss, and significantly improves light-load efficiency and electromagnetic compatibility performance.

Description

Technical Field

[0001] This invention belongs to the field of switching power supply control technology, specifically a DCM implementation method based on the BOOST mode of a Buck_Boost converter. Background Technology

[0002] A four-switch Buck-Boost converter is a power supply topology that smoothly converts an input voltage into a stable output voltage, whether high or low. Its topology is as follows: Figure 1 As shown. This topology, due to its seamless switching between buck and boost capabilities, holds an irreplaceable position in applications with wide input voltage variations, such as battery-powered devices, automotive electronics, and industrial power supplies.

[0003] For a four-switch Buck-Boost converter, the converter operates in Boost mode when the input voltage is lower than the output voltage. In this mode, the inductor undergoes an energy storage and release phase in each switching cycle. When the load current is large, the inductor current remains greater than zero throughout the entire switching cycle, and the converter operates in a continuously conducting state. However, as the load current gradually decreases, the trough of the inductor current will decrease accordingly.

[0004] In traditional control schemes, when the load current decreases to the point where the inductor current valley touches the zero current boundary, a forced continuous conduction mode strategy is typically adopted. This involves using control methods to force the inductor current to continue flowing in the reverse direction until the end of a cycle, thus maintaining the appearance of continuous conduction. While this strategy avoids the changes in control loop response caused by entering an intermittent conduction state, it introduces the following two fundamental defects at the physical level.

[0005] First, the forced continuous conduction mode introduces circulating current losses, leading to a sharp deterioration in efficiency under light load. In forced continuous conduction, the inductor current flows in reverse for a portion of each switching cycle. This reverse current does not provide effective energy to the output, but instead generates Joule heat loss in the power switching transistors, the inductor's DC resistance, and the printed circuit board trace resistance that form the current path. Specifically, when the inductor current reverses, the upper Buck transistor and the lower Boost transistor conduct, and the reverse current flows through the on-resistance of these two power transistors, generating conduction losses proportional to the square of the current. Simultaneously, when the reverse current ends and the current reverses again, the body diode of the power transistor undergoes a reverse recovery process, introducing additional reverse recovery losses. The sum of these two losses significantly increases as a percentage of the useful output power under light load conditions, directly causing the converter to fail to meet increasingly stringent energy efficiency standards under light load conditions such as standby or sleep modes.

[0006] Secondly, the forced change in switching frequency to achieve continuous conduction leads to frequency drift. In the continuous conduction state of Boost mode, the volt-second balance of the inductor determines the ratio of the energy storage phase to the energy release phase in the switching cycle. When the load decreases, if the system continues to operate at a fixed frequency, the average inductor current will naturally decrease, and its trough will inevitably fall below the zero current line. To maintain continuous conduction, traditional solutions must extend the switching cycle to allow the inductor current to rise and fall over a longer period, thus maintaining the appearance of continuous conduction at a lower average current level. This causes the switching frequency to decrease monotonically as the load decreases. The large-scale drift in switching frequency not only prevents the design of input and output filters from being optimized for specific frequency bands, leading to the spread of electromagnetic interference noise spectrum, but may also cause the converter's operating frequency to enter the audible range, causing audio noise problems and severely limiting the converter's applicability in noise-sensitive applications.

[0007] In summary, the forced continuous conduction scheme used by traditional Buck-Boost converters in Boost mode under light load inherently suffers from a structural contradiction between efficiency and frequency. Maintaining continuous conduction inevitably sacrifices light-load efficiency and causes frequency drift, while allowing natural transition to intermittent conduction faces the problem of frequency continuous variation with load in traditional schemes. Therefore, there is an urgent need for a control method that can maintain a near-constant switching frequency while achieving intermittent conduction to eliminate circulating current losses in Boost mode under light load. This invention is proposed to resolve this technical contradiction. Summary of the Invention

[0008] The purpose of this invention is to provide a DCM implementation method based on the BOOST mode of a Buck-Boost converter, so as to solve the problems of low efficiency and inability to maintain constant frequency in the Boost mode of a four-switch Buck-Boost converter under light load in the prior art as mentioned in the background art.

[0009] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: A DCM implementation method based on the BOOST mode of a Buck-Boost converter, wherein the four-switch Buck-Boost converter includes a Buck upper MOSFET, a Buck lower MOSFET, a Boost upper MOSFET, a Boost lower MOSFET, and an inductor; including: The inductor current state is detected while the converter is operating in Boost mode; In response to the first condition indicating that the inductor current has decreased to the light load threshold, the converter is forced to switch from Boost mode to Buck-Boost mode and a shutdown signal is generated to hard-shut down the Boost transistor, keeping it off in Buck-Boost mode. In Buck-Boost mode, the timing of each switching cycle is reconstructed, including at least a first time period and a second time period. During the first time period, the inductor current is established via the upper Buck transistor and the lower Boost transistor, and during the second time period, the inductor current decreases via the upper Buck transistor and the upper Boost transistor for freewheeling. By adjusting the duration of at least one of the first and second time periods, the change in inductor current drop time caused by load variation is compensated to maintain the switching frequency within the target frequency range.

[0010] According to the above technical solution, detecting the inductor current state to generate a first condition indicating that the inductor current has decreased to a light-load threshold includes: Monitoring the valley value of inductor current; and When the valley value of the inductor current is detected to be zero within a consecutive preset number of switching cycles, it is determined that the first condition is met.

[0011] According to the above technical solution, it also includes: Set a timing window that corresponds to a portion of the expected switching cycle; The current switching cycle is counted as a valid zero-crossing cycle only if the valley zero-crossing event of the inductor current occurs within the timing window; and When the number of consecutive counts of valid zero-crossing cycles reaches a preset number, the first condition is triggered to avoid false triggering caused by accidental noise.

[0012] According to the above technical solution, hard shutdown of the Boost converter includes: Regardless of what switching command the control logic in Buck-Boost mode generates for the Boost transistor, the command is masked by a turn-off signal, forcing the Boost transistor to remain in the off state.

[0013] Based on the above technical solution, the timing sequence of each switching cycle is reconstructed, including: Within a switching cycle, the first time period, the second time period, and the third time period are set sequentially. During the first period, the upper Buck transistor and the lower Boost transistor are turned on, causing the inductor current to rise in order to store energy. During the second period, the upper Buck transistor and the upper Boost transistor are turned on, causing the inductor current to decrease so that energy can be transferred to the output. During the third period, only the upper Buck transistor is turned on. Under the condition that the input voltage is less than the output voltage, after a fixed period of time, the inductor current decreases and the energy is transferred to the output terminal.

[0014] According to the above technical solution, it also includes: Monitor the trough of the inductor current at the end of the third time period; Based on the deviation between the valley value and the target value, the duration of the first time period is dynamically adjusted to adjust the initial value of the inductor current before the start of the second time period.

[0015] According to the above technical solution, by adjusting the duration of at least one of the first time period and the second time period, the switching frequency is maintained within the target frequency range, including: The third time period is set as a minimum conduction time with a fixed duration; An adjustment signal is generated based on the error between the switching frequency and the reference frequency; and The duration of the first time period is dynamically adjusted by regulating the signal to compensate for the change in the slope of the inductor current drop caused by load changes, thereby stabilizing the switching frequency.

[0016] According to the above technical solution, it also includes: After forcibly entering Buck-Boost mode, the average value of the inductor current is continuously monitored; When the average inductor current exceeds the recovery threshold, the shutdown signal is removed and Boost mode operation is re-enabled. There is a hysteresis band between the recovery threshold and the light load threshold to prevent oscillating switching between modes.

[0017] According to the above technical solution, the converter is forced to switch from Boost mode to Buck-Boost mode when the input voltage is lower than the output voltage.

[0018] According to the above technical solution, in Buck-Boost mode, the peak value of the inductor current in each switching cycle is positively correlated with the load current, so that the converter can maintain an approximately constant switching frequency over a wide load range.

[0019] Compared with the prior art, the present invention has the following beneficial effects: By detecting the continuous zero crossing of the inductor current valley, a physical quantity that directly reflects the reduction of load, the system is forced to switch to Buck-Boost mode and hard-shut down the Boost transistor, eliminating the circulating current loss caused by forced continuous conduction and improving light-load efficiency. At the same time, by reconstructing the switching timing, the Toff time, which originally changed monotonically with the reduction of load, is split into an actively adjustable first and second time period, and dynamic compensation is driven by frequency error. This achieves near constant frequency operation in the essentially variable frequency DCM state, reducing the complexity of electromagnetic interference handling. Attached Figure Description

[0020] Figure 1 This is a topology diagram of a four-switch Buck-Boost converter; Figure 2 This is the main logic block diagram of the control method of the present invention; Figure 3This is the logic diagram for determining the working mode of the present invention; Figure 4 This is a truth table for the signals corresponding to different operating modes of the present invention; Figure 5 This is the logic circuit diagram for DCM state determination in this invention; Figure 6 This is a timing diagram for DCM state determination in this invention; Figure 7 This is a waveform diagram of the continuous conduction state in Boost mode of the present invention; Figure 8 This is a diagram showing the operating state of each power transistor in the Boost converter under intermittent conduction conditions according to the present invention. Figure 9 The waveforms of inductor current, SW1, and SW2 in the Boost mode of this invention under intermittent conduction state are shown. Figure 10 This is a waveform diagram of the inductor current corresponding to the operating state of each power transistor under the intermittent conduction state of the present invention. Figure 11 This is a diagram showing the switching states of CCM and DCM in the Boost mode of this invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] Example 1

[0023] like Figure 1 As shown, the control method of this invention is applied to a four-switch Buck-Boost converter, which includes a Buck upper transistor HS1, a Buck lower transistor LS1, a Boost upper transistor HS2, a Boost lower transistor LS2, and an inductor L. The control objective is: when the converter operates in Boost mode and the output load is reduced to the point where the inductor current valley continuously crosses zero, a special Buck-Boost mode is forcibly entered, HS2 is hard-shut down, and the switching timing is dynamically adjusted to achieve approximately constant frequency.

[0024] The core logic of this method can be implemented using digital logic circuits. For details, refer to... Figure 2The main logic block diagram shown is used to generate mode switching and Boost power-off instructions based on the input voltage VIN, output voltage VOUT, and DCM status signal. The main logic block diagram circuit connection is as follows: The circuit consists of a first comparator COMP1, a second comparator COMP2, a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a first NAND gate NAND1, a second NAND gate NAND2, a first NOR gate NOR1, a second NOR gate NOR2, and a first selector SEL1.In this circuit, the first comparator COMP1 receives a 0.9VOUT signal at its positive input and a VIN signal at its negative input. Its output is connected to the A input of the first selector SEL1 and outputs a VOUT_HI signal. The second comparator COMP2 receives a 0.9VIN signal at its positive input and a VOUT signal at its negative input, outputting a VIN_HI signal. The first inverter INV1 receives a DCM signal at its input and is connected to the upper input of the second NAND gate NAND2. Its output is a DCM_N signal, connected to the SELA input of the first selector SEL1 and the upper input of the first NAND gate NAND1. The input of the second inverter INV2 is connected to the upper input of the first NAND gate NAND1. The output terminals are connected together, and the output terminal outputs the RESET_DCM signal and is connected to the upper input terminal of the first NOR gate NOR1; the input terminal of the third inverter INV3 is connected to the output terminal of the second NAND gate NAND2, and the output terminal outputs the RESET_DCM signal and is connected to the lower input terminal of the second NOR gate NOR2; the input terminal of the fourth inverter INV4 is connected to the upper input terminal of the second NOR gate NOR2 and the output terminal of the first NOR gate NOR1, and the output terminal is connected to the input terminal of the fifth inverter INV5; the input terminal of the fifth inverter INV5 is connected to the output terminal of the fourth inverter INV4, and the output terminal outputs the signal HG2_DIS; the upper input terminal of the first NAND gate NAND1 receives the DCM_N signal and is connected to the first inverter... The output of INV1 is connected to the SELA terminal of the first selector. Its lower input receives the HG_ON signal and is connected to the lower input of the second NAND gate NAND2. Its output is connected to the input of the second inverter INV2. The upper input of the second NAND gate NAND2 receives the DCM signal and is connected to the input of the first inverter INV1. Its lower input receives the HG_ON signal and is connected to the lower input of the first NAND gate NAND1. Its output is connected to the input of the third inverter INV3. The upper input of the first NOR gate NOR1 receives the RESET_DCM signal and is connected to the output of the second inverter INV2. Its lower input is connected to the output of the second NOR gate NOR2. Its output is connected to the second NOR gate NOR2. The upper input terminal of the first NOR gate is connected to the input terminal of the fourth inverter INV4; the upper input terminal of the second NOR gate NOR2 is connected to the output terminal of the first NOR gate NOR1 and the input terminal of the fourth inverter INV4, the lower input terminal receives the SET_DCM signal and is connected to the output terminal of the third inverter INV3, and the output terminal is connected to the lower input terminal of the first NOR gate NOR1; the A input terminal of the first selector SEL1 receives the VOUT_HI signal and is connected to the output terminal of the first comparator COMP1, the B input terminal receives the LOW signal, the SEL1 input terminal receives the DCM_N signal and is connected to the output terminal of the first inverter INV1 and the upper input terminal of the first NAND gate NAND1, and the OUT terminal outputs the BOOST_MODE signal.

[0025] The working principle of the above circuit directly reflects the forced switching and hard shutdown mechanism of this invention. When 0.9VOUT is greater than VIN, VOUT_HI is high and VIN_HI is low, and the circuit operates in Boost mode. When VOUT is less than 0.9VIN, VOUT_HI is low and VIN_HI is high, and the circuit operates in Buck mode. When 0.9VOUT is less than VIN and VOUT is greater than 0.9VIN, VOUT_HI is low and VIN_HI is low, and the circuit operates in BB mode, i.e., Buck-Boost mode. When the system operates in the CCM state of Boost mode, VOUT_HI is high and DCM_N is high. The first selector selects the signal output from input A to output OUT, and BOOST_MODE is high. When the load begins to decrease and the inductor current repeatedly crosses zero continuously, the Boost mode switches to DCM state. At this time, DCM=1. When HG_ON=1, SET_DCM=1, RESET_DCM=0, and HG2_DIS=1, turning off HS2. Since DCM_N=0, the first selector outputs the signal from input B to output OUT, at which point BOOST_MODE=0. The system forcibly enters Buck_Boost mode. Here, HG_ON is the upper transistor turn-on signal, HG2_DIS is the HS2 turn-off signal, LOW is the low signal, and BOOST_MODE is the Boost mode signal. The HG2_DIS signal is the hard turn-off signal; it blocks any commands that could turn on HS2, achieving a hard turn-off.

[0026] Furthermore, to ensure the accuracy of mode switching, this invention employs the following... Figure 3The circuit shown determines the operating mode based on the input / output comparison signal and the charging pulse signal. Specifically, the circuit consists of a first NOR gate (NOR1), a second NOR gate (NOR2), a third NOR gate (NOR3), a fourth NOR gate (NOR4), a fifth NOR gate (NOR5), a first inverter (INV1), and a second inverter (INV2). The first input of the first NOR gate (NOR1) receives the signal VOUT_HI and is connected to the third input of the fourth NOR gate (NOR4). Its second input receives the signal Ton_pulse and is connected to the second input of the third NOR gate (NOR3). The third input is connected to the output of the second NOR gate (NOR2) and the input of the first inverter (INV1). The output of the third inverter (NOR1) is connected to the first input of the second NOR gate (NOR2). Similarly, the first input of the second NOR gate (NOR2) is connected to the output of the first NOR gate (NOR1), and the second input... The input signal VIN_HI is connected to the first input terminal of the third NOR gate NOR3, and the output terminal is connected to the third input terminal of the first NOR gate NOR1 and the input terminal of the first inverter INV1. The first input terminal of the third NOR gate NOR3 receives the signal VIN_HI and is connected to the second input terminal of the second NOR gate NOR2. The second input terminal receives the signal Ton_pulse and is connected to the second input terminal of the first NOR gate NOR1. The third input terminal is connected to the input terminal of the fourth NOR gate NOR4 and the input terminal of the second inverter INV2. The input terminals are connected to each other, and the output terminal is connected to the first input terminal of the fourth NOR gate NOR4; the first input terminal of the fourth NOR gate NOR4 is connected to the output terminal of the third NOR gate NOR3, the second input terminal receives the signal VOUT_HI and is connected to the first input terminal of the first NOR gate NOR1, and the output terminal is connected to the third input terminal of the third NOR gate NOR3 and the input terminal of the second inverter; the first input terminal of the fifth NOR gate NOR5 receives the signal Buck and is connected to the output terminal of the first inverter INV1, and the second input terminal receives the signal Boost. The input of the first inverter INV1 is connected to the third input of the first NOR gate NOR1 and the output of the second NOR gate NOR2, and its output signal Buck is connected to the first input of the fifth NOR gate NOR5. The input of the second inverter INV2 is connected to the third input of the third NOR gate NOR3 and the output of the fourth NOR gate NOR4, and its output signal Boost is connected to the second input of the fifth NOR gate NOR5. Its decision logic follows... Figure 4The truth table shown indicates that when VOUT_HI is low and VIN_HI is high, the circuit operates in Buck mode; when VOUT_HI is high and VIN_HI is low, the circuit operates in Boost mode; and when both VOUT_HI and VIN_HI are low, the circuit operates in BB mode, i.e., Buck-Boost mode. Figure 3 In the middle, Ton_pulse is the pulse signal that begins each charging cycle.

[0027] The first condition for light-load detection in this invention is implemented by a DCM state judgment logic circuit, which generates a DCM flag signal by continuously counting inductor current zero-crossing events. Specifically, refer to... Figure 5The DCM state determination logic circuit shown consists of a first NOR gate (NOR1), a second NOR gate (NOR2), a third NOR gate (NOR3), a fourth NOR gate (NOR4), a first inverter (INV1), a first D flip-flop (DFF1), a second D flip-flop (DFF2), a third D flip-flop (DFF3), a fourth D flip-flop (DFF4), and a fifth D flip-flop (DFF5). Specifically, the first input of the first NOR gate (NOR1) receives the signal ZCD, and its second input is connected to the output of the second NOR gate (NOR2). Its output is connected to the first input of the second NOR gate (NOR2) and the input of the first inverter (INV1). The first input of the second NOR gate (NOR2) is connected to the output of the first NOR gate (NOR1) and the input of the first inverter (INV1). Its second input receives the signal Ton_pulse, and its output is connected to the second input of the first NOR gate (NOR1). The first input of the third NOR gate (NOR3) is connected to the Q5 output of the fifth D flip-flop (DFF). The second input terminal receives the signal Clear, the third input terminal receives the signal DCM and is connected to the output of the fourth NOR gate NOR4, and the output terminal is connected to the first input of the fourth NOR gate NOR4; the first input terminal of the fourth NOR gate NOR4 is connected to the output of the third NOR gate, the second input terminal receives the signal EN_N, the output terminal outputs the signal DCM and is connected to the third input of the third NOR gate NOR3; the input terminal of the first inverter INV1 is connected to the output of the first NOR gate NOR1 and the first input terminal of the second NOR gate NOR2, and the output terminal outputs the signal ZCD clock, ZCD_CLK. The first D flip-flop DFF1 is connected to the CLK terminal; the CLK terminal of the first D flip-flop DFF1 receives the signal ZCD_CLK and is also connected to the output of the first inverter INV1. Its D terminal is connected to the QN1 terminal and the CLK terminal of the second D flip-flop DFF2. The RST terminal receives the signal EN_N. The CLK terminal of the second D flip-flop DFF2 is connected to the D terminal and QN1 terminal of the first D flip-flop DFF1. Its D terminal is connected to the QN2 terminal and the CLK terminal of the third D flip-flop DFF3. The RST terminal receives the signal EN_N. The CLK terminal of the third D flip-flop DFF3 is connected to the D terminal of the second D flip-flop DFF2. The D terminal is connected to the QN2 terminal, the D terminal is connected to the QN3 terminal and the CLK terminal of the fourth D flip-flop DFF4, and the RST terminal receives the signal EN_N; the CLK terminal of the fourth D flip-flop DFF4 is connected to the D terminal of the third D flip-flop DFF3 and the QN3 terminal, the D terminal is connected to the QN4 terminal and the CLK terminal of the fifth D flip-flop DFF5, and the RST terminal receives the signal EN_N; the CLK terminal of the fifth D flip-flop DFF5 is connected to the D terminal of the fourth D flip-flop DFF4 and the QN4 terminal, the D terminal is connected to the QN5 terminal, the Q5 terminal is connected to the first input terminal of the third NOR gate NOR3, and the RST terminal receives the signal EN_N.

[0028] The operating timing of this circuit is as follows: Figure 6As shown. When the enable signal EN_N flips to low, the circuit starts working. When the inductor current IL is less than 0, the zero-crossing detection signal ZCD generates a pulse signal, which is input to the first NOR gate NOR1. At this time, the ZCD_CLK signal receives the change in the previous stage signal, and its potential flips from low to high. Then, when the inductor current discharges and a new cycle begins, the Ton_pulse signal generates a pulse signal to indicate the start of a new charging cycle, and the inductor current rises. At this time, the ZCD_CLK signal receives the change in the previous stage signal, and its potential flips from high to low. Thus, due to the alternating influence of the zero-crossing detection signal ZCD pulse signal and the charging cycle start signal Ton_pulse pulse signal, ZCD_CLK will periodically and continuously flip high and low multiple times, forming a clock signal. This clock signal is provided to the five series-connected D flip-flops in the subsequent stage. The function of the series-connected D flip-flops is to count the ZCD_CLK signal, and similarly, to count the ZCD signal. Since the EN_N signal flips low at the beginning, the DCM signal is initially at a low potential and is in a reserved state. When the 16th rising edge of ZCD_CLK arrives, i.e., the 16th pulse of ZCD, the DCM signal is set to high, and the Buck-Boost converter switches from continuous conduction to discontinuous conduction (DCM). Here, ZCD is the inductor current zero-crossing detection signal, ZCD_CLK is the ZCD clock signal, Ton_pulse is the inductor current charging cycle start signal, and DCM is the discontinuous conduction state signal. During this process, multiple consecutive zero-crossing counts constitute the first condition, and the Clear signal locks the DCM state, preventing mode oscillation.

[0029] When the DCM signal is high, the system enters Buck-Boost mode and turns off HS2. The switching timing is then reconstructed to achieve approximately constant frequency. In the continuously on state, the operating waveform of Boost mode is as follows: Figure 7 As shown in the diagram. At this time, the upper transistor HS1 of the Buck converter is normally on, and the lower transistor LS1 is normally off. In one cycle, when the upper transistor HS2 of the Boost converter is off and the lower transistor LS2 is on, the potential of SW2 is less than the potential of SW1, and the inductor current gradually increases over time. When the upper transistor HS2 is on and the lower transistor LS2 is off, the potential of SW2 is greater than the potential of SW1, and the inductor current gradually decreases over time until the next cycle begins, and so on. When the load decreases, the inductor current will also gradually decrease. When the inductor current valley in the continuous conduction state continuously and repeatedly drops to near zero current, the circuit will change from a continuous conduction state to an intermittent conduction state (DCM).

[0030] Aiming at the drawback of frequency variation in the discontinuous conduction mode (DCM) of the above Boost mode, after the system enters the discontinuous conduction mode (DCM), the upper switch HS2 of Boost is forcibly turned off, and the system operates in the Buck-Boost mode, so as to achieve an approximately constant frequency effect. Figure 8 It shows the operating states of each power switch of Boost in the discontinuous conduction mode (DCM). At this time, HS2 is equivalent to a diode. The peak value of the inductor current in each cycle will decrease as the load decreases, ensuring the energy utilization rate. Figure 9 It is the waveforms of the inductor current, SW1, and SW2 of the Boost mode in the discontinuous conduction mode (DCM). Figure 10 It is the inductor current waveform corresponding to the operating states of each switch when the Boost mode operates in the discontinuous conduction mode (DCM).

[0031] Preferably, the process of timing reconstruction is as follows. When the load current is low, after the valley value of the inductor current in the continuous conduction state of the Boost mode continuously crosses zero for many times without interruption, the system switches to the discontinuous conduction state and turns off HS2. At this time, HS2 is equivalent to a diode. When the Boost mode operates in the discontinuous conduction state, the Buck mode is introduced, and at this time the circuit operates in the Buck-Boost mode. In one discontinuous conduction state cycle, the inductor current rises during the BoostTon (i.e., the conduction time in the boost stage), and at this time the HS1 switch and the LS2 switch are turned on, and the inductor current rises to store energy. When BoostTon ends and enters BoostToff, the HS1 switch is turned on, and the inductor current decreases to provide energy for the load. When BoostToff ends and enters the Buck mode, since VIN < VOUT at this moment, the on-time of the lower switch LS1 of Buck is min_off, that is, the BuckToff time is min_off, and then it enters BuckTon (i.e., the conduction time in the buck stage). During the BuckTon period, only the HS1 switch is turned on, and BuckTon is a fixed conduction time. When BuckTon ends, it enters BoostTon again. Then the circuit enters the next discontinuous conduction state cycle, and so on. Among them, the BoostTon period corresponds to the first period, the BoostToff period corresponds to the second period, and the BuckTon period corresponds to the third period. By fixing the minimum conduction time of BuckTon and dynamically adjusting the duration of BoostTon according to the frequency error, the compensation and stability of the switching frequency are achieved.

[0032] Because the Ton and Toff times are reduced in Boost mode, and the peak inductor current decreases as the load current decreases in the intermittent conduction state, the system is in a near-constant frequency state after adjusting the Ton and Toff times. Compared to the traditional control mode where the Boost mode frequency decreases as the load decreases, this new intermittent conduction implementation method significantly reduces system frequency variations. Figure 9 The minimum inductor current will result in a negative current, which allows the average current of each cycle to gradually approach zero current, enabling the system to maintain this operating state even within a very small load range.

[0033] Figure 11 The diagram illustrates the switching between continuous and intermittent conduction states of the Buck-Boost converter in Boost mode. It shows that when the inductor current is too low in Boost mode, the converter is forcibly switched to Buck-Boost mode, and the HS2 transistor is turned off. This allows the converter to achieve higher efficiency and a constant operating frequency.

[0034] In summary, this invention solves the technical problems of low efficiency and frequency drift under light load DCM by detecting the physical phenomenon of continuous zero crossing of the inductor current valley, which reflects the essential nature of light load, and forcibly switching the Boost upper transistor to Buck-Boost mode. Then, by adjusting the Toff and Ton durations through reconfigured timing, it achieves constant frequency and high efficiency DCM operation.

[0035] Example 2

[0036] Based on Example 1, this embodiment further provides a method for achieving high-precision constant frequency control by dynamically adjusting the duration of the BoostToff period through a closed-loop frequency error, and establishes its discrete-time domain adjustment model.

[0037] In the scheme described in Embodiment 1, the switching frequency is stabilized by fixing the minimum on-time of the BuckTon period (i.e., the second period) and dynamically adjusting the duration of the BoostToff period (i.e., the first period). When the input voltage... or output voltage The slope of the decrease in inductor current during fluctuations As frequency deviations change, relying solely on preset open-loop adjustment rules is insufficient to accurately compensate for them. This embodiment introduces a proportional-integral controller based on frequency error to calculate the BoostToff time correction required for each switching cycle in real time, thereby locking the switching frequency within the target frequency range.

[0038] Define the target switching period as The corresponding target frequency is In the first At the end of each switching cycle, the actual switching cycle is measured. And calculate the periodic error:

[0039]

[0040] The cycle error is input to a digital proportional-integral controller to generate the BoostToff time correction for the current cycle. Its discrete-domain expression is:

[0041]

[0042] in This is the proportionality coefficient. This is the integral coefficient. This correction is added to the BoostToff time base value of the previous period. The BoostToff time instruction value for this cycle is obtained above:

[0043]

[0044] in It can be estimated based on the steady-state volt-second balance relationship. In intermittent conduction mode, a complete switching cycle... From the first period Second period and the third period Composition, namely:

[0045]

[0046] in Fixed to a minimum constant value , Determined by the peak inductor current and input / output voltage, it changes slowly when the load is stable. Therefore, closed-loop regulation is used. Direct compensation is available Compared to The deviation.

[0047] Furthermore, to improve the dynamic response performance of frequency locking under light load, the gain can be adjusted. , According to the peak value of inductor current or load current The size is segmented. The lighter the load, the smaller the value. The lower, the same Changes The more significant the impact, the more appropriate it is to reduce the gain to avoid overshoot. Therefore, the closed-loop regulation method described above elevates traditional open-loop timing compensation to adaptive regulation, enabling the converter to maintain strict constant-frequency characteristics even under input voltage fluctuations and load step changes.

[0048] Example 3

[0049] Based on Example 1, this embodiment further explores the implementation of the light-load detection condition of "the inductor current valley crossing zero for multiple consecutive switching cycles", provides an effective zero-crossing detection mechanism with an adaptive time window, and establishes a quantitative relationship model between window parameters and circuit operating state.

[0050] In the DCM state judgment logic circuit of Embodiment 1, the zero-crossing detection signal ZCD is directly used to trigger the ZCD_CLK signal to flip and drive the counter. However, in actual circuits, after the inductor current crosses zero, high-frequency ringing occurs due to the resonance between the parasitic capacitance and the inductor. The ringing waveform may repeatedly cross the threshold of the zero-current comparator, generating multiple false ZCD pulses, leading to counting errors and thus causing false triggering or triggering delay under light load conditions. To solve this problem, this embodiment introduces an adaptive timing window synchronized with the switching cycle, receiving ZCD pulses only as valid zero-crossing events within the window.

[0051] Specifically, at the beginning of each switching cycle (i.e., when the Ton_pulse pulse arrives), a programmable timer is started, and after a delay time... Then a width of is generated The window signal. Only when the ZCD pulse appears within the valid period of this window is it recognized as a valid zero-crossing event, used to trigger the toggle of the ZCD_CLK signal. ZCD pulses outside the window are masked. Delay time and window width Based on the current input voltage Output voltage and estimated peak inductor current Dynamically adjust to achieve self-adaptation.

[0052] The mathematical basis for this adaptive window is as follows: In the Boost mode continuous conduction state, the inductor current changes from the peak value... Time required to drop to zero From the descending slope The decision is:

[0053]

[0054] Let the end of the third time period (BoostTon) be the peak current time, and the time relative to the start of the cycle (Ton_pulse) be... Then the predicted absolute zero-crossing time. It can be represented as:

[0055]

[0056] Aligning the center time of the adaptive window with the zero-crossing time of the prediction, we have:

[0057]

[0058] Therefore, the window delay time can be obtained:

[0059]

[0060] Inductor current peak It can be obtained through the peak sampling circuit of the previous cycle, or estimated based on the output power and input voltage, for example. Window width The selection of the appropriate bandwidth needs to balance noise immunity and response speed: too wide a bandwidth may include ringing pulses, while too narrow a bandwidth may miss true zero-crossing pulses due to calculation errors. Preferably, Set to 5% to 10% of the expected switching cycle, that is:

[0061]

[0062] in The current estimated switching period can be taken from the target period. Or the measurement value from the previous period.

[0063] When the DCM detection circuit captures valid ZCD pulses within a consecutive preset number (e.g., 16) of times, it determines that the first condition is met and forces the system to enter Buck-Boost mode. This adaptive window mechanism significantly improves the noise immunity and reliability of zero-crossing detection, making it particularly suitable for applications with dynamically changing input and output voltages.

[0064] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should be included in the scope of the present invention.

[0065] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0066] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A DCM implementation method based on the BOOST mode of a Buck-Boost converter, wherein the four-switch Buck-Boost converter includes a Buck upper MOSFET, a Buck lower MOSFET, a Boost upper MOSFET, a Boost lower MOSFET, and an inductor; characterized in that: include: The inductor current state is detected while the converter is operating in Boost mode; In response to the first condition indicating that the inductor current has decreased to the light load threshold, the converter is forced to switch from Boost mode to Buck-Boost mode and a shutdown signal is generated to hard-shut down the Boost transistor, keeping it off in Buck-Boost mode. In Buck-Boost mode, the timing of each switching cycle is reconstructed, including at least a first time period and a second time period. During the first time period, the inductor current is established via the upper Buck transistor and the lower Boost transistor, and during the second time period, the inductor current decreases via the upper Buck transistor and the upper Boost transistor for freewheeling. By adjusting the duration of at least one of the first and second time periods, the change in inductor current drop time caused by load variation is compensated to maintain the switching frequency within the target frequency range.

2. The DCM implementation method based on Buck_Boost converter BOOST mode according to claim 1, characterized in that: Detecting the inductor current state to generate a first condition indicating that the inductor current has decreased to a light-load threshold includes: Monitoring the valley value of inductor current; and When the valley value of the inductor current is detected to be zero within a consecutive preset number of switching cycles, it is determined that the first condition is met.

3. The DCM implementation method based on Buck_Boost converter BOOST mode according to claim 2, characterized in that: Also includes: Set a timing window that corresponds to a portion of the expected switching cycle; The current switching cycle is counted as a valid zero-crossing cycle only if the valley zero-crossing event of the inductor current occurs within the timing window; as well as When the number of consecutive counts of valid zero-crossing cycles reaches a preset number, the first condition is triggered to avoid false triggering caused by accidental noise.

4. The DCM implementation method based on Buck_Boost converter BOOST mode according to claim 1, characterized in that: Hard shutdown of the Boost converter includes: Regardless of what switching command the control logic in Buck-Boost mode generates for the Boost transistor, the command is masked by a turn-off signal, forcing the Boost transistor to remain in the off state.

5. The DCM implementation method based on Buck_Boost converter BOOST mode according to claim 1, characterized in that: Reconstruct the timing sequence for each switching cycle, including: Within a switching cycle, the first time period, the second time period, and the third time period are set sequentially. During the first period, the upper Buck transistor and the lower Boost transistor are turned on, causing the inductor current to rise in order to store energy. During the second time period, the upper Buck transistor and the upper Boost transistor are turned on, causing the inductor current to decrease so that energy can be transferred to the output; and During the third period, only the upper Buck transistor is turned on. Under the condition that the input voltage is less than the output voltage, after a fixed period of time, the inductor current decreases and energy is transferred to the output terminal.

6. The DCM implementation method based on Buck_Boost converter BOOST mode according to claim 5, characterized in that: Also includes: Monitor the trough value of the inductor current at the end of the first time period; Based on the deviation between the valley value and the target value, the duration of the first time period is dynamically adjusted to adjust the initial value of the inductor current before the start of the second time period.

7. The DCM implementation method based on Buck_Boost converter BOOST mode according to claim 1, characterized in that: By adjusting the duration of at least one of the first and second time periods, the switching frequency is maintained within the target frequency range, including: The third time period is set as a minimum conduction time with a fixed duration; An adjustment signal is generated based on the error between the switching frequency and the reference frequency; and The duration of the first time period is dynamically adjusted by regulating the signal to compensate for the change in the slope of the inductor current rise caused by load changes, thereby stabilizing the switching frequency.

8. The DCM implementation method based on Buck_Boost converter BOOST mode according to claim 1, characterized in that: Also includes: After forcibly entering Buck-Boost mode, the average value of the inductor current is continuously monitored; When the average inductor current exceeds the recovery threshold, the shutdown signal is removed and Boost mode operation is re-enabled. There is a hysteresis band between the recovery threshold and the light load threshold to prevent oscillating switching between modes.

9. A DCM implementation method based on Buck_Boost converter BOOST mode according to claim 1, characterized in that: The converter is forced to switch from Boost mode to Buck-Boost mode when the input voltage is lower than the output voltage.

10. A DCM implementation method based on Buck_Boost converter BOOST mode according to claim 1, characterized in that: In Buck-Boost mode, the peak value of the inductor current in each switching cycle is positively correlated with the load current, so that the converter can maintain an approximately constant switching frequency over a wide load range.

Images