A t-type three-level cascaded solid-state transformer topology and control method

Abstract

The disclosure provides a T-type three-level cascaded solid-state transformer topology and a control method. The topology comprises three phase units; each phase unit is composed of a plurality of power units, and the input sides of the plurality of power units are connected in series and the output sides are connected in parallel; each power unit comprises an AC input stage, an isolation conversion stage and a DC output stage connected in sequence; wherein the AC input stage adopts a T-type neutral point clamped three-level full-bridge topology; the isolation conversion stage adopts a T-type dual active bridge topology; and the DC output stage is composed of a plurality of phase-staggered parallel bidirectional half-bridge conversion units. The disclosure combines the T-type NPC three-level full-bridge, the T-type dual active bridge and the staggered parallel DC-DC three levels to construct a T-type SST topology with three-level cascades as the core, which has the advantages of multi-level low stress and modularization and easy expansion.

Description

Technical Field

[0001] This disclosure relates to the field of solid-state transformer technology, specifically to a T-type three-level cascaded solid-state transformer topology and control method. Background Technology

[0002] A solid-state transformer (SST), also known as a power electronic transformer, is a new type of power conversion device based on power electronics technology and the principle of high-frequency electromagnetic induction. Existing solid-state transformers typically employ a multi-stage power conversion structure, using power electronic devices to complete AC-DC-DC or AC-DC-AC energy conversion, and utilizing high-frequency transformers to achieve electrical isolation.

[0003] Currently, the power conversion topologies applied to the high-voltage side of solid-state transformers in existing technologies mainly include two mainstream structures: modular multilevel converter schemes and traditional two-level cascaded H-bridge schemes.

[0004] However, all of the above-mentioned existing topologies have significant technical drawbacks. Among them, the modular multilevel converter scheme has a complex overall system architecture, requires a large number of power electronic devices, resulting in high system control difficulty and low scalability; the traditional two-level cascaded H-bridge scheme is limited by the inherent two-level modulation characteristics, resulting in high voltage stress on the switching devices.

[0005] In summary, existing solid-state transformer topologies generally suffer from technical problems such as low scalability and high voltage stress on devices, which restrict the operating efficiency of the equipment. Summary of the Invention

[0006] This disclosure addresses the problems existing in the prior art by providing a T-type three-level cascaded solid-state transformer topology and control method, which can solve the problems of low scalability and high voltage stress on devices in existing solid-state transformer topologies, thereby improving the operating efficiency of the equipment.

[0007] To achieve the above objectives, the technical solution adopted in this disclosure is as follows: The first aspect of this disclosure provides a T-type three-level cascaded solid-state transformer topology, comprising three phase units; each phase unit consists of multiple power units, with the input sides of the multiple power units connected in series and the output sides connected in parallel; each power unit includes an AC input stage, an isolation conversion stage, and a DC output stage connected in sequence; wherein, the AC input stage adopts a T-type midpoint clamped three-level full-bridge topology, including two first bridge arms and two DC support capacitors, each first bridge arm consisting of two main switching devices and two auxiliary switching devices; the connection point of the two DC support capacitors connected in series forms the midpoint potential, and each first bridge arm is connected to the midpoint potential respectively; the isolation conversion stage adopts a T-type dual active bridge topology, including a three-level inverter full-bridge circuit, a dual active bridge converter, and a three-level rectifier full-bridge circuit; the three-level inverter full-bridge circuit is located on the primary side of the dual active bridge converter, and the three-level rectifier full-bridge circuit is located on the secondary side of the dual active bridge converter; the DC output stage consists of multiple bidirectional half-bridge conversion units connected in parallel with phase interleaving.

[0008] In some embodiments of this disclosure, the two first bridge arms have the same structure and connection method; the two main switching devices of each first bridge arm are connected in series, the connection point of the series connection is the first node, and the two ends are respectively connected to two DC support capacitors; the two auxiliary switching devices are connected back to back in a common source manner to form a bidirectional current flow path, wherein the first end of the bidirectional current flow path is connected to the first node, the second end of the bidirectional current flow path is connected to the midpoint potential, and together with the two main switching devices, they form a T-shaped midpoint clamping path.

[0009] In some embodiments of this disclosure, the input terminal of the three-level inverter full-bridge circuit serves as the input terminal of the isolation converter stage, the output terminal of the three-level inverter full-bridge circuit is connected to the input terminal of the dual active bridge converter, the output terminal of the dual active bridge converter is connected to the input terminal of the three-level rectifier full-bridge circuit, and the output terminal of the three-level rectifier full-bridge circuit serves as the output terminal of the isolation converter stage; wherein, the three-level inverter full-bridge circuit and the three-level rectifier full-bridge circuit have symmetrical structures and are both composed of two second bridge arms, each second bridge arm being composed of two main switching devices and two auxiliary switching devices connected back-to-back in a common-source manner; the dual active bridge converter includes a high-frequency transformer and an equivalent transmission inductance, the equivalent transmission inductance being composed of the leakage inductance of the high-frequency transformer and an external auxiliary inductance.

[0010] In some embodiments of this disclosure, each bidirectional half-bridge converter includes two switching devices and a filter inductor, wherein the two switching devices are connected in series, and the connection point of the two switching devices in series is a second node, and the filter inductor is connected to the second node.

[0011] In some embodiments of this disclosure, three high-voltage AC input ports and a common low-voltage DC output port are provided corresponding to the three phase units; the input terminals of the AC input stages of all power units in the same phase unit are connected in series and then connected to the corresponding high-voltage AC input ports; the output terminal of the AC input stage of each power unit is connected to the input terminal of the isolation conversion stage in the same power unit; the output terminal of the isolation conversion stage of each power unit is connected to the input terminal of the DC output stage in the same power unit; and the output terminals of the DC output stages of all power units in the same phase unit are connected in parallel and then connected to the common low-voltage DC output port.

[0012] In some embodiments of this disclosure, three access circuits are also included. The three phase units are respectively connected to the corresponding high-voltage AC input ports through the corresponding access circuits. Each access circuit includes an input circuit breaker, a soft starter circuit, and an input inductor. The soft starter circuit consists of a pre-charge resistor and a bypass relay connected in parallel with the pre-charge resistor.

[0013] In some embodiments of this disclosure, the three phase units are phase A, phase B, and phase C, and the phase A, phase B, and phase C have the same structure; the three phase units are independent of each other.

[0014] A second aspect of this disclosure provides a control method for a T-type three-level cascaded solid-state transformer, applicable to the T-type three-level cascaded solid-state transformer topology provided in the first aspect or any embodiment thereof. The control method employs a hierarchical architecture combining a system-level power equalization and voltage coordination control strategy and a power unit-level autonomous control strategy. The system-level power equalization and voltage coordination control strategy includes: collecting operating parameters of each power unit and calculating the actual total power of the system; calculating the power deviation based on the actual total power of the system and a preset total power target value; and adjusting the power deviation based on the total number and operating status of the power units. Proportional-integral (PI) calculations are performed to generate the total system power command. Based on the three-phase power balance relationship, the total system power command is sequentially distributed to each phase unit, and then distributed to each power unit within each phase unit. Combined with the high-voltage side DC voltage of each power unit, the power reference value of each power unit is adjusted to achieve system-level power equalization and coordinated control. The power unit-level autonomous control strategy includes: performing independent closed-loop regulation on the AC input stage, isolation conversion stage, and DC output stage within each power unit step by step to complete the full-link power conversion of AC rectification, isolation voltage regulation, and low-voltage regulation, thereby achieving power unit-level autonomous control.

[0015] In some embodiments of this disclosure, independent closed-loop control is performed stage by stage for each power unit, including: for the AC input stage, a voltage-current dual closed-loop control strategy is adopted to regulate the on / off state of the switching devices of each first bridge arm, matching the midpoint potential to output positive, zero, and negative levels, thereby completing the controllable rectification and conversion of high-voltage AC power and outputting high-voltage DC power; for the isolation converter stage, a phase-shift modulation-based power control strategy is adopted to achieve bidirectional power transmission by regulating the phase shift angle between the three-level inverter full-bridge circuit and the three-level rectifier full-bridge circuit; and the current change of the equivalent transmission inductor is regulated by configuring the mid-level ratio and the inter-bridge phase shift ratio. The system adopts a trend-following approach to achieve soft-switching control of switching devices. Simultaneously, it employs a zero-sequence voltage injection control method combining feedforward compensation and feedback regulation. It collects the DC-side capacitor voltage deviation, generates feedback compensation through proportional-integral calculations, and synthesizes the midpoint regulation current by combining it with the system's zero-sequence voltage feedforward component. This achieves dynamic balance of the DC-side midpoint potential and low-frequency pulsation suppression in the isolation converter stage, outputting high-voltage DC power after isolation conversion. For each bidirectional half-bridge converter unit in the DC output stage, an equal-phase-interval interleaved PWM modulation strategy is used to perform low-voltage regulation and parallel current sharing control on the high-voltage DC power after isolation conversion, achieving balanced power distribution among the bidirectional half-bridge converter units and outputting low-voltage DC power.

[0016] In some embodiments of this disclosure, the three-phase power balance relationship includes: In the formula, This represents the summation over phases A, B, and C. Indicates the relationship between each phase n Summing the power units, Indicates the first The first The active power of each power unit This indicates the total active power exchanged between the entire machine and external systems.

[0017] Compared with the prior art, this disclosure has the following beneficial effects: This disclosure combines a T-type NPC three-level full-bridge, a T-type dual active bridge, and an interleaved parallel DC-DC three-stage structure to construct a T-type SST topology with three-level cascade as its core, combining the advantages of multi-level low stress and modular easy expansion. Simultaneously, this disclosure proposes a hierarchical control strategy adapted to this topology, enabling coordinated operation of system-level coordinated optimization and power unit-level autonomous control, effectively achieving key control objectives such as three-level midpoint potential balance and output current sharing. Furthermore, each power unit possesses independent voltage support and fault isolation capabilities, enabling autonomous unit operation and improving the overall system's operational reliability and fault tolerance. Attached Figure Description

[0018] Figure 1This is a schematic diagram of the overall architecture of a T-type three-level cascaded solid-state transformer topology provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of the power unit structure of a T-type three-level cascaded solid-state transformer topology provided in an embodiment of this disclosure; Figure 3 This is a schematic diagram of the AC input stage of a T-type three-level cascaded solid-state transformer topology provided in this embodiment of the disclosure; Figure 4 This is a schematic diagram of the isolation transformer stage of a T-type three-level cascaded solid-state transformer topology provided in this embodiment of the disclosure; Figure 5 This is a schematic diagram of the DC output stage of a T-type three-level cascaded solid-state transformer topology provided in an embodiment of this disclosure; Figure 6 This is a schematic diagram of the hierarchical architecture of a control method for a T-type three-level cascaded solid-state transformer provided in this embodiment of the disclosure; Figure 7 This is a block diagram of the T-type NPC rectifier topology control method for a T-type three-level cascaded solid-state transformer provided in this embodiment of the disclosure; Figure 8 This is a working state diagram of the T-type DAB primary-side inverter unit in a T-type three-level cascaded solid-state transformer control method provided in this embodiment of the disclosure; Figure 9 This is a current waveform diagram of a T-type DAB under a specific operating sequence in a T-type three-level cascaded solid-state transformer control method provided in this embodiment of the disclosure; Figure 10 This is a diagram illustrating the zero-sequence voltage injection midpoint potential control structure of a feedforward plus feedback compensation control method for a T-type three-level cascaded solid-state transformer provided in this embodiment of the disclosure. Figure 11 This is an interleaved parallel DC-DC control block diagram of a T-type three-level cascaded solid-state transformer control method provided in this embodiment of the disclosure; Figure 12 This is an interleaved parallel DC-DC output current waveform diagram of a control method for a T-type three-level cascaded solid-state transformer provided in this embodiment. Detailed Implementation

[0019] The present disclosure will now be further described with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present disclosure and should not be construed as limiting the scope of protection of the present disclosure. It should be noted that the following detailed descriptions are exemplary and intended to provide further explanation of this application.

[0020] The acquisition, transmission, storage, use, and processing of data in this disclosed technical solution comply with relevant national laws and regulations. In the embodiments of this disclosure, certain existing industry solutions such as software, components, and models may be mentioned. These should be considered exemplary, intended only to illustrate the feasibility of implementing the technical solution of this disclosure, and do not imply that the applicant has already used or necessarily used such solutions.

[0021] All terms used in this disclosure have the same meaning as understood by one of ordinary skill in the art to which this disclosure pertains, unless otherwise specifically defined. It should also be understood that terms defined in general dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant art, and not as idealized or highly formalized, unless expressly defined herein.

[0022] For ease of understanding, the technical terms appearing in the embodiments of this disclosure are explained in advance. Unless otherwise specified, the following definitions apply throughout the entire specification.

[0023] SST: Solid State Transformer; a new type of transformer based on a multi-stage power electronic conversion architecture, which can realize voltage transformation, high-frequency electrical isolation, bidirectional energy transmission and power quality regulation; NPC: Neutral Point Clamped; it is the mainstream three-level topology in the field of power electronics. It can stabilize the DC bus neutral point potential, output stepped three-level voltage, and suppress switching harmonics and device voltage stress. This disclosure adopts a T-type NPC configuration, which is suitable for medium- and high-voltage high-power power conversion scenarios. AC-DC: Alternating Current-Direct Current; it can realize the conversion and voltage regulation of AC power to DC power. As the core conversion stage of the SST topology disclosed in this paper, it provides a stable high-voltage DC input power to the subsequent isolation conversion circuit.

[0024] DAB: Dual Active Bridge; it can achieve high-frequency electrical isolation and bidirectional power transmission through phase shift control, and has the characteristics of soft switching, low loss and fast dynamic response. This disclosure adopts a T-type DAB structure to further reduce the operating stress of power devices and adapt to high-voltage isolation conversion scenarios.

[0025] DC-DC: Direct Current to Direct Current conversion; it can realize the adjustment of DC voltage and the precise distribution of DC power. This disclosure adopts a bidirectional half-bridge converter unit interleaved parallel structure, which effectively reduces output current ripple and ensures the stability of high power output of the system.

[0026] This disclosure provides a T-type three-level cascaded solid-state transformer topology, such as... Figure 1 As shown, it mainly includes three high-voltage AC input ports (A1, B1, C1), three identical phase units (phase A, phase B, and phase C), and a unified low-voltage DC output port. Its core lies in adopting a modular three-level power unit cascaded topology, combined with a hierarchical and coordinated control method, to achieve efficient and reliable power conversion.

[0027] Three high-voltage AC input ports, A1, B1, and C1, are connected to subsequent power units via three independent input links. Taking the A-phase input link as an example, an input circuit breaker QS11, a soft-start circuit, and an input inductor L11 are sequentially arranged from the AC grid side to the power unit. The soft-start circuit is composed of a pre-charging resistor R11 and a bypass relay QS21 connected in parallel with it. Similarly, the B-phase and C-phase input links are respectively equipped with input circuit breakers QS12 and QS13, input inductors L21 and L31, and soft-start circuits composed of pre-charging resistors R12 and R13 and bypass relays QS22 and QS23. The structure of each phase is completely identical. The above input terminal structure design provides overcurrent limiting, fault isolation, and start-up process protection functions for the embodiments of this disclosure.

[0028] In a single-phase link, the low-voltage DC output terminals of all power units are connected in parallel to form the DC output port of that phase. Taking phase A as an example, if... Figure 1 The output terminals of the multiple power units 1 shown are connected in parallel to form the A-phase DC output port; similarly, the B-phase and C-phase DC output ports can be obtained. These three-phase output ports are further connected in parallel on the low-voltage side to form a unified low-voltage DC bus, that is, the three-phase output ports are connected in parallel to a unified common low-voltage DC output port. The bus side is equipped with output circuit breakers (QS31, QS32), filter inductors (L41, L51), and a DC-side soft-start circuit composed of soft-start resistors (R21, R22) and bypass relays (QS41, QS42) to complete the final protection and filtering output.

[0029] Each phase unit is composed of multiple power units 1 connected together. In this embodiment, taking phase A as an example, it contains several power units 1, which are connected in series to the phase A high-voltage AC bus to achieve natural voltage division under the input voltage. Phase B and phase C are structurally identical to phase A. The three phase units are not directly electrically connected to each other, forming three independent and symmetrical input links. All power units have the same structure, the same control method, and operate independently, possessing good scalability and ease of maintenance.

[0030] In this embodiment of the disclosure, the internal structure of each power unit is as follows: Figure 2 As shown, it includes a three-stage conversion circuit connected in sequence: AC input stage 1-1, isolation conversion stage 1-2 and DC output stage 1-3.

[0031] First, for the AC input stage, this stage adopts a T-type midpoint clamping full-bridge topology.

[0032] Specific topology as follows Figure 3 As shown, the bridge includes four main switching devices (S11~S12, S15~S16), four auxiliary switching devices (S13~S14, S17~S18), and two series-connected DC support capacitors C1 and C2. Each pair of main switching devices and two auxiliary switching devices constitutes a first bridge arm, resulting in two first bridge arms in total. The connection point of the two series-connected DC support capacitors C1 and C2 forms the midpoint O1 of the DC bus, enabling each first bridge arm to output... Three levels.

[0033] See Figure 3 One of the first bridge arms has a specific structure consisting of main switching devices S11 and S12 connected in series, with their connection point defined as the midpoint of the bridge arm. This midpoint is connected to the DC bus midpoint O1 via two auxiliary switching devices S13 and S14 connected in series, thus forming a T-shaped midpoint clamping path. Specifically, auxiliary switching device S13... S14 is connected back-to-back in a common-source configuration, forming a bidirectional current flow path. The other first bridge arm consists of main switching devices S15 and S16 connected in series, with their connection point defined as the midpoint of the bridge arm. This midpoint is connected to the DC bus midpoint O1 via two auxiliary switching devices S17 and S18 connected in series, thus forming a T-type midpoint clamping path.

[0034] This stage of the circuit operates as a rectifier, converting the input high-voltage AC power into stable DC power.

[0035] Second, for the isolation transformation stage, this stage adopts a T-type dual active bridge topology.

[0036] Specific topology as follows Figure 4 As shown, it includes a three-level inverter full-bridge circuit, a dual active bridge converter, and a three-level rectifier full-bridge circuit. The three-level inverter full-bridge circuit is located on the primary side of the dual active bridge converter, and the three-level rectifier full-bridge circuit is located on the secondary side of the dual active bridge converter.

[0037] The dual active bridge converter includes a high-frequency transformer and an equivalent transmission inductance L, which consists of the leakage inductance of the high-frequency transformer and an external auxiliary inductance.

[0038] The three-level inverter full-bridge circuit consists of two second bridge arms. Each second bridge arm comprises two main switching devices connected in series (such as S31~S32, or S35~S36) and two auxiliary switching devices connected back-to-back in a common-source configuration (such as S33~S34, or S37~S38). The midpoint of the bridge arm is controllably connected to the midpoint of the DC bus via the auxiliary switching devices, thereby achieving three-level output. The midpoints of the two bridge arms are respectively connected to the two ends of the primary winding of the high-frequency transformer of the dual active bridge converter, and to the midpoint of the DC bus formed by the series connection of DC support capacitors C1 and C2 on the input side via the auxiliary switching devices. The equivalent voltage between connection point a and connection point b is V. ab , V ab This is the output voltage of the primary-side multilevel bridge arm.

[0039] The three-level rectifier full-bridge circuit transformer and the three-level inverter full-bridge circuit are symmetrically arranged, both consisting of two second bridge arms. Each second bridge arm comprises two series-connected main switching devices (such as S41~S42, or S45~S46) and two auxiliary switching devices (such as S43~S44, or S47~S48) connected back-to-back in a common-source configuration. The midpoints of the two bridge arms are respectively connected to the two ends of the secondary winding of the high-frequency transformer of the dual active bridge converter, and to the midpoint of the DC bus formed by the series-connected DC support capacitors C3 and C4 on the output side through the auxiliary switching devices, thus forming a T-type dual active bridge converter topology with symmetrical primary and secondary sides. The equivalent voltage between connection point c and connection point d is V. cd , V cd The equivalent voltage of the output voltage of the secondary bridge arm is reflected to the primary side by the transformer turns ratio n.

[0040] This stage of the circuit is mainly responsible for converting the high-voltage DC power supplied by the previous stage into a stable low-voltage DC power output that meets the system requirements, thereby realizing the voltage level conversion.

[0041] Third, for the DC output stage, this stage consists of multiple bidirectional half-bridge converter units connected in parallel with phase interleaving.

[0042] This stage is used for final regulation of the DC output from the isolation converter stage, and its specific topology is as follows: Figure 5As shown, the system consists of multiple (three shown) identical bidirectional half-bridge converter units connected in parallel with staggered phases. Each bidirectional half-bridge converter unit includes two series-connected switching devices (such as S51~S52, S61~S62, or S71~S72) and a filter inductor (such as L1, L2, or L3). The outputs of S51 and S52, S61 and S62, and S71 and S72 are connected to L1, L2, and L3, respectively. The inputs of all bidirectional half-bridge converter units are connected in parallel to the secondary DC bus of the preceding DAB, and the outputs are connected in parallel to the low-voltage DC output of the power unit. A DC support capacitor C5 is also connected in series at the output. The control employs staggered PWM modulation for each phase, which significantly reduces the total output current ripple and improves power quality. This structure also possesses phase-level fault tolerance.

[0043] This disclosure also provides a control method for a T-type three-level cascaded solid-state transformer, applicable to the T-type three-level cascaded solid-state transformer topology provided in the above embodiments. In this disclosure, the control method employs a hierarchical architecture combining a system-level power equalization coordination control strategy and a power unit-level autonomous control strategy.

[0044] Layered architecture, such as Figure 6 As shown, the left side is the system coordination control module, which acts as the upper-level control unit. It receives the total power / voltage command from the system level, performs internal calculations, and assigns an independent control reference value to each cascaded unit. This achieves power balancing among multiple units and optimization of the system-level dynamic response, providing top-level constraints for the autonomous control of each power unit. The right side, within the dashed box, is the power unit-level autonomous control module (only two units are shown in the figure, but it can actually be expanded to N units). Each power unit adopts a dual-closed-loop PI control + three-stage conversion circuit topology (T-type NPC, T-type DAB, and interleaved DC-DC, corresponding to the AC input stage, isolation conversion stage, and DC output stage, respectively). This architecture enables closed-loop voltage regulation, electrical isolation, and low-voltage side regulated output within the power unit. At the same time, through autonomous control between power units, it ensures voltage consistency among cascaded units.

[0045] In this embodiment, the system-level power equalization and coordination control strategy includes: collecting the operating parameters of each power unit and calculating the actual total power of the system; calculating the power deviation based on the actual total power of the system and the preset total power target value; performing proportional-integral calculation on the power deviation based on the total number and operating status of the power units to generate a total system power command; distributing the total system power command sequentially to each phase unit according to the three-phase power balance relationship, then distributing it to each power unit within each phase unit, and adjusting the power reference value of each power unit in conjunction with the high-voltage side DC voltage of each power unit to achieve system-level power equalization and coordination control.

[0046] Specifically, the system-level coordination control module collects the DC-side output voltage of each power unit in real time. With current ,in, For the first l Xiangdi k The actual value of the high-voltage DC side voltage of each power unit. For the first l Xiangdi k The actual value of the high-voltage DC side current of each power unit is obtained, and the actual total power of the system is calculated based on this value. Compare the actual total power with the target total power of the system. The power deviation is compared and combined with the current number of effective power units and operating status of the system (e.g., online / offline, fault / normal). The result is then calculated by the PI controller to generate the total system power command. Subsequently, based on the three-phase power balance relationship, the system's total power command... The voltage is broken down into phases and further distributed to individual power units within each phase. During this process, the system-level coordination control module synchronously monitors the DC-side voltage of each power unit. Furthermore, the DC-side voltage is dynamically adjusted through autonomous voltage control of the power unit, based on the preliminary calculations. l Xiangdi k Power reference value of each power unit Real-time correction is performed. Through this closed-loop regulation, power units with excessively high DC-side voltage will have their power output reduced appropriately, while power units with excessively low DC-side voltage will have their power output increased accordingly. This automatically brings the DC-side voltages of all series-connected power units closer to the same level, achieving dynamic voltage balance among the power units. This control method achieves dynamic autonomous balancing of the DC voltages of power units in a three-level cascaded system without adding additional voltage equalization hardware circuitry. It effectively avoids overvoltage damage to devices caused by uneven voltage distribution among power units, improving the stability and reliability of the system operation.

[0047] In one specific embodiment, the three-phase power balance relationship includes: In the formula, This represents the summation over phases A, B, and C. Indicates the relationship between each phase n Summing the power units, Indicates the first The first The active power of each power unit This indicates the total active power exchanged between the entire machine and external systems.

[0048] Each power unit receives its own Subsequently, the module controller independently completes all control of the three-stage conversion. In this embodiment, the power unit-level autonomous control strategy includes: performing independent closed-loop regulation on the AC input stage, isolation conversion stage, and DC output stage within each power unit to complete the full-link power conversion of AC rectification, isolation voltage regulation, and low-voltage regulation, thereby realizing power unit-level autonomous control.

[0049] In some embodiments, for the AC input stage, a voltage-current dual closed-loop control strategy is adopted to regulate the on / off state of the switching devices of each first bridge arm, match the midpoint potential to output positive, zero and negative levels, complete the controllable rectification and conversion of high-voltage AC power, and output high-voltage DC power.

[0050] Specifically, such as Figure 7 As shown, the control system adopts a dual closed-loop structure based on a rotating coordinate system (dq axis) for both voltage and current. The outer loop is the voltage loop, which is based on the target value of the DC bus voltage on the high-voltage side after rectification. Compared with actual value The deviation is taken as input, where, The target value of the high-voltage DC side voltage for the k-th power unit in phase l is given. For the first l Xiangdi k The actual value of the high-voltage DC side voltage of each power unit is used to output active current commands through a PI regulator. This is to maintain a stable DC voltage. The inner loop is a current loop, receiving... and the set reactive current command (Usually set to zero to achieve unity power factor), compared with the measured grid-side three-phase AC current after coordinate transformation. , A comparison is made. The current PI regulator outputs the corresponding voltage command. and Then, the measured grid-side three-phase AC voltage is transformed using coordinates. , The difference is then compared, and the deviation value is subjected to inverse Park transform to obtain the voltage modulation signal in the two-phase stationary coordinate system (α-β). Then, a three-phase modulated wave is generated by the inverse Clark transform. The drive signals for each switching device of the NPC full bridge are then obtained through carrier phase-shift modulation. g (t) This structure enables tracking of the three-phase AC current on the grid side, ensuring that the input current is sinusoidal and in phase with the grid voltage.

[0051] Furthermore, to suppress DC-side capacitor voltage imbalance caused by asymmetrical switching states or load fluctuations, this disclosure introduces midpoint potential balance control in the modulation stage. This is achieved by real-time detection of the voltage deviation between the two supporting capacitors. Calculate a zero-sequence voltage compensation amount. This compensation amount is injected into the sinusoidal modulation wave. Without affecting the line voltage, the injection time of each phase bridge arm to the midpoint current is dynamically fine-tuned, thereby automatically balancing the capacitor voltage and ensuring the three levels of the three-level output. Symmetric and stable.

[0052] In some embodiments, a phase-shift modulation-based power control strategy is adopted for the isolation converter stage. By adjusting the phase shift angle between the three-level inverter full-bridge circuit and the three-level rectifier full-bridge circuit, bidirectional power transmission is achieved. By configuring the intermediate level ratio and the inter-bridge phase shift ratio, the current change trend of the equivalent transmission inductor is adjusted to achieve soft-switching control of the switching devices. At the same time, a zero-sequence voltage injection control method combining feedforward compensation and feedback regulation is adopted. The DC-side capacitor voltage deviation is collected, and a feedback compensation amount is generated through proportional-integral calculation. Combined with the zero-sequence voltage feedforward component of the system, the midpoint regulation current is synthesized to achieve dynamic balance of the DC-side midpoint potential and low-frequency pulsation suppression of the isolation converter stage, and output high-voltage DC power after isolation conversion.

[0053] Specifically, with Figure 8 Taking the operating state of the primary inverter unit as an example, Figure 8 In [ t 0 ~t In section 8, for switching devices S11~S18, a high level indicates conduction, and a low level indicates turn-off. By controlling the conduction combination of each bridge arm, the primary voltage of the transformer can be adjusted. It exhibits a five-level switching characteristic. The primary-side inverter full-bridge and the secondary-side rectifier full-bridge achieve bidirectional energy transfer by adjusting the phase shift angle between the bridges.

[0054] Based on phase-shift modulation, a coordinated adjustment mechanism between the intermediate level ratio and the inter-bridge phase shift ratio is introduced. The voltage and inductor current waveforms corresponding to a specific switching sequence are as follows: Figure 9 As shown in the figure, the horizontal axis is the time axis (marked as...). t 0 ~t 9) The vertical axis represents the voltage / current amplitude. V ab The output voltage of the primary-side multilevel bridge arm, its amplitude includes V in 0.5 V in Multiple voltage levels correspond to different conduction states of the bridge arm switching transistors; among them, For the original side bridge arm output V in The effective duty cycle of the voltage level is used to characterize the energy injection time on the primary side. V cd For the secondary bridge arm output voltage Vout The equivalent voltage reflected to the primary side after the transformer turns ratio n has an amplitude of nV out ,in, This refers to the duty cycle of the secondary arm voltage relative to the primary arm voltage, i.e., the inter-bridge phase shift ratio. This represents the equivalent inductance current connected in series in the primary circuit of the transformer. Under any switching state, the inductance current is... The values ​​at each time point can be obtained recursively from the following formula: ; in, This is the output voltage of the primary side bridge arm of the high-frequency transformer. This is the equivalent output voltage of the secondary arm of the high-frequency transformer. The equivalent transmission inductance of the converter includes the leakage inductance of the high-frequency transformer and the external auxiliary inductance. This is for the current in the equivalent transmission inductor L. This is achieved by appropriately configuring the intermediate level ratio. Phase shift ratio between bridges It can effectively control the changing trend of inductor current in each switching state range, so that the current flows through its anti-parallel diode before the key switching device is turned on, so as to complete the junction capacitance discharge and realize soft switching.

[0055] Meanwhile, to address the DC-side midpoint potential imbalance problem caused by the conduction of the midpoint clamping path in the T-type three-level bridge arm, a midpoint potential balance control method based on zero-sequence voltage injection is introduced, such as... Figure 10 As shown in the figure, It is the zero-sequence voltage component; The feedforward control current is calculated from the zero-sequence voltage component using the midpoint potential model. This is the reference value for the midpoint potential deviation; This represents the actual deviation of the voltage across the upper and lower voltage divider capacitors on the DC side. k p +k i / s Pass functions to the PI controller; The feedback compensation current output by the PI controller; For system disturbance current; C1 and C2 are the combined current resulting from the superposition of feedforward current, feedback compensation current and disturbance current; C1 and C2 are the upper and lower voltage divider capacitors on the DC side. 1 / (C1+C2)S The transfer function of the integral element of the voltage divider capacitor is given, and its output is the actual midpoint potential deviation. The actual deviation of the midpoint potential. Its reference value The comparison is performed, and the difference is passed through a PI controller to generate a feedback compensation amount. Simultaneously, the zero-sequence voltage component is calculated based on the real-time operating status of the converter. This component is processed by the switch and midpoint potential model to obtain the corresponding feedforward control current. The feedforward control current Feedback compensation amount and system disturbance current The sum of these three factors results in the total current acting at the midpoint of the DC side. This current, after integrating through the DC-side voltage divider capacitor, ultimately determines the actual deviation between the upper and lower capacitor voltages. .

[0056] By compensating for the zero-sequence voltage through a feedforward compensation circuit, the average current flowing through the DC side midpoint can be increased. Approaching zero ensures that the midpoint potential achieves dynamic balance within one fundamental frequency cycle. The introduction of a feedback loop then uses a PI regulator to generate a compensation quantity based on the real-time voltage difference between the upper and lower capacitors C1 and C2. This signal is then superimposed onto the modulation wave, effectively suppressing low-frequency voltage pulsations at the DC-side midpoint caused by factors such as load fluctuations. The synergistic effect of feedforward and feedback together achieves balanced control of the midpoint potential.

[0057] In some embodiments, for each bidirectional half-bridge converter unit of the DC output stage, an equal-phase interval interleaved PWM modulation strategy is adopted to perform low-voltage regulation and parallel current sharing control on the high-voltage DC power after isolation conversion, so as to realize the balanced distribution of output power of each bidirectional half-bridge converter unit and output low-voltage DC power.

[0058] Specifically, such as Figure 11 As shown, this stage employs a dual-loop control system with both current and voltage. The voltage loop controls the output voltage. Feedback value and target reference value The deviation between them is taken as input, where, For the first l Xiangdi k Target value of low-voltage side voltage for each power unit For the first l Xiangdi k The actual low-voltage side voltage of each power unit is calculated by the voltage regulator to generate the total output current command. This loop is primarily used to maintain the stability of the module's output voltage. The current loop receives this current command and uses it as the current for each parallel phase inductor. , , The reference benchmark. The current regulator uses current commands. With actual current The deviation is used as input to track and adjust the inductor current value of each phase, ensuring that the output current accurately follows the command and achieves current sharing among parallel phases. The output signal of the current regulator... 、 、 The signal is sent to the PWM modulator to generate pulse signals that drive the switching transistors of each phase. g1, g2, g3 Finally, the final output inductor current for each phase is obtained. 、 、 .

[0059] In the output stage control of this disclosure, each parallel DC-DC converter unit is controlled using an interleaved modulation strategy. That is, at the same switching frequency, the drive signals of each phase generator are staggered in phase at equal intervals. For example... Figure 12 As shown, in Stage, inductor current in each phase 、 、 They exhibit the characteristic of having the same amplitude but staggered phases. The three-phase currents are connected in parallel and superimposed at the output terminal to form the total output current. Due to phase interleaving, the ripple troughs and peak values ​​of the currents in each phase occur at different times, thus canceling each other out during superposition and effectively suppressing the output current. The ripple is reduced, improving the power quality of the DC bus on the output side.

[0060] As described above, in this embodiment, the three-phase AC power is connected to independent cascaded power units A, B, and C. Each power unit independently completes the full power conversion process from AC rectification and isolation to DC output. After being converted by the power module cluster within each phase, the electrical energy first converges at the DC output port of that phase, and then the DC outputs of the three phases converge again on a unified low-voltage DC bus, ultimately forming a modular, highly reliable solid-state transformer topology with electrical isolation characteristics.

[0061] It should be noted that the terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different parts. Terms such as "including" or "contains" mean that the element preceding the word covers the element listed after the word, and do not exclude the possibility of covering other elements as well.

[0062] Although operations are described in a specific order in the accompanying drawings in this disclosure, it should not be construed as requiring these operations to be performed in the specific order or serial order shown, or requiring all of the shown operations to obtain the desired result. In certain environments, multitasking and parallel processing may be advantageous.

[0063] Finally, it should be noted that the above content is only used to illustrate the technical solution of this disclosure, and is not intended to limit the scope of protection of this disclosure. Simple modifications or equivalent substitutions made by those skilled in the art to the technical solution of this disclosure do not depart from the substance and scope of the technical solution of this disclosure.

Claims

1. A T-type three-level cascaded solid-state transformer topology, characterized in that, It includes three phase units; each phase unit consists of multiple power units, with the input sides of the power units connected in series and the output sides connected in parallel; each power unit includes an AC input stage, an isolation conversion stage, and a DC output stage connected in sequence; wherein, The AC input stage adopts a T-type midpoint clamped three-level full-bridge topology, including two first bridge arms and two DC support capacitors. Each first bridge arm consists of two main switching devices and two auxiliary switching devices. The connection point of the two DC support capacitors connected in series forms the midpoint potential, and each first bridge arm is connected to the midpoint potential. The isolation converter stage adopts a T-type dual active bridge topology, including a three-level inverter full-bridge circuit, a dual active bridge converter, and a three-level rectifier full-bridge circuit; the three-level inverter full-bridge circuit is located on the primary side of the dual active bridge converter, and the three-level rectifier full-bridge circuit is located on the secondary side of the dual active bridge converter; The DC output stage consists of multiple bidirectional half-bridge converter units connected in parallel with phase interleaving.

2. The T-type three-level cascaded solid-state transformer topology according to claim 1, characterized in that, The two first bridge arms have the same structure and connection method; the two main switching devices of each first bridge arm are connected in series, the connection point of the series connection is the first node, and the two ends are respectively connected to the two DC support capacitors; the two auxiliary switching devices are connected back to back in a common source manner to form a bidirectional current flow path, wherein the first end of the bidirectional current flow path is connected to the first node, the second end of the bidirectional current flow path is connected to the midpoint potential, and together with the two main switching devices, they form a T-shaped midpoint clamping path.

3. The T-type three-level cascaded solid-state transformer topology according to claim 2, characterized in that, The input terminal of the three-level inverter full-bridge circuit serves as the input terminal of the isolation converter stage. The output terminal of the three-level inverter full-bridge circuit is connected to the input terminal of the dual active bridge converter. The output terminal of the dual active bridge converter is connected to the input terminal of the three-level rectifier full-bridge circuit. The output terminal of the three-level rectifier full-bridge circuit serves as the output terminal of the isolation converter stage. The three-level inverter full-bridge circuit and the three-level rectifier full-bridge circuit are symmetrical in structure and each consists of two second bridge arms. Each second bridge arm consists of two main switching devices and two auxiliary switching devices connected back to back in a common-source manner. The dual active bridge converter includes a high-frequency transformer and an equivalent transmission inductor, wherein the equivalent transmission inductor is composed of the leakage inductance of the high-frequency transformer and an external auxiliary inductor.

4. The T-type three-level cascaded solid-state transformer topology according to claim 3, characterized in that, Each of the bidirectional half-bridge converter units includes two switching devices and a filter inductor, wherein the two switching devices are connected in series, and the connection point of the two switching devices in series is a second node, and the filter inductor is connected to the second node.

5. The T-type three-level cascaded solid-state transformer topology according to any one of claims 1-4, characterized in that, It also includes three high-voltage AC input ports and one common low-voltage DC output port, which are provided corresponding to the three phase units; The input terminals of the AC input stages of all the power units within the same phase unit are connected in series and then connected to the corresponding high-voltage AC input port. The output terminal of the AC input stage of each power unit is connected to the input terminal of the isolation converter stage within the same power unit. The output terminal of the isolation converter stage of each power unit is connected to the input terminal of the DC output stage within the same power unit. The output terminals of the DC output stages of all the power units within the same phase unit are connected in parallel and then connected to the common low-voltage DC output port.

6. The T-type three-level cascaded solid-state transformer topology according to claim 5, characterized in that, It also includes three access circuits, and the three phase units are respectively connected to the corresponding high-voltage AC input ports through the corresponding access circuits. Each access circuit includes an input circuit breaker, a soft starter circuit, and an input inductor, wherein the soft starter circuit consists of a pre-charge resistor and a bypass relay connected in parallel with the pre-charge resistor.

7. The T-type three-level cascaded solid-state transformer topology according to any one of claims 1-4, characterized in that, The three phase units are phase A, phase B, and phase C, and the phase A, phase B, and phase C have the same structure; the three phase units are independent of each other.

8. A control method for a T-type three-level cascaded solid-state transformer, characterized in that, Applicable to the T-type three-level cascaded solid-state transformer topology as described in any one of claims 1-7, the control method adopts a hierarchical architecture combining a system-level power equalization and voltage coordination control strategy and a power unit-level autonomous control strategy; wherein, The system-level power equalization and coordination control strategy includes: collecting the operating parameters of each power unit and calculating the actual total power of the system; calculating the power deviation based on the actual total power of the system and the preset total power target value; performing proportional-integral calculation on the power deviation based on the total number and operating status of the power units to generate a total system power command; distributing the total system power command sequentially to each phase unit according to the three-phase power balance relationship, then distributing it to each power unit within each phase unit, and adjusting the power reference value of each power unit in conjunction with the high-voltage side DC voltage of each power unit to achieve system-level power equalization and coordination control. The power unit hierarchical autonomous control strategy includes: performing independent closed-loop regulation on the AC input stage, isolation conversion stage, and DC output stage within each power unit to complete the full-link power conversion of AC rectification, isolation voltage regulation, and low-voltage regulation, thereby realizing power unit hierarchical autonomous control.

9. The control method according to claim 8, characterized in that, The step-by-step independent closed-loop control of the AC input stage, isolation conversion stage, and DC output stage within each power unit includes: For the AC input stage, a voltage-current dual closed-loop control strategy is adopted to regulate the on / off state of the switching devices of each first bridge arm, and match the midpoint potential to output positive, zero and negative levels, thereby completing the controllable rectification and conversion of high-voltage AC power and outputting high-voltage DC power. For the isolation converter stage, a phase-shift modulation-based power control strategy is adopted. By adjusting the phase shift angle between the three-level inverter full-bridge circuit and the three-level rectifier full-bridge circuit, bidirectional power transmission is achieved. By configuring the intermediate level ratio and the inter-bridge phase shift ratio, the current change trend of the equivalent transmission inductor is adjusted to achieve soft-switching control of the switching devices. At the same time, a zero-sequence voltage injection control method combining feedforward compensation and feedback regulation is adopted. The DC-side capacitor voltage deviation is collected, and a feedback compensation amount is generated through proportional-integral calculation. Combined with the zero-sequence voltage feedforward component of the system, the midpoint regulation current is synthesized to achieve dynamic balance of the DC-side midpoint potential and low-frequency pulsation suppression of the isolation converter stage, and output high-voltage DC power after isolation conversion. For each of the bidirectional half-bridge converter units in the DC output stage, an equal-phase-interval staggered PWM modulation strategy is adopted to perform low-voltage regulation and parallel current sharing control on the high-voltage DC power after isolation conversion, so as to achieve balanced distribution of output power of each of the bidirectional half-bridge converter units and output low-voltage DC power.

10. The control method according to claim 8, characterized in that, The three-phase power balance relationship includes: ； In the formula, This represents the summation over phases A, B, and C. Indicates the relationship between each phase n Summing the power units, Indicates the first The first The active power of each power unit This indicates the total active power exchanged between the entire machine and external systems.

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