Split-phase dual half-bridge inverter standby control method and device and electronic equipment

Abstract

This application provides a standby control method, apparatus, and electronic device for a split-phase dual half-bridge inverter. The method includes: acquiring a first output voltage and a first output current at a first AC output terminal of the split-phase dual half-bridge inverter, and a second output voltage and a second output current at a second AC output terminal; when the first output voltage, the second output voltage, the first output current, and the second output current meet the standby conditions, switching the modulation mode of the split-phase dual half-bridge inverter from bipolar modulation to unipolar modulation; when the first output voltage, the second output voltage, the first output current, and the second output current meet the load conditions, restoring the modulation mode of the split-phase dual half-bridge inverter to bipolar modulation. This application can reduce the standby power consumption of the system and effectively avoid structural distortion of the actual output voltage.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a standby control method, device, and electronic equipment for a split-phase dual half-bridge inverter. Background Technology

[0002] With the widespread application of energy storage inverters in battery energy storage systems, the system's standby power consumption has become a crucial indicator affecting overall energy efficiency and range. Even under standby or light-load conditions, although the output power of the energy storage inverter is low, the control circuitry and power devices still experience continuous energy loss. This standby loss directly leads to a decrease in the system's standby range, especially in off-grid or backup power supply scenarios.

[0003] Currently, the mainstream strategies for reducing standby power consumption mainly include periodically shutting down the PWM signal and skip-cycle control. Periodically shutting down the PWM reduces the number of switching operations by intermittently turning off the drive signal of the power switch, while skip-cycle control reduces standby power consumption by keeping the main power switch off and only momentarily turning it on when the output voltage is below a set threshold. Both methods reduce standby power consumption to some extent and have their own applications in unipolar and bipolar PWM modulation: bipolar modulation has mature control logic and good engineering reliability; unipolar modulation reduces the switching frequency by having only a portion of the bridge arm carry high-frequency switching within half a cycle, which is beneficial for reducing switching losses.

[0004] However, the periodic shutdown of PWM, due to its audible frequency (approximately 20Hz to 20kHz), can easily cause mechanical vibrations in magnetic components such as transformers and inductors, generating audible noise. Simultaneously, it leads to pulsed output voltage changes, increasing output ripple, affecting system dynamic response, and reducing light-load performance. While skip-cycle control can reduce standby power consumption, it may introduce control complexity and stability issues. Although unipolar modulation reduces the equivalent switching frequency, its closed-loop regulation and dynamic response performance are relatively poor, and its software control complexity is high. When applied to a split-phase dual half-bridge topology, due to the freewheeling characteristics of the energy storage elements, the actual output voltage deviates from the desired voltage in amplitude and phase, resulting in significant output voltage distortion. Summary of the Invention

[0005] The purpose of this invention is to provide a standby control method, device, and electronic equipment for a split-phase dual half-bridge inverter, which solves the problem that existing split-phase dual half-bridge inverters cannot simultaneously achieve low standby power consumption and high-quality output waveform under standby conditions.

[0006] According to a first aspect of the present invention, a standby control method for a split-phase dual half-bridge inverter is provided, comprising: acquiring a first output voltage and a first output current at a first AC output terminal of the split-phase dual half-bridge inverter, and a second output voltage and a second output current at a second AC output terminal; When the first output voltage, the second output voltage, the first output current, and the second output current meet the standby conditions, at the zero-crossing point of the output voltage at the corresponding AC output terminal, the modulation mode of the split-phase dual half-bridge inverter is switched from bipolar modulation to unipolar modulation. Under the unipolar modulation, the duty cycle of each AC output terminal is corrected according to the volt-second balance relationship of the freewheeling phase of the first AC output terminal and the second AC output terminal, and the PWM comparison value is determined according to the corrected duty cycle. When the first output voltage, the second output voltage, the first output current, and the second output current meet the load conditions, the modulation mode of the split-phase dual half-bridge inverter is restored to bipolar modulation at the zero-crossing point of the output voltage at the corresponding AC output terminal.

[0007] In one optional embodiment, the standby conditions include: Both the first output voltage and the second output voltage are greater than the first voltage threshold, and both the first output current and the second output current are less than the first current threshold. The load conditions include: Either the first output voltage or the second output voltage is less than the second voltage threshold, or either the first output current or the second output current is greater than the second current threshold.

[0008] In one alternative embodiment, the first voltage threshold is greater than the second voltage threshold, and the first current threshold is less than the second current threshold.

[0009] In one optional embodiment, under the unipolar modulation, the duty cycle is corrected according to the volt-second balance relationship during the freewheeling phases of the first AC output terminal and the second AC output terminal, including: For either the first AC output terminal or the second AC output terminal, perform the following steps as the current output terminal: The output current of the current output terminal is determined to be the current of the filter capacitor corresponding to the current output terminal; Determine the change in inductor ripple current based on the change in current of the corresponding filter inductor at the current output terminal during the conduction period; Based on the volt-second balance relationship, determine the voltage bias coefficient of the filter inductor during the freewheeling phase; The charge balance relationship of the filter capacitor current within one switching cycle is determined based on the current of the filter capacitor, the change in the inductor ripple current, and the voltage bias coefficient. Based on the charge balance relationship, the corrected duty cycle of the current output terminal is determined.

[0010] In an optional embodiment, the voltage bias coefficient is expressed as: k = (Vdc - Vref) / (Vdc + Vref); Where k is the voltage bias coefficient of the current output terminal, Vdc is the DC bus voltage, and Vref is the target output voltage of the current output terminal.

[0011] In an optional embodiment, the change in inductor ripple current is expressed as: di = (Vdc - Vref) × Duty × Ts / L; Where di is the change in inductor ripple current at the current output terminal, Vdc is the DC bus voltage, Vref is the target output voltage at the current output terminal, Duty is the duty cycle of the current output terminal in the current switching cycle, Ts is the switching cycle, and L is the filter inductance value corresponding to the current output terminal.

[0012] In one optional embodiment, the charge balance relationship of the filter capacitor current during one switching cycle is as follows: Ic×Ts=(Duty×Ts)×di / 2+(k×Duty×Ts)×di / 2; Where Ic is the current of the filter capacitor corresponding to the current output terminal, k is the voltage bias coefficient of the current output terminal, Duty is the duty cycle of the current output terminal in the current switching cycle, Ts is the switching cycle, and di is the change in inductor ripple current of the current output terminal.

[0013] In an optional embodiment, the modified duty cycle is expressed as: ; Among them, Duty new The current output is the corrected duty cycle, L is the filter inductance value corresponding to the current output, Ts is the switching period, Ic is the current of the filter capacitor corresponding to the current output, Vdc is the DC bus voltage, Vref is the target output voltage of the current output, and Sqrt() is the square root operation.

[0014] In an optional embodiment, the step of determining the PWM comparison value based on the corrected duty cycle is expressed as: Cmp = Period × (1 - Duty) new ); Where Cmp is the PWM compare value corresponding to the current output, Period is the PWM period count value, and Duty is... new This is the corrected duty cycle for the current output.

[0015] In an optional embodiment, after determining the PWM comparison value based on the modified duty cycle, the method further includes: Write the PWM comparison value corresponding to the first AC output terminal into the register of the first PWM module, and the first PWM module outputs the drive signal that controls the circuit where the first AC output terminal is located; Write the PWM comparison value corresponding to the second AC output terminal into the register of the second PWM module, and the second PWM module outputs the drive signal that controls the circuit where the second AC output terminal is located; The logic for the first PWM module and the second PWM module to output drive signals includes: outputting a high-level drive signal when the count value of the time base counter increases and the corresponding PWM comparison value is greater than the time base counter, and outputting a low-level drive signal when the count value decreases and the corresponding PWM comparison value is less than the time base counter.

[0016] In one optional embodiment, after correcting the respective duty cycles, the method further includes: For the first AC output terminal and the second AC output terminal, closed-loop adjustment is performed according to the error between their actual output voltage and the target output voltage to obtain their respective closed-loop adjustment values; The closed-loop adjustment is superimposed on the corresponding corrected duty cycle to obtain the final duty cycle of the corresponding AC output terminal.

[0017] In one optional embodiment, the split-phase dual half-bridge inverter includes a first half-bridge and a second half-bridge, the first half-bridge including a first switch and a second switch connected in series, and the second half-bridge including a third switch and a fourth switch connected in series. In the bipolar modulation mode, the first switch and the second switch are complementary in conduction, and the third switch and the fourth switch are complementary in conduction. Under the unipolar modulation method: during the positive half-cycle of the first output voltage corresponding to the first AC output terminal, the first switch is controlled to switch on at high frequency, and the second switch is controlled to remain in a normally off state; during the negative half-cycle of the first output voltage, the second switch is controlled to switch on at high frequency, and the first switch is controlled to remain in a normally off state. During the positive half-cycle of the second output voltage corresponding to the second AC output terminal, the third switch is controlled to switch on at high frequency, and the fourth switch is controlled to remain in a normally off state; during the negative half-cycle of the second output voltage, the fourth switch is controlled to switch on at high frequency, and the third switch is controlled to remain in a normally off state.

[0018] According to a second aspect of the present invention, a standby control device for a split-phase dual half-bridge inverter is provided, the device comprising: The acquisition module is used to acquire the first output voltage and first output current of the first AC output terminal, and the second output voltage and second output current of the second AC output terminal in the split-phase dual half-bridge inverter. The standby switching module is used to switch the modulation mode of the split-phase dual half-bridge inverter from bipolar modulation to unipolar modulation at the zero-crossing point of the output voltage at the corresponding AC output terminal when the first output voltage, the second output voltage, the first output current and the second output current meet the standby conditions. The modulation compensation module is used to correct the duty cycle of the first AC output terminal and the second AC output terminal respectively according to the volt-second balance relationship of the freewheeling phase under the unipolar modulation, and determine the PWM comparison value according to the corrected duty cycle. The load recovery module is used to restore the modulation mode of the split-phase dual half-bridge inverter to bipolar modulation at the zero-crossing point of the output voltage at the corresponding AC output terminal when the first output voltage, the second output voltage, the first output current and the second output current meet the load conditions.

[0019] According to a third aspect of the present invention, an electronic device is provided, comprising: a power converter, an input unit, a memory, at least one processor, and an output interface, wherein the memory stores program instructions executable on the processor, and the processor can execute a standby control method for a split-phase dual half-bridge inverter by calling the program instructions.

[0020] According to the present invention, by acquiring the voltage and current of the first and second AC output terminals of the split-phase dual half-bridge inverter, the modulation mode is smoothly switched from bipolar to unipolar modulation at the voltage zero-crossing point when the standby conditions are met. This effectively reduces the switching frequency of the power switching transistors, thereby reducing high-frequency switching losses and lowering the system's standby power consumption. Simultaneously, addressing the inherent non-zero level freewheeling defect in the topology under unipolar modulation, the duty cycle is corrected using open-loop prediction based on the volt-second balance relationship of the freewheeling phase in each AC output terminal's circuit. This compensates for the freewheeling deviation caused by the hardware, effectively avoiding structural distortion of the actual output voltage and ensuring high-quality sinusoidal waveform output under standby conditions. Furthermore, bipolar modulation is restored at the corresponding zero-crossing point when the load conditions are met, ensuring that the system possesses extremely low standby power consumption while also maintaining excellent dynamic response capability and load stability in the face of sudden load changes. Attached Figure Description

[0021] Figure 1 A schematic diagram of the topology of the split-phase double half-bridge provided in an embodiment of this application; Figure 2 A flowchart illustrating the steps of the standby control method for a split-phase dual half-bridge inverter provided in this application embodiment; Figure 3 This is a schematic diagram illustrating the principle of the PWM module generating drive signals by up and down counting, as provided in an embodiment of this application. Figure 4 A schematic diagram of the output voltage distortion waveform without duty cycle correction under unipolar modulation provided in an embodiment of this application; Figure 5 A schematic diagram illustrating the principle of the inductor current and charge balance relationship in the next switching cycle of unipolar modulation, provided in an embodiment of this application. Figure 6 A schematic diagram of a unipolar modulation high-quality output voltage waveform after applying the duty cycle correction method of this application is provided for an embodiment of this application; Figure 7 A schematic flowchart illustrating another standby control method for a split-phase dual half-bridge inverter provided in this application embodiment; Figure 8 This is a structural block diagram of the standby control device for a split-phase dual half-bridge inverter provided in an embodiment of this application; Figure 9 A block diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0023] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to limit the application. The singular forms “a,” “said,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms, and “multiple” generally includes at least two unless the context clearly indicates otherwise.

[0024] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0025] It should be understood that although the terms first, second, third, etc., may be used in the embodiments of this application, these descriptions should not be limited to these terms. These terms are only used to distinguish the descriptions. For example, first may also be referred to as second without departing from the scope of the embodiments of this application, and similarly, second may also be referred to as first.

[0026] Depending on the context, the words “if” or “suppose” as used here can be interpreted as “when” or “in response to determination” or “in response to detection.” Similarly, depending on the context, the phrases “if determination” or “if detection (of the stated condition or event)” can be interpreted as “when determination” or “in response to determination” or “when detection (of the stated condition or event)” or “in response to detection (of the stated condition or event).”

[0027] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or device. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device that includes said element.

[0028] It should be noted that any symbols and / or numbers present in the specification that are not marked in the accompanying drawings are not reference numerals.

[0029] The optional embodiments of this application are described in detail below with reference to the accompanying drawings.

[0030] The split-phase dual half-bridge inverter provided in this embodiment of the invention is mainly used to convert DC power on the DC bus into AC power, and is suitable for energy storage systems or uninterruptible power supply systems that meet specific grid specifications.

[0031] Please see Figure 1 In this embodiment, the split-phase dual half-bridge inverter includes: a positive DC bus, a negative DC bus, a reference neutral point N, and an AC output terminal. Specifically, the AC output terminal includes a first AC output terminal L1 and a second AC output terminal L2.

[0032] In the specific circuit connection structure, a first half-bridge and a second half-bridge are connected in parallel between the positive DC bus and the negative DC bus: the first half-bridge consists of a first switch Q1 and a second switch Q2 connected in series, and the common connection point of the first switch Q1 and the second switch Q2 is the first AC output terminal L1. The second half-bridge consists of a third switch Q3 and a fourth switch Q4 connected in series, and the common connection point of the third switch Q3 and the fourth switch Q4 is the second AC output terminal L2.

[0033] To achieve output voltage smoothing and filtering, the first AC output terminal L1 and the second AC output terminal L2 are each connected to an independent filter circuit. Specifically, the first AC output terminal L1 is connected to the external load through a filter inductor and to the reference neutral point N through a filter capacitor; similarly, the second AC output terminal L2 is connected to the external load through a filter inductor and to the reference neutral point N through a filter capacitor. Thus, a split-phase output topology of "L1 to N" and "L2 to N" is formed in the overall physical architecture, with the reference neutral point N as the reference.

[0034] In terms of drive control channel configuration, the controller (such as a DSP or microcontroller) inside the split-phase dual half-bridge inverter is equipped with multiple independent pulse width modulation (PWM) modules. Specifically, the control terminals of the first switch Q1 and the second switch Q2 are connected to the first output terminal 1A and the second output terminal 1B of the first PWM module (PWM1), respectively; the control terminals of the third switch Q3 and the fourth switch Q4 are connected to the first output terminal 2A and the second output terminal 2B of the second PWM module (PWM2), respectively.

[0035] It is particularly important to note that, due to the hardware limitation of the split-phase dual half-bridge topology, where the two half-bridges independently undergo LC filtering via the neutral point N, when the system is under light load or standby conditions, if the control mode is directly switched from bipolar modulation to conventional unipolar modulation (i.e., forcibly turning off the switch of one bridge arm within half a power frequency cycle), the current of the freewheeling components in the circuit (such as the first and second filter inductors) will not be able to form an ideal zero-level freewheeling state through the normal bridge arm loop. This inherent non-zero-level freewheeling defect in the topology will directly lead to structural distortions in the amplitude and phase of the actual voltage at the AC output terminal.

[0036] Based on the aforementioned hardware interaction architecture and circuit topology, this application provides a standby control method for a split-phase dual half-bridge inverter. Figure 2 A flowchart illustrating a standby control method for a split-phase dual half-bridge inverter is shown, comprising the following steps: S10, obtain the first output voltage and first output current of the first AC output terminal in the split-phase dual half-bridge inverter, and the second output voltage and second output current of the second AC output terminal; During normal system operation, the controller can collect electrical parameters from both output channels via its internal sampling circuit, serving as the basis for subsequent judgments regarding operating mode switching and closed-loop control. Before entering standby mode, the system defaults to bipolar modulation.

[0037] In the bipolar modulation mode, for the first half-bridge, the first switch Q1 and the second switch Q2 are complementary in conduction (including dead time); for the second half-bridge, the third switch Q3 and the fourth switch Q4 are complementary in conduction (including dead time).

[0038] It should be noted that obtaining the first output voltage and first output current at the first AC output terminal, and the second output voltage and second output current at the second AC output terminal of the split-phase dual half-bridge inverter can be achieved through continuous real-time sampling via an analog-to-digital converter; it can also be timed sampling according to a preset fixed period (e.g., every 100 microseconds); it can also be performed in response to external trigger signals (such as load sudden interruption) for single or burst sampling; or it can be sampled at a specific moment based on a PWM synchronization signal. The specific acquisition method can be selected according to the actual system resources and control requirements.

[0039] like Figure 3As shown in the figure, the PWM module inside the controller uses an up-down counting method (i.e., the time base counter first increments from 0 to the maximum count value and then decrements from the maximum count value to 0) to generate a high-frequency drive signal. In this counting mode, it is set that when the count value of the time base counter is greater than the PWM comparison value Cmp, the output drive signal is at a high level; when the count value is less than the PWM comparison value, the output drive signal is at a low level. Thus, an inverse relationship exists between the generated duty cycle Duty and the comparison value Cmp, and its mathematical expression is: Duty = 1 - Cmp / Period; For the inverter leg in this embodiment, under bipolar modulation, ignoring the influence of dead time, when the drive signal is at a high level (the duration ratio is the duty cycle Duty), the half-bridge output voltage is +Vdc; when the drive signal is at a low level (the duration ratio is 1 - Duty), the half-bridge output voltage is -Vdc. Therefore, within a complete switching cycle, the average output voltage Vave of the half-bridge can be expressed as: Vave = Duty × Vdc + (1 - Duty) × (-Vdc) = (2 × Duty - 1) × Vdc; Assume that the normalized target modulation wave calculated by the system closed-loop regulation is m × sin(wt), where m is the modulation coefficient (the value range is usually 0 < m ≤ 1). To make the average voltage actually output by the half-bridge strictly track this target modulation wave, that is, it is desired that Vave = m × sin(wt) × Vdc, the mapping relationship between the target duty cycle Duty and the modulation wave can be deduced, and the corresponding comparison value for the PWM module is: Cmp = m × sin(wt) × Period; Since the value range of the target modulation wave m × sin(wt) is , including the negative value interval, and the comparison value Cmp of the PWM module is an unsigned integer variable, and its effective legal range is strictly limited between [0, Period]. Therefore, it is necessary to translate the modulation wave so that it is mapped to the interval [0, Period], and the corresponding Cmp calculation formula is: Cmp = 0.5 × Period × (1 - m × sin(wt)); Through the above formula, the controller can map the sinusoidal modulation wave including positive and negative polarities to an unsigned count value under the bipolar modulation mode.

[0040] S20, when the first output voltage, the second output voltage, the first output current, and the second output current meet the standby conditions, at the zero crossing of the voltage at the corresponding AC output terminal, switch the modulation mode of the split-phase double half-bridge inverter from bipolar modulation to unipolar modulation; The controller determines whether the system meets standby conditions based on real-time acquired first output voltage, second output voltage, first output current, and second output current. Standby conditions are typically set as follows: an output voltage higher than a certain threshold and an output current lower than a certain threshold indicate that the system is in a light-load or no-load operating state. In this state, the losses of power devices and control circuits account for a relatively high proportion of total power consumption, making it necessary to reduce standby power consumption by switching modulation methods. When the standby conditions are met, the switching is not performed immediately, but rather waits for the zero-crossing point of the corresponding AC output voltage before switching. Switching at the zero-crossing point is chosen because the output voltage is zero at this point, minimizing the impact on the output waveform and avoiding voltage spikes or current surges during switching, ensuring a smooth system transition.

[0041] In one possible implementation, the standby condition includes: both the first output voltage VL1 and the second output voltage VL2 are greater than a first voltage threshold V. limit1 Furthermore, both the first output current IL1 and the second output current IL2 are less than the first current threshold I. limit1 .

[0042] When the above conditions are met simultaneously, the system is determined to enter standby mode and the modulation mode is switched. After switching to unipolar modulation mode, in order to reduce the switching losses of the main power switching transistors, the controller changes the drive logic of each switching transistor as follows: During the positive half-cycle of the first output voltage corresponding to the first AC output terminal, the first switch Q1 is controlled to switch on at high frequency, and the second switch Q2 is controlled to remain normally off. During the negative half-cycle of the first output voltage, the second switch Q2 is controlled to switch on at high frequency, and the first switch Q1 is controlled to remain normally off.

[0043] Similarly, during the positive half-cycle of the second output voltage corresponding to the second AC output terminal, the third switch Q3 is controlled to switch on at high frequency, and the fourth switch Q4 is controlled to remain normally off; during the negative half-cycle of the second output voltage, the fourth switch Q4 is controlled to switch on at high frequency, and the third switch Q3 is controlled to remain normally off.

[0044] Under the aforementioned unipolar modulation timing, since only one switching transistor performs high-frequency chopping within half a power frequency cycle, ignoring the effects of dead time and non-ideal freewheeling, the output voltage during the positive half-cycle (Duty period) is +Vdc, and theoretically, the output voltage is 0 during the 1-Duty period; similarly, the negative half-cycle switches between -Vdc and 0. Under these ideal conditions, the average voltage of unipolar modulation is Vave = Duty × Vdc (positive half-cycle) or Vave = Duty × (-Vdc) (negative half-cycle).

[0045] To track the target modulated wave m×sin(wt), the ideal duty cycle should be its absolute value, i.e., Duty=|m×sin(wt)|. Combining this with the inverse ratio generation method of the PWM counter (Duty=1-Cmp / Period), it can be deduced that under unipolar modulation, regardless of whether the output voltage is positive or negative, the basic comparison value Cmp is always between [0,Period], and the mathematical expression changes to: Cmp=Period×(1-|m×sin(wt)|); However, for the split-phase dual half-bridge topology, when both the upper and lower bridge arms are off during the 1-Duty time period, the voltage is not at zero level due to the freewheeling current of the energy storage element. This causes a deviation in amplitude and phase between the actual output voltage and the expected voltage m×sin(wt)×Vdc. For example Figure 4 As shown, Figure 4 The actual output voltage waveform when using an open-loop sinusoidal modulation wave is shown. The voltage is obviously distorted, and the generation method of the modulation wave needs to be corrected to output a high-quality sinusoidal waveform.

[0046] S30, under unipolar modulation, the duty cycle of each AC output terminal is corrected according to the volt-second balance relationship of the freewheeling phase of the first AC output terminal and the second AC output terminal, and the PWM comparison value is determined according to the corrected duty cycle. The split-phase dual half-bridge topology has inherent structural defects under the aforementioned unipolar modulation. During the 1-Duty freewheeling period, because both the upper and lower bridge arms are forcibly turned off by software or are in dead time, the inductor current can only freewheel through the loop formed by the anti-parallel diode and the filter capacitor. This results in the output voltage not being at an ideal zero level during this stage. This non-zero level freewheeling causes amplitude and phase deviations between the actual output voltage and the desired target voltage (e.g., Figure 4 (The waveform shown is distorted). Therefore, it is necessary to perform open-loop duty cycle prediction correction based on the actual physical circuit.

[0047] For either the first AC output terminal or the second AC output terminal, the controller takes it as the current output terminal and independently executes the following duty cycle correction steps: First, in standby mode, the external load current is extremely small, and the standby ripple current mainly flows through the internal circuit formed by the filter inductor and filter capacitor. Therefore, the current output current I at the current output terminal can be approximated as the current Ic of the filter capacitor corresponding to that current output terminal.

[0048] Next, based on the change in current of the corresponding filter inductor at the current output terminal during the conduction period, the change in inductor ripple current is determined.

[0049] Assuming the target output voltage at the current output terminal is: Vref = m × sin(wt) × Vdc, during the conduction period (Duty × Ts), the voltage across the filter inductor is: Vdc - Vref; during the abnormal freewheeling period, because the current is clamped to the bus through the diode, the voltage across the filter inductor becomes: -Vdc - Vref. According to the voltage-current relationship of the inductor element, the change in inductor current during the conduction time Duty × Ts satisfies: di = (Vdc - Vref) × Duty × Ts / L; Where di is the change in inductor ripple current at the current output terminal, Vdc is the DC bus voltage, Vref is the target output voltage at the current output terminal, Duty is the duty cycle of the current output terminal in the current switching cycle, Ts is the switching cycle, and L is the filter inductance value corresponding to the current output terminal.

[0050] Then, based on the volt-second balance relationship, the voltage bias coefficient of the filter inductor during the freewheeling phase is determined; During the freewheeling period of the filter inductor, due to abnormal freewheeling, the inductor voltage becomes -Vdc - Vref. According to the inductor volt-second balance principle, the current change di during the conduction period is equal to the current change during the freewheeling period, i.e., di = -(-Vdc - Vref) × k × Duty × Ts / L. Combining the determined inductor ripple current change di, the two equations can be solved by eliminating di, and the voltage bias coefficient can be obtained, resulting in: k = (Vdc - Vref) / (Vdc + Vref); Where k is the voltage bias coefficient of the current output terminal, Vdc is the DC bus voltage, and Vref is the target output voltage of the current output terminal.

[0051] The charge balance relationship of the filter capacitor current within one switching cycle is determined based on the current of the filter capacitor, the change in the inductor ripple current, and the voltage bias coefficient. like Figure 5 As shown, within a complete switching cycle, the integral of the filter capacitor current is equivalent to the area of ​​the inductor ripple current triangle. This triangle area consists of the conduction phase (base is Duty×Ts, height is the corresponding proportional portion of di) and the freewheeling phase (base is k×Duty×Ts, height is the corresponding proportional portion of di). From this, the charge balance equation for capacitor charging and discharging can be constructed, resulting in: Ic×Ts=(Duty×Ts)×di / 2+(k×Duty×Ts)×di / 2; Where Ic is the current of the filter capacitor corresponding to the current output terminal, Ts is the switching period, Duty is the duty cycle of the current output terminal in the current switching period, and di is the change in the inductor ripple current of the current output terminal.

[0052] Finally, based on the charge balance relationship, determine the corrected duty cycle of the current output terminal; Substituting the previously obtained expressions for the voltage bias coefficient k and the inductor ripple current change di into the charge balance equation, and after simplification and term extraction, the desired duty cycle required to offset the non-zero level freewheeling current can be calculated, yielding: ; Among them, Duty new The current output is the corrected duty cycle, L is the filter inductance value corresponding to the current output, Ts is the switching period, Ic is the current of the filter capacitor corresponding to the current output, Vdc is the DC bus voltage, and Vref is the target output voltage of the current output.

[0053] Once the corrected duty cycle at the current output is determined, the PWM comparison value Cmp can be determined based on the corrected duty cycle.

[0054] Because the PWM module inside the control chip typically uses an up-and-down counting mode, the PWM comparison value is inversely proportional to the duty cycle. Therefore, the corrected duty cycle... new The register count value, converted to an unsigned integer, is represented as: Cmp = Period × (1 - Duty) new ); Where Cmp is the PWM compare value corresponding to the current output, Period is the PWM period count value, and Duty is the duty cycle count. new This is the corrected duty cycle for the current output.

[0055] In one possible implementation, after determining the PWM comparison value based on the modified duty cycle, the method further includes: Write the PWM comparison value corresponding to the first AC output terminal into the register of the first PWM module, and the first PWM module outputs the drive signal that controls the circuit where the first AC output terminal is located. By updating the value of the comparison register at the bottom layer of the first PWM module, the first switch Q1 and the second switch Q2 of the first half-bridge can perform unipolar operation according to the corrected duty cycle, thereby completing the output distortion compensation of the circuit where the first AC output terminal L1 is located.

[0056] Write the PWM comparison value corresponding to the second AC output terminal into the register of the second PWM module, and the second PWM module outputs the drive signal that controls the circuit where the second AC output terminal is located; Similarly, by updating the register of the second PWM module, the second half-bridge is made independent of the first half-bridge, and the third switch Q3 and the fourth switch Q4 are controlled to perform corresponding high-frequency chopping or normally off operations according to their dedicated corrected duty cycles, so as to compensate for the waveform distortion of the second AC output terminal L2.

[0057] The logic for outputting drive signals by the first PWM module and the second PWM module includes: when the count value of the time base counter increases and the corresponding PWM comparison value is greater than the time base counter, a high-level drive signal is output; when the count value decreases and the corresponding PWM comparison value is less than the time base counter, a low-level drive signal is output.

[0058] Based on the aforementioned logic rules, the underlying hardware comparator converts the unsigned PWM comparison value into a precise pulse width modulation signal in real time, which is then sent to the drive circuits of each half-bridge switch. This achieves the goal of maintaining high-quality sine wave output on both channels even with extremely low standby power consumption. Figure 6 As shown.

[0059] In one possible implementation, the correction of the respective duty cycles further includes: For the first AC output terminal and the second AC output terminal, closed-loop adjustment is performed according to the error between their actual output voltage and the target output voltage to obtain their respective closed-loop adjustment values; To eliminate the static error in the open-loop prediction model caused by hardware parameters (such as inductance drift with temperature) and dead-zone effects, the system acquires the actual output voltages of the two channels in real time and calculates the difference between them and the corresponding target reference voltages. The obtained errors are then input into either a proportional-integral (PI) or proportional-resonant (PR) regulator to calculate the closed-loop regulation amount used to eliminate steady-state errors.

[0060] The closed-loop adjustment is superimposed on the corresponding corrected duty cycle to obtain the final duty cycle of the corresponding AC output terminal.

[0061] The calculated closed-loop regulation is directly fed forward and superimposed onto the corrected duty cycle calculated by the open-loop prediction, forming a composite control strategy combining "feedforward prediction + feedback fine-tuning". Using this final duty cycle to calculate the PWM comparison value can further improve the accuracy of the output voltage and the dynamic robustness of the system.

[0062] S40, when the first output voltage, the second output voltage, the first output current and the second output current meet the load conditions, at the zero-crossing point of the output voltage at the corresponding AC output terminal, the modulation mode of the split-phase dual half-bridge inverter is restored to bipolar modulation. During unipolar standby operation, if an external load is suddenly connected or increased, the system quickly exits the low-power state to ensure stable output voltage.

[0063] The load conditions include: either the first output voltage or the second output voltage is less than the second voltage threshold (voltage drop occurs), or either the first output current or the second output current is greater than the second current threshold (load current surge). If either of the two outputs triggers the above conditions, the system determines that it needs to exit standby mode.

[0064] To prevent the inverter from frequently oscillating between bipolar modulation and unipolar modulation under critical load, this embodiment introduces hysteresis control logic in its design, that is, setting the first voltage threshold to be greater than the second voltage threshold and the first current threshold to be less than the second current threshold.

[0065] When the exit condition is met, the controller also connects at the zero-crossing point of the AC output voltage corresponding to the affected or triggered condition, forcibly restoring the control strategy to the bipolar modulation mode in S10, and the full bridge resumes high-frequency operation to provide sufficient load capacity.

[0066] It should be noted that, in order to adapt to different application scenarios and load characteristics, in addition to the threshold judgment method based on direct comparison of voltage and current mentioned above, standby conditions and load conditions may also include at least one of the following state judgment methods: Power output-based judgment: The first output power is calculated based on the first output voltage and first output current obtained from the first AC output terminal; the second output power is calculated based on the second output voltage and second output current from the second AC output terminal. Standby conditions include: both the first and second output powers are less than a preset first power threshold. Load conditions include: either the first or second output power is greater than a preset second power threshold.

[0067] Based on load impedance characteristics: The first equivalent load impedance is calculated based on the first output voltage and the first output current; the second equivalent load impedance is calculated based on the second output voltage and the second output current. Standby conditions include: both the first and second equivalent load impedances are greater than a preset first impedance threshold (i.e., indicating that the external system is under extremely light load or open circuit). Load conditions include: either the first or second equivalent load impedance is less than a preset second impedance threshold (i.e., indicating that an effective electrical device is connected externally).

[0068] The above-mentioned judgment methods based on voltage and current thresholds, output power, and load impedance can be used independently in practical applications, or they can be combined with each other through logical "AND" and "OR" relationships.

[0069] Figure 7 A flowchart illustrating another standby control method for a split-phase dual half-bridge inverter is shown, and the specific process is as follows: Step 1: Obtain the first output voltage VL1 and the first output current IL1 of the first AC output terminal L1 in the split-phase dual half-bridge inverter, and the second output voltage VL2 and the second output current IL2 of the second AC output terminal L2, and then proceed to Step 2. Step 2: Determine whether the first output voltage VL1 and the second output voltage VL2 are both greater than the first voltage threshold Vlimit1, and whether the first output current IL1 and the second output current IL2 are both less than the first current threshold Ilimit1. If yes, proceed to step 3; otherwise, maintain the normal bipolar modulation mode and return to step 1. Step 3: At the zero-crossing point of the output voltage (VL1 or VL2) at the corresponding AC output terminal, smoothly switch the modulation mode of the split-phase dual half-bridge inverter from bipolar modulation to unipolar modulation, and then proceed to step 4. Step 4: Determine the first output current IL1 and the second output current IL2 as the current Ic of their respective filter capacitors, and then proceed to Step 5. Step 5: Based on the current change of the filter inductors corresponding to the first AC output terminal L1 and the second AC output terminal L2 during the conduction period, determine the corresponding inductor ripple current change di, and then proceed to step 6. Step 6: Based on the volt-second balance relationship, determine the voltage bias coefficient k of the filter inductors corresponding to the first AC output terminal L1 and the second AC output terminal L2 during the freewheeling stage, and then proceed to Step 7. Step 7: Based on the current Ic of the filter capacitor, the change in the inductor ripple current di, and the voltage bias coefficient k, determine the charge balance relationship of the filter capacitor current Ic corresponding to the first AC output terminal L1 and the second AC output terminal L2 within one switching cycle, and then proceed to step 8. Step 8: Based on the charge balance relationship, determine the corrected duty cycles (Duty) for the first AC output terminal L1 and the second AC output terminal L2, respectively. new Proceed to step nine; Step 9: Perform closed-loop adjustment based on the error between the actual output voltages (VL1, VL2) of the first AC output terminal L1 and the second AC output terminal L2 and the target output voltage Vref, respectively, to obtain the corresponding closed-loop adjustment amount, and then add the closed-loop adjustment amount to the corresponding corrected duty cycle. new As the final duty cycle, proceed to step ten; Step 10: Determine the PWM comparison value Cmp corresponding to the first AC output terminal L1 and the second AC output terminal L2 according to the final duty cycle, and write it into the corresponding PWM module register to output the drive signal. Then execute Step 11. Step 11: Determine whether either the first output voltage VL1 or the second output voltage VL2 is less than the second voltage threshold Vlimit2, or whether either the first output current IL1 or the second output current IL2 is greater than the second current threshold Ilimit2. If so, at the zero-crossing point of the output voltage at the corresponding AC output terminal, restore the modulation mode of the split-phase dual half-bridge inverter to bipolar modulation and return to step 1. If not, maintain unipolar modulation and return to step 1.

[0070] like Figure 8 As shown, one embodiment of this application provides a standby control device 50 for a split-phase dual half-bridge inverter, which includes: The acquisition module 51 is used to acquire the first output voltage and the first output current of the first AC output terminal, and the second output voltage and the second output current of the second AC output terminal in the split-phase dual half-bridge inverter. The standby switching module 52 is used to switch the modulation mode of the split-phase dual half-bridge inverter from bipolar modulation to unipolar modulation at the zero-crossing point of the output voltage at the corresponding AC output terminal when the first output voltage, the second output voltage, the first output current and the second output current meet the standby conditions. The modulation compensation module 53 is used to correct the duty cycle of each AC output terminal and the second AC output terminal respectively according to the volt-second balance relationship of the freewheeling phase under unipolar modulation, and to determine the PWM comparison value according to the corrected duty cycle. The load recovery module 54 is used to restore the modulation mode of the split-phase dual half-bridge inverter to bipolar modulation at the zero-crossing point of the output voltage at the corresponding AC output terminal when the first output voltage, the second output voltage, the first output current and the second output current meet the load conditions.

[0071] Each module in the above-mentioned device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0072] like Figure 9As shown, one embodiment of the present invention provides an electronic device 700. The electronic device 700 includes a memory 701, a processor 702, and an input / output (I / O) interface 703. The memory 701 is used to store instructions. The processor 702 is used to execute the standby control method for a split-phase dual-half-bridge inverter according to embodiments of the present application by calling the instructions stored in the memory 701. The processor 702 is connected to both the memory 701 and the I / O interface 703, for example, via a bus system and / or other forms of connection mechanisms (not shown). The memory 701 can be used to store programs and data, including the program for the standby control method for a split-phase dual-half-bridge inverter according to embodiments of the present application. The processor 702 executes various functional applications and data processing of the electronic device 700 by running the program stored in the memory 701.

[0073] In this embodiment, the processor 702 can be implemented in at least one of the following hardware forms: digital signal processor (DSP), field programmable gate array (FPGA), and programmable logic array (PLA). The processor 702 can be one or a combination of several of the following: central processing unit (CPU) or other processing units with data processing capability and / or instruction execution capability.

[0074] The memory 701 in this embodiment may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), flash memory, hard disk drive (HDD), or solid state drive (SSD).

[0075] In this embodiment, the I / O interface 703 can be used to receive input instructions (such as numeric or character information, and to generate key signal inputs related to user settings and function control of the electronic device 700), and can also output various information (such as images or sounds) to the outside. In this embodiment, the I / O interface 703 may include one or more of the following: a physical keyboard, function keys (such as volume control keys, power buttons, etc.), a mouse, a joystick, a trackball, a microphone, a speaker, and a touch panel.

[0076] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the field of this application that are not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0077] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

[0078] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A standby control method for a split-phase dual half-bridge inverter, characterized in that... include: Obtain the first output voltage and first output current of the first AC output terminal, and the second output voltage and second output current of the second AC output terminal in the split-phase dual half-bridge inverter. When the first output voltage, the second output voltage, the first output current, and the second output current meet the standby conditions, at the zero-crossing point of the output voltage at the corresponding AC output terminal, the modulation mode of the split-phase dual half-bridge inverter is switched from bipolar modulation to unipolar modulation. Under the unipolar modulation, the duty cycle of each AC output terminal is corrected according to the volt-second balance relationship of the freewheeling phase of the first AC output terminal and the second AC output terminal, and the PWM comparison value is determined according to the corrected duty cycle. When the first output voltage, the second output voltage, the first output current, and the second output current meet the load conditions, the modulation mode of the split-phase dual half-bridge inverter is restored to bipolar modulation at the zero-crossing point of the output voltage at the corresponding AC output terminal.

2. The standby control method for a split-phase dual half-bridge inverter as described in claim 1, characterized in that: The standby conditions include: Both the first output voltage and the second output voltage are greater than the first voltage threshold, and both the first output current and the second output current are less than the first current threshold. The load conditions include: Either the first output voltage or the second output voltage is less than the second voltage threshold, or either the first output current or the second output current is greater than the second current threshold.

3. The standby control method for a split-phase dual half-bridge inverter as described in claim 2, characterized in that: The first voltage threshold is greater than the second voltage threshold, and the first current threshold is less than the second current threshold.

4. The standby control method for a split-phase dual half-bridge inverter as described in claim 1, characterized in that, Under the unipolar modulation, the duty cycle is corrected according to the volt-second balance relationship during the freewheeling phases of the first AC output terminal and the second AC output terminal, including: For either the first AC output terminal or the second AC output terminal, perform the following steps as the current output terminal: The output current of the current output terminal is determined to be the current of the filter capacitor corresponding to the current output terminal; Determine the change in inductor ripple current based on the change in current of the corresponding filter inductor at the current output terminal during the conduction period; Based on the volt-second balance relationship, determine the voltage bias coefficient of the filter inductor during the freewheeling phase; The charge balance relationship of the filter capacitor current within one switching cycle is determined based on the current of the filter capacitor, the change in the inductor ripple current, and the voltage bias coefficient. Based on the charge balance relationship, the corrected duty cycle of the current output terminal is determined.

5. The standby control method for a split-phase dual half-bridge inverter as described in claim 4, characterized in that: The voltage bias coefficient is expressed as follows: k = (Vdc - Vref) / (Vdc + Vref); Where k is the voltage bias coefficient of the current output terminal, Vdc is the DC bus voltage, and Vref is the target output voltage of the current output terminal.

6. The standby control method for a split-phase dual half-bridge inverter as described in claim 4, characterized in that: The change in inductor ripple current is expressed as: di = (Vdc - Vref) × Duty × Ts / L; Where di is the change in inductor ripple current at the current output terminal, Vdc is the DC bus voltage, Vref is the target output voltage at the current output terminal, Duty is the duty cycle of the current output terminal in the current switching cycle, Ts is the switching cycle, and L is the filter inductance value corresponding to the current output terminal.

7. The standby control method for a split-phase dual half-bridge inverter as described in claim 4, characterized in that: The charge balance relationship of the filter capacitor current during one switching cycle is as follows: Ic×Ts=(Duty×Ts)×di / 2+(k×Duty×Ts)×di / 2; Where Ic is the current of the filter capacitor corresponding to the current output terminal, k is the voltage bias coefficient of the current output terminal, Duty is the duty cycle of the current output terminal in the current switching cycle, Ts is the switching cycle, and di is the change in inductor ripple current of the current output terminal.

8. The standby control method for a split-phase dual half-bridge inverter as described in claim 4, characterized in that: The corrected duty cycle is expressed as follows: ； Among them, Duty new The current output is the corrected duty cycle, L is the filter inductance value corresponding to the current output, Ts is the switching period, Ic is the current of the filter capacitor corresponding to the current output, Vdc is the DC bus voltage, Vref is the target output voltage of the current output, and Sqrt() is the square root operation.

9. The standby control method for a split-phase dual half-bridge inverter as described in claim 8, characterized in that: The determination of the PWM comparison value based on the corrected duty cycle is expressed as: Cmp = Period × (1 - Duty) new ); Where Cmp is the PWM compare value corresponding to the current output, Period is the PWM period count value, and Duty is... new This is the corrected duty cycle for the current output.

10. The standby control method for a split-phase dual half-bridge inverter as described in claim 1, characterized in that, After determining the PWM comparison value based on the corrected duty cycle, the following is also included: Write the PWM comparison value corresponding to the first AC output terminal into the register of the first PWM module, and the first PWM module outputs the drive signal that controls the circuit where the first AC output terminal is located; Write the PWM comparison value corresponding to the second AC output terminal into the register of the second PWM module, and the second PWM module outputs the drive signal that controls the circuit where the second AC output terminal is located; The logic for the first PWM module and the second PWM module to output drive signals includes: outputting a high-level drive signal when the count value of the time base counter increases and the corresponding PWM comparison value is greater than the time base counter, and outputting a low-level drive signal when the count value decreases and the corresponding PWM comparison value is less than the time base counter.

11. The standby control method for a split-phase dual half-bridge inverter as described in claim 1, characterized in that, After correcting the corresponding duty cycles, it also includes: For the first AC output terminal and the second AC output terminal, closed-loop adjustment is performed according to the error between their actual output voltage and the target output voltage to obtain their respective closed-loop adjustment values; The closed-loop adjustment is superimposed on the corresponding corrected duty cycle to obtain the final duty cycle of the corresponding AC output terminal.

12. A standby control method for a split-phase dual half-bridge inverter as described in any one of claims 1-11, characterized in that: The split-phase dual half-bridge inverter includes a first half-bridge and a second half-bridge. The first half-bridge includes a first switch and a second switch connected in series, and the second half-bridge includes a third switch and a fourth switch connected in series. In the bipolar modulation mode, the first switch and the second switch are complementary in conduction, and the third switch and the fourth switch are complementary in conduction. Under the unipolar modulation method: during the positive half-cycle of the first output voltage corresponding to the first AC output terminal, the first switch is controlled to switch on at high frequency, and the second switch is controlled to remain in a normally off state; during the negative half-cycle of the first output voltage, the second switch is controlled to switch on at high frequency, and the first switch is controlled to remain in a normally off state. During the positive half-cycle of the second output voltage corresponding to the second AC output terminal, the third switch is controlled to switch on at high frequency, and the fourth switch is controlled to remain in a normally off state; during the negative half-cycle of the second output voltage, the fourth switch is controlled to switch on at high frequency, and the third switch is controlled to remain in a normally off state.

13. A standby control device for a split-phase dual half-bridge inverter, characterized in that, The device includes: The acquisition module is used to acquire the first output voltage and first output current of the first AC output terminal, and the second output voltage and second output current of the second AC output terminal in the split-phase dual half-bridge inverter. The standby switching module is used to switch the modulation mode of the split-phase dual half-bridge inverter from bipolar modulation to unipolar modulation at the zero-crossing point of the output voltage at the corresponding AC output terminal when the first output voltage, the second output voltage, the first output current and the second output current meet the standby conditions. The modulation compensation module is used to correct the duty cycle of the first AC output terminal and the second AC output terminal respectively according to the volt-second balance relationship of the freewheeling phase under the unipolar modulation, and determine the PWM comparison value according to the corrected duty cycle. The load recovery module is used to restore the modulation mode of the split-phase dual half-bridge inverter to bipolar modulation at the zero-crossing point of the output voltage at the corresponding AC output terminal when the first output voltage, the second output voltage, the first output current and the second output current meet the load conditions.

14. An electronic device, characterized in that, include: The device includes a power converter, an input unit, a memory, at least one processor, and an output interface. The memory stores program instructions that can be executed on the processor, which can call the program instructions to perform the standby control method for a split-phase dual half-bridge inverter as described in any one of claims 1 to 12.

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