A SAW filter package structure and a preparation method thereof

Abstract

The application discloses a SAW filter packaging structure and a preparation method thereof. The packaging structure comprises a supporting substrate layer, a functional layer and a piezoelectric single crystal material thin layer arranged on the supporting substrate layer in sequence, an interdigital transducer and a signal transmission electrode arranged on the piezoelectric single crystal material thin layer, and a PAD with a solder ball arranged on the lower surface of the supporting substrate layer. A cover wafer cover is arranged on the supporting substrate layer, a groove is formed on the lower surface of the cover wafer cover to form a cavity for accommodating the functional layer, the piezoelectric single crystal material thin layer and the interdigital transducer. A signal transmission through hole penetrates the piezoelectric single crystal material thin layer, the functional layer and the supporting substrate layer, and is filled with conductive metal to electrically connect the signal transmission electrode and the corresponding PAD. A metal material layer is arranged on the periphery of the piezoelectric single crystal material thin layer on the supporting substrate layer, is bonded to a conductive metal thin layer on the lower surface of the cover wafer, and is connected to the PAD through the conductive metal in the grounding shielding through hole to realize electromagnetic shielding. The application further provides a corresponding preparation method. Through the vertical through hole interconnection and the peripheral grounding shielding structure, the application realizes the miniaturization, low insertion loss and good anti-electromagnetic interference performance of the SAW filter, and improves the packaging reliability and integration.

Description

Technical Field

[0001] This invention belongs to the field of SAW filter packaging technology, specifically relating to a SAW filter packaging structure and its fabrication method. Background Technology

[0002] Surface acoustic wave (SAW) devices are solid-state devices that use sound waves generated by interdigital transducers fabricated on piezoelectric wafers to process electrical signals. They can be used as filters, delay lines, oscillators, etc., and are widely used in electronic information systems such as communications and radar. With the development of next-generation electronic information systems and 5G communications, SAW devices are evolving towards miniaturization, integrability, and higher performance. Wafer-level packaging (WLP) technology has become an important development direction for SAW filter packaging due to its ability to significantly reduce package size and manufacturing costs.

[0003] Currently, wafer-level packaging of SAW filters mainly borrows from semiconductor wafer-level packaging processes. The key technology involves forming a cavity above the working area of ​​the surface acoustic wave (SAW) filter wafer and using redistribution lines (RDL) to route signal lines to the outside of the device for connection to the substrate. There are two main implementation methods. One method involves attaching two layers of polyimide resin film to the wafer surface using a lamination device. This resin film forms a protective cavity to protect the working area, while electroplating and other processes are used to bring the pads around the chip to the device surface to complete the packaging. Although this method is relatively simple, the resin film structure has low strength and poor environmental tolerance, making it difficult to meet the requirements of high-reliability, hermetically tight applications. The other method involves directly bonding a capped wafer to a piezoelectric wafer to form a sealed cavity. However, due to the limitations of typical piezoelectric single-crystal materials (such as lithium niobate)... The coefficient of thermal expansion is approximately Lithium tantalate The coefficient of thermal expansion is approximately ) and silicon materials (thermal expansion coefficient is approximately The coefficients of thermal expansion of the two materials differ significantly, inevitably leading to thermal and lattice mismatch issues between wafers during heterogeneous bonding. Furthermore, piezoelectric wafer materials such as lithium niobate and lithium tantalate inherently have low strength, making them susceptible to substrate material cracking and bonding seal failure during bonding and subsequent use due to thermal stress. This results in low packaging yield and poor reliability.

[0004] In recent years, piezoelectric on insulator (POI) substrates have been proposed as a novel piezoelectric single-crystal composite thin film structure material. They typically consist of a thin layer of piezoelectric single-crystal material (such as LT / LN) and a functional layer (such as...). The device consists of a support substrate layer (such as high-resistivity Si or SiC). The introduction of the support substrate layer makes it possible to achieve hermetic wafer-level packaging of SAW devices using semiconductor technology. However, how to design a hermetic packaging structure based on POI wafers that can achieve reliable signal extraction and form good electromagnetic shielding, and simplify the fabrication process, remains a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] The technical problem to be solved by this invention is to address the issues of insufficient strength and poor airtightness of the resin film cavity structure in existing wafer-level packaging, as well as substrate cracking and bonding failure caused by the difference in thermal expansion coefficients between piezoelectric materials and silicon during direct bonding of cap wafers, while simultaneously achieving vertical signal extraction and effective electromagnetic shielding.

[0006] To address the aforementioned technical problems, one aspect of the present invention provides a SAW filter packaging structure, characterized by comprising: a supporting substrate layer; a cap wafer covering the upper surface of the supporting substrate layer; a functional layer disposed on the upper surface of the supporting substrate layer; a piezoelectric single crystal material thin layer disposed on the functional layer; a plurality of PADs disposed on the lower surface of the supporting substrate layer, each PAD having a solder ball disposed on its lower surface; the functional layer and the piezoelectric single crystal material thin layer being disposed inside the cap wafer; an interdigital transducer and a signal transmission electrode disposed on the upper surface of the piezoelectric single crystal material thin layer; a plurality of signal transmission vias formed on the upper surface of the piezoelectric single crystal material thin layer, the signal transmission vias sequentially penetrating the piezoelectric single crystal material thin layer, the functional layer, and the supporting substrate layer; each signal transmission via being filled with conductive metal, one end of the conductive metal in each signal transmission via being electrically connected to the corresponding signal transmission electrode, and the other end being electrically connected to the corresponding PAD.

[0007] Another aspect of the present invention provides a method for fabricating a SAW filter packaging structure, comprising:

[0008] S1: Multiple vias are fabricated on a POI wafer, wherein the POI wafer comprises, from bottom to top, a supporting substrate layer, a functional layer, and a thin layer of piezoelectric single crystal material; the vias include signal transmission vias and grounding shielding vias; the vias penetrate the thin layer of piezoelectric single crystal material, the functional layer, and the supporting substrate layer.

[0009] S2: An interdigital transducer and a signal transmission electrode are fabricated on the upper surface of the piezoelectric single crystal material thin layer, and the signal transmission electrode is electrically connected to the conductive metal in the signal transmission through hole.

[0010] S3: Etch away the piezoelectric single crystal material thin layer and functional layer around the interdigital transducer and signal transmission electrode, expose part of the upper surface of the support substrate layer, and fabricate a metal material layer on the exposed upper surface of the support substrate layer, so that the metal material layer is electrically connected to the conductive metal in the ground shielding via.

[0011] S4: Provide a cap wafer, etch a groove on the lower surface of the cap wafer, and fabricate a thin layer of conductive metal on the lower surface of the cap wafer and the inner side of the groove.

[0012] S5: Bond the cap wafer to the POI wafer, so that the conductive metal layer on the lower surface of the cap wafer is bonded to the metal material layer on the POI wafer to form a sealed cavity to accommodate the piezoelectric single crystal material layer, functional layer, interdigital transducer and signal transmission electrode.

[0013] S6: Fabricate a PAD on the lower surface of the support substrate layer of the POI wafer, make the PAD electrically connected to the conductive metal in the via, and fabricate solder balls on the PAD.

[0014] S7: Dice the wafer to obtain a single device and test it.

[0015] The present invention has at least the following beneficial effects

[0016] This invention utilizes a POI wafer composed of a support substrate layer, a functional layer, and a thin layer of piezoelectric single crystal material as its foundation. The high strength of the support substrate layer and its thermal expansion coefficient, similar to that of the cap wafer, effectively prevent substrate breakage and bonding failure during bonding and use. Simultaneously, the cap wafer bonds to the metal material layer on the support substrate layer to form a hermetically tight cavity, significantly improving packaging reliability and environmental tolerance. Furthermore, by pre-setting signal transmission vias penetrating the thin layer of piezoelectric single crystal material, the functional layer, and the support substrate layer within the POI wafer, vertical signal extraction is achieved, enabling interdigital transduction. The transducer and signal transmission electrodes can be directly fabricated on the conductive metal exposed by the via, eliminating the need for additional rewiring processes and electrode thickening steps, thus simplifying the process and reducing parasitic parameters. At the same time, by setting a ground shielding via through the support substrate layer, the conductive metal thin layer on the lower surface and inner side of the cap wafer forms a complete grounding loop with the PAD through the metal material layer, the ground shielding via, and the PAD, achieving effective electromagnetic shielding for the internal interdigital transducer. Ultimately, a high-performance SAW filter package device with small size, good hermeticity, strong electromagnetic interference resistance, and suitable for mass production is obtained. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of the present invention;

[0018] Figure 2 This is a schematic diagram of the POI wafer fabrication process;

[0019] Figure 3 This is a schematic diagram of the via fabrication process of the present invention. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0022] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0023] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0024] Please see Figure 1One aspect of the present invention provides a SAW filter packaging structure, characterized in that it includes: a supporting substrate layer; a cap wafer covering the upper surface of the supporting substrate layer; a functional layer disposed on the upper surface of the supporting substrate layer; a piezoelectric single crystal material thin layer disposed on the upper surface of the functional layer; a plurality of PADs disposed on the lower surface of the supporting substrate layer, each PAD having a solder ball disposed on its lower surface; the functional layer and the piezoelectric single crystal material thin layer being disposed inside the cap wafer; an interdigital transducer and a signal transmission electrode disposed on the upper surface of the piezoelectric single crystal material thin layer; a plurality of signal transmission vias formed on the upper surface of the piezoelectric single crystal material thin layer, the signal transmission vias sequentially penetrating the piezoelectric single crystal material thin layer, the functional layer, and the supporting substrate layer; each signal transmission via being filled with conductive metal, one end of the conductive metal in each signal transmission via being electrically connected to the corresponding signal transmission electrode, and the other end being electrically connected to the corresponding PAD.

[0025] Preferably, a conductive metal thin layer is provided on the lower surface of the cap wafer and the inner side surface of the cap wafer; a metal material layer is provided on the supporting substrate layer, and the metal material layer is located outside the piezoelectric single crystal material thin layer; the conductive metal thin layer on the lower surface of the cap wafer is bonded to the metal material layer on the supporting substrate layer.

[0026] Preferably, the supporting substrate layer has a plurality of grounding shielding vias running vertically through it; each grounding shielding via is filled with conductive metal, one end of the conductive metal in each grounding shielding via is electrically connected to the corresponding metal material layer, and the other end is electrically connected to the corresponding PAD.

[0027] Preferably, an annular step is provided at the upper end of the supporting substrate layer, and the annular step is located on the periphery of the piezoelectric single crystal material thin layer; the metal material layer is disposed on the surface of the step.

[0028] Preferably, the plurality of grounding shielding vias are evenly spaced on the steps of the supporting substrate layer.

[0029] Preferably, a groove is formed on the bottom of the cap wafer to form a cavity for accommodating a thin layer of piezoelectric single crystal material, a functional layer, an interdigital transducer, and a signal transmission electrode.

[0030] Another aspect of the present invention provides a method for fabricating a SAW filter packaging structure, comprising:

[0031] S1: Multiple vias are fabricated on a POI wafer, wherein the POI wafer comprises, from bottom to top, a supporting substrate layer, a functional layer, and a thin layer of piezoelectric single crystal material; the vias include signal transmission vias and grounding shielding vias; the vias penetrate the thin layer of piezoelectric single crystal material, the functional layer, and the supporting substrate layer.

[0032] S2: An interdigital transducer and a signal transmission electrode are fabricated on the upper surface of the piezoelectric single crystal material thin layer, and the signal transmission electrode is electrically connected to the conductive metal in the signal transmission through hole.

[0033] S3: Etch away the piezoelectric single crystal material thin layer and functional layer around the interdigital transducer and signal transmission electrode, expose part of the upper surface of the support substrate layer, and fabricate a metal material layer on the exposed upper surface of the support substrate layer, so that the metal material layer is electrically connected to the conductive metal in the ground shielding via.

[0034] S4: Provide a cap wafer, etch a groove on the lower surface of the cap wafer, and fabricate a thin layer of conductive metal on the lower surface of the cap wafer and the inner side of the groove.

[0035] S5: Bond the cap wafer to the POI wafer, so that the conductive metal layer on the lower surface of the cap wafer is bonded to the metal material layer on the POI wafer to form a sealed cavity to accommodate the piezoelectric single crystal material layer, functional layer, interdigital transducer and signal transmission electrode.

[0036] S6: Fabricate a PAD on the lower surface of the support substrate layer of the POI wafer, make the PAD electrically connected to the conductive metal in the via, and fabricate solder balls on the PAD.

[0037] S7: Dice the wafer to obtain a single device and test it.

[0038] Preferably, the via is processed by laser etching and has a diameter of 30~80μm; after filling with conductive metal, the upper and lower surfaces of the POI wafer are ground and polished to expose the two ends of the conductive metal.

[0039] Preferably, the bonding of the cap wafer and the POI wafer is performed in a nitrogen atmosphere, and the metal material layer and the conductive metal thin layer on the lower surface of the cap wafer achieve hermetic encapsulation of the structure through Cu-Sn or Au-Sn eutectic bonding, or Au-Au or Cu-Cu metal bonding.

[0040] The following embodiments are provided for the above technical solution:

[0041] This embodiment provides a method for fabricating a SAW filter packaging structure, particularly involving pre-fabricating metallized vias in a POI wafer to achieve vertical interconnection and grounding shielding. The following is in conjunction with... Figure 2 and Figure 3 Please provide a detailed explanation.

[0042] Step S1: Fabricate vias on the POI wafer and fill them with conductive metal.

[0043] POI wafers were fabricated using ion implantation lift-off (Smart-Cut) technology. For example... Figure 1As shown, this technology involves implanting H or He ions into a piezoelectric wafer (such as LT or LN) to form a damage layer, then bonding it to a support wafer, and finally peeling it off after heat treatment to form a layer consisting of a thin layer of piezoelectric single crystal material (such as LT / LN) and a functional layer (such as... A POI wafer is composed of a piezoelectric single crystal film and a supporting substrate layer (such as high-resistivity Si or SiC). After CMP polishing, an ideal piezoelectric single crystal film layer is obtained.

[0044] Via fabrication: A via fabrication step is added between the functional layer transfer and CMP polishing of the POI wafer. Based on the pad positions and wafer arrangement during filter design, array vias are created using laser etching. There are two types of vias: signal transmission vias (recommended diameter 40-80 μm) and ground shielding vias (recommended diameter 30-60 μm). For ground shielding vias, after subsequent etching to remove part of the piezoelectric single-crystal material thin layer and functional layer, the ground shielding vias only penetrate the supporting substrate layer. Ground shielding vias can also be fabricated after step S3 using the same process; however, to simplify the process flow, ground shielding vias and signal transmission vias can be fabricated simultaneously in step S1.

[0045] Metallization Filling: The vias are filled with conductive metal using conventional electroplating processes (such as copper plating). After filling, the top and bottom surfaces of the POI wafer are ground and polished to ensure that the top and bottom ends of the metal filling in the vias are exposed and flat. The completed structure is as follows. Figure 3 As shown, a piezoelectric single-crystal composite thin film structure wafer with pre-set vias is formed.

[0046] Step S2: Fabricate the interdigital transducer and signal transmission electrodes

[0047] On the surface of a thin layer of piezoelectric single-crystal material on the POI wafer, interdigital transducers (IDTs) and signal transmission electrodes are fabricated according to design requirements. During fabrication, photolithographic alignment accuracy must be ensured so that the signal transmission electrodes are directly fabricated on the exposed conductive metal of the signal transmission vias, forming a reliable electrical connection. The IDTs and electrodes can be made of Cu, Al, or Au. In this step, the signal transmission electrodes do not require additional thickness; they can be made of the same material and have the same thickness as the interdigital transducers.

[0048] Step S3: Expose the encapsulation area and fabricate a metal material layer

[0049] Etching to expose the substrate: Etching removes the thin layer of piezoelectric single-crystal material and the functional layer in the packaging area of ​​the POI wafer, exposing the upper surface of the supporting substrate layer. To ensure sufficient removal, slight over-etching can be performed, i.e., a small amount of substrate support material is removed. The functional pattern (IDT) should be located inside the packaging area.

[0050] Fabrication of the metal material layer: A metal material (such as Cu / Au), identical to that used in the interdigital transducer, is sputtered onto the exposed support substrate surface (outer periphery of the piezoelectric single-crystal material thin layer) to form a metal material layer. Simultaneously, ensure that this metal material layer is electrically connected to the conductive metal within the grounding shield via created in step S1. The stepped structure here does not affect the sputtering effect.

[0051] Step S4: Prepare capped wafer

[0052] A cap wafer is provided (preferably made of the same material as the POI wafer support substrate, such as silicon; that is, the cap wafer is a silicon wafer, and the support substrate is also a silicon substrate). A groove is etched on the lower surface of the cap wafer using deep silicon etching technology. The depth of this groove should ensure a certain gap between its top surface and the IDT after subsequent bonding. Subsequently, a conductive metal thin layer is fabricated on the lower surface of the cap wafer and the inner side of the groove using electroplating or sputtering. The material can be Au, Cu, or Sn. This metal thin layer is used for subsequent bonding and to form electromagnetic shielding.

[0053] Step S5: Wafer bonding and sealing

[0054] In nitrogen ( Wafer bonding is performed in an atmosphere to prevent metal layer oxidation. The prepared cap wafer is aligned and bonded to the POI wafer, so that the conductive metal layer on the lower surface of the cap wafer is connected to the metal material layer on the support substrate of the POI wafer through Cu-Sn or Au-Sn eutectic bonding. After bonding, the protrusions of the cap wafer contact the exposed support substrate material, forming a sealed cavity that houses the piezoelectric single crystal material layer, functional layer, interdigital transducer, and signal transmission electrode. Simultaneously, the conductive metal layer of the cap forms a grounding loop with the subsequent PAD through grounding shielding vias, achieving electromagnetic shielding of the IDT. Three to five grounding shielding vias can be evenly distributed around the perimeter of a single chip pattern to achieve ideal shielding.

[0055] Step S6: Fabricate the PAD and solder balls

[0056] PAD patterns are fabricated on the lower surface of the support substrate layer of the POI wafer, ensuring that the PAD size is slightly larger than the via diameter and completely covers the fill metal within the via, thus achieving electrical connection between the PAD and the conductive metal within the signal transmission via and the ground shielding via. Finally, solder balls are fabricated on the PAD using a printing process, with a recommended solder ball diameter of 60~80μm and a height of 30~50μm.

[0057] Using the dicing process in conventional semiconductor manufacturing, the bonded wafer is diced into individual devices, and the SAW filter packaging structure of this embodiment is completed after passing the test.

[0058] In summary, this invention proposes a SAW filter packaging structure based on a POI wafer and its fabrication method. Signal transmission vias and ground shielding vias are pre-fabricated simultaneously in a POI wafer composed of a support substrate layer, a functional layer, and a piezoelectric single-crystal material thin layer, and vertical interconnects are achieved by filling them with conductive metal. Subsequently, interdigital transducers and signal transmission electrodes are fabricated on the piezoelectric single-crystal material thin layer, allowing the electrodes to be directly electrically connected to the conductive metal within the signal transmission vias. Next, a portion of the support substrate layer is etched to expose it, and a metal material layer is fabricated, connecting it to the ground shielding via. Finally, a cap wafer with a conductive metal thin layer is bonded to the metal material layer on the POI wafer to form a sealed cavity. PADs and solder balls are fabricated on the lower surface of the support substrate layer. This invention avoids substrate breakage and bonding failure during heterogeneous bonding by utilizing the similar thermal expansion coefficients of the supporting substrate layer and the cap wafer. At the same time, it enables short-distance signal extraction through vertical vias, eliminating the need for additional rewiring processes. Furthermore, it connects the conductive metal layer of the cap to ground through ground shielding vias, forming a complete electromagnetic shielding circuit. This significantly improves the hermeticity, structural strength, reliability, and electromagnetic interference resistance of the package, achieving miniaturization, low insertion loss, and high-performance packaging suitable for mass production of SAW filters.

[0059] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A SAW filter packaging structure, characterized in that, include: Support substrate layer; A cap wafer is provided on the upper surface of the supporting substrate layer; a functional layer is provided on the upper surface of the supporting substrate layer; a thin layer of piezoelectric single crystal material is provided on the top of the functional layer; a plurality of PADs are provided on the lower surface of the supporting substrate layer, and solder balls are provided on the lower surface of each PAD; the functional layer and the thin layer of piezoelectric single crystal material are placed inside the cap wafer. The upper surface of the piezoelectric single crystal material thin layer is provided with an interdigital transducer and a signal transmission electrode; the upper surface of the piezoelectric single crystal material thin layer is provided with a plurality of signal transmission vias, which sequentially penetrate the piezoelectric single crystal material thin layer, the functional layer and the supporting substrate layer; each signal transmission via is filled with conductive metal, one end of the conductive metal in each signal transmission via is electrically connected to the corresponding signal transmission electrode, and the other end is electrically connected to the corresponding PAD.

2. The SAW filter packaging structure according to claim 1, characterized in that, A conductive metal thin layer is provided on the lower surface and the inner side surface of the cap wafer; a metal material layer is provided on the supporting substrate layer, and the metal material layer is located outside the piezoelectric single crystal material thin layer; the conductive metal thin layer on the lower surface of the cap wafer is bonded to the metal material layer on the supporting substrate layer.

3. The SAW filter packaging structure according to claim 2, characterized in that, The supporting substrate layer has multiple grounding shielding vias running vertically through it; each grounding shielding via is filled with conductive metal, one end of the conductive metal in each grounding shielding via is electrically connected to the corresponding metal material layer, and the other end is electrically connected to the corresponding PAD.

4. The SAW filter packaging structure according to claim 3, characterized in that, An annular step is provided at the upper end of the supporting substrate layer, and the annular step is located on the periphery of the piezoelectric single crystal material thin layer; the metal material layer is disposed on the surface of the step.

5. The SAW filter packaging structure according to claim 3, characterized in that, The multiple grounding shielding through holes are evenly distributed on the steps of the supporting substrate layer.

6. A SAW filter packaging structure according to claim 1 or 2, characterized in that, The cap wafer has a groove on its underside to form a cavity for accommodating a thin layer of piezoelectric single crystal material, a functional layer, an interdigital transducer, and a signal transmission electrode.

7. A method for fabricating a SAW filter packaging structure, used to fabricate the SAW filter packaging structure according to any one of claims 1 to 6, characterized in that, include: S1: Multiple vias are fabricated on a POI wafer, wherein the POI wafer comprises, from bottom to top, a supporting substrate layer, a functional layer, and a thin layer of piezoelectric single crystal material; the vias include signal transmission vias and grounding shielding vias; the vias penetrate the thin layer of piezoelectric single crystal material, the functional layer, and the supporting substrate layer. S2: An interdigital transducer and a signal transmission electrode are fabricated on the upper surface of the piezoelectric single crystal material thin layer, and the signal transmission electrode is electrically connected to the conductive metal in the signal transmission through hole. S3: Etch away the piezoelectric single crystal material thin layer and functional layer around the interdigital transducer and signal transmission electrode, expose part of the upper surface of the support substrate layer, and fabricate a metal material layer on the exposed upper surface of the support substrate layer, so that the metal material layer is electrically connected to the conductive metal in the ground shielding via. S4: Provide a cap wafer, etch a groove on the lower surface of the cap wafer, and fabricate a thin layer of conductive metal on the lower surface of the cap wafer and the inner side of the groove. S5: Bond the cap wafer to the POI wafer, so that the conductive metal layer on the lower surface of the cap wafer is bonded to the metal material layer on the POI wafer to form a sealed cavity to accommodate the piezoelectric single crystal material layer, functional layer, interdigital transducer and signal transmission electrode. S6: Fabricate a PAD on the lower surface of the support substrate layer of the POI wafer, make the PAD electrically connected to the conductive metal in the via, and fabricate solder balls on the PAD. S7: Dice the wafer to obtain a single device and test it.

8. The method for fabricating a SAW filter packaging structure according to claim 7, characterized in that, The vias are processed by laser etching, with a diameter of 30~80μm. After filling with conductive metal, the upper and lower surfaces of the POI wafer are ground and polished to make the wafer surface flat and expose the two ends of the conductive metal.

9. The method for fabricating a SAW filter packaging structure according to claim 7, characterized in that, The bonding of the cap wafer and the POI wafer is carried out in a nitrogen atmosphere. The metal material layer and the conductive metal thin layer on the lower surface of the cap wafer achieve hermetic encapsulation of the structure through Cu-Sn or Au-Sn eutectic bonding, or Au-Au or Cu-Cu metal bonding.

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