Dual-mode redundancy based anti-single event upset hardened voter and storage cell

Abstract

The application relates to the technical field of integrated circuit reinforcement design, and provides an anti-single-event-upset reinforcement voter and a storage unit based on dual-mode redundancy. Through improved design of the circuit structure, a reinforcement voting structure formed by a path controller 01, a path controller 02 and three-state output stages 1-5 with the same structure is formed, the module memory function is customized, the characteristics that the final output of the circuit remains the last output state when the inputs of the flip-flops are inconsistent are utilized, the anti-single-event-upset capability and reliability of the dual-mode redundancy design in the flip-flop holding stage are obviously improved, the problem that a traditional voter cannot shield errors in the flip-flop holding stage is solved, and the stable work of the circuit in a radiation environment is ensured.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit hardened design technology, and relates to a hardened voting device and memory unit based on dual-mode redundancy to resist single-event upsets. Background Technology

[0002] Single-event upsets (SEUs) are phenomena where high-energy particles collide with semiconductor devices, causing an abnormal flip in the logic state of the memory or logic cells within the device. Widely present in special radiation environments such as aerospace and nuclear reactors, SEUs can severely affect the normal operation of integrated circuits containing these cells, and may even lead to system failure. To resist SEUs, triple mode redundancy and dual interlocked storage cell (DICE) structures are among the most widely used radiation hardening solutions.

[0003] However, traditional triple redundancy relies solely on combinational logic voters for a 2-out-of-3 output and lacks reliable error masking capabilities, especially during the flip-flop hold phase. Therefore, improving the voter's resistance to single-event effects has become one of the technical problems to be solved. Summary of the Invention

[0004] To address the problems existing in the above-mentioned traditional methods, this invention proposes a dual-mode redundancy-based anti-single-event upset hardened voter and a storage unit, which can improve the voter's anti-single-event effect capability.

[0005] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: On the one hand, a dual-mode redundancy-based anti-single-event upset hardened voter is provided, including a path controller 01, a path controller 02, and three-state output stages 1 to 5 with identical structures; The input terminal of the path controller 01 is used to connect to the output terminal of the first flip-flop. The output terminal of the path controller 01 is connected to the first input terminal of the tri-state output stage 1 and the second input terminal of the tri-state output stage 2, respectively. The input terminal of the path controller 02 is used to connect to the output terminal of the second flip-flop. The output terminal of the path controller 02 is connected to the first input terminal of the tri-state output stage 2 and the second input terminal of the tri-state output stage 1, respectively. The enable terminals of both the path controller 01 and the path controller 02 are used to receive enable signals. The output terminals of the three-state output stage 1 are connected to the second input terminal of the three-state output stage 3, the first input terminal of the three-state output stage 4, and the first input terminal of the three-state output stage 5, respectively. The output terminals of the three-state output stage 2 are connected to the first input terminal of the three-state output stage 3, the second input terminal of the three-state output stage 4, and the second input terminal of the three-state output stage 5, respectively. The output terminal of the three-state output stage 3 is connected to the output terminal of the path controller 01. The output terminal of the three-state output stage 4 is connected to the output terminal of the path controller 02. The output terminal of the three-state output stage 5 is used to output the voting results. Path controller 01 and path controller 02 are used to synchronously turn on and off under the control of the enable signal. The three-state output stages are interconnected to form a dual-interlocked storage unit structure. When the enable signal is valid, the dual-interlocked storage unit structure outputs the current output state according to the output signal of the currently input flip-flop. When the enable signal is invalid, the output of the dual-interlocked storage unit structure remains at the previous output state. The enable signal is valid when the output signals of the first flip-flop and the second flip-flop are consistent, and the enable signal is invalid when the output signals of the first flip-flop and the second flip-flop are inconsistent.

[0006] In one embodiment, the path controller 01 is a tri-state buffer.

[0007] In one embodiment, the path controller 02 is a tri-state buffer.

[0008] In one embodiment, each tri-state output stage includes a PMOS transistor and an NMOS transistor. The gate of the PMOS transistor serves as the first input terminal of the tri-state output stage, and the gate of the NMOS transistor serves as the second input terminal of the tri-state output stage. The drain of the PMOS transistor is connected to the drain of the NMOS transistor and then led out as the output terminal of the tri-state output stage. The source of the PMOS transistor is used to connect to the power supply, and the source of the NMOS transistor is used to ground.

[0009] In one embodiment, the aforementioned dual-mode redundancy-based anti-single-event upset hardened voter further includes an XNOR gate. The first input of the XNOR gate is used to connect to the output of the first flip-flop, the second input of the XNOR gate is used to connect to the output of the second flip-flop, and the output of the XNOR gate is connected to the enable terminals of the path controller 01 and the path controller 02, respectively.

[0010] On the other hand, a storage unit is also provided, including a first flip-flop, a second flip-flop, a path controller 01, a path controller 02, and three-state output stages 1 to 5 with identical structures; the first flip-flop and the second flip-flop have identical structures; The input terminal of the path controller 01 is connected to the output terminal of the first flip-flop. The output terminal of the path controller 01 is connected to the first input terminal of the tri-state output stage 1 and the second input terminal of the tri-state output stage 2, respectively. The input terminal of the path controller 02 is connected to the output terminal of the second flip-flop. The output terminal of the path controller 02 is connected to the first input terminal of the tri-state output stage 2 and the second input terminal of the tri-state output stage 1, respectively. The enable terminals of both the path controller 01 and the path controller 02 are used to receive enable signals. The output terminals of the three-state output stage 1 are connected to the second input terminal of the three-state output stage 3, the first input terminal of the three-state output stage 4, and the first input terminal of the three-state output stage 5, respectively. The output terminals of the three-state output stage 2 are connected to the first input terminal of the three-state output stage 3, the second input terminal of the three-state output stage 4, and the second input terminal of the three-state output stage 5, respectively. The output terminal of the three-state output stage 3 is connected to the output terminal of the path controller 01. The output terminal of the three-state output stage 4 is connected to the output terminal of the path controller 02. The output terminal of the three-state output stage 5 is used to output the voting results. Path controller 01 and path controller 02 are used to synchronously turn on and off under the control of the enable signal. The three-state output stages are interconnected to form a dual-interlocked storage unit structure. When the enable signal is valid, the dual-interlocked storage unit structure outputs the current output state according to the output signal of the currently input flip-flop. When the enable signal is invalid, the output of the dual-interlocked storage unit structure remains at the previous output state. The enable signal is valid when the output signals of the first flip-flop and the second flip-flop are consistent, and the enable signal is invalid when the output signals of the first flip-flop and the second flip-flop are inconsistent.

[0011] One of the above technical solutions has the following advantages and beneficial effects: The aforementioned dual-mode redundancy-based hardened voter and storage unit, through improved circuit structure design, forms a hardened voting structure consisting of path controller 01, path controller 02, and three-state output stages 1 to 5 with identical structures. It features a customized module memory function, utilizing the characteristic that the final output of the circuit still maintains the previous output state when the inputs of each flip-flop are inconsistent. This significantly improves the dual-mode redundancy design's anti-single-event capability and reliability during the flip-flop holding phase, solves the problem that traditional voters cannot shield errors during the flip-flop holding phase, and ensures stable operation of the circuit in a radiated environment. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of a voting output circuit structure in a memory based on dual-mode redundancy and reinforced against single-event upsets in one embodiment. Figure 2 This is a schematic diagram of the structural composition of a dual-mode redundancy-based anti-single-event upset hardened voter in one embodiment; Figure 3 This is a schematic diagram of the circuit structure of a hardened voter based on dual-mode redundancy to resist single-event upsets in one embodiment; Figure 4 This is a schematic diagram of an XNOR gate in one embodiment; Figure 5 This is a schematic diagram of a voting output circuit structure for a storage unit in one embodiment. Detailed Implementation

[0014] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention.

[0015] It should be noted that, in this document, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The presentation of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments. The term "and / or" as used herein refers to any combination of one or more of the associated listed items, and all possible combinations, and includes such combinations.

[0016] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0017] In one embodiment, such as Figure 1 This diagram illustrates a voting output circuit structure in a memory that is hardened against single-event upsets based on dual-mode redundancy. The structure of this voting output circuit includes a voting device hardened against single-event upsets based on dual-mode redundancy, as shown below. Figure 2As shown, the system includes path controller 01, path controller 02, and three-state output stages 1 to 5 with identical structures. The input of path controller 01 is connected to the output Q_A of the first flip-flop, and its output is connected to the first input of three-state output stage 1 and the second input of three-state output stage 2. The input of path controller 02 is connected to the output Q_B of the second flip-flop, and its output is connected to the first input of three-state output stage 2 and the second input of three-state output stage 1. The enable terminals of both path controller 01 and path controller 02 are used to receive the enable signal EN.

[0018] The output terminals of tri-state output stage 1 are connected to the second input terminal of tri-state output stage 3, the first input terminal of tri-state output stage 4, and the first input terminal of tri-state output stage 5, respectively. The output terminals of tri-state output stage 2 are connected to the first input terminal of tri-state output stage 3, the second input terminal of tri-state output stage 4, and the second input terminal of tri-state output stage 5, respectively. The output terminal of tri-state output stage 3 is connected to the output terminal of path controller 01, the output terminal of tri-state output stage 4 is connected to the output terminal of path controller 02, and the output terminal of tri-state output stage 5 is used to output the voting result. The power supply terminal of each tri-state output stage is connected to the power supply Vdd, and the ground terminal of each tri-state output stage is grounded to GND.

[0019] Path controllers 01 and 02 are used to synchronously turn on and off under the control of the enable signal EN. The three-state output stages are interconnected to form a dual interlocked memory cell structure (DICE). When the enable signal EN is valid, the dual interlocked memory cell structure outputs the current output state according to the output signal of the currently input flip-flop. When the enable signal EN is invalid, the output of the dual interlocked memory cell structure remains the previous output state. The enable signal EN is valid when the output signals of the first flip-flop and the second flip-flop are consistent, and the enable signal EN is invalid when the output signals of the first flip-flop and the second flip-flop are inconsistent.

[0020] It is understandable that in the memory cell where the dual-mode redundancy-based hardened voter against single-event upsets is applied, the first and second flip-flops are typically two identical flip-flops forming a redundant flip-flop module. The clock terminals (Clk) of both flip-flops are connected to the same clock signal to ensure synchronous operation. The input terminals of both flip-flops are connected to the same input signal to ensure synchronous reception of the same control and data signals, thus achieving dual-mode redundancy data input. This realizes the dual-mode redundancy design. The output terminals (Q_A) of the first flip-flop and Q_B of the second flip-flop are connected to the voter, providing input data to the voter.

[0021] The required enable signal EN can be provided from the controller of the storage unit to control the switching of path controllers 01 and 02 in the voting unit. When the outputs Q_A and Q_B of the first and second flip-flops are not at the same level, the enable signal EN is invalid (e.g., low or high level), thereby turning off path controllers 01 and 02. This allows path controllers 01 and 02 to temporarily disconnect the output signals of the flip-flops from the DICE structure.

[0022] When the output terminals Q_A and Q_B of the first and second flip-flops are at the same level, the enable signal EN is active (e.g., high or low level), thereby activating path controllers 01 and 02. This allows path controllers 01 and 02 to output their respective flip-flop output signals to the DICE structure in the voter, which then outputs the signals to the final output terminal Q of the memory cell. Thus, if one of the flip-flops experiences a single-event flip, causing an output anomaly, the final output terminal Q retains the previous output state, achieving both decision and error masking functions.

[0023] The path controller 01 can be, but is not limited to, a four-way tri-state buffer, an eight-way tri-state buffer, or an open-drain / open-collector buffer (OD / OC), as long as it can be used for the required path on / off control. Similarly, the path controller 02 can also be, but is not limited to, a four-way tri-state buffer, an eight-way tri-state buffer, or an open-drain / open-collector buffer (OD / OC), as long as it can be used for the required path on / off control. The tri-state output stage can be, but is not limited to, a CMOS push-pull tri-state output stage, an inverter + series switch tri-state output stage, or a transmission gate + general buffer tri-state output stage, as long as it can be used to construct the required DICE structure.

[0024] The aforementioned dual-mode redundancy-based hardened voter against single-event upsets, through the improved design of the circuit structure, forms a hardened voting structure consisting of path controller 01, path controller 02, and three-state output stages 1 to 5 with identical structures. It features a customized module memory function, utilizing the characteristic that the final output of the circuit still maintains the previous output state when the inputs of each flip-flop are inconsistent. This significantly improves the single-event upset resistance and reliability of the dual-mode redundancy design during the flip-flop holding phase, solves the problem that traditional voters cannot shield errors during the flip-flop holding phase, and ensures stable operation of the circuit in a radiated environment.

[0025] In one embodiment, such as Figure 3 As shown, the path controller 01 is a tri-state buffer TSB1.

[0026] It is understandable that in this embodiment, a tri-state buffer TSB1 is directly used to control the signal path from the first flip-flop to the DICE structure, thus simplifying the circuit design. Under normal operating conditions (no single-event flip-flop): the two flip-flops work synchronously, Q_A=Q_B, the enable signal EN is valid, controlling the tri-state buffer TSB1 and the path controller 02 to conduct, and finally the output terminal Q is consistent with the level state of the output terminals of the two flip-flops, and the circuit outputs normally.

[0027] When a single trigger experiences a single-event flip (i.e., Q_A ≠ Q_B), the enable signal EN becomes invalid, controlling the three-state buffer TSB1 and the path controller 02 to shut down. This prevents the current erroneous output state caused by the single-event flip from reaching the DICE structure of the voter through the three-state buffer TSB1 and the path controller 02, ensuring that the state stored in the voter's DICE structure remains the previous state, thus effectively masking the erroneous state.

[0028] In one embodiment, such as Figure 3 As shown, the path controller 02 is a tri-state buffer TSB2.

[0029] It is understandable that in this embodiment, the tri-state buffer TSB2 is directly used to control the signal path from the second flip-flop to the DICE structure, thereby further simplifying the circuit design. Under normal operating conditions (no single-event flip-flop): the two flip-flops work synchronously, Q_A=Q_B, the enable signal EN is valid, controlling the tri-state buffers TSB1 and TSB2 to conduct, and finally the output terminal Q is consistent with the level state of the output terminals of the two flip-flops, and the circuit outputs normally.

[0030] When a single trigger experiences a single-event flip (i.e., Q_A ≠ Q_B), the enable signal EN becomes invalid, controlling the three-state buffers TSB1 and TSB2 to turn off. This prevents the current erroneous output state caused by the single-event flip from reaching the DICE structure of the voter through the three-state buffers TSB1 and TSB2, ensuring that the state stored in the voter's DICE structure remains the previous state, thus effectively masking the erroneous state.

[0031] In one embodiment, each tri-state output stage includes a PMOS transistor and an NMOS transistor. The gate of the PMOS transistor serves as the first input terminal of the tri-state output stage, and the gate of the NMOS transistor serves as the second input terminal of the tri-state output stage. The drains of the PMOS transistor and the NMOS transistor are connected and then led out as the output terminal of the tri-state output stage. The source of the PMOS transistor is used to connect to the power supply Vdd, and the source of the NMOS transistor is used to ground GND.

[0032] It is understood that in this embodiment, the DICE structure in the voting device adopts... Figure 3 The circuit design shown achieves high integration and simplified structure of the voter using CMOS technology. Furthermore, this structure can also achieve the following two purposes: First, when the voltage levels of outputs Q_A and Q_B are inconsistent, the tri-state buffers TSB1 and TSB2 shut down their respective signal transmission paths; for example, both buffers become high-impedance, and this high-impedance state is maintained by providing weak feedback. Second, in addition to maintaining this high-impedance state, it can also prevent the high-impedance state from being overturned, i.e., prevent single-event upsets in this part of the structure.

[0033] In one embodiment, the above-mentioned dual-mode redundancy-based anti-single-event upset hardened voter further includes an XNOR gate. The first input of the XNOR gate is used to connect to the output of the first flip-flop, the second input of the XNOR gate is used to connect to the output of the second flip-flop, and the output of the XNOR gate is connected to the enable terminals of the path controller 01 and the path controller 02, respectively.

[0034] It is understood that this embodiment also introduces, such as Figure 4 The XOR gate shown automatically generates the required enable signal EN based on the output of the trigger, thereby reducing the control loop length and improving the response speed of the enable control in a direct adaptive enable control manner.

[0035] Specifically, the outputs of the two flip-flops (Q_A and Q_B) can also be determined by an XNOR gate to output the corresponding enable signal EN, thereby controlling the switching of the tri-state buffers. When the output levels of the first flip-flop (Q_A) and the second flip-flop (Q_B) are inconsistent, the enable signal EN output by the XNOR gate is low (invalid), thus turning off tri-state buffers TSB1 and TSB2, making the outputs of both tri-state buffers high impedance.

[0036] When the outputs Q_A and Q_B of the first and second flip-flops are at the same level, the enable signal EN of the XOR gate is high (valid), thus enabling the tri-state buffers TSB1 and TSB2. This allows the tri-state buffers TSB1 and TSB2 to output signals to the DICE structure in the voter, which then outputs the signal to the final output Q of the memory cell. In this way, when one of the flip-flops experiences a single-event flip, causing an output anomaly, the state of the final output Q remains the same as the previous output state, thereby achieving the decision and error masking functions.

[0037] In some implementations, in the circuit design of the dual-mode redundancy-based anti-single-event upset hardened voter described above, it is necessary to ensure that the enable signal EN arrives at the tri-state buffer earlier than the input signal (i.e., the output signal of the flip-flop). Therefore, optionally, a regular buffer can be inserted between each flip-flop and the corresponding tri-state buffer to delay the output signal of the flip-flop, thereby ensuring that the enable signal EN arrives at the tri-state buffer earlier than the output signal of the flip-flop.

[0038] In some implementations, both flip-flops can be D flip-flops. D flip-flops are simple in structure and reliable, which can effectively reduce circuit costs and ensure reliability; other types of flip-flops can also be used to meet design requirements, therefore, D flip-flops are preferred but not limited to D flip-flops.

[0039] In one embodiment, such as Figure 5 As shown, a storage unit is also provided, including a first flip-flop, a second flip-flop, a path controller 01, a path controller 02, and three-state output stages 1 to 5 with identical structures; the first and second flip-flops have the same structure. The input terminal of path controller 01 is connected to the output terminal of the first flip-flop, and the output terminal of path controller 01 is connected to the first input terminal of three-state output stage 1 and the second input terminal of three-state output stage 2, respectively. The input terminal of path controller 02 is connected to the output terminal of the second flip-flop, and the output terminal of path controller 02 is connected to the first input terminal of three-state output stage 2 and the second input terminal of three-state output stage 1, respectively. The enable terminals of both path controller 01 and path controller 02 are used to receive the enable signal EN.

[0040] The output of tri-state output stage 1 is connected to the second input of tri-state output stage 3, the first input of tri-state output stage 4, and the first input of tri-state output stage 5, respectively. The output of tri-state output stage 2 is connected to the first input of tri-state output stage 3, the second input of tri-state output stage 4, and the second input of tri-state output stage 5, respectively. The output of tri-state output stage 3 is connected to the output of path controller 01, the output of tri-state output stage 4 is connected to the output of path controller 02, and the output of tri-state output stage 5 is used to output the voting result. Path controllers 01 and 02 are used to synchronously switch on and off under the control of the enable signal EN. The interconnected tri-state output stages form a double-interlocked storage unit structure. When the enable signal EN is valid, the double-interlocked storage unit structure outputs the current output state according to the output signal of the currently input flip-flop. When the enable signal EN is invalid, the output of the double-interlocked storage unit structure remains the previous output state. The enable signal EN is valid when the output signals of the first flip-flop and the second flip-flop are consistent, and invalid when the output signals of the first flip-flop and the second flip-flop are inconsistent.

[0041] It is understood that the above-mentioned storage unit may also include other existing circuit parts not listed. This embodiment improves the voting output circuit structure of the storage unit to shield the error problem caused by single-event upset in the holding phase of the voter.

[0042] The aforementioned memory cell improves its internal circuit structure by applying a dual-mode redundancy-based hardened voter to effectively shield the voter from errors caused by single-event upsets during the flip-flop holding phase, thereby enhancing the memory cell's operational reliability in a radiated environment.

[0043] In one embodiment, the path controller 01 is a tri-state buffer.

[0044] In one embodiment, the path controller 02 is a tri-state buffer.

[0045] In one embodiment, each tri-state output stage includes a PMOS transistor and an NMOS transistor. The gate of the PMOS transistor serves as the first input terminal of the tri-state output stage, and the gate of the NMOS transistor serves as the second input terminal of the tri-state output stage. The drain of the PMOS transistor is connected to the drain of the NMOS transistor and then led out as the output terminal of the tri-state output stage. The source of the PMOS transistor is used to connect to the power supply, and the source of the NMOS transistor is used to ground.

[0046] In one embodiment, the storage unit further includes an XOR gate, the first input of which is connected to the output of the first flip-flop, the second input of which is connected to the output of the second flip-flop, and the output of which is connected to the enable terminals of the path controller 01 and the path controller 02, respectively.

[0047] It is understood that the explanations of the circuit parts in the other embodiments of the above-mentioned storage unit can be understood by referring to the explanations of the corresponding circuit parts in the embodiments of the dual-mode redundancy anti-single-event upset hardened voter, and will not be repeated here.

[0048] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0049] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of protection of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and all such modifications and improvements fall within the scope of protection of the present invention.

Claims

1. A hardened voting device based on dual-mode redundancy to resist single-event upsets, characterized in that, Includes path controller 01, path controller 02, and three-state output stages 1 to 5 with identical structures; The input terminal of the path controller 01 is used to connect to the output terminal of the first flip-flop. The output terminal of the path controller 01 is connected to the first input terminal of the tri-state output stage 1 and the second input terminal of the tri-state output stage 2, respectively. The input terminal of the path controller 02 is used to connect to the output terminal of the second flip-flop. The output terminal of the path controller 02 is connected to the first input terminal of the tri-state output stage 2 and the second input terminal of the tri-state output stage 1, respectively. The enable terminals of both the path controller 01 and the path controller 02 are used to receive enable signals. The output terminals of the three-state output stage 1 are connected to the second input terminal of the three-state output stage 3, the first input terminal of the three-state output stage 4, and the first input terminal of the three-state output stage 5, respectively. The output terminals of the three-state output stage 2 are connected to the first input terminal of the three-state output stage 3, the second input terminal of the three-state output stage 4, and the second input terminal of the three-state output stage 5, respectively. The output terminal of the three-state output stage 3 is connected to the output terminal of the path controller 01. The output terminal of the three-state output stage 4 is connected to the output terminal of the path controller 02. The output terminal of the three-state output stage 5 is used to output the voting results. Path controller 01 and path controller 02 are used to synchronously turn on and off under the control of the enable signal. The three-state output stages are interconnected to form a dual-interlocked storage unit structure. When the enable signal is valid, the dual-interlocked storage unit structure outputs the current output state according to the output signal of the currently input flip-flop. When the enable signal is invalid, the output of the dual-interlocked storage unit structure remains at the previous output state. The enable signal is valid when the output signals of the first flip-flop and the second flip-flop are consistent, and the enable signal is invalid when the output signals of the first flip-flop and the second flip-flop are inconsistent.

2. The dual-mode redundancy-based anti-single-event upset hardened voting device according to claim 1, characterized in that, The path controller 01 is a tri-state buffer.

3. The dual-mode redundancy-based anti-single-event upset hardened voting device according to claim 1, characterized in that, The path controller 02 is a tri-state buffer.

4. The dual-mode redundancy-based anti-single-event upset hardened voting device according to any one of claims 1 to 3, characterized in that, Each tri-state output stage includes a PMOS transistor and an NMOS transistor. The gate of the PMOS transistor serves as the first input terminal of the tri-state output stage, and the gate of the NMOS transistor serves as the second input terminal of the tri-state output stage. The drains of the PMOS transistor and the NMOS transistor are connected and then led out as the output terminal of the tri-state output stage. The source of the PMOS transistor is used to connect to the power supply, and the source of the NMOS transistor is used to ground.

5. The dual-mode redundancy-based anti-single-event upset hardened voting device according to claim 4, characterized in that, It also includes an XOR gate, the first input of which is used to connect to the output of the first flip-flop, the second input of which is used to connect to the output of the second flip-flop, and the output of which is connected to the enable terminals of the path controller 01 and the path controller 02, respectively.

6. A storage unit, characterized in that, It includes a first flip-flop, a second flip-flop, a path controller 01, a path controller 02, and three-state output stages 1 to 5 with identical structures; the first flip-flop and the second flip-flop have the same structure. The input terminal of the path controller 01 is connected to the output terminal of the first flip-flop. The output terminal of the path controller 01 is connected to the first input terminal of the tri-state output stage 1 and the second input terminal of the tri-state output stage 2, respectively. The input terminal of the path controller 02 is connected to the output terminal of the second flip-flop. The output terminal of the path controller 02 is connected to the first input terminal of the tri-state output stage 2 and the second input terminal of the tri-state output stage 1, respectively. The enable terminals of both the path controller 01 and the path controller 02 are used to receive enable signals. The output terminals of the three-state output stage 1 are connected to the second input terminal of the three-state output stage 3, the first input terminal of the three-state output stage 4, and the first input terminal of the three-state output stage 5, respectively. The output terminals of the three-state output stage 2 are connected to the first input terminal of the three-state output stage 3, the second input terminal of the three-state output stage 4, and the second input terminal of the three-state output stage 5, respectively. The output terminal of the three-state output stage 3 is connected to the output terminal of the path controller 01. The output terminal of the three-state output stage 4 is connected to the output terminal of the path controller 02. The output terminal of the three-state output stage 5 is used to output the voting results. Path controller 01 and path controller 02 are used to synchronously turn on and off under the control of the enable signal. The three-state output stages are interconnected to form a dual-interlocked storage unit structure. When the enable signal is valid, the dual-interlocked storage unit structure outputs the current output state according to the output signal of the currently input flip-flop. When the enable signal is invalid, the output of the dual-interlocked storage unit structure remains at the previous output state. The enable signal is valid when the output signals of the first flip-flop and the second flip-flop are consistent, and the enable signal is invalid when the output signals of the first flip-flop and the second flip-flop are inconsistent.

7. The storage unit according to claim 6, characterized in that, The path controller 01 is a tri-state buffer.

8. The storage unit according to claim 6, characterized in that, The path controller 02 is a tri-state buffer.

9. The storage unit according to any one of claims 6 to 8, characterized in that, Each tri-state output stage includes a PMOS transistor and an NMOS transistor. The gate of the PMOS transistor serves as the first input terminal of the tri-state output stage, and the gate of the NMOS transistor serves as the second input terminal of the tri-state output stage. The drains of the PMOS transistor and the NMOS transistor are connected and then led out as the output terminal of the tri-state output stage. The source of the PMOS transistor is used to connect to the power supply, and the source of the NMOS transistor is used to ground.

10. The storage unit according to claim 9, characterized in that, It also includes an XOR gate, the first input of which is connected to the output of the first flip-flop, the second input of which is connected to the output of the second flip-flop, and the output of which is connected to the enable terminals of the path controller 01 and the path controller 02, respectively.

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