Self-calibrating dynamic delay chain circuit and self-calibrating delay system

Abstract

The self-calibration dynamic delay chain circuit and the self-calibration delay system can realize true self-calibration and dynamic characteristics, set a measurement delay chain which is completely same as a target delay chain, do not affect the working process of the target delay chain, can realize real-time sensing of the real delay capability of the target delay chain in the current environment, completely get rid of the dependence on the nominal value of the process library, and through the closed-loop feedback mechanism of measurement, calculation and update, can automatically offset the initial error caused by the manufacturing process deviation, and improve the measurement accuracy. In addition, by using an accurate reference clock period as a calibration, adjusting the number of delay units in the measurement delay chain to make the total delay time approximate to the reference clock period, the small error in the measurement of a single delay unit can be improved, and the measurement accuracy can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor integrated circuit design, specifically to a self-calibrating dynamic delay chain circuit and a self-calibrating delay system. Background Technology

[0002] Delay chain circuits are a commonly used circuit structure that can achieve a fixed delay for input signals. They are widely used in circuits such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR), phase splitters, and Delay-Locked Loops (DLLs). The basic principle is to design a series of fine-grained delay units, which are then connected in series as needed using a control word to form a chain with a predetermined delay time, thereby achieving precise delay control of the input signal.

[0003] Traditional delay chain designs typically rely on nominal delay values ​​provided by process libraries. However, due to factors such as process deviations, the actual delay time of each delay unit in the manufactured chip deviates significantly from the nominal value, making it difficult to achieve precise delay control. Summary of the Invention

[0004] This application provides a self-calibrating dynamic delay chain circuit and a self-calibrating delay system capable of achieving precise delay control.

[0005] A self-calibrating dynamic delay chain circuit, characterized in that it is applied to a delay control circuit, the self-calibrating dynamic delay chain circuit comprising:

[0006] Target delay chain;

[0007] The measurement delay chain includes delay units with the same structure as the target delay chain;

[0008] The measurement control module, connected to both the measurement delay chain and the delay control circuit, is used for:

[0009] The number of delay units connected to the conductive path in the measurement delay chain is dynamically adjusted. When the total delay time generated by the measurement delay chain approaches the reference clock period of the reference clock signal, the target number of the delay units connected to the conductive path is obtained, and the target number is sent to the delay control circuit.

[0010] The delay control circuit is configured to, in response to the received target quantity, obtain the delay amount of each delay unit in the target delay chain based on the reference clock period and the target quantity, dynamically calculate a control word in combination with the expected delay duration, and send the control word to the target delay chain to achieve delay calibration of the target delay chain.

[0011] In one embodiment, the delay unit is a digital unit, and the measurement control module includes:

[0012] A measurement state machine is connected to the measurement delay chain and the delay control circuit respectively, and is used to output the delay control signal, the reference clock signal and the test signal;

[0013] The measurement delay chain is also used to output a zero-delay clock signal and a delayed clock signal generated according to the delay control signal after receiving the reference clock signal;

[0014] A sampling register group includes a first register, a second register, a third register, and a fourth register; the clock terminals of the first register and the second register are respectively connected to the measurement delay chain to receive the zero-delay clock signal; the data terminal of the first register is connected to the measurement state machine to receive the test signal; the data terminals of the second register and the fourth register are respectively connected to the output terminal of the first register; the clock terminal of the fourth register is used to receive the delayed clock signal; the data terminal of the third register is connected to the output terminal of the second register, and the clock terminal of the third register is connected to the output terminal of the fourth register.

[0015] The measurement state machine is also used to determine the relationship between the current total delay time and the reference clock period based on the sampling result of the third register, and to iteratively adjust the number of delay units connected to the conductive path based on the binary search algorithm until the search interval is narrowed to the point where it cannot be further divided, at which point the binary search algorithm is terminated, and the target number is obtained based on the current number of delay units connected to the conductive path.

[0016] In one embodiment, the measurement control module is further configured to:

[0017] Repeat the binary search algorithm a preset number of times to obtain multiple target quantity samples;

[0018] The average value of the multiple target quantity samples is obtained, and the average value is sent to the delay control circuit as the final target quantity.

[0019] In one embodiment, the preset number of times is The measurement control module is further used to accumulate the target number of samples for the preset number of times, and then shift the accumulation result to the right by M bits to obtain the average value.

[0020] In one embodiment, the measurement state machine is further configured to: obtain the initial target quantity under the initial PVT environment and the current target quantity under the current PVT environment, and calculate a compensation factor based on the initial target quantity and the current target quantity, wherein the compensation factor is equal to the quotient of the current target quantity and the initial target quantity;

[0021] The self-calibrating dynamic delay chain circuit also includes:

[0022] The PVT compensation module is connected to the measurement state machine, the delay control circuit, and the target delay chain, respectively. It is used to obtain the initial control word sent by the delay control circuit corresponding to the initial target quantity; multiply the compensation factor by the value of the initial control word as the value of the current control word and send it to the target delay chain to realize the delay calibration of the target delay chain under the current PVT environment.

[0023] In one embodiment, the measurement control module further includes a gating module, which is connected to the measurement state machine and the measurement delay chain respectively. The measurement state machine is also used to control the gating module to turn on or block the reference clock signal sent to the measurement delay chain.

[0024] In one embodiment, the measurement state machine is further configured to set the test signal to a first level and control the gating module to turn on the reference clock signal before iteratively adjusting the number of delay units connected to the conductive path based on the binary search algorithm, so that the sampling register group is reset according to the first level.

[0025] In one embodiment, the measurement state machine is further used for:

[0026] After the reset is completed, the gating module is controlled to block the reference clock signal, and during the blocking period, the test signal is set from the first level to the second level so that the test signal meets the hold time and setup time requirements of the sampling register group before the reference clock signal is turned on again.

[0027] After the test signal stabilizes at the second level, the gate module is controlled to turn on the reference clock signal again, triggering the sampling register group to perform phase comparison sampling.

[0028] In one embodiment, the measurement control module further includes:

[0029] The synchronization module is connected to the output of the third register and the measurement state machine, respectively, and is used to synchronize the output result of the third register before sending it to the measurement state machine.

[0030] In one embodiment, there are multiple target delay chains, and the measurement delay chain and the measurement control module constitute a shared measurement calibration unit, which is used to provide a uniform number of targets for the multiple target delay chains to achieve multi-channel calibration.

[0031] A self-calibrating delay system includes a delay control circuit and a self-calibrating dynamic delay chain circuit as described in any of the above embodiments.

[0032] The self-calibrating dynamic delay chain circuit and self-calibrating delay system of this application achieve true self-calibration and dynamic characteristics. By setting a measurement delay chain that is exactly the same as the target delay chain, it does not affect the operation of the target delay chain and can sense the actual delay capability of the target delay chain in the current environment in real time, completely eliminating the dependence on the nominal value of the process library. At the same time, by constructing a closed-loop feedback mechanism of measurement → calculation → update, it can automatically offset the initial error caused by manufacturing process deviations, thereby improving measurement accuracy. In addition, by using a precise reference clock period as calibration, the total delay time can be made close to the reference clock period by adjusting the number of delay units in the measurement delay chain, which can improve the small error in the measurement of a single delay unit and improve measurement accuracy. Attached Figure Description

[0033] Figure 1 A schematic diagram of a system architecture for a self-calibrating dynamic delay chain circuit provided in this application embodiment;

[0034] Figure 2 This is a schematic diagram of the internal circuit structure of the measurement control module in an embodiment of this application;

[0035] Figure 3 This is a schematic diagram of the signal timing relationship of the sampling register group in an embodiment of this application;

[0036] Figure 4 This is a schematic diagram of the process for obtaining the target quantity based on the binary search algorithm in an embodiment of this application;

[0037] Figure 5 This is a schematic diagram of the dynamic calibration process based on the PVT compensation factor in the embodiments of this application;

[0038] Figure 6 This is a schematic diagram of the overall architecture of another self-calibration delay system provided in an embodiment of this application. Detailed Implementation

[0039] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0040] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0041] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly. The connection can be a direct connection or an indirect connection.

[0042] Furthermore, the use of terms such as "first" and "second" in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. If the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed in this application.

[0043] This invention provides a self-calibrating dynamic delay chain circuit, applied to a delay control circuit 100, such as... Figure 1 As shown, the self-calibrating dynamic delay chain circuit includes a target delay chain 120, a measurement delay chain 110, and a measurement control module 130. The measurement delay chain 110 includes delay units with the same structure as those in the target delay chain 120. The measurement control module 130 is connected to both the measurement delay chain 110 and the delay control circuit 100, and is used to: dynamically adjust the number of delay units connected to the conductive path in the measurement delay chain 110; when the total delay time generated by the measurement delay chain 110 approaches the reference clock period of the reference clock signal, obtain the target number of delay units connected to the conductive path, and send the target number to the delay control circuit 100; the delay control circuit 100 is configured to, in response to the received target number, obtain the delay amount of each delay unit in the target delay chain 120 based on the reference clock period and the target number, dynamically calculate a control word in conjunction with the expected delay duration, and send the control word to the target delay chain 120 to achieve delay calibration of the target delay chain 120.

[0044] It can be understood that the target delay chain 120 consists of multiple series-connected delay units and is the core component for performing the actual signal delay function. The target delay chain 120 receives the signal to be processed and dynamically adjusts the number of delay units connected to the conductive path according to the received control word. The measurement delay chain 110 has the same specifications and number of delay units as the target delay chain 120, and the connection structure of each delay unit is also the same. Thus, under the same process, voltage, and temperature (PVT) environment, the delay characteristics of each unit in the measurement delay chain 110 are highly consistent with those of the units in the target delay chain 120. The measurement delay chain 110 does not directly process the service signal, but acts as a "probe". By measuring the delay time of each delay unit in the measurement delay chain 110, the delay time of each delay unit in the target delay chain 120 can be obtained.

[0045] Specifically, the total delay time generated by the measurement delay chain 110 is equal to the sum of the delay times of each delay unit connected to the conductive path in the measurement delay chain 110. Since each delay unit has the same structure, the delay time generated is also the same. Therefore, the total delay time can be adjusted by adjusting the number of delay units connected to the conductive path in the measurement delay chain 110.

[0046] For example, in one implementation, a signal can be set, and the total delay time is obtained by measuring the time difference between the input and output delay chains 110 of this signal. By continuously adjusting the number of connected delay units, the total delay time is compared with the reference clock period of the reference clock signal. If the total delay time is lower than the reference clock period, the number of delay units is increased; if it is higher than the reference clock period, the number of delay units is decreased, until further increasing or decreasing the number of delay units cannot make the difference between the total delay time and the reference clock period smaller. At this point, the total delay time is considered to be close to the reference clock period of the reference clock signal. Then, the target number of delay units in the conductive path is obtained. Since the divider requires more circuit resources and has a more complex structure, after obtaining the target number, it can be sent to an external delay control circuit 100. The delay amount of each delay unit is obtained by calculating the quotient of the reference clock period and the target number, and a control word is calculated in combination with the user's desired delay duration. This control word is then sent to the target delay chain 120 to perform delay according to the new control word, thereby achieving delay calibration. During this period, the measurement control module 130 will continuously acquire the target quantity in real time, and the delay control circuit 100 will also update the control word according to the target quantity received in real time to ensure the dynamic calibration of the target delay chain 120.

[0047] The reference clock signal can be a high-precision clock signal provided by a standard clock. By using it as a standard ruler, the number of delay units that can fill the standard ruler can be found. This can convert tiny time quantities that are difficult to measure directly into precise integer count values, thereby improving measurement accuracy.

[0048] The aforementioned self-calibrating dynamic delay chain circuit achieves true self-calibration and dynamic characteristics. By setting a measurement delay chain 110 that is identical to the target delay chain 120, it not only does not affect the operation of the target delay chain 120, but also senses the actual delay capability of the target delay chain 120 in the current environment in real time, completely eliminating dependence on the nominal values ​​of the process library. Simultaneously, by constructing a closed-loop feedback mechanism of measurement → calculation → update, it can automatically offset the initial errors caused by manufacturing process deviations, improving measurement accuracy. Furthermore, by using a precise reference clock period as calibration, and adjusting the number of delay units in the measurement delay chain 110 to make the total delay time approximate this reference clock period, it can improve the small errors in the measurement of individual delay units, thus enhancing measurement accuracy.

[0049] In one embodiment, the delay unit is a digital unit, such as... Figure 2 As shown, the measurement control module 130 includes: a measurement state machine 131 and a sampling register group. The measurement state machine 131 is connected to the measurement delay chain 110 and the delay control circuit 100, respectively, and is used to output a delay control signal, a reference clock signal, and a test signal. The measurement delay chain 110 is also used to output a zero-delay clock signal CLK_ZERO and a delayed clock signal CLK_DLY generated according to the delay control signal after receiving the reference clock signal. The sampling register group includes a first register D1, a second register D2, a third register D3, and a fourth register D0. The clock terminals of the first register D1 and the second register D2 are connected to the measurement delay chain 110, respectively, and are used to receive the zero-delay clock signal CLK_ZERO. The data terminal of the first register D1 is connected to the measurement state machine 131. The measurement state machine 131 is connected to receive the test signal CAL; the data terminals of the second register D2 and the fourth register D0 are respectively connected to the output terminal of the first register D1; the clock terminal of the fourth register D0 is used to receive the delayed clock signal CLK_DLY; the data terminal of the third register D3 is connected to the output terminal of the second register D2, and the clock terminal of the third register D3 is connected to the output terminal of the fourth register D0; wherein, the measurement state machine 131 is also used to determine the relationship between the current total delay time and the reference clock period based on the sampling result of the third register D3, and iteratively adjust the number of delay units connected to the conductive path based on the binary search algorithm until the search interval is narrowed to the point where it cannot be further divided, then terminate the binary search algorithm, and obtain the target number based on the current number of delay units connected to the conductive path.

[0050] The delay control signal is used to configure the number of delay units connected to the conductive path in the measurement delay chain 110. The reference clock signal is the time base of the circuit and is a standard clock signal. After receiving the reference clock signal, the measurement delay chain 110 splits it into two outputs. On one hand, the reference clock signal is output with zero delay to obtain a zero-delay clock signal. On the other hand, the reference clock signal is output with delay according to the delay control signal to obtain a delayed clock signal CLK_DLY. Thus, the time difference between the delayed clock signal CLK_DLY and the zero-delay clock signal CLK_ZERO is the total delay time of the delay units connected to the conductive path. The test signal is used as the signal for time delay measurement and is output through the sampling register group under the drive of the zero-delay clock signal CLK_ZERO and the delayed clock signal CLK_DLY, respectively.

[0051] Specifically, the first register D1 serves as the signal acquisition stage. Its clock input is connected to the measurement delay chain 110 to receive the zero-delay clock signal CLK_ZERO, and its data input is connected to the measurement state machine 131 to receive the test signal CAL. The CAL signal is sampled on the rising edge of CLK_ZERO, such as... Figure 3 As shown, the rising edge of the test signal is synchronized to the zero-delay reference clock domain, and its output is denoted as D1Q, which is then used as the data input to the second register D2 and the fourth register D0, respectively. The second register D2, as a periodic delay stage, also receives the zero-delay clock signal CLK_ZERO at its clock input. When the next rising edge of CLK_ZERO arrives, the state of D1Q is propagated backward by one clock cycle. Therefore, the rising edge of D2Q lags behind D1Q by exactly one complete reference clock cycle. The fourth register D0, as a delay sampling stage, is connected to the measurement delay chain 110 at its clock input, receiving the delayed clock signal CLK_DLY. The delayed clock CLK_DLY is used to sample D1Q. When the rising edge of CLK_DLY arrives, i.e., after the total delay time, D0 outputs a rising pulse. The output signal D0Q of D0 is essentially a trigger edge determined by the total delay time. The third register D3 serves as the core comparator, with its data input connected to the output of the second register D2 and its clock input connected to the output of the fourth register D0. This means that the trigger edge determined by the total delay time is used to desample D2Q.

[0052] Since D2Q carries information about a reference clock cycle and D0Q carries information about the total delay time, the sampling result D3Q of the third register D3 directly reflects the relationship between the total delay time and the reference clock cycle. Specifically, if the output of the third register D3 is 0, it indicates that the rising edge of CLK_DLY arrives early, causing D0 to transition early. In this case, when the clock edge of D3 arrives, D2Q has not yet been established, so the total delay time is less than the reference clock cycle. If the output of the third register D3 is 1, it indicates that the rising edge of CLK_DLY arrives late, causing D0 to transition late. In this case, when the clock edge of D3 arrives, D2Q has already stabilized at a high level, so the total delay time is greater than the reference clock cycle.

[0053] Furthermore, the measurement state machine 131 reads the sampling result of the third register D3 in real time and executes the following binary search algorithm to obtain the target number. Initially, the value of the delay control signal DLY is set to half of the maximum delay range Nmax of the measurement delay chain 110 (Nmax is the number of all delay units in the measurement delay chain 110), i.e., Nmax / 2. After the first sampling, the output D3Q of the third register D3 is read. If D3Q=0, it indicates that the total delay time is less than the reference clock period, and the current delay unit number needs to be increased. At this time, the search interval is adjusted to the upper half of the interval [Nmax / 2, Nmax], and the value of the delay control signal DLY is set to the middle value of this interval, i.e., (Nmax / 2 + Nmax / 2). (ax) / 2; If D3Q=1, it indicates that the total delay time is greater than the reference clock period, and the number of current delay units needs to be reduced. At this time, the search interval is adjusted to the lower half of the region [0, Nmax / 2], and the value of the delay control signal DLY is set to the middle value of this interval, i.e., (Nmax / 2+0) / 2; then continue to sample and read the output D3Q of D3 for the second time, and continue to adjust the search interval in the same way as above, where the value of the delay control signal DLY is a positive integer. When calculating the middle value, it can be rounded up or down to ensure that the value of the delay control signal DLY is a positive integer. Repeat the above adjustment-sampling-decision process, and reduce the search interval by half each time. When the search interval is adjusted to the point where it can no longer be split, the number of delay units connected to the conductive path at this time is taken as the target number. The flowchart of the binary iteration process can be found in [reference]. Figure 4 As shown.

[0054] Thus, this embodiment, through the aforementioned fully digital register sampling architecture and binary search logic, can achieve high-precision measurement with minimal numerical delay and minimal area overhead without any analog measurement components, perfectly meeting the demands of modern integrated circuits for high precision and low power consumption.

[0055] In one embodiment, the measurement control module 130 is further configured to: repeatedly execute the binary search algorithm a preset number of times to obtain multiple target quantity samples; obtain the average value of the multiple target quantity samples, and send the average value as the final target quantity to the delay control circuit 100.

[0056] Understandably, to further eliminate the impact of random noise on the results of a single measurement and improve the accuracy and stability of the target quantity, the measurement control module 130 is also configured to execute an optimization strategy of averaging multiple measurements. Specifically, each measurement state machine 131 executes an independent measurement process; that is, the state machine reinitializes the search interval and executes the complete reset-establishment-sampling-binary iterative process from the beginning until it converges to obtain a single sample of the target quantity. After executing a preset number of times, the average of all obtained target quantity samples is obtained and sent to the delay control circuit 100 as the target quantity. If the average is a decimal, it needs to be rounded before being output as the target quantity.

[0057] In one embodiment, the preset number of times is The number of times is M, where M is a positive integer; the measurement control module 130 is also used to accumulate the target number of samples for the preset number of times, and then shift the accumulated result to the right by M bits to obtain the average value.

[0058] The average value can be equal to the sum of the target number of samples divided by . And round down. It's understandable that using a divider for averaging requires significant circuit resources and consumes a lot of power; therefore, the preset number of divisions can be controlled to... The accumulated result is represented as a binary number. In binary arithmetic, shifting an integer right by M bits is equivalent to dividing that integer by... And round down, so the measurement control module 130 only needs to have a shift function, for example, by setting a shift register, to obtain the average value of all target quantity samples.

[0059] For example, suppose the samples S1=101, S2=99, S3=100, and S4=100 are measured sequentially. The cumulative result Sum=101+99+100+100=400, which is 110010000 in binary. Shifting this right by M=2 bits gives 1100100=100, which is the same as the average value of 100 obtained through division. Therefore, this method allows for high-precision noise filtering with minimal hardware, ensuring the robustness of the self-calibrating dynamic delay chain circuit under various noise environments.

[0060] In one embodiment, the measurement state machine 131 is further configured to: acquire the initial target quantity under the initial PVT environment and the current target quantity under the current PVT environment, and calculate a compensation factor based on the initial target quantity and the current target quantity, wherein the compensation factor is equal to the quotient of the current target quantity and the initial target quantity; the self-calibrating dynamic delay chain circuit further includes: a PVT compensation module 140, which is connected to the measurement state machine 131, the delay control circuit 100 and the target delay chain 120 respectively, and is configured to acquire the initial control word sent by the delay control circuit 100 corresponding to the initial target quantity; and use the product of the compensation factor and the initial control word as the current control word and send it to the target delay chain 120 to realize the delay calibration of the target delay chain 120 under the current PVT environment.

[0061] It is understandable that during circuit power-on initialization or initial calibration (at which time the PVT environment is denoted as T0), the measurement control module 130 performs a complete binary search and averaging process, enabling the measurement state machine 131 to obtain the initial target quantity, denoted as n0, which represents the number of delay units required to complete one clock cycle under the initial PVT environment T0. As the circuit operates, the measurement control module 130 continues to execute the measurement process, and the measurement state machine 131 obtains the current target quantity n1 under the current PVT environment T1 in real time. Due to possible changes in ambient temperature, the current target quantity may differ from the initial target quantity if the expected delay time remains unchanged. Besides sending the target quantity to the external delay control circuit 100 to recalculate the control word, this embodiment provides another method with faster calibration speed and without frequent involvement of the external delay control circuit 100 in calculations. This method calculates the compensation factor K = n1 / n0, where K directly reflects the change factor of the current cell delay relative to the initial cell delay. Then, K is sent to the PVT compensation module 140. The PVT compensation module 140 multiplies the compensation factor K with the value DLY0 of the initial control word from the delay control circuit 100 to obtain the current control word value DLY_K = K × DLY0, which is then sent to the target delay chain 120 to achieve delay calibration at the current temperature. For details of the PVT compensation process, please refer to [reference needed]. Figure 5 The flowchart is shown.

[0062] Thus, by setting up the PVT compensation module 140 and cooperating with the measurement state machine 131 to execute a dynamic calibration strategy based on the compensation factor, the problem of delay cell characteristic drift caused by changes in the PVT environment during circuit operation is solved.

[0063] In one embodiment, the measurement control module 130 further includes a gating module 132, which is connected to the measurement state machine 131 and the measurement delay chain 110 respectively. The measurement state machine 131 is also used to control the gating module 132 to turn on or block the reference clock signal sent to the measurement delay chain 110.

[0064] It is understandable that by setting the gating module 132, it can be ensured that the transition of the test signal CAL during the measurement process will not cause metastability in the register, and the start and end times of the measurement can be precisely controlled. The gating module 132 can be composed of one or more logic gates, used as a high-speed switch. The measurement state machine 131 can output a reference clock signal CLK to the input terminal of the gating module 132 and output a gating signal GATE to the control terminal of the gating module 132.

[0065] In one embodiment, the measurement state machine 131 is further configured to set the test signal to a first level and control the gating module 132 to turn on the reference clock signal before iteratively adjusting the number of delay units accessing the conductive path based on the binary search algorithm, so that the sampling register group is reset according to the first level.

[0066] The first level is the opposite of the level in the subsequent transition direction, and it can be a low level. After the CAL signal stabilizes at the first level, the measurement state machine 131 immediately sends a control command to the gating module 132 to turn on the reference clock signal. The duration of the state machine control clock being turned on must be greater than the signal propagation time of each register in the sampling register group. Through this series of shift and sampling operations, all nodes in the entire register chain are forced to be refreshed to the first level.

[0067] This ensures that the sampling register group (including the first to fourth registers D0-D3) is in a defined initial state before each binary search iteration begins, eliminating residual data or metastability risks from the previous measurement. This is a "zeroing" step for the entire measurement timing, achieving low-cost, high-reliability fully digital synchronous reset.

[0068] In one embodiment, the measurement state machine 131 is further configured to: after a reset is completed, control the gating module 132 to block the reference clock signal, and during the blocking period, set the test signal from a first level to a second level so that the test signal meets the hold time and setup time requirements of the sampling register group before the reference clock signal is turned on again; after the test signal stabilizes at the second level, control the gating module 132 to turn on the reference clock signal again, triggering the sampling register group to perform phase comparison sampling.

[0069] After confirming that the sampling register group has been reset, i.e. all nodes are at the first level, the measurement state machine 131 first controls the gating module 132 to immediately block the reference clock signal (CLK). At this time, the clock input terminals of the measurement delay chain 110 and all sampling registers (D0-D3) are forcibly locked at the invalid level (i.e., the first level). No matter how the test signal changes, it will not interfere with the reset edge that has just ended, ensuring that the reset data (first level) is held in the register for a sufficient time, perfectly meeting the register's hold time requirement and preventing sampling errors caused by "premature data changes". Secondly, during the "safe window" period of clock hold-down, the measurement state machine 131 controls the test signal CAL to transition from a first level (e.g., low level) to a second level (e.g., high level). The transitioned CAL signal (second level) begins to propagate to the data input of the sampling register group. After a period of time, the reference clock signal is turned on again. The duration between the CAL signal transition and the reference clock signal being turned on again is set to ensure that the transitioned CAL signal reaches the first register D1, thereby meeting the setup time requirement of the first register D1 and improving sampling accuracy. The initialization process of the sampling register group can be found in [reference needed]. Figure 4 The flowchart shown.

[0070] Thus, after the synchronous reset operation is completed, the measurement state machine 131 is configured to execute a blocking-jumping-turning timing control strategy, which can accurately capture the small time difference generated by the delay chain, while avoiding metastability problems caused by signal jumps and clock edge conflicts.

[0071] In one embodiment, the measurement control module 130 further includes a synchronization module 133, which is connected to the output of the third register D3 and the measurement state machine 131 respectively, and is used to synchronize the output result of the third register D3 before sending it to the measurement state machine 131.

[0072] It is understandable that the third register D3 is driven by the output of the fourth register D0. Its clock domain is essentially an asynchronous or semi-asynchronous clock domain determined by the delay chain, which may have a potential phase difference with the main clock domain of the measurement state machine 131. Directly sending this signal into the state machine may lead to logical misjudgment or metastability propagation. Therefore, the measurement control module 130 can solve the problem of state machine logic jump errors caused by clock phase mismatch by setting the synchronization module 133.

[0073] In one embodiment, reference Figure 6 As shown, there are multiple target delay chains. The measurement delay chain and the measurement control module constitute a shared measurement calibration unit, which is used to provide a uniform number of targets for multiple target delay chains to achieve multi-channel calibration.

[0074] It is understandable that, in order to meet the requirements of high-performance systems (such as DDR memory interfaces, multi-phase clock generators, high-speed serial transceiver arrays, etc.) for independent and precise delay control of multiple signals, while maximizing the saving of circuit area and power consumption, the self-calibrating dynamic delay chain circuit of this application is configured as a multi-channel architecture.

[0075] The entire circuit consists of only one measurement delay chain and one measurement control module, which together serve as the circuit's common reference source, responsible for real-time sensing of process, voltage, and temperature (PVT) characteristics under the current circuit environment. Each target delay chain has an identical structure, with independent input and output signals, and independent expected delay requirements. This allows for parallel operation, handling different data channels or different clock phases separately.

[0076] Specifically, the measurement control module starts up and drives the shared measurement delay chain to execute a binary search algorithm to measure the number of units required to fill one reference clock cycle under the current PVT environment, i.e., the target number. This target number reflects the average delay capability of the delay units in all current target delay chains. Then, the delay control circuit configures the corresponding control word for each channel according to the expected delay duration of each channel. When there is a change in the PVT environment, the PVT compensation module can perform PVT compensation on each channel according to the K value, thereby realizing the delay calibration of each channel.

[0077] This invention also provides a self-calibrating dynamic delay chain circuit applied to a delay control circuit 100. The self-calibrating dynamic delay chain circuit includes: a target delay chain 120, a measurement delay chain 110, a measurement control module 130, and a PVT compensation module 140. The measurement control module 130 includes a measurement state machine 131, a sampling register group, a gating module 132, and a synchronization module 133. The connection relationships and working principles between the modules are as described in the above embodiments and will not be repeated here.

[0078] This invention also provides a self-calibrating delay system, characterized in that it includes a delay control circuit 100 and a self-calibrating dynamic delay chain circuit as described in any of the above embodiments. The structure and beneficial effects of this self-calibrating delay system can be found in the above embodiments.

[0079] The above description is only a preferred embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made based on the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A self-calibrating dynamic delay chain circuit, characterized in that, The self-calibrating dynamic delay chain circuit, applied to delay control circuits, includes: Target delay chain; The measurement delay chain includes delay units with the same structure as the target delay chain; The measurement control module, connected to both the measurement delay chain and the delay control circuit, is used for: The number of delay units connected to the conductive path in the measurement delay chain is dynamically adjusted. When the total delay time generated by the measurement delay chain approaches the reference clock period of the reference clock signal, the target number of the delay units connected to the conductive path is obtained, and the target number is sent to the delay control circuit. The delay control circuit is configured to, in response to the received target quantity, obtain the delay amount of each delay unit in the target delay chain based on the reference clock period and the target quantity, dynamically calculate a control word in combination with the expected delay duration, and send the control word to the target delay chain to achieve delay calibration of the target delay chain.

2. The self-calibrating dynamic delay chain circuit according to claim 1, characterized in that, The delay unit is a digital unit, and the measurement control module includes: A measurement state machine is connected to the measurement delay chain and the delay control circuit respectively, and is used to output the delay control signal, the reference clock signal and the test signal; The measurement delay chain is also used to output a zero-delay clock signal and a delayed clock signal generated according to the delay control signal after receiving the reference clock signal; A sampling register group includes a first register, a second register, a third register, and a fourth register; the clock terminals of the first register and the second register are respectively connected to the measurement delay chain to receive the zero-delay clock signal; the data terminal of the first register is connected to the measurement state machine to receive the test signal; the data terminals of the second register and the fourth register are respectively connected to the output terminal of the first register; the clock terminal of the fourth register is used to receive the delayed clock signal; the data terminal of the third register is connected to the output terminal of the second register, and the clock terminal of the third register is connected to the output terminal of the fourth register. The measurement state machine is also used to determine the relationship between the current total delay time and the reference clock period based on the sampling result of the third register, and to iteratively adjust the number of delay units connected to the conductive path based on the binary search algorithm until the search interval is narrowed to the point where it cannot be further divided, at which point the binary search algorithm is terminated, and the target number is obtained based on the current number of delay units connected to the conductive path.

3. The self-calibrating dynamic delay chain circuit according to claim 2, characterized in that, The measurement control module is also used for: Repeat the binary search algorithm a preset number of times to obtain multiple target quantity samples; The average value of the multiple target quantity samples is obtained, and the average value is sent to the delay control circuit as the final target quantity.

4. The self-calibrating dynamic delay chain circuit according to claim 3, characterized in that, The preset number of times is The measurement control module is further used to accumulate the target number of samples for the preset number of times, and then shift the accumulation result to the right by M bits to obtain the average value.

5. The self-calibrating dynamic delay chain circuit according to claim 2, characterized in that, The measurement state machine is also used to: obtain the initial target quantity under the initial PVT environment and the current target quantity under the current PVT environment, and calculate a compensation factor based on the initial target quantity and the current target quantity, wherein the compensation factor is equal to the quotient of the current target quantity and the initial target quantity; The self-calibrating dynamic delay chain circuit also includes: The PVT compensation module is connected to the measurement state machine, the delay control circuit, and the target delay chain, respectively. It is used to obtain the initial control word sent by the delay control circuit corresponding to the initial target quantity; multiply the compensation factor by the value of the initial control word as the value of the current control word and send it to the target delay chain to realize the delay calibration of the target delay chain under the current PVT environment.

6. The self-calibrating dynamic delay chain circuit according to claim 2, characterized in that, The measurement control module further includes a gating module, which is connected to the measurement state machine and the measurement delay chain respectively. The measurement state machine is also used to control the gating module to turn on or block the reference clock signal sent to the measurement delay chain.

7. The self-calibrating dynamic delay chain circuit according to claim 6, characterized in that, The measurement state machine is also used to set the test signal to a first level and control the gating module to turn on the reference clock signal before iteratively adjusting the number of delay units connected to the conductive path based on the binary search algorithm, so that the sampling register group is reset according to the first level.

8. The self-calibrating dynamic delay chain circuit according to claim 7, characterized in that, The measurement state machine is also used for: After the reset is completed, the gating module is controlled to block the reference clock signal, and during the blocking period, the test signal is set from the first level to the second level so that the test signal meets the hold time and setup time requirements of the sampling register group before the reference clock signal is turned on again. After the test signal stabilizes at the second level, the gate module is controlled to turn on the reference clock signal again, triggering the sampling register group to perform phase comparison sampling.

9. The self-calibrating dynamic delay chain circuit according to claim 2, characterized in that, The measurement control module also includes: The synchronization module is connected to the output of the third register and the measurement state machine, respectively, and is used to synchronize the output result of the third register before sending it to the measurement state machine.

10. The self-calibrating dynamic delay chain circuit according to any one of claims 1-9, characterized in that, The number of target delay chains is multiple, and the measurement delay chains and the measurement control module constitute a shared measurement calibration unit, which is used to provide a uniform number of targets for multiple target delay chains to achieve multi-channel calibration.

11. A self-calibrating delay system, characterized in that, It includes a delay control circuit and a self-calibrating dynamic delay chain circuit as described in any one of claims 1-10.

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