Phase interpolator, clock data recovery circuit, and serial communication transceiver

Abstract

The application relates to a phase interpolator, a clock data recovery circuit and a serial communication transceiver. The phase interpolator comprises an input clock module, a phase driving module, a current source array, a decoder and an output load module, the current source array is connected with the decoder and the phase driving module, the phase driving module is further connected with the input clock module and the output load module; the current source array comprises a plurality of current source groups, the phase driving module comprises a plurality of pairs of differential phase driving tubes; the output load module comprises a first load resistor and a second load resistor, and the differential output ends of the phase driving module are respectively connected with the two load resistors; the decoder is configured to decode current source switch control signals to control N2 current paths in N1 adjacent current source groups in the current source array to be turned on to obtain an output clock signal. The technical scheme of the application can obtain a larger output swing and circuit bandwidth with smaller chip area and lower chip cost.

Description

Technical Field

[0001] This invention relates to the field of high-speed clock signal interpolation, specifically to a phase interpolator, a clock data recovery circuit, and a serial communication transceiver. Background Technology

[0002] With the development of high-speed serial communication technology, high-speed serial communication interfaces have become a core interconnection technology in fields such as data centers and high-speed storage. Among them, the serializer deserializer (Ser Des), as the core circuit of the high-speed serial interface, is widely used for long-distance, high-bandwidth data transmission. In Ser Des, the clock data recovery (CDR) circuit is the core module for achieving data synchronization, while the phase interpolator, as the core submodule of the clock data recovery circuit, adjusts the phase of the input clock signal to achieve high-precision phase calibration, thereby meeting the synchronization requirements of high-speed data transmission.

[0003] Currently, most mainstream phase interpolators are two-phase interpolators. These two-phase interpolators can only select two adjacent input clock signals for phase interpolation at a time, and the number of current sources activated each time is small, resulting in a small total output current and thus a low swing of the interpolated clock signal. A lower clock signal swing also means weaker noise immunity, so the performance of this type of two-phase interpolator is poor.

[0004] To improve the swing of the clock signal obtained by a two-phase interpolator, existing technologies typically add an inductor to the output of the two-phase interpolator. However, since inductors are relatively large, adding them to the output of a two-phase interpolator significantly increases the layout area of ​​the circuit, leading to higher chip manufacturing costs. Summary of the Invention

[0005] To address the technical problem that existing two-phase interpolators cannot achieve large output signal swing in a small-area, low-cost architecture, thus failing to meet the ever-increasing performance requirements of high-speed serial communication systems, this invention provides a phase interpolator, a clock data recovery circuit, and a serial communication transceiver. The technical solution of this invention can improve the output swing and bandwidth of the phase interpolator with a smaller chip area and lower chip cost, reduce the jitter of the interpolated output clock signal, improve the bandwidth and linearity of the output clock signal, and enhance the performance of the phase interpolator.

[0006] To achieve the above objectives, a first aspect of the present invention provides a phase interpolator, comprising: an input clock module, a phase driving module, a current source array, a decoder, and an output load module, wherein the current source array is connected to the decoder and the phase driving module, and the phase driving module is further connected to the input clock module and the output load module; The input clock module is used to output multiple input clock signals with different phases to the phase drive module; The current source array includes multiple current source groups, and the phase drive module includes multiple pairs of differential phase drive transistors. Each current source group and each pair of differential phase drive transistors are connected in a one-to-one correspondence. Each pair of differential phase drive transistors receives the input clock signal of a different phase. The output load module includes a first load resistor and a second load resistor. The differential output terminal of the phase drive module is connected to the first load resistor and the second load resistor respectively. During each phase interpolation process, the decoder is configured as follows: The clock control signal with the first bit width is decoded according to the set decoding rules to obtain the current source switch control signal with the second bit width; and The switch control signal is output to the current source array to control the conduction of N2 current paths in N1 adjacent current source groups in the current source array. Through the N2 current paths, current-weighted phase interpolation is performed on N1 input clock signals of different phases received by N1 pairs of differential phase drive transistors connected to the N1 adjacent current source groups to obtain an interpolated differential clock current signal. The interpolated differential clock current signal is then output to the output load module, so that the output load module converts the interpolated differential clock current signal into an interpolated differential clock voltage signal through a first load resistor and a second load resistor, so as to obtain the output clock signal of the target phase based on the differential clock voltage signal. Where N1 is an integer greater than 2, N2 is an integer greater than 16, and N2 = 16 × (N1 - 1).

[0007] The technical solution of the present invention can improve the output swing and bandwidth of the phase interpolator, reduce the jitter of the output clock signal obtained by interpolation, and improve the bandwidth and linearity of the output clock signal without increasing the size of the device.

[0008] In one possible implementation of the first aspect, each pair of differential phase driving transistors of the phase driving module includes a first phase driving transistor and a second phase driving transistor; the differential output terminal of the phase driving module includes a first output terminal 1143 and a second output terminal. The gate of the first phase driving transistor receives a clock signal of a predetermined phase from a plurality of input clock signals; the gate of the second phase driving transistor receives an inverted clock signal that is 180 degrees out of phase with the predetermined phase; the sources of the first and second phase driving transistors are connected together to the output terminal of the current source group corresponding to the differential phase driving transistor; the drain of the first phase driving transistor is connected to the first output terminal 1143 in the differential output terminal of the phase driving module, and the first output terminal 1143 is connected to the first load resistor; the drain of the second phase driving transistor is connected to the second output terminal in the differential output terminal of the phase driving module, and the second output terminal is connected to the second load resistor.

[0009] By configuring multiple phase-driven transistors to receive multiple sets of differential clock signals, where each set of differential clock signals drives at least one pair of transistors connected in parallel, and the two clock signals in each set are out of phase, differential transmission of the input clock is achieved, suppressing common-mode noise interference to the input signal. By connecting the sources of two driving transistors to the output terminals of corresponding current source groups, the output current of the same current source is evenly distributed to the two driving transistors, maintaining the matching characteristics of the two driving currents. By connecting the drain of the first driving transistor to the first output terminal 1143 and the first load resistor, and connecting the drain of the second driving transistor to the second output terminal and the second load resistor, the differential current is symmetrically output to the load, improving the symmetry of the differential output signal, thereby reducing the phase mismatch of the output signal and improving the phase accuracy of the output clock.

[0010] In one possible implementation of the first aspect, each current source group includes N3 parallel current paths, each current path including a current source transistor and a switching transistor; the source of the current source transistor is connected to the power supply ground; the drain of the current source transistor is connected to the source of the switching transistor; the drain of the switching transistor serves as the output terminal of the current path, and the output terminals of all current paths within the same current source group are connected to the sources of a pair of differential phase driving transistors corresponding to the current source group; the gate of the current source transistor is connected to a fixed bias voltage terminal; the gate of the switching transistor receives one bit of the current source switching control signal output by the decoder, where N3 is a positive integer.

[0011] Because each current source group has N3 parallel current paths, multi-level adjustment of the output current of a single current source group can be achieved to adapt to interpolation requirements with different phase weights. By connecting the source of the current source transistor to the power supply ground and the gate to a fixed bias voltage, the current source transistor outputs a constant current, ensuring the stability of the current amplitude of a single current path. By connecting the gate of the switching transistor to a single current source switching control signal, independent on / off control of each current path can be achieved, precisely adjusting the number of current paths participating in interpolation. Furthermore, by connecting the output terminals of all current paths in the same group to the source of the corresponding differential drive transistor, multiple controllable currents participate in weighted interpolation synchronously, thereby improving the linearity of phase interpolation adjustment and ensuring the adjustability of the interpolation process.

[0012] In one possible implementation of the first aspect, N1=3, N2=32, and N3=16.

[0013] By limiting N1 to 3, three adjacent phases are selected for interpolation, increasing the total interpolated current while avoiding excessive phase involvement that would increase circuit complexity. By limiting N3 to 16, each current source group contains 16 current paths, ensuring the adjustable range of a single current source. By limiting N2 to 32, the total number of conductable current paths in the three current source groups is 32, perfectly matching the parameters of N1 and N3. The three factors work together to improve the output swing while also reducing the complexity of the circuit implementation.

[0014] In one possible implementation of the first aspect, the first bit width is 7 and the second bit width is 128.

[0015] By setting the clock control signal width to 7 bits, 128 control levels are provided, enabling fine-grained phase adjustment. By setting the current source switch control signal width to 128 bits, independent switching control of all current paths can be achieved, matching the control requirements of multi-path current source arrays. By decoding the 7-bit control signal into a 128-bit switch control signal, a one-to-one correspondence between the current source switch control signal and the current path is achieved, ensuring the accuracy of phase adjustment.

[0016] In one possible implementation of the first aspect, the input clock module outputs eight input clock signals, the eight input clock signals having a phase interval of 45 degrees.

[0017] The input clock module outputs eight input clocks with a 45-degree phase interval, thus fully covering the entire phase range from 0 to 360 degrees and providing a uniform input phase reference for multi-phase interpolation. Combined with the interpolation method using N1 adjacent phases, the difference between adjacent phases involved in the interpolation remains stable, improving the linearity of the weighted interpolation and ensuring the phase uniformity of the output clock across the entire phase range.

[0018] In one possible implementation of the first aspect, the formula for calculating the target phase is: target phase = × The decimal value of the clock control signal / 2^ the first bit width.

[0019] This calculation formula establishes a linear mapping relationship between the clock control signal value and the target phase, allowing phase adjustment to be uniformly adjusted according to changes in the clock control signal. Combined with a first bit width of 7, linear interpolation is achieved across the entire phase range, reducing nonlinear errors in phase interpolation.

[0020] In one possible implementation of the first aspect, the decoder uses a sliding window decoding rule, wherein the size of the sliding window is N2, and the sliding window moves one bit to the right for each increment of the value of the clock control signal, and the sliding window moves cyclically.

[0021] Because the decoder uses a sliding window decoding rule with a sliding window size of N², the total number of current paths activated during each interpolation remains stable, ensuring a constant amplitude of the differential clock current signal. As the clock control signal value increases by one, the sliding window moves one bit to the right, enabling continuous switching between adjacent phases involved in the interpolation and ensuring continuous phase adjustment. Furthermore, because the sliding window moves cyclically, uninterrupted interpolation adjustment is achieved across the entire phase range from 0 to 360 degrees, avoiding phase jumps and thus improving the stability of the output clock signal.

[0022] In one possible implementation of the first aspect, the input clock signal is a square wave with a duty cycle of 50%.

[0023] By using a square wave with a 50% duty cycle as the input clock signal, the high and low levels of the input clock signal have equal durations, ensuring symmetrical turn-on and turn-off timing of the differential phase drive transistor. This, in turn, keeps the duty cycle of the differential clock voltage signal stable and reduces the impact of duty cycle distortion on the phase of the output clock signal.

[0024] In a second aspect, the present invention provides a clock data recovery circuit, including the phase interpolator as described in the first aspect and any possible implementation thereof.

[0025] Thirdly, the present invention provides a serial communication transceiver, including a clock data recovery circuit as described in the second aspect.

[0026] Compared with the prior art, the beneficial effects of the present invention are as follows: The phase interpolator provided by this invention connects a current source array to a decoder and a phase drive module respectively, allowing the switching control signal output by the decoder to directly act on the current source array. Simultaneously, the output current of the current source array can directly supply the phase drive module, reducing signal loss during intermediate transmission and ensuring the synchronization of the control signal and current output. By connecting the phase drive module to the input clock module and the output load module respectively, the input clock signal can be directly input to the differential phase drive transistors, and the driven differential current can be directly output to the load module, avoiding signal attenuation during intermediate transmission and ensuring the integrity of the input clock and the transmission efficiency of the output current. By connecting each current source group to each pair of differential phase drive transistors in a one-to-one correspondence, the output current of each current source group can accurately supply the drive transistor of the corresponding phase, ensuring that the drive current of different phases can be independently controlled and avoiding current crosstalk between different phases. Furthermore, the clock control signal with the first bit width is decoded by the decoder according to the set decoding rules to obtain the current source switch control signal with the second bit width, and the switch control signal is output to the current source array, thereby realizing the conversion from the upper control command to the current source on / off control signal, providing a control basis for regulating the current path involved in interpolation.

[0027] Furthermore, during each phase interpolation process, a switch control signal controls the conduction of N2 current paths in N1 adjacent current source groups in the current source array. With N1 being an integer greater than 2, N2 being an integer greater than 16, and N2 = 16 × (N1 - 1), three or more current source groups corresponding to adjacent phases can be selected to participate in the interpolation, simultaneously conducting a larger number of current paths. Compared to a two-phase interpolation scheme that conducts 16 current paths, this invention doubles the total number of conducting paths, increasing the total current of the differential clock after interpolation. Because the total current of the differential clock after interpolation increases, the swing of the output clock signal of the target phase is improved, reducing the relative impact of noise on the output clock signal, and thus reducing the phase jitter of the output clock signal. In addition, since the output load module only includes a first load resistor and a second load resistor, the current-to-voltage conversion can be completed without the need for additional inductors, thereby reducing the circuit layout area and lowering the chip manufacturing cost.

[0028] Furthermore, because the total number of current paths in the present invention is greater than the 16 paths in the traditional two-phase interpolator, the total differential clock current after interpolation is larger than that of the traditional solution. This solves the inherent problem of the traditional solution having too small a total differential clock current, requiring a large load resistor to maintain the output swing. Since the increase in the total differential clock current in the present invention is achieved by selecting N1 adjacent current source groups and conducting multiple current paths, rather than by increasing the size of a single current source transistor, the parasitic capacitance of the output node is not increased. This avoids the contradiction in the traditional solution where increasing the current increases parasitic capacitance and reduces bandwidth. In addition, since the output load module includes a first load resistor and a second load resistor, given a sufficiently large total differential clock current, the resistance values ​​of the first and second load resistors can be made smaller. The smaller load resistor, combined with the unincreased parasitic capacitance, significantly reduces the RC time constant of the output node, thereby improving the signal operating bandwidth of the phase interpolator while maintaining the output signal swing. Finally, the interpolated differential clock current signal is converted into an interpolated differential clock voltage signal through the output load module, and the target phase output clock signal is obtained based on the differential clock voltage signal, thereby completing the multi-phase interpolation output.

[0029] In summary, the technical solution of the present invention can improve the output swing and bandwidth of the phase interpolator, reduce the jitter of the output clock signal obtained by interpolation, and improve the bandwidth and linearity of the output clock signal without increasing the size of the device. Attached Figure Description

[0030] Figure 1 This is an 8-phase clock signal illustrated according to an exemplary embodiment.

[0031] Figure 2 This is a phase relationship diagram illustrating phase interpolation using two phases, according to an exemplary embodiment.

[0032] Figure 3 This is a structural block diagram of a phase interpolator according to an exemplary embodiment.

[0033] Figure 4 This is a block diagram illustrating the current source array, phase drive module, and output load module in a phase interpolator according to an exemplary embodiment.

[0034] Figure 5 This is a circuit diagram illustrating an output load module according to an exemplary embodiment.

[0035] Figure 6 This is a circuit diagram illustrating a current source array, a phase drive module, and an output load module in a phase interpolator according to an exemplary embodiment.

[0036] Figure 7 This is a circuit diagram of a current source array and a phase drive module in a phase interpolator according to an exemplary embodiment.

[0037] Figure 8 This is a schematic diagram of an output voltage swing according to an exemplary embodiment.

[0038] Figure 9 This is a schematic diagram of the circuit bandwidth of a phase interpolator according to an exemplary embodiment.

[0039] Figure 10 This is a block diagram illustrating a clock data recovery circuit according to an exemplary embodiment.

[0040] Figure 11 This is a block diagram illustrating a serial communication transceiver according to an exemplary embodiment. Detailed Implementation

[0041] Unless otherwise defined, the technical or scientific terms used in this specification and claims shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. Specific embodiments of the invention will be described below with reference to the accompanying drawings. It should be noted that, in order to provide a concise description, this specification cannot provide a detailed description of all features of the actual embodiments. Without departing from the spirit and scope of the invention, those skilled in the art can make modifications and substitutions to the embodiments of the invention, and the resulting embodiments are also within the protection scope of the invention.

[0042] Illustrative embodiments of the present invention include, but are not limited to, a phase interpolator, a clock data recovery circuit, and a serial communication transceiver.

[0043] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0044] In related technologies, a two-phase interpolator is used to interpolate multiple clocks with different phases generated by the clock generation circuit to produce clocks with smaller phase intervals, thereby reducing the phase jitter of the sampling clock and thus meeting the phase adjustment requirements of the CDR circuit to align the recovery clock edge with the serial data center and achieve accurate data sampling.

[0045] For example, using Figure 1The 8-phase clock signal shown is used as the input clock signal. This 8-phase clock includes: clk_000, clk_045, clk_090, clk_135, clk_180, clk_225, clk_270, and clk_315. During each phase interpolation, two adjacent phases are selected from these 8 phases for interpolation. For example, selecting... Figure 2 The clk_000 and clk_045 shown are used for phase interpolation. However, in the existing technology, when this two-phase interpolation method is applied to the CDR phase adjustment scenario of high-speed serial communication interface, that is, the high-speed SerDes application scenario that is the mainstream in the current data center interconnect and high-speed storage interconnect fields, this two-phase phase interpolator cannot achieve a large output signal swing in a small area and low cost architecture, and it is difficult to meet the ever-increasing performance requirements of high-speed serial communication systems.

[0046] In view of this, the present invention provides a phase interpolator, a clock data recovery circuit, and a serial communication transceiver. The technical solution of the present invention can improve the output swing and bandwidth of the phase interpolator with a smaller chip area and lower chip cost without using an inductor in the output load module, reduce the jitter of the output clock signal obtained by interpolation, improve the bandwidth and linearity of the output clock signal, and improve the performance of the phase interpolator.

[0047] Figure 3 According to some embodiments of the present invention, a structural block diagram of a phase interpolator 110 is illustrated, with reference to... Figure 3 The phase interpolator 110 includes an input clock module 111, a phase drive module 114, a current source array 115, a decoder 112, and an output load module 113. The current source array 115 is connected to the decoder 112 and the phase drive module 114, and the phase drive module 114 is also connected to the input clock module 111 and the output load module 113. The input clock module 111 outputs multiple input clock signals of different phases to the phase drive module 114.

[0048] Figure 4 According to some embodiments of the present invention, it is shown that Figure 3 The diagram illustrates the connection relationships between the current source array 115, the phase drive module 114, and the output load module 113 in the phase interpolator 110. (See reference...) Figure 4 The current source array 115 includes multiple current source groups. In some embodiments, the current source array 115 includes eight current source groups. It should be understood that the specific number of current source groups can be set according to actual needs.

[0049] The phase driving module 114 includes multiple pairs of differential phase driving transistors. Exemplarily, the phase driving module 114 includes eight pairs of differential phase driving transistors. Each current source group 1151 is connected to each pair of differential phase driving transistors in a one-to-one correspondence. Each pair of differential phase driving transistors is used to receive input clock signals of different phases. In some embodiments, each pair of differential phase driving transistors in the phase driving module 114 includes a first phase driving transistor 1141 and a second phase driving transistor 1142; the differential output terminals of the phase driving module 114 include a first output terminal 1143 and a second output terminal 1144. Figure 4 As shown, the first phase drive transistor 1141 is connected to the first output terminal 1143, and the second phase drive transistor 1142 is connected to the second output terminal 1144. For example, Figure 4 The first phase drive transistor 1141 and the second phase drive transistor 1142 are a pair of differential phase drive transistors connected to the same current source group 1151.

[0050] In some embodiments, the output load module 113 includes a first load resistor R1 and a second load resistor R2, and the differential output terminal of the phase drive module 114 is connected to the first load resistor R1 and the second load resistor R2 respectively. Figure 5 According to some embodiments of the present invention, the specific circuit of the output load module 113 is illustrated, with reference to... Figure 5 The output load module 113 includes a first load resistor R1 and a second load resistor R2. The first load resistor R1 is connected to the first output terminal 1143 in the differential output terminal, and the second load resistor R2 is connected to the second output terminal 1144 in the differential output terminal.

[0051] During each phase interpolation process, decoder 112 is configured to: decode the clock control signal with a first bit width according to a set decoding rule to obtain a current source switch control signal with a second bit width; and output the switch control signal to the current source array 115 to control the conduction of N2 current paths in N1 adjacent current source groups 1151 in the current source array 115, so as to conduct the N1 differential phase drive transistors connected to the N1 adjacent current source groups 1151 through the N2 current paths. Input clock signals of different phases are subjected to current-weighted phase interpolation to obtain interpolated differential clock current signals. The interpolated differential clock current signals are then output to output load module 113, so that output load module 113 converts the interpolated differential clock current signals into interpolated differential clock voltage signals through first load resistor R1 and second load resistor R2, so as to obtain the output clock signal of the target phase based on the differential clock voltage signal; where N1 is an integer greater than 2, N2 is an integer greater than 16, and N2 = 16 × (N1 - 1).

[0052] The technical solution of the present invention can improve the output swing and bandwidth of the phase interpolator 110 without increasing the size of the device, reduce the jitter of the output clock signal obtained by interpolation, and improve the bandwidth and linearity of the output clock signal.

[0053] In some embodiments, each current source group 1151 includes N3 parallel current paths, each current path including a current source transistor and a switching transistor; the source of the current source transistor is connected to the power supply ground; the drain of the current source transistor is connected to the source of the switching transistor; the drain of the switching transistor serves as the output terminal of the current path, and the output terminals of all current paths in the same current source group 1151 are connected to the source of a pair of differential phase driving transistors corresponding to the current source group 1151; the gate of the current source transistor is connected to a fixed bias voltage terminal; the gate of the switching transistor receives one bit of the current source switching control signal output by the decoder 112, where N3 is a positive integer.

[0054] Since each current source group 1151 has N3 parallel current paths, multi-level adjustment of the output current of a single current source group can be achieved to adapt to interpolation requirements with different phase weights. By connecting the source of the current source transistor to the power supply ground and the gate to a fixed bias voltage, the current source transistor outputs a constant current, ensuring the stability of the current amplitude of a single current path. By connecting the gate of the switching transistor to a single current source switching control signal, independent on / off control of each current path can be achieved, precisely adjusting the number of current paths participating in interpolation. Furthermore, by connecting the output terminals of all current paths in the same group to the source of the corresponding differential drive transistor, multiple controllable currents synchronously participate in weighted interpolation, thereby improving the linearity of phase interpolation adjustment and ensuring the adjustability of the interpolation process.

[0055] In some embodiments, the input clock module 111 outputs eight input clock signals, with a phase interval of 45 degrees between them. By outputting eight input clocks with a 45-degree phase interval, the input clock module 111 can completely cover the full phase range from 0 to 360 degrees, providing a uniform input phase reference for multi-phase interpolation. Combined with the interpolation method using N1 adjacent phases, the difference between adjacent phases involved in the interpolation remains stable, improving the linearity of the weighted interpolation and thus ensuring the phase uniformity of the output clock across the entire phase range.

[0056] In some embodiments, the formula for calculating the target phase is: Target phase = × Decimal value of clock control signal / 2^First bit width. This calculation formula establishes a linear mapping relationship between the clock control signal value and the target phase, allowing phase adjustment to be uniformly adjusted according to changes in the clock control signal. Combined with a first bit width of 7, linear interpolation is achieved across the entire phase range, reducing nonlinear errors in phase interpolation.

[0057] In some embodiments, the decoder 112 uses a sliding window decoding rule with a sliding window size of N². For every increment of the clock control signal value by 1, the sliding window moves one bit to the right, and this movement is cyclical. Because the decoder 112 uses a sliding window decoding rule with a sliding window size of N², the total number of current paths activated during each interpolation remains stable, ensuring a constant amplitude of the differential clock current signal. The shift of the sliding window to the right for every increment of the clock control signal value allows for continuous switching between adjacent phases involved in the interpolation, ensuring continuous phase adjustment. Furthermore, the cyclic movement of the sliding window enables uninterrupted interpolation adjustment across the entire phase range from 0 to 360 degrees, avoiding phase jumps and thus improving the stability of the output clock signal.

[0058] In some embodiments, N1=3, N2=32, and N3=16. By limiting N1 to 3, three adjacent phases are selected for interpolation, increasing the total interpolated current while avoiding excessive phase involvement that would increase circuit complexity. By limiting N3 to 16, each current source group 1151 contains 16 current paths, ensuring the adjustment range of a single current source. By limiting N2 to 32, the total number of conductable current paths in the three current source groups 1151 is 32, perfectly matching the parameters of N1 and N3. These three factors work together to improve the output swing while maintaining circuit complexity.

[0059] In some embodiments, the first bit width is 7 bits and the second bit width is 128 bits. By setting the bit width of the clock control signal to 7 bits, 128 control levels can be provided, enabling fine-grained phase adjustment. By setting the bit width of the current source switch control signal to 128 bits, independent switching control of all current paths can be achieved, matching the control requirements of the multi-path current source array 115. By decoding the 7-bit control signal into a 128-bit switch control signal, a one-to-one correspondence between the current source switch control signal and the current path is achieved, ensuring the accuracy of phase adjustment.

[0060] To facilitate understanding of the technical solution of this invention, the following will use N1=3, N2=32, and N3=16 as examples, combined with... Figure 6 and Figure 7 The technical solution of the present invention will be described by way of example.

[0061] refer to Figure 6 The phase drive module 114 includes eight pairs of differential phase drive transistors, namely... Figure 6The transistors M1 and M2, M3 and M4, M5 and M6, M7 and M8, M9 and M10, M11 and M12, M13 and M14, and M15 and M16 are included. M1 through M16 are all NMOS transistors. For each pair of differential phase drive transistors, the NMOS transistor connected to the first load resistor R1 is the first phase drive transistor 1141; the NMOS transistor connected to the second load resistor R2 is the second phase drive transistor 1142. For example... Figure 6 The eight NMOS transistors M1, M3, M5, M7, M9, M11, M13 and M15, which are odd-numbered transistors connected to the first load resistor R1, are all first phase drive transistors 1141; Figure 6 The eight NMOS transistors with even-numbered designations M2, M4, M6, M8, M10, M12, M14 and M16, which are connected to the second load resistor R2, are all second phase drive transistors 1142.

[0062] Multiple phase drive transistors are configured to receive multiple sets of differential clock signals, wherein each set of differential clock signals drives at least one pair of transistors connected in parallel, and the two clock signals in each set are out of phase with each other.

[0063] Optionally, the gate of the first phase driving transistor 1141 receives a clock signal of a predetermined phase from a plurality of input clock signals; the gate of the second phase driving transistor 1142 receives an inverted clock signal that is 180 degrees out of phase with respect to the predetermined phase; the source of the first phase driving transistor 1141 and the source of the second phase driving transistor 1142 are connected together to the output terminal of the current source group 1151 corresponding to the differential phase driving transistor; the drain of the first phase driving transistor 1141 is connected to the first output terminal 1143 in the differential output terminal of the phase driving module 114, and the first output terminal 1143 is connected to the first load resistor R1; the drain of the second phase driving transistor 1142 is connected to the second output terminal 1144 in the differential output terminal of the phase driving module 114, and the second output terminal 1144 is connected to the second load resistor R2.

[0064] It should be noted that not every pair of phase drive transistors has the same phase clock input signal received by the first phase drive transistor 1141, nor every pair of phase drive transistors has the same phase clock input signal received by the second phase drive transistor 1142.

[0065] For example, Figure 7 M1, as shown, is the first phase driver 1141 in a pair of differential phase driver transistors. The gate of M1 receives... Figure 1 Of the eight input clock signals shown, clk_000, M2 acts as the second phase driver transistor 1142, and the gate of M2 receives... Figure 1Among the eight input clock signals shown, clk_180 is the inverted clock signal with a phase difference of 180 degrees from clk_000. For example, M3 serves as the first phase driver 1141 in another pair of differential phase driver transistors, and the gate of M3 receives... Figure 1 Of the eight input clock signals shown, clk_045, M4 acts as the second phase driver transistor 1142, and the gate of M2 receives... Figure 1 Of the eight input clock signals shown, clk_225 is the inverted clock signal with a phase difference of 180 degrees from clk_045. Similarly, the gate of M5 receives... Figure 1 The eight input clock signals shown include clk_090, the gate receive of M6, and the inverted clock signal clk_270 corresponding to clk_090. The gate receive of M7... Figure 1 Of the eight input clock signals shown, clk_135 is received by the gate of M8, and its inverted clock signal clk_315 is received by the gate of M9. Clk_180 is received by the gate of M9, and its inverted clock signal clk_000 is received by the gate of M10. Clk_225 is received by the gate of M11, and its inverted clock signal clk_045 is received by the gate of M12. Clk_270 is received by the gate of M13, and its inverted clock signal clk_090 is received by the gate of M14. Clk_315 is received by the gate of M15, and its inverted clock signal clk_135 is received by the gate of M16.

[0066] By configuring multiple phase-driven transistors to receive multiple sets of differential clock signals, where each set of differential clock signals drives at least one pair of transistors connected in parallel, and the two clock signals in each set are out of phase, differential transmission of the input clock is achieved, suppressing common-mode noise interference to the input signal. By connecting the sources of two driving transistors to the output terminal 1150 of the corresponding current source group 1151, the output current of the same current source is evenly distributed to the two driving transistors, maintaining the matching characteristics of the two driving currents. By connecting the drain of the first driving transistor to the first output terminal 1143 and the first load resistor R1, and the drain of the second driving transistor to the second output terminal 1144 and the second load resistor R2, the differential current is symmetrically output to the load, improving the symmetry of the differential output signal, thereby reducing the phase mismatch of the output signal and improving the phase accuracy of the output clock.

[0067] Figure 6 and Figure 7Each of the eight current source groups 1151 shown includes 16 parallel current paths, and each current path includes two NMOS transistors connected in series, one of which serves as a current source transistor and the other as a switch transistor.

[0068] It should be noted that Ms1<0:15> represents the 16 switching transistors in the current source group 1151 corresponding to M1 and M2. The gates of these 16 switching transistors receive one bit of the 16-bit control signal en<0:15> from the 128-bit switching control signal en<0:127> output by decoder 112, thereby controlling the on / off state of these 16 switching transistors. The drains of these transistors are all connected to the source of M1 and M2 as the output terminals of the current source group 1151 corresponding to M1 and M2. Mb1<0:15> represents the 16 current source transistors in the current source group 1151 corresponding to M1 and M2. The sources of these 16 current source transistors are all connected to the power supply ground terminal VSS, the gates of these transistors are all connected to the fixed bias voltage terminal vb, and the drains of these transistors are all connected to the source of the corresponding switching transistor. The 16 current paths (not shown) in the current source group 1151 corresponding to M1 and M2 are respectively composed of Ms10 and Mb10, Ms11 and Mb11, Ms12 and Mb12, Ms12 and Mb12, Ms13 and Mb13, Ms14 and Mb14, Ms15 and Mb15, Ms16 and Mb16, Ms17 and Mb17, Ms18 and Mb18, Ms19 and Mb19, Ms110 and Mb110, Ms111 and Mb112, Ms113 and Mb113, Ms114 and Mb114, and Ms115 and Mb115.

[0069] Correspondingly, Ms2<0:15> represents the 16 switching transistors in the current source group 1151 corresponding to M3 and M4. The gates of these 16 switching transistors receive one bit from the 16-bit control signal en<16:31> in the 128-bit switching control signal en<0:127> output by decoder 112, thereby controlling the on / off state of these 16 switching transistors. The drains of these transistors are all connected to the source of M3 and M4 as the output terminals of the current path. Mb2<0:15> represents the 16 current source transistors in the current source group 1151 corresponding to M3 and M4. The sources of these 16 current source transistors are all connected to the power supply ground terminal VSS, the gates of these transistors are all connected to the fixed bias voltage terminal vb, and the drains of these transistors are all connected to the source of the corresponding switching transistor. The 16 current paths (not shown) in the current source group 1151 corresponding to M3 and M4 are respectively composed of Ms20 and Mb20, Ms21 and Mb21, Ms22 and Mb22, Ms22 and Mb22, Ms23 and Mb23, Ms24 and Mb24, Ms25 and Mb25, Ms26 and Mb26, Ms27 and Mb27, Ms28 and Mb28, Ms29 and Mb29, Ms210 and Mb210, Ms211 and Mb212, Ms213 and Mb213, Ms214 and Mb214, and Ms215 and Mb215.

[0070] Similarly, Ms8<0:15> represents the 16 switching transistors in the current source group 1151 corresponding to M15 and M16. The gates of these 16 switching transistors receive one bit from the 16-bit control signal en<112:127> in the 128-bit switching control signal en<0:127> output by decoder 112, thereby controlling the on / off state of these 16 switching transistors. The drains of these transistors, as current paths, are all connected to the sources of M15 and M16. Mb8<0:15> represents the 16 current source transistors in the current source group 1151 corresponding to M15 and M16. The sources of these 16 current source transistors are all connected to the power supply ground terminal VSS, the gates of these transistors are all connected to the fixed bias voltage terminal vb, and the drains of these transistors are all connected to the source of the corresponding switching transistor. The 16 current paths (not shown) in the current source group 1151 corresponding to M15 and M16 are respectively composed of Ms80 and Mb80, Ms81 and Mb81, Ms82 and Mb82, Ms82 and Mb82, Ms83 and Mb83, Ms84 and Mb84, Ms85 and Mb85, Ms86 and Mb86, Ms87 and Mb87, Ms88 and Mb88, Ms89 and Mb89, Ms810 and Mb810, Ms811 and Mb812, Ms813 and Mb813, Ms814 and Mb814, and Ms815 and Mb815.

[0071] It should be noted that each current path is not always on. Instead, each current path can be independently controlled by connecting its gate to a current source switch control signal, thereby precisely adjusting the number of current paths involved in the interpolation.

[0072] for Figure 6 The high-speed phase interpolator 110 shown, during each phase interpolation process, decoder 112 decodes the 7-bit clock control signal In<6:0> into a 128-bit current source switch control signal en<0:127> according to the sliding window decoding rule described above. The high 3 bits of the clock control signal In<6:0> are used to select 3 of the 8 phases, and the low 4 bits are used for gating. Figure 6 The current diagram shown contains a total of 128 current paths, of which 32 are dedicated to current. For example, when the clock control signal input to decoder 112 is 0000000, the 32 bits of en<0:31> in the resulting current source switch control signal en<0:127> are all 1, and the 96 bits of en<32:127> are all 0. When the clock control signal input to decoder 112 is 0000001, the resulting current source switch control signal en<0:127> is shifted one bit to the right compared to the current source switch control signal obtained when the clock control signal is 0000000. That is, the first bit of en<0:127> is 0, the second to thirty-third bits are all 1, and the remaining bits are 0, resulting in a total of 32 bits being 1. Similarly, for each bit incremented in the value of In<6:0>, the resulting current source switch control signal en<0:127> shifts one bit to the right, and 32 bits in en<0:127> are always set to 1, while the remaining bits are set to 0.

[0073] In this way, it is possible to utilize the time each phase insertion is performed. Figure 6 The phase interpolator 110 shown selects three adjacent clock phases from the aforementioned eight clock phases for interpolation. Specifically, during each interpolation, the current source switch control signal is used to select the phases. Figure 6 The phase interpolator 110 shown has a total of 32 current paths in the three adjacent current source groups 1151, which means that the switching transistors in these 32 current paths are turned on.

[0074] In a specific embodiment of the present invention, taking N1=3 and N2=32 as an example, when the value of the input control signal in<6:0> is 1, the decoder 112 is configured to select the input clock signals of the three phases clk_000, clk_045, and clk_090 for interpolation. The switch control signal output by the decoder 112 controls the three adjacent current source groups 1151 in the current source array 115 corresponding to the three phases, so that a total of N2=32 current paths are turned on. Among them, the number of current paths allocated to clk_000 is 16, to clk_045 is 10, and to clk_090 is 6. Then the clock signals of clk_000, clk_045, and clk_090 respectively drive the three pairs of differential phase drive transistors M1 and M2, M3 and M4, and M5 and M6, thereby controlling the conduction of the current paths in their corresponding current source groups 1151. These three clock currents, weighted by different weights (16:10:6), are combined at the first output terminal 1143 and the second output terminal 1144, respectively, to complete the current-weighted phase interpolation. The resulting current signal is the interpolated differential clock current signal. This differential clock current signal is sent to the output load module 113 for current-to-voltage conversion, thereby obtaining the output clock signal interpolated using the three phases clk_000, clk_045, and clk_090.

[0075] In the relevant two-phase interpolation scheme, only two adjacent phases can be selected for interpolation simultaneously. For example, selecting clk_000 and clk_045 for interpolation controls the two adjacent current source groups 1151 corresponding to these two phases in the current array, so that a total of 16 current paths are turned on. For example, the number of current paths allocated to clk_000 is 8, and the number allocated to clk_045 is 8. Then, the clock signals of clk_000 and clk_045 drive the two pairs of differential phase drive transistors M1 and M2, and M3 and M4 respectively, thereby controlling the conduction of the current paths in their corresponding current source groups 1151. The corresponding differential clock current signal is denoted as I1, and the voltage corresponding to the first output terminal 1143 is denoted as V1. V1 = VDD - R1 * I1. When no current flows through R1, the voltage value corresponding to the first output terminal 1143 is VDD. In other words, the voltage variation range of V1 is [VDD - R1 * I1, VDD], and the swing Vswing1 of V1 is R1 * I1.

[0076] In the technical solution of this invention, it is assumed that when the input clock signals of the three phases clk_000, clk_045 and clk_090 are selected for interpolation, the current flowing through the first output terminal 1143 is I2, and the voltage value corresponding to the first output terminal 1143 is denoted as V2. Then V2 = VDD - R1 * I2. When no current flows through R1, the voltage value corresponding to the first output terminal 1143 is VDD. In other words, the voltage variation range corresponding to the first output terminal 1143 is: [VDD - R1 * I2, VDD], and the swing Vswing2 of V2 is R1 * I2.

[0077] Since the output current is the same when each current path is turned on, I2 is twice I1. Therefore, if... Figure 8 As shown, in the technical solution of this invention, the swing of V2, Vswing2, is twice the swing of V1, Vswing1. It is easy to understand that since the voltage corresponding to the first output terminal 1143 is a ternary wave, in actual use, this voltage signal needs to be post-processed, for example, amplified into a square wave. If the swing of this ternary wave is small, the edge jitter of the converted square wave will be large, resulting in increased noise in the final interpolated clock signal and reduced linearity, thus affecting the performance of the phase interpolator 110.

[0078] Since the swing of V2, Vswing2, in the technical solution of the present invention is twice the swing of V1, Vswing1, the technical solution of the present invention improves the swing of the voltage at the first output terminal 1143 compared with the related two-phase interpolation technical solution, thereby reducing the noise of the interpolation clock signal, improving the linearity of the interpolation clock signal, and thus improving the performance of the phase interpolator 110.

[0079] Furthermore, for application in high-speed serial communication scenarios, it is necessary to expand the output bandwidth of the high-speed interpolator. Therefore, this can be achieved by appropriately configuring the resistance values ​​of the first load resistor R1 and the second load resistor R2 in the output load module 113. For example, these two resistance values ​​can be configured to be greater than 0.5 times and less than twice the corresponding resistance values ​​in the two-phase interpolator. By reducing the resistance values ​​in the output load module 113, no additional inductor is required, while simultaneously obtaining a larger output voltage swing and higher bandwidth. Figure 9 As shown, L1 is the circuit bandwidth when no inductor is set in the correlated two-phase interpolator, L2 is the circuit bandwidth when an inductor is set in the correlated two-phase interpolator, and L3 is the circuit bandwidth when the phase interpolator 110 provided by the present invention uses adjacent three-phase interpolation. Therefore, the technical solution of the present invention not only overcomes the bandwidth bottleneck caused by parasitic parameters in traditional two-phase interpolators, but also provides better high-frequency gain and lower phase noise for signal recovery in high-speed serial communication scenarios, ensuring the integrity of the output signal at extremely high frequencies.

[0080] In some embodiments, the first load resistor R1 and the second load resistor R2 have the same resistance value, both ranging from 80 to 120 ohms. By setting the first load resistor R1 and the second load resistor R2 to the same resistance value, the symmetrical characteristics of the differential clock current signal to differential clock voltage signal conversion are ensured, and the balance of the differential clock voltage signal is maintained. By limiting the resistance values ​​of the two resistors to 80 to 120 ohms, the load impedance is small, which can expand the signal operating bandwidth of the phase interpolator 110.

[0081] In some embodiments, the input clock signal is a square wave with a 50% duty cycle. By using a square wave with a 50% duty cycle for the input clock signal, the high and low levels of the input clock signal have equal durations, ensuring symmetrical turn-on and turn-off timing of the differential phase drive transistor. This, in turn, keeps the duty cycle of the differential clock voltage signal stable and reduces the impact of duty cycle distortion on the phase of the output clock signal.

[0082] In summary, the technical solution provided by this invention has the following advantages: The phase interpolator 110 provided by this invention connects the current source array 115 to the decoder 112 and the phase drive module 114 respectively, so that the switching control signal output by the decoder 112 can directly act on the current source array 115, and the output current of the current source array 115 can directly supply the phase drive module 114, reducing signal loss during intermediate transmission and ensuring the synchronization of the control signal and the current output. By connecting the phase drive module 114 to the input clock module 111 and the output load module 113 respectively, the input clock signal can be directly input to the differential phase drive transistors, and the differential current after driving can be directly output to the load module, avoiding signal attenuation during intermediate transmission and ensuring the integrity of the input clock and the transmission efficiency of the output current. By connecting each current source group 1151 to each pair of differential phase drive transistors in a one-to-one correspondence, the output current of each current source group 1151 can be accurately supplied to the corresponding phase drive transistor, ensuring that the drive current of different phases can be independently controlled and avoiding current crosstalk between different phases. Furthermore, the decoder 112 decodes the clock control signal with the first bit width according to the set decoding rules to obtain the current source switch control signal with the second bit width, and outputs the switch control signal to the current source array 115, thereby realizing the conversion from the upper control command to the current source on / off control signal, and providing a control basis for regulating the current path involved in interpolation.

[0083] Furthermore, during each phase interpolation process, the N2 current paths in the N1 adjacent current source groups 1151 of the current source array 115 are controlled to conduct via a switch control signal. Since N1 is an integer greater than 2, N2 is an integer greater than 16, and N2 = 16 × (N1 - 1), three or more adjacent phase-corresponding current source groups 1151 can be selected to participate in the interpolation, simultaneously conducting a larger number of current paths. Compared to a two-phase interpolation scheme that conducts 16 current paths, this invention doubles the total number of conducting paths, thereby increasing the total differential clock current after interpolation. Because the total differential clock current increases after interpolation, the swing of the output clock signal of the target phase is improved, reducing the relative impact of noise on the output clock signal, and thus reducing the phase jitter of the output clock signal. In addition, since the output load module 113 only includes a first load resistor R1 and a second load resistor R2, the current-to-voltage conversion can be completed without the need for additional inductors, thereby reducing the circuit layout area and lowering the chip manufacturing cost.

[0084] Furthermore, because the total number of current paths in the present invention is greater than the 16 paths of the traditional two-phase interpolator, the total differential clock current after interpolation is larger than that of the traditional solution. This solves the inherent problem of the traditional solution having too small a total differential clock current, requiring a large load resistor to maintain the output swing. Since the increase in the total differential clock current in the present invention is achieved by selecting N1 adjacent current source groups and conducting multiple current paths, rather than by increasing the size of a single current source transistor, the parasitic capacitance of the output node is not increased. This avoids the contradiction in the traditional solution where increasing the current increases parasitic capacitance and reduces bandwidth. Since the output load module 113 only includes a first load resistor and a second load resistor, given a sufficiently large total differential clock current, the resistance values ​​of the first and second load resistors can be made smaller. The smaller load resistor, combined with the unincreased parasitic capacitance, significantly reduces the RC time constant of the output node, thereby increasing the signal operating bandwidth of the phase interpolator 110 while maintaining the output signal swing. Finally, the interpolated differential clock current signal is converted into an interpolated differential clock voltage signal through the output load module 113, and the target phase output clock signal is obtained based on the differential clock voltage signal, thereby completing the multi-phase interpolation output.

[0085] The technical solution of the present invention can improve the output swing and bandwidth of the phase interpolator 110 without increasing the size of the device, reduce the jitter of the output clock signal obtained by interpolation, and improve the bandwidth and linearity of the output clock signal, thereby improving the performance of the phase interpolator 110.

[0086] Furthermore, embodiments of the present invention also provide a clock data recovery circuit 11, such as... Figure 10As shown, the clock data recovery circuit 11 includes a phase interpolator 110 as described in any of the above embodiments of the present invention.

[0087] Furthermore, embodiments of the present invention also provide a serial communication transceiver 10, such as... Figure 11 As shown, the serial communication transceiver 10 includes, as follows: Figure 10 A clock data recovery circuit 11 is shown.

[0088] In this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "multiple" refers to two or more unless otherwise expressly defined.

[0089] The above description of the embodiments is intended to enable those skilled in the art to understand and apply the present invention. It will be apparent to those skilled in the art that various modifications can be made to these embodiments, and the general principles described herein can be applied to other embodiments without creative effort. Therefore, the present invention is not limited to the embodiments described herein, and any improvements and modifications made by those skilled in the art based on the disclosure of the present invention without departing from the scope and spirit of the invention are within the scope of the present invention.

Claims

1. A phase interpolator, characterized in that, include: The system includes an input clock module, a phase drive module, a current source array, a decoder, and an output load module, wherein the current source array is connected to the decoder and the phase drive module, and the phase drive module is also connected to the input clock module and the output load module. The input clock module is used to output multiple input clock signals with different phases to the phase drive module; The current source array includes multiple current source groups, and the phase drive module includes multiple pairs of differential phase drive transistors. Each current source group and each pair of differential phase drive transistors are connected in a one-to-one correspondence. Each pair of differential phase drive transistors receives the input clock signal of a different phase. The output load module includes a first load resistor and a second load resistor. The differential output terminal of the phase drive module is connected to the first load resistor and the second load resistor respectively. During each phase interpolation process, the decoder is configured as follows: The clock control signal with the first bit width is decoded according to the set decoding rules to obtain the current source switch control signal with the second bit width; and The switch control signal is output to the current source array to control the conduction of N2 current paths in N1 adjacent current source groups in the current source array. Through the N2 current paths, current-weighted phase interpolation is performed on N1 input clock signals of different phases received by N1 pairs of differential phase drive transistors connected to the N1 adjacent current source groups to obtain an interpolated differential clock current signal. The interpolated differential clock current signal is then output to the output load module, so that the output load module converts the interpolated differential clock current signal into an interpolated differential clock voltage signal through a first load resistor and a second load resistor, so as to obtain the output clock signal of the target phase based on the differential clock voltage signal. Where N1 is an integer greater than 2, N2 is an integer greater than 16, and N2 = 16 × (N1 - 1).

2. The phase interpolator according to claim 1, characterized in that, Each pair of differential phase driving transistors in the phase driving module includes a first phase driving transistor and a second phase driving transistor; the differential output terminal of the phase driving module includes a first output terminal and a second output terminal. The gate of the first phase driving transistor receives a clock signal of a predetermined phase from a plurality of input clock signals; The gate of the second phase driving transistor receives an inverted clock signal that is 180 degrees out of phase with the predetermined phase; The source of the first phase driving transistor and the source of the second phase driving transistor are both connected to the output terminal of the current source group corresponding to the differential phase driving transistor; The drain of the first phase driving transistor is connected to the first output terminal of the differential output terminal of the phase driving module, and the first output terminal is connected to the first load resistor; the drain of the second phase driving transistor is connected to the second output terminal of the differential output terminal of the phase driving module, and the second output terminal is connected to the second load resistor.

3. The phase interpolator according to claim 2, characterized in that, Each current source group includes N3 parallel current paths, and each current path includes a current source transistor and a switching transistor. The source of the current source transistor is connected to the power supply ground. The drain of the current source transistor is connected to the source of the switching transistor. The drain of the switching transistor serves as the output terminal of the current path. The output terminals of all current paths within the same current source group are connected to the sources of a pair of differential phase drive transistors corresponding to the current source group. The gate of the current source transistor is connected to a fixed bias voltage terminal. The gate of the switching transistor receives one bit of the current source switching control signal output by the decoder, where N3 is a positive integer.

4. The phase interpolator according to claim 3, characterized in that, N1=3, N2=32, N3=16.

5. The phase interpolator according to claim 4, characterized in that, The first bit width is 7, and the second bit width is 128.

6. The phase interpolator according to claim 5, characterized in that, The input clock module outputs eight input clock signals, with a phase interval of 45 degrees between the eight input clock signals.

7. The phase interpolator according to claim 1, characterized in that, The formula for calculating the target phase is: Target phase = × The decimal value of the clock control signal / 2^ the first bit width.

8. The phase interpolator according to claim 1, characterized in that, The decoder uses a sliding window decoding rule, with the sliding window being N² in size. When the value of the clock control signal increases by 1, the sliding window moves one bit to the right, and the sliding window moves cyclically.

9. The phase interpolator according to claim 1, characterized in that, The input clock signal is a square wave with a duty cycle of 50%.

10. A clock data recovery circuit, characterized in that, Includes the phase interpolator as described in any one of claims 1 to 9.

11. A serial communication transceiver, characterized in that, Includes the clock data recovery circuit as described in claim 10.

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