Semiconductor switch with degradation detection

Abstract

The present disclosure relates to semiconductor switches with degradation detection. Described herein is a semiconductor device with a power transistor. The power transistor is composed of a plurality of transistor cells, where the power transistor has two or more gate electrodes to allow for individual switching of the respective two or more groups of transistor cells. The semiconductor device further comprises a metallization layer arranged on a semiconductor die, shaping a main electrode of the power transistor; a clamping circuit configured to limit a voltage drop across the power transistor; a degradation detection circuit configured to detect a degradation of the metallization layer, where the degradation detection circuit is integrated in the same semiconductor die as the first transistor; and a gate control circuit configured to activate and deactivate the two or more groups of transistor cells by providing gate signals to the two or more gate electrodes of the first transistor. When the degradation detection circuit detects a degradation and the clamping circuit is active, at least one group of transistor cells is inactive.

Description

Technical Field

[0001] This disclosure relates to the field of power semiconductor switches, and more particularly to semiconductor devices having power transistors and degradation detection capabilities. Background Technology

[0002] One concept in current measurement, often used in conjunction with power transistors, involves the use of so-called sensing transistors. Power transistors (such as DMOS transistors) typically consist of multiple transistor cells (transistor cell arrays) connected in parallel. However, some transistor cells in the cell array form separate transistors (i.e., sensing transistors). Sensing transistors can operate at approximately the same operating point as power transistors, but have a much smaller effective area. Therefore, the current flowing through the power transistor and the sensing transistor is approximately proportional in this arrangement, where the scaling factor K corresponds (at least theoretically) to the ratio of the effective areas of the two transistors. That is, the effective area of ​​the sensing transistor is K times smaller than the effective area of ​​the power transistor.

[0003] During operation, semiconductor chips, including power transistors, can be exposed to varying thermal loads, which can lead to degradation and ultimately failure over time. Concepts exist for performing so-called "health checks" on semiconductor chips using integrated circuit devices. However, these concepts are often limited to specific applications, or they fail to identify specific problems until it is too late to ensure reliable continued operation (failed operation). For prior art, refer to publication US20230194595A1. Summary of the Invention

[0004] This document describes a semiconductor device having a power transistor. In one embodiment, the power transistor comprises a plurality of transistor cells, wherein the power transistor has two or more gate electrodes to allow individual switching of corresponding two or more sets of transistor cells. The semiconductor device further includes: a metallization layer disposed on a semiconductor die to form the main electrode of the power transistor; a clamping circuit configured to limit a voltage drop across the power transistor; a degradation detection circuit configured to detect degradation of the metallization layer, wherein the degradation detection circuit is integrated in the same semiconductor die as the first transistor; and a gate control circuit configured to activate and deactivate two or more sets of transistor cells by providing gate signals to two or more gate electrodes of the first transistor. When the degradation detection circuit detects degradation and the clamping circuit is active, at least one set of transistor cells is deactivated.

[0005] Furthermore, a method is described herein, in one embodiment, comprising turning on and off a power transistor, wherein the power transistor comprises a plurality of transistor cells, and wherein the power transistor has two or more gate electrodes to allow individual switching of corresponding two or more sets of transistor cells. The method also includes detecting degradation of a metallization layer disposed on a semiconductor die, the metallization layer forming the main electrode of the power transistor; and using a clamping circuit to limit the voltage drop across the power transistor. When degradation is detected and the clamping circuit is active, at least one set of transistor cells is prevented from becoming active. Attached Figure Description

[0006] The invention can be better understood by referring to the following figures and description. The components in the figures are not necessarily drawn to scale; rather, the focus is on illustrating the principles of the invention. Furthermore, in the figures, the same reference numerals denote corresponding parts. In the figures:

[0007] Figure 1 The illustration shows an example of a current measurement circuit that uses a sensing transistor to measure current.

[0008] Figure 2 The diagram shows Figure 1 The example illustrates the resistance of the chip metallization and includes clamping circuitry.

[0009] Figure 3 These are images of the surface of a semiconductor chip recorded using a microscope. Figure 2 The circuitry is integrated into the semiconductor chip;

[0010] Figure 4 It is a schematic cross-sectional view through a semiconductor chip;

[0011] Figure 5 and Figure 2 The example is similar, with additional degradation detection circuitry.

[0012] Figure 6 The illustration shows an example of a semiconductor device with power transistors, where some transistor cells are not activated when the clamping circuit drives the power transistors into a conductive (linear) state.

[0013] Figure 7 It's a diagram. Figure 6 The flowchart shows the function of the circuit. Detailed Implementation

[0014] Figure 1 An exemplary embodiment of a current measurement circuit including a sensing transistor is shown. In the depicted example, the electrical load R LOAD With the help of power transistor T LTo perform the switching. Flow through power transistor T L (And therefore also flows through the load R) LOAD The current of ) is from I LOAD Indicates. Power transistor T L It can be like Figure 1 The high-side switch is shown. That is, the power transistor T... L The main current path (drain-source current path in the case of a MOS transistor) is connected between the power supply terminal VS and the output (output pin OUT), and the load R LOAD This can be connected to the output during operation. It should be understood that this disclosure is not limited to high-side transistors. The concepts described herein can be readily applied to circuits with low-side switches.

[0015] Including sensing transistor T S The current sensing circuit 20 is coupled to the power transistor T. L The current sensing circuit 20 is configured to provide a measurement current I0, which represents the current transmitted through the power transistor T. L Load current I LOAD As stated in the introduction, the sensed current I0 is approximately equal to the load current I. LOAD Proportional, i.e., I0 = I LOAD / K (scale factor K). For current measurement, transistor T S and T L They should have the same (or at least similar) characteristics and operate (approximately) at the same operating point. Therefore, two transistors T... L and T S The gate electrodes of the two transistors are connected to each other. Similarly, the two transistors T L and T S The drain electrodes are connected to each other. Furthermore, in the high-side arrangement, transistor T... L and T S The drain electrode is connected to the power supply terminal VS, and a power supply voltage V is applied to this power supply terminal VS during operation. S .

[0016] In order to make transistor T L and T S Both operate at the same operating point, transistor T L and T S The drain-source voltages of both should be the same. In the depicted embodiment, this is achieved by means of an operational amplifier OA and another transistor T0, which together ensure that the sensing transistor T... S The source voltage at point T is adjusted to match that of the power transistor T. L The source voltage at that point is the same value. As a result, transistor T... L and T SThe drain-source voltages of both are essentially equal. Note that an operational amplifier is not strictly necessary. A device exists to ensure that the measured current I0 is equal to the load current I. LOAD Other concepts related to (approximate) ratios. Specific implementations will depend on application requirements.

[0017] exist Figure 1 In the example, sensing transistor T S It is connected in series with another transistor T0 (i.e., their main current path) so that the same measuring current I0 flows through transistor T. S Both T0 and T0. In the example depicted, transistor T0 is a p-channel MOS transistor, while transistor T... S and T L It is an n-channel MOS transistor. The gate of transistor T0 is driven by the output signal of operational amplifier OA, where the input of operational amplifier OA is coupled to transistor T0. S and T L The source electrode. It should be understood that a p-channel transistor can also be used as a power transistor (and a sensing transistor) to construct a similar circuit.

[0018] Operational amplifier OA and transistor T0 together form the feedback loop. The inverting input of operational amplifier OA is connected to sensing transistor T0. S The source electrode of the operational amplifier OA, the non-inverting input of which is connected to the power transistor T, is connected to the source electrode of the operational amplifier OA. L The source electrode. If the sensing transistor T S The source voltage at the point is less than that of the power transistor T. L The source voltage at point O is then the operational amplifier O A The voltage at the output of transistor T0 increases. As a result, the gate-source voltage at transistor T0 becomes smaller, which has the effect of increasing the on-resistance of transistor T0. The increase in the on-resistance of transistor T0 has the effect of increasing the on-resistance of sensing transistor T. S The effect of increased source voltage at the point is that the feedback loop of operational amplifier OA is stable, and therefore, operational amplifier OA drives transistor T0, causing transistor T... L and T S The voltages at the source electrodes are essentially equal, thus compensating for the difference in drain-source voltages between the power transistor and the sensing transistor. As a result, the sensing transistor and the power transistor operate at essentially the same operating point.

[0019] exist Figure 1 In the example, the sensing current I0 is at the sensing pin I S The output is located at pin IS, and the output current at pin IS is expressed as I. S (In this example, I) S =I0). Sensing resistor R SIt can be connected to the sensing pin IS. Sensing resistor R S It is typically connected between the sensing pin IS and a reference voltage (e.g., ground potential, 0V). Therefore, the resulting voltage V at the sensing pin IS... IS Equal to current I S With resistance R S The product (V) IS =R S ·I S =I LOAD ·R S / K). In other words, resistor R S Sensing current I S It is converted into the corresponding voltage signal.

[0020] Figure 2 The diagram illustrates the relationship between... Figure 1 The circuit shown is essentially the same, in which Figure 2 Includes an additional clamping circuit 21. Furthermore, a resistor R is shown. MET1 and R MET2 (Together considered as R) MET ), where the resistance R MET Arranged on power transistor T L The resistor R is between the source electrode and the output pin OUT. MET (In particular) formed by chip metallization, and therefore can be considered as parasitic resistance. In this example, the non-inverting input of operational amplifier OA is connected to the chip metallization at a specific contact point, which can be considered as being formed by resistor R. MET1 and R MET2 The intermediate tap of the voltage divider. The resistance of the interconnects (e.g., vias or plated through-holes connecting different metallization layers) also affects these resistors R. MET1 and / or R MET2 It makes a contribution. Resistor R MET It is lateral resistance, meaning that the current through these resistors flows essentially in the lateral direction (i.e., essentially parallel to the chip surface), while transistor T... L and T S It can be a vertical transistor (see also) Figure 4 In this array, current flows essentially "from top to bottom" through the transistor cell array in a direction that is essentially perpendicular to the chip surface.

[0021] Clamping circuit 21 is connected to power transistor T L Between the drain and gate, and configured to limit the power transistor T when the inductive load is turned off. L The voltage drop across the transistor (drain-source voltage). When transistor T... LWhen switched off, without clamping circuitry, the drain-source voltage increases until the transistor breaks down. Clamping circuitry (also known as active clamping) provides protection against this situation. When transistor T... L When turned on, it operates in saturation mode (low on-resistance), but when the transistor is turned off, it is driven to its linear mode, where the on-resistance is higher. The inductive load demagnetizes rapidly as energy stored in the clamping circuit is dissipated. However, when the clamping circuit is active, the power transistor T... L The junction temperature may rise significantly because the clamping circuit operates in linear mode. Temperature cycling caused by active clamping is one reason for chip metallization degradation.

[0022] Figure 3 This shows images taken with the aid of a microscope, including those from... Figure 2 A magnified image (photograph) of the semiconductor chip 100 of the circuit. The image of the semiconductor chip 100 shows the chip metallization 101 covering most of the chip surface. Furthermore, Figure 3 The diagram illustrates the contact position 102 of the bonding lead used to connect the chip metallization 101 to the output pin OUT of the chip 100. Figure 3 The output pin OUT itself is not visible because it is usually placed on the lead frame on which the chip 100 is mounted.

[0023] also, Figure 3 The diagram illustrates circuit section 150, which includes power transistors T for driving and operating. L And most of the circuitry required for current measurement using a sensing transistor. As mentioned above, the power and sensing transistors can be implemented as vertical transistors and formed by multiple transistor cells in a cell array. In the case of a vertical transistor, the drain-source current path starts from the top side of the semiconductor chip (in... Figure 3 (As can be seen) it extends through the chip to the bottom side of the chip. Figure 3 In the depicted example, chip metallization 101 forms the source electrode on the top side of the semiconductor die, while transistor T S and T L The drain electrode is located on the bottom side of the semiconductor die.

[0024] resistor R MET A schematic diagram is superimposed on an image of semiconductor chip 100. At this point, it is important to understand the resistance R. MET It is not a specific circuit component implemented at a specific location (locally). Instead, the resistance extends in the lateral direction and is distributed across the entire chip metallization 101 (depending on what current density field is formed in the metallization during operation).

[0025] Chip metallide 101 can be located in multiple positions (e.g., in R...) MET1 With R MET2 See the nodes between. Figure 2 The connection (tap) is made at point ). Figure 3 In the example shown, the resistor R MET One contact is directly adjacent to one of the chip contact locations 102, and the other contact is located near the circuit section 150, where, for example, an operational amplifier OA is also arranged. It can be understood that the voltage divider R... MET1 R MET2 This is a simplified model based on reality. The thickness of the chip metallization layer can range from approximately 2 to 50 μm.

[0026] Chip contact location 102 is, for example, the location where a bonding wire is connected to a chip metallization (e.g., by means of a wire bonding process). In other exemplary embodiments, jigs, strips (strip bonding), etc., may be used instead of bonding wires. The geometry of chip contact location 102 may vary depending on the connection technology used.

[0027] The chip metallide 101 can be contacted at multiple locations. Figure 3 In the illustrated example, another contact is shown near circuit section 150 (on the left). Resistor R can then be... MET (Based on the modeling) it can be viewed as two (or more) resistors connected in parallel. Then, the resistance value R... MET This represents the average value of different local current paths through the chip metallization 101.

[0028] As already mentioned, the semiconductor chip and the chip metallization 101 undergo extensive temperature cycling during integrated circuit operation. As described above, temperature cycling can be caused by the aforementioned voltage clamping mechanism (clamping circuit 21). The (local) temperature can fluctuate more or less regularly between room temperature and, for example, 300°C or higher. Cyclic temperature fluctuations exceeding 200°C are not uncommon. These fluctuations can gradually lead to microcracks 110 in the chip metallization 101, and an increase in the resistance value R. MET The increase is due to the increasing number of microcracks. The study (by monitoring the resistance value R) MET It has been shown that for the resistance value R MET Specific changes in resistance (e.g., an increase of 200%) make semiconductor chip failures increasingly likely. Therefore, monitoring the resistance value R... MET This allows for the prediction that a semiconductor chip is nearing the end of its lifespan before it actually fails. In safety-critical applications, such as certain components of autonomous vehicles, this prediction can be a key advantage in preventing greater damage.

[0029] Finally, it should be noted that the resistance R MET Changes also affect the sensing current i0 and the load current i LOAD The proportionality factor K between them. This comes from... Figure 2 The middle is clear. If the resistance R MET Due to defects such as microcracks and delamination, the voltage at the non-inverting input of operational amplifier OA will also change. As a result, operational amplifier OA cannot ensure the voltage at transistor T. S and T L Equal source voltages.

[0030] Figure 4 yes Figure 3 A schematic cross-sectional view of a semiconductor chip. It should be understood that... Figure 4 This is not drawn to scale and only includes those aspects necessary for understanding the exemplary embodiments discussed herein. The structure of such a semiconductor chip is known to those skilled in the art.

[0031] exist Figure 4 The left-hand side schematically illustrates an array of transistor cells integrated in a semiconductor chip 100. Examples depicted include vertical DMOS transistors. S and T L The drain electrode is formed by metallization 102 on the bottom side of the chip. The source electrode is formed by metallization 101 on the top side of the chip 100. The bottom-side metallization can be mounted on a lead frame or any other chip carrier, for example, by means of a die bonding process. The top-side metallization 101 is connected to the chip pin OUT of the lead frame, for example, by means of a wire bonding process (bonding lead 120). The resistance of the metallization 101 is given by resistor R. MET Indicates (see also) Figure 3 The circuit section 150, which contains most of the other circuit components, is located in... Figure 4 The right-hand side. The resistor R formed by the chip metallization 101. MET Specifically, it is made of power transistor T L The metallization is partially formed during operation and is exposed to heat load and deteriorates due to the (cyclic) heat load.

[0032] Defects typically occur near the metallization layers where the bonding leads connect, where thermal loads induce (thermo)mechanical stress and strain, which in turn can lead to the aforementioned defects such as cracks, delamination, etc. At this point, it is important to understand that it is the temperature gradient (i.e., the temperature difference between two points of proximity) that causes the mechanical stress, rather than temperature itself.

[0033] Figure 5 The example is basically the same as Figure 2 The same as shown. However, Figure 5The circuit includes an additional degradation detection circuit 40, which is configured to detect degradation based on one or more voltages V tapped at the metallization layer. MET1 V MET2 V MET3 To detect metallization layer 101 (see Figure 4 The degradation of the metallization layer 101. As described above, the metallization layer 101 can be considered as a distributed resistance that can be tapped at various locations within the metallization layer 101. Figure 5 In the diagram, the metallization layer 101 is illustrated as a resistive voltage divider, which is also a simplified model of the actual circuit. In reality, the metallization layer can be considered as a complex resistive circuit composed of multiple transistors coupled in series and parallel. The degradation detection circuit can be configured to amplify these voltages V. MET1 V MET2 V MET3 The amplified voltage is then compared to a corresponding threshold. If the amplified voltage V... MET1 V MET2 V MET3 If one or more voltages exceed a corresponding threshold, degradation of the metallization layer is detected. Voltages V tapped at different locations within the metallization layer... MET1 V MET2 V MET3 The assessment can reveal information about which specific parts of the metallization layer are affected. That is, the voltage V... MET1 V MET2 V MET3 The evaluation allows the degradation detection circuit to roughly locate the degraded portions of the metallization layer. In the depicted example, signal S DEG This indicates whether degradation has been detected. In some embodiments, signal S... DEG It indicates whether degradation has been detected, and if so, which portion(s) of the metallization layer is affected.

[0034] According to the embodiments described herein, the semiconductor device includes a power transistor T composed of a plurality of transistor units. L Among them, power transistor T L Having two or more gate electrodes to allow two or more sets of corresponding transistor cells T L0 , ...T Ln-1 Individual switching. A group of transistor units can include one or more individual transistor units. Power transistors are also known as split-gate transistors. Figure 6 An example is shown (the upper part of the illustration).

[0035] Metallization layer 101 is disposed on forming power transistor T LThe first main electrode is located on the semiconductor die 100. In the case of an n-channel MOS transistor, the first main electrode is the source electrode. The semiconductor device also includes a clamping circuit 21 configured to limit the power transistor T. L Voltage drop V across the terminals DS ; and a degradation detection circuit 40, configured to detect degradation based on one or more voltage signals V tapped at the metallization layer 101. MET To detect the degradation of the metallization layer (see Figure 4 In some embodiments, the degradation detection circuit 40 may be integrated with the power transistor T. L In the same semiconductor die.

[0036] Figure 6 The illustrated circuit also includes a gate control circuit 30, which is configured to control the gate of the power transistor T. L The gate electrode provides the corresponding gate signal V G0 , …,V Gn-1 To individually activate and deactivate the mentioned group of transistor cells T L0 ,…,T Ln-1 When the degradation detection circuit 40 detects degradation (and by means of signal S) DEG (to send a signal notification) and the clamping circuit 21 is valid (via signal S) CLAMP When a signal is sent to notify the user, at least one group of transistor cells is deactivated (i.e., prevented from activating). In this context, a group of transistor cells being deactivated means that the corresponding transistor cells are in a blocked state and no current can flow through them (except for some negligible leakage current). Figure 6 In the example, T L0 This can represent a group of transistor units that are not activated (i.e., inactive), even though clamping circuit 21 is active and allows other groups of transistor units to operate in linear mode (thus allowing inductive loads to be demagnetized).

[0037] When power transistor T L When the voltage across the terminals becomes too high (i.e., exceeds the threshold defined by the clamping circuit), the clamping circuit 21 becomes active. In this case, the clamping circuit 21 reduces the gate voltage V. G Pulled high enough to prevent transistor T L The level is completely off. However, when degradation is detected, the gate control circuit 30 will ensure that at least one set of transistor cells is turned off. By deactivating approximately 10% of the effective area (transistor cells), the temperature around the junction lead contacts can be reduced, thereby reducing localized thermal stress and slowing down the further degradation process.

[0038] As described above, the degradation detection circuit 40 can tap two or more voltage signals at two or more corresponding locations on the metallization layer 101. The voltage signals (collectively represented as V) MET Each of these can be processed and compared with a corresponding threshold to allow the degradation detection circuit 40 to roughly locate the degraded portions of the metallization layer 101. The degradation detection circuit 40 can signal the gate control circuit 30 to notify which portions of the metallization layer 101 are degraded, and based on this information, the gate control circuit 30 can determine which group of transistor cells is invalid when the clamping circuit 21 is active. Voltage signal V MET It can depend on the resistance of a specific portion of the metallization layer 101. In essence, the degradation detection circuit 40 can detect the increased resistance of the metallization layer 101 or certain portions of the metallization layer 101.

[0039] With the help of Figure 7 The flowchart further illustrates the above concepts. Figure 7 The diagram illustrates the operation of power transistors (see example...). Figure 6 transistor T L A method for a semiconductor device, wherein a power transistor comprises a plurality of transistor units, and wherein the power transistor has two or more gate electrodes to allow individual switching of corresponding two or more sets of transistor units. According to Figure 7 The method includes turning a power transistor on and off (block S10). The method also includes detecting degradation of a metallization layer disposed on a semiconductor die and forming the main electrode (e.g., the source electrode) of the power transistor (block S20). The power transistor can be used to connect (and disconnect) an inductive load from a power supply voltage. To protect the power transistor, the method includes using a clamping circuit to limit the voltage drop across the power transistor (e.g., the drain-source voltage V). DS (Box S30). It should be noted that various clamping circuits are known in the field of power electronics. Furthermore, the method includes: when degradation is detected and the clamping circuit is effective, preventing at least one group of transistor units from becoming active (Box S40).

[0040] In one example, the clamping circuit can drive the power transistor to operate in a linear mode, thereby allowing demagnetizing current to flow through the power transistor and dissipate the energy stored in the inductive load. Some exemplary embodiments described herein are summarized below.

[0041] In one embodiment, at least one group of transistor cells that remain inactive when the clamping circuit is active includes at least one transistor cell. In one embodiment, the gate control circuit is configured to select at least one group of transistor cells (which remain inactive when the clamping circuit is active) based on the output of the degradation detection circuit. This output can indicate whether degradation has been detected.

[0042] In some embodiments, it can indicate which portions of the metallization layer are degraded. Therefore, the degradation detection circuit can be configured to detect degradation of a specific portion of the metallization layer by evaluating the resistance of that specific portion. Evaluation of resistance can be accomplished by evaluating a voltage signal. Thus, in one embodiment, the degradation detection circuit can be configured to detect degradation of a specific portion of the metallization layer by evaluating a voltage signal tapped at a specific location in the metallization layer, and evaluating the voltage signal can include comparing the voltage signal to a corresponding threshold. The voltage signal can be amplified before comparing the amplified signal to the corresponding threshold.

[0043] In one embodiment, at least one group of transistor cells (which remain inactive when the clamping circuit is active) depends on which specific portions of the metallization layer are detected as deteriorated. Furthermore, when the deterioration detection circuit does not signal deterioration, the gate control circuit can activate at least a portion of at least one group of transistor cells (which are inactive when deterioration is detected).

[0044] Although the invention has been illustrated and described with respect to one or more embodiments, substitutions and / or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular, with respect to the various functions performed by the foregoing components or structures (units, components, devices, circuits, systems, etc.), unless otherwise specified, the terminology used to describe these components (including references to "method") is intended to correspond to any component or structure that performs the specified function of the described component (e.g., is functionally equivalent), even if it is not structurally equivalent to the disclosed structure that performs the function in the exemplary embodiments of the invention illustrated herein.

Claims

1. A semiconductor device, comprising: Composed of multiple transistor units (T L0 , …T Ln-1 The first transistor (T) is composed of L ), wherein the first transistor (T) L It has two or more gate electrodes to allow individual switching of corresponding two or more sets of transistor cells; A metallization layer (101) is disposed on a semiconductor die, the metallization layer forming the first transistor (T). L The main electrode; Clamping circuit (21) is configured to limit the first transistor (T) L Voltage drop across (V) DS ); The degradation detection circuit (40) is configured to detect degradation of the metallization layer (101); The gate control circuit (30) is configured to control the gate by directing the first transistor (T) L The two or more gate electrodes provide the gate signal (V). G0 , …V Gn -1) to activate and deactivate the two or more sets of transistor units, wherein at least one set of transistor units is inactive when degradation is detected by the degradation detection circuit (40) and the clamping circuit (21) is active.

2. The semiconductor device according to claim 1, The at least one set of transistor units that remain inactive when the clamping circuit (21) is active includes at least one transistor unit.

3. The semiconductor device according to claim 1 or 2, The clamping circuit (21) is configured to drive the first transistor (T) when it is active. L ), causing the first transistor (T) L It operates in linear mode.

4. The semiconductor device according to any one of claims 1 to 3, The gate control circuit (30) is configured to select the at least one group of transistor units based on the output of the degradation detection circuit (40), wherein the at least one group of transistor units remains inactive when the clamping circuit (21) is active.

5. The semiconductor device according to any one of claims 1 to 4, The degradation detection circuit (40) is configured to detect degradation of a specific portion of the metallization layer (101) by evaluating the resistance of that specific portion.

6. The semiconductor device according to any one of claims 1 to 5, The degradation detection circuit (40) is configured to evaluate voltage signals (V) tapped at one or more specific locations on the metallization layer (101). MET ( ) to detect the degradation of one or more specific portions of the metallization layer (101).

7. The semiconductor device according to claim 6, The voltage signal (V) is evaluated. MET This includes the voltage signal (V) MET ) is compared with the corresponding threshold.

8. The semiconductor device according to claim 7, The voltage signal (V) is evaluated. MET This includes amplifying the voltage signal (V). MET And the amplified voltage signal (V) MET ) is compared with the corresponding threshold.

9. The semiconductor device according to any one of claims 5 to 8, The at least one set of transistor cells that remain inactive when the clamping circuit (21) is active depends on which specific portions of the metallization layer (101) are detected as degraded.

10. The semiconductor device according to any one of claims 1 to 9, in, When the degradation detection circuit does not signal degradation, the gate control circuit (30) is configured to turn on the first transistor (T) L When the at least one group of transistor units is activated, at least a portion of the at least one group of transistor units is activated.

11. The semiconductor device according to any one of claims 1 to 10, The degradation detection circuit and the first transistor (T) L They are integrated into the same semiconductor die.

12. A method comprising: Turning the first transistor (T) on and off L The first transistor consists of multiple transistor units (T) L0 , …T Ln-1 ) constitutes, wherein the first transistor (T) L It has two or more gate electrodes to allow individual switching of corresponding two or more sets of transistor cells; The degradation of a metallization layer (101) disposed on a semiconductor die, the metallization layer (101) forming the first transistor (T) is detected. L The main electrode; Using clamping circuit (21) to limit the first transistor (T) L Voltage drop across (V) DS ); When degradation is detected and the clamping circuit (21) is active, the at least one set of transistor units is prevented from becoming active.

13. The method according to claim 12, in, The clamping circuit (21) drives the first transistor (T) when it is active. L ), causing the first transistor (T) L It operates in linear mode.

14. The method according to claim 12, The detection of degradation includes detecting degradation of one or more specific portions of the metallization layer (101) by evaluating the resistance of one or more specific portions of the metallization layer (101).

15. The method according to claim 14, in, The at least one set of transistor units that are prevented from becoming active when the clamping circuit (21) is active depends on which particular portion of the metallization layer (101) is detected as deteriorated.

Images