Method and apparatus for controlling input tolerance input / output level shifter

Abstract

Methods and apparatuses are provided for controlling an input tolerance input / output (I / O) level shifter, which is used to couple an I / O pad to a buffer circuit within an input receiver circuit. The method can include performing voltage detection based gate bias control for a first N-type transistor within the input tolerance I / O level shifter, including performing a voltage detection operation on a received voltage level on the I / O pad to generate a voltage detection result, and generating a self-control signal corresponding to the voltage detection result for gate bias control, and selectively performing a level down operation to generate a level down voltage as the self-control signal according to the received voltage level for controlling the gate bias of the first N-type transistor according to the voltage detection result.

Description

Technical Field

[0001] This invention relates to circuit control, and more particularly to a method and related apparatus for controlling a level shifter as an input / output (I / O) level shifter. Background Technology

[0002] According to relevant technologies, the nominal voltage of some I / O devices conforming to newer technologies may be 1.8 volts (V), while the nominal voltage of some I / O devices conforming to older technologies may be 3.3 V. For compatibility with older technologies, it is desirable for circuit designers to operate at voltages higher than the device's nominal voltage for input tolerance cells. For example, when an I / O device has a nominal voltage of 1.8 V, it is desirable for the circuit designer to interface with a 3.3 V voltage. However, regarding device reliability, 1.8 V I / O devices in input tolerance cells may be severely degraded due to excessive voltage differences during transient behavior, potentially shortening their lifespan. In particular, time-dependent oxide breakdown and hot carrier injection may occur. Therefore, a novel approach and related architecture are needed to address these issues with little or no side effects. Summary of the Invention

[0003] The purpose of this invention is to provide a method and related equipment for controlling a level offsetter as an input-tolerant I / O level offsetter, so as to solve the above-mentioned problems.

[0004] At least one embodiment of the present invention provides a device for controlling a level offsetter as an input-tolerant I / O level offsetter, which can be used to couple an I / O pad to a buffer circuit within an input receiver circuit to act as a sub-circuit of the input receiver circuit. The device may include a voltage-detection-based gate bias control circuit for voltage-detection-based gate bias control of a first N-type transistor within the input-tolerant I / O level offsetter, wherein a second N-type transistor within the input-tolerant I / O level offsetter is coupled to the first N-type transistor, and a gate of the second N-type transistor is coupled to a power supply voltage. Additionally, the voltage-detection-based gate bias control circuit may include a voltage detection and control circuit coupled to the I / O pad, and a level-down device coupled to the voltage detection and control circuit and a gate of the first N-type transistor. For example, the voltage detection and control circuit can be used to perform at least one voltage detection operation on a received voltage level on the I / O pad to generate at least one voltage detection result, which is used to generate a self-control signal corresponding to the at least one voltage detection result for gate bias control, wherein the at least one voltage detection result indicates whether the received voltage level corresponds to a logic high state or a logic low state; and the level reduction device can be used to selectively perform a level reduction operation based on the at least one voltage detection result to generate a level reduction voltage based on the received voltage level as the self-control signal for controlling a gate bias of the first N-type transistor.

[0005] At least one embodiment of the present invention provides a method for controlling a level offsetter as an input-tolerant I / O level offsetter, wherein the input-tolerant I / O level offsetter can be used to couple an I / O pad to a buffer circuit within an input receiver circuit to act as a sub-circuit of the input receiver circuit. The method may include: performing voltage-sensing-based gate bias control on a first N-type transistor within the input-tolerant I / O level offsetter, wherein a second N-type transistor within the input-tolerant I / O level offsetter is coupled to the first N-type transistor, and a gate of the second N-type transistor is coupled to a power supply voltage. For example, the voltage-detection-based gate bias control of the first N-type transistor within the input tolerance I / O level offset may further include: performing at least one voltage detection operation on a received voltage level on the input / output pad to generate at least one voltage detection result for generating an automatic control signal corresponding to the at least one voltage detection result to perform gate bias control, wherein the at least one voltage detection result indicates whether the received voltage level corresponds to a logic high state or a logic low state; and selectively performing a level-down operation based on the at least one voltage detection result to generate a level-down voltage as the automatic control signal for controlling a gate bias of the first N-type transistor.

[0006] One of the many advantages of this invention is that, through appropriate design, the method and related apparatus of this invention can dynamically manage the input receiver circuit to ensure its proper operation under various conditions. For example, when an I / O device has a nominal voltage of 1.8 V, it can be used to interface with both 1.8 V and 3.3 V voltage interfaces, thereby reducing related costs. In particular, the method and related apparatus of this invention can maintain the normal operation of the input receiver circuit over time without significant degradation. Furthermore, the method and related apparatus of this invention can solve the problems of related technologies with little or no side effects. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of a device for controlling a level offset as an input tolerance I / O level offset according to an embodiment of the present invention, wherein the device can be operated according to a method for controlling a level offset as an input tolerance I / O level offset.

[0008] Figure 2 A single-transistor level offset control scheme is illustrated.

[0009] Figure 3 A multi-transistor level offset control scheme of the method is illustrated according to an embodiment of the present invention.

[0010] Figure 4 An embodiment of the present invention is illustrated Figure 3 The hardware architecture involved in this multi-transistor level offset control scheme is shown.

[0011] Figure 5 The lower half of the illustration depicts an embodiment of the present invention. Figure 3 The multi-transistor architecture normal voltage configuration involved in the multi-transistor level offset control scheme shown is as follows: Figure 5 Its upper half is depicted Figure 2 The normal voltage configuration of the single-transistor architecture involved in this single-transistor level offset control scheme is shown for better understanding.

[0012] Figure 6 The lower half of the illustration depicts an embodiment of the present invention. Figure 5 The lower half shows the relevant signals for the normal voltage configuration of this multi-transistor architecture, where Figure 6 Its upper half is depicted Figure 5 The upper part shows the relevant signals for the normal voltage configuration of this single-transistor architecture for better understanding.

[0013] Figure 7 The lower half of the illustration depicts an embodiment of the present invention. Figure 3 The abnormal voltage configuration of the multi-transistor architecture involved in the multi-transistor level offset control scheme shown is as follows: Figure 7 Its upper half is depicted Figure 2 The abnormal voltage configuration of the single-transistor architecture involved in this single-transistor level offset control scheme is shown for better understanding.

[0014] Figure 8 The lower half of the illustration depicts an embodiment of the present invention. Figure 7 The lower half shows the relevant signals for the abnormal voltage configuration of this multi-transistor architecture, where Figure 8 Its upper half is depicted Figure 7 The upper part shows the relevant signals for abnormal voltage configuration of this single-transistor architecture for better understanding.

[0015] Figure 9 The illustration depicts another embodiment of the present invention. Figure 7 The lower half shows the relevant signals for abnormal voltage configuration of this multi-transistor architecture.

[0016] Figure 10 An embodiment of the present invention illustrates a workflow of the method.

[0017] [Symbol Explanation]

[0018] 10: Input / Output (I / O) Pads

[0019] 19: Level Offset

[0020] 20: Input Tolerance Input / Output (I / O) Level Offset

[0021] 21: First N-type transistor

[0022] 22: Second N-type transistor

[0023] 30: Pre-drive circuit

[0024] 40: Buffer circuit

[0025] 100: Equipment

[0026] 110: Gate bias control circuit based on voltage detection

[0027] 111: Voltage detection and control circuit

[0028] 1111: First voltage detection and path control sub-circuit

[0029] 1112: Second voltage detection and path control sub-circuit

[0030] 112: Level reduction device

[0031] NM0~NM3: N-type transistors

[0032] PM1, PM2: P-type transistors

[0033] IO: Received voltage level

[0034] IE: Input enable signal

[0035] O: Data output signal

[0036] Va: Automatic control signal

[0037] Vb, VB, IOA, Vb_fresh, Vb_1.5_yr, Vb_10_yr, IOA_fresh, IOA_1.5_yr, IOA_10_yr: Intermediate signals

[0038] VCC, VCC18: Power supply voltage

[0039] Vds0, Vds2, Vds3, Vds(NM0), Vds(NM2), Vds(NM3): Drain-to-source voltages

[0040] VIO: Predetermined voltage level

[0041] Vtn: Threshold voltage

[0042] S10, S11, S12, S20: Steps Detailed Implementation

[0043] Figure 1 This is a schematic diagram of an apparatus 100 for controlling a level offsetter (e.g., a level offsetter having at least two transistors) as an input tolerance I / O level offsetter 20 according to an embodiment of the present invention, wherein the apparatus 100 can operate according to a method for controlling the level offsetter as an input tolerance I / O level offsetter. The input tolerance I / O level offsetter 20 can be used to couple an I / O pad 10 to a buffer circuit 40 (e.g., an I / O buffer circuit) within an input receiver circuit to act as a sub-circuit of the input receiver circuit. According to some embodiments, a plurality of sub-circuits of the input receiver circuit may include the I / O pad 10, the input tolerance I / O level offsetter 20, the buffer circuit 40, etc., on one of the receive paths of the input receiver circuit, and the apparatus 100 may include at least a portion of the plurality of sub-circuits (e.g., a portion or all of the sub-circuits). For example, the apparatus 100 may include the entire input receiver circuit, and in particular, may represent the input receiver circuit, but the invention is not limited thereto.

[0044] like Figure 1 As shown, device 100 may include a voltage-sensing-based gate bias control circuit 110 for voltage-sensing-based gate bias control of a first N-type transistor 21 within an input tolerance I / O level offset 20, wherein a second N-type transistor 22 within the input tolerance I / O level offset 20 is coupled to the first N-type transistor 21, and a gate of the second N-type transistor 22 (not shown) Figure 1 The gate bias control circuit 110 based on voltage detection may include a voltage detection and control circuit 111 coupled to the I / O pad 10, and a gate (not shown) coupled to the voltage detection and control circuit 111 and the first N-type transistor 21. Figure 1 A voltage level reduction device 112. The voltage detection and control circuit 111 may include a first voltage detection and path control sub-circuit 1111 and a second voltage detection and path control sub-circuit 1112.

[0045] The voltage detection and control circuit 111 can perform at least one voltage detection operation (e.g., one or more voltage detection operations) on a received voltage level IO on the I / O pad 10 to generate at least one voltage detection result (e.g., one or more voltage detection results), which is used to generate an automatic control signal Va corresponding to the at least one voltage detection result for gate bias control. The at least one voltage detection result indicates whether the received voltage level IO corresponds to a logic high state or a logic low state. The level reduction device 112 can selectively perform a level reduction operation based on the at least one voltage detection result to generate a level reduction voltage as an automatic control signal Va based on the received voltage level IO, for controlling the gate bias of the first N-type transistor 21. For better understanding, when the received voltage level IO is in the logic high state, the received voltage level IO can be equal to a predetermined higher voltage IO. H When the received voltage level IO is in this logic low state, the received voltage level IO can be equal to a predetermined lower voltage IO. L Among them, the lower voltage IO is predetermined L This can be the ground voltage. For example, for a predetermined higher voltage IO. H Applications equal to the power supply voltage VCC, IO H = VCC = 1.8 V and IO L = 0 V, and for the predetermined higher voltage IO H Applications with voltages greater than the power supply voltage VCC, IO H = 3.3 V > VCC = 1.8 V and IO L = 0 V, but the invention is not limited thereto. In some examples, the power supply voltage VCC, a predetermined higher voltage IO H and / or a predetermined lower voltage IO L It can be changed.

[0046] The first voltage detection and path control subcircuit 1111 can selectively open a signal path between the I / O pad 10 and the level reduction device 112 based on at least one voltage detection result, allowing the level reduction device 112 to perform the level reduction operation to generate the level reduction voltage as a self-control signal Va. The second voltage detection and path control subcircuit 1112 can selectively close a power path between the power supply voltage VCC and an output terminal of the level reduction device 112 based on at least one voltage detection result, allowing the level reduction device 112 to correctly output the level reduction voltage as the self-control signal Va without being affected by the power supply voltage VCC. Specifically, the at least one voltage detection result may include a first voltage detection result at a first time point and a second voltage detection result at a second time point, wherein the first voltage detection result indicates that the received voltage level IO corresponds to the logic high state, and the second voltage detection result indicates that the received voltage level IO corresponds to the logic low state. For example, the first voltage detection and path control subcircuit 1111 can open the signal path at a first time point based on the first voltage detection result, allowing the level reduction device 112 to perform the level reduction operation to generate the level reduction voltage as the self-control signal Va. The second voltage detection and path control subcircuit 1112 can close the power path at the first time point based on the first voltage detection result, allowing the level reduction device 112 to correctly output the level reduction voltage as the self-control signal Va, unaffected by the power supply voltage VCC. Furthermore, the first voltage detection and path control subcircuit 1111 can close the signal path at a second time point based on the second voltage detection result to prevent the level reduction device 112 from performing the level reduction operation. The second voltage detection and path control subcircuit 1112 can open the power path at the second time point based on the second voltage detection result to generate the self-control signal Va based on the power supply voltage VCC.

[0047] based on Figure 1 The architecture shown indicates that the device 100, operating according to this method, can dynamically manage the input receiver circuitry to ensure its proper operation under various conditions. For better understanding, Figure 2A single-transistor level offset control scheme is illustrated, where the power supply voltage VCC18 can be used as an example of the aforementioned power supply voltage VCC, and VCC18 = 1.8V. Assuming that the voltage applied across the drain and source of any N-type transistor NM can be called the drain-to-source voltage Vds, for example, corresponding to the drain-to-source voltage Vds(NM) of any N-type transistor NM, when the level offset 19 has only a single transistor, such as the N-type transistor NM0 shown in sub-figure (a), the drain-to-source voltage Vds(NM0) of the N-type transistor NM0 can be written as the drain-to-source voltage Vds0 shown in sub-figure (b). When the received voltage level IO is equal to a predetermined voltage level VIO, such as 3.3 V (e.g., IO = 3.3 V), the drain-to-source voltage Vds0 of the N-type transistor NM0 can be equal to the voltage difference between the received voltage level IO (especially the predetermined voltage level VIO) and the voltage level of the intermediate signal IOA on the input terminal of the pre-drive circuit 30 (or the output terminal of the level offsetter 19). When IO = 3.3 V, IOA = 1.8 V - Vtn, where "Vtn" can represent the threshold voltage (or turn-on voltage) of the N-type transistor NM. Depending on the process variations, if Vtn > 0.3 V, then Vds > 1.8 V, which indicates a reliability problem; in particular, as shown in sub-figure (c), Vds0 > 1.8 V indicates excessive oxide stress. In contrast, the method and apparatus 100 of the present invention can dynamically manage the input receiver circuit to ensure that the input receiver circuit operates correctly under various conditions.

[0048] Figure 3 According to an embodiment of the present invention, a multi-transistor level offset control scheme of the method is illustrated, wherein the power supply voltage VCC18 can be used as an example of the aforementioned power supply voltage VCC, VCC18 = 1.8 V, and the intermediate signal VB can be used as... Figure 1An example of the intermediate signal Vb is shown. As shown in sub-figure (a), the plurality of sub-circuits of this input receiver circuit may include I / O pads 10, input tolerance I / O level offsetters 20, pre-drive circuits 30, buffer circuits 40, etc., on the receiving path, while the gate bias control circuit 110 based on voltage detection may be integrated into the receiving path as one of the plurality of sub-circuits. The first N-type transistor 21 and the second N-type transistor 22 may be implemented as N-type transistors NM2 and NM3, respectively. When the input tolerance I / O level offsetter 20 has a plurality of transistors, such as N-type transistors NM2 and NM3, the drain-to-source voltages Vds(NM2) and Vds(NM3) of N-type transistors NM2 and NM3 may be written as the drain-to-source voltages Vds2 and Vds3 shown in sub-figure (b), respectively. N-type transistors NM2 and NM3 can split excessive voltage into two voltages to withstand it (labeled "Vds3 + Vds2" in sub-figure (b) for simplicity). When the received voltage level IO is equal to the predetermined voltage level VIO, such as 3.3 V (e.g., IO = 3.3 V), the drain-to-source voltage Vds2 of N-type transistor NM2 can be equal to the voltage difference between the received voltage level IO (especially the predetermined voltage level VIO) and the voltage level of the intermediate signal VB, while the drain-to-source voltage Vds3 of N-type transistor NM3 can be equal to the voltage difference between the voltage level of the intermediate signal VB and the voltage level of the intermediate signal IOA at the input terminal of the pre-drive circuit 30 (or the output terminal of the input tolerance I / O level offset 20). As shown in sub-figure (c), Vds2 < 1.8 V and Vds3 < 1.8 V, and there is no problem of excessive oxidation stress.

[0049] For example, when an I / O device has a nominal voltage of 1.8 V, it can be used to interface with both 1.8 V and 3.3 V voltage interfaces to reduce associated costs. In particular, over time, the method and apparatus 100 of this invention can maintain the normal operation of the input receiver circuit without significant degradation.

[0050] Figure 4 An embodiment of the present invention is illustrated Figure 3The hardware architecture involved in the multi-transistor level offset control scheme shown herein includes transistors (e.g., N-type and P-type transistors) that can be metal-oxide-semiconductor field-effect transistors (MOSFETs), such as N-type MOSFETs (or "NMOSFETs") and P-type MOSFETs (or "PMOSFETs"), but the invention is not limited thereto. The types of these transistors can be varied without hindering the implementation of the invention. Additionally, the input receiver circuit can set an input enable signal IE to an input enable / disable state to indicate whether data buffering for the receiving path is enabled. When the input enable signal IE is set to the input enable state, the buffer circuit 40 can perform data buffering for the receiving path to output the received data to a subsequent circuit, such as a data processing circuit, via the data output signal O.

[0051] The partial hardware architecture of the voltage-sensing-based gate bias control circuit 110 can be described as follows. In the voltage sensing and control circuit 111, the first voltage sensing and path control sub-circuit 1111 may include a first switch coupled to the I / O pad 10, such as a P-type transistor PM1, used to selectively open the signal path based on at least one voltage sensing result, allowing the level-down device 112 to perform the level-down operation to generate the level-down voltage as a self-control signal Va. The second voltage sensing and path control sub-circuit 1112 may include a second switch coupled to the I / O pad 10, such as a P-type transistor PM2, used to selectively close the power path based on at least one voltage sensing result, allowing the level-down device 112 to correctly output the level-down voltage as the self-control signal Va, unaffected by the power supply voltage VCC, such as power supply voltage VCC18. Figure 4 As shown, a gate of P-type transistor PM1 and a gate of P-type transistor PM2 are coupled to power supply voltage VCC18 and I / O pad 10, respectively. A source of P-type transistor PM1 (e.g., the terminal facing the left) and a source of P-type transistor PM2 (e.g., the terminal facing upward) are coupled to I / O pad 10 and power supply voltage VCC18, respectively. A drain of P-type transistor PM1 and a drain of P-type transistor PM2 are coupled to an input terminal (e.g., the left terminal) and an output terminal (e.g., the upper terminal) of level reduction device 112, respectively.

[0052] Additionally, the level-down device 112 may include a diode-connected transistor, such as NM1, coupled to the gate of the voltage detection and control circuit 111 and the first N-type transistor 21 (e.g., NM2), to perform the level-down operation to generate the level-down voltage as a self-control signal Va. A drain (e.g., the downward-facing terminal) and a gate of the N-type transistor NM1 are electrically connected to each other and coupled to the signal path (between the I / O pad 10 and the level-down device 112), for example, through the signal path of the source and drain of the P-type transistor PM1. A source (e.g., the upward-facing terminal) of the N-type transistor NM1 is coupled to the power path (between the power supply voltage VCC18 and the level-down device 112), for example, through the power path of the source and drain of the P-type transistor PM2.

[0053] For example, when IO = 0 V, the relevant operations may include:

[0054] (1) The first voltage detection and path control sub-circuit 1111 (or the P-type transistor PM1 within it) can close the signal path at the second time point according to the second voltage detection result to prevent the level reduction device 112 from performing the level reduction operation, and the second voltage detection and path control sub-circuit 1112 (or the P-type transistor PM2 within it) can open the power path at the second time point according to the second voltage detection result to generate a self-control signal Va according to the power supply voltage VCC;

[0055] (2) The second voltage detection and path control sub-circuit 1112 (or its P-type transistor PM2) can turn on the power supply voltage VCC18 (e.g., VCC18 = 1.8 V) to its lower terminal to generate a self-control signal Va, wherein the self-control signal Va may have a slight voltage drop compared to the power supply voltage VCC18; and

[0056] (3) Under the control of the gate bias control circuit 110 based on voltage detection, when IO = 0 V, Vds2 = Vds3 = 0 V in the input tolerance I / O level offset 20, there is no need to worry about reliability.

[0057] For example, when IO = 3.3 V, the relevant operations may include:

[0058] (1) The first voltage detection and path control sub-circuit 1111 (or the P-type transistor PM1 within it) can open the signal path at the first time point according to the first voltage detection result, so as to allow the level reduction device 112 to perform the level reduction operation to generate the level reduction voltage as the self-control signal Va, and the second voltage detection and path control sub-circuit 1112 (or the P-type transistor PM2 within it) can close the power path at the first time point according to the first voltage detection result, so as to allow the level reduction device 112 to correctly output the level reduction voltage as the self-control signal Va, without being affected by the power supply voltage VCC;

[0059] (2) The first voltage detection and path control sub-circuit 1111 (or its P-type transistor PM1) and the level reduction device 112 (or its N-type transistor NM1) can turn on the received voltage level IO (e.g., IO = 3.3 V) to the output terminal of the level reduction device 112 to generate the level reduction voltage as the self-control signal Va. Compared to the received voltage level IO, the intermediate signal at the input terminal of the level reduction device 112 can have a very small voltage drop, which can be ignored. Furthermore, compared to this intermediate signal, the self-control signal Va can have a slight voltage drop, which is equal to Vtn. Therefore, the voltage level of the self-control signal Va can be considered equal to (3.3 V - Vtn); and

[0060] (3) Under the control of the gate bias control circuit 110 based on voltage detection, when IO = 3.3 V, in the input tolerance I / O level offset 20, Vds2 < 1.8 V and Vds3 < 1.8 V, there is no need to worry about reliability. The voltage level of the intermediate signal Vb can be equal to (3.3V - (2 * Vtn)), the drain-to-source voltage Vds2 (or Vds(NM2)) can be equal to (2 * Vtn), and the drain-to-source voltage Vds3 (or Vds(NM3)) can be equal to (1.5V - Vtn).

[0061] For example, the threshold voltage Vtn can be equal to 0.5 V, but the present invention is not limited thereto. As long as it does not impede the implementation of the present invention, the threshold voltage Vtn can be equal to any value of various types, such as 0.3 V, 0.5 V, 0.7 V, etc.

[0062] based on Figure 4In the illustrated hardware architecture, a self-control signal Va is received as the gate bias voltage of the first N-type transistor 21 (e.g., N-type transistor NM2), and an input tolerance I / O level offset 20 is coupled to a voltage-sensing-based gate bias control circuit 110 to receive the self-control signal Va and operate accordingly, where the self-control signal Va is associated with the received voltage level I / O. Because the self-control signal Va is generated by the voltage-sensing-based gate bias control circuit 110 based on the received voltage level I / O, and not by any other circuit, the voltage-sensing-based gate bias control circuit 110 can operate automatically and independently. Therefore, the device 100 operating according to this method can function smoothly without additional control, making the entire hardware architecture very compact and highly efficient.

[0063] According to certain embodiments, Figure 4 The hardware architecture shown can be varied. For example, the diode-connected transistor can be implemented as a P-type transistor, wherein a drain and a gate of the P-type transistor are electrically connected to each other and coupled to the power supply path, and a source of the P-type transistor is coupled to the signal path.

[0064] The first voltage detection result at the first time point indicates that the received voltage level IO corresponds to the logic high state, and the received voltage level IO may be equal to a predetermined voltage level VIO such as 3.3 V (e.g., IO = 3.3 V). In particular, at the first time point, the power supply voltage VCC, for example, the power supply voltage VCC18, is less than the received voltage level IO. Figure 5 The lower half of the illustration depicts an embodiment of the present invention. Figure 3 The multi-transistor architecture normal voltage configuration involved in the multi-transistor level offset control scheme shown is as follows: Figure 5 Its upper half is depicted Figure 2 The single-transistor level offset control scheme is illustrated with the normal voltage configuration of the single-transistor architecture for better understanding. Under the same conditions, for example, at an operating frequency of 150 megahertz (MHz), the process corresponds to PTNT, the voltage is normal voltage (NV), and the temperature is 25 degrees Celsius (°C):

[0065] (1) Figure 5 The single-transistor architecture shown in the upper part will have reliability issues under normal voltage configuration, where Vds0 = Vds(MN0) = 2.0V > 1.8V; and

[0066] (2) Figure 5The multi-transistor architecture shown in the lower half has no reliability issues under normal voltage configuration, where Vb = (3.3V - (2 * Vtn)), so Vds2 = Vds(NM2) = (2 * Vtn) < 1.8 V and Vds3 = Vds(NM3) = (1.5V - Vtn) < 1.8 V.

[0067] To better understand, some implementation details can be further explained below. Multiple corner cases regarding process variation can include PTNT, PFNF, PSNS, PFNS, and PSNF (or TT, FF, SS, FS, and SF), any of which can be used to define the operating speed of the PMOSFET and NMOSFET, where "F" represents Fast, "T" represents Typical, and "S" represents Slow. Different combinations are possible with voltage variations (e.g., from -10% to +10%) and temperature variations (e.g., from -40°C to 125°C). Common combinations include:

[0068] (1) Typical Case (TC): TT, VCC, 25°C;

[0069] (2) Worst Case (WC): SS, VCC changes by -10%, 125°C; and

[0070] (3) Best Case (BC): FF, VCC changes by +10%, -40°C.

[0071] Taking VCC18=1.8V as an example, NV is 1.8V. Theoretically, when VCC18=1.98V, there could be more serious reliability issues in a single-transistor architecture.

[0072] Figure 6 The lower half of the illustration depicts an embodiment of the present invention. Figure 5 The lower half shows the relevant signals for the normal voltage configuration of this multi-transistor architecture, where Figure 6 Its upper half is depicted Figure 5 The upper half shows the relevant signals for the normal voltage configuration of this single-transistor architecture for better understanding. The horizontal axis represents time in nanoseconds (ns), and the vertical axis represents voltage in volts (V). Figure 6 As shown in the upper part, Vds0 > 1.8 V, indicating a potential reliability issue. (As...) Figure 6As shown in the lower half, Vds2 < 1.8 V, indicating that there will be no reliability issues.

[0073] Figure 7 The lower half of the illustration depicts an embodiment of the present invention. Figure 3 The abnormal voltage configuration of the multi-transistor architecture involved in the multi-transistor level offset control scheme shown is as follows: Figure 7 Its upper half is depicted Figure 2 The single-transistor architecture abnormal voltage configuration involved in this single-transistor level offset control scheme is shown for better understanding. Under the same conditions, for example, at an operating frequency of 150 MHz, a process corresponding to PTNT, a high voltage (HV) voltage, and a temperature of -40°C:

[0074] (1) Figure 7 The single-transistor architecture shown in the upper part has reliability issues with abnormal voltage configurations, where Vds0 > 1.8 V; and

[0075] (2) Figure 7 The abnormal voltage configuration of the multi-transistor architecture shown in the lower half will not have reliability issues, where Vds2 < 1.8 V and Vds3 < 1.8 V.

[0076] Figure 8 The lower half of the illustration depicts an embodiment of the present invention. Figure 7 The lower half shows the relevant signals for the abnormal voltage configuration of this multi-transistor architecture, where Figure 8 Its upper half is depicted Figure 7 The upper part shows the relevant signals for abnormal voltage configurations of this single-transistor architecture for better understanding. For example... Figure 8 As shown in the upper part, the intermediate signal IOA can change significantly over time, for example, from the intermediate signal IOA_fresh corresponding to the time when a new product is manufactured to the intermediate signal IOA_1.5_yr corresponding to 1.5 years later. This indicates a reliability problem, where the abnormal curve of the intermediate signal IOA_1.5_yr indicates that the N-type transistor NM0 degrades after 1.5 years. Figure 8 As shown in the lower half, the intermediate signals Vb and IOA do not change significantly over time. For example, the intermediate signals Vb_fresh and IOA_fresh, which correspond to the time when the new product is manufactured, remain unchanged from the intermediate signals Vb_1.5_yr and IOA_1.5_yr, which correspond to the time 1.5 years later. This indicates that there will be no reliability issues.

[0077] Figure 9 The illustration depicts another embodiment of the present invention. Figure 7The lower half shows the relevant signals for abnormal voltage configurations in this multi-transistor architecture. For example... Figure 9 As shown, the intermediate signals Vb and IOA do not change significantly over time. For example, the intermediate signals Vb_fresh and IOA_fresh, which correspond to the time when the new product is manufactured, remain unchanged from the intermediate signals Vb_10_yr and IOA_10_yr, which correspond to the time 10 years later. This indicates that there will be no reliability issues.

[0078] Figure 10 A workflow of the method is illustrated according to an embodiment of the present invention. Device 10 (or its components) can be adapted according to... Figure 10 Follow the workflow shown.

[0079] In step S10, the voltage-detection-based gate bias control circuit 110 can perform voltage-detection-based gate bias control on the first N-type transistor 21 within the input tolerance I / O level offsetter 20. Step S10 may include multiple sub-steps such as steps S11 and S12.

[0080] In step S11, the voltage detection and control circuit 111 can perform a voltage detection operation (e.g., any of the above-mentioned voltage detection operations) on the received voltage level IO on the I / O pad 10 to generate a voltage detection result (e.g., the first voltage detection result or the second voltage detection result), so as to generate an automatic control signal Va corresponding to the voltage detection result for gate bias control, wherein the voltage detection result indicates whether the received voltage level IO corresponds to the logic high state or the logic low state.

[0081] In step S12, the level reduction device 112 may selectively perform a level reduction operation (e.g., the level reduction operation described above) based on the voltage detection result (i.e., the voltage detection result just obtained in step S11) to generate a level reduction voltage (e.g., the level reduction voltage described above) as a self-control signal Va based on the received voltage level IO, so as to control the gate bias voltage of the first N-type transistor 21.

[0082] In step S20, device 10 can receive the self-control signal Va using the input tolerance I / O level offset 20 to operate according to the self-control signal Va. For the sake of simplicity, similar content will not be repeated here in this embodiment.

[0083] To better understand, this method can be used Figure 10 The workflow shown is for illustrative purposes only, but the invention is not limited thereto. According to some embodiments, one or more steps may be performed... Figure 10 Add, delete, or modify in the workflow shown.

[0084] The method and apparatus 100 of the present invention can be applied to 28nm / 22nm / 14nm 3.3V bidirectional I / O and input receiver I / O via a 1.8V I / O device, and can be applied to bidirectional I / O and input receiver I / O with signal high voltage tolerance. Furthermore, the method and apparatus 100 of the present invention (especially the voltage-sensing-based gate bias control circuit 110 therein) can be widely used to solve the reliability problem of input receiver level offsetters. It can be self-controlled from I / O pad signals (e.g., the received voltage level IO on I / O pad 10) and used for high-voltage tolerant input receivers. It utilizes a level reduction device 112 to generate a gate bias voltage for a first N-type transistor 21 (e.g., N-type transistor NM2, which can be implemented as an N-type MOSFET), wherein a lower gate bias voltage better solves the input receiver level offsetter reliability problem.

[0085] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be within the scope of the present invention.

Claims

1. A device for controlling a level offsetter as an input-tolerance input / output level offsetter, the input-tolerance input / output level offsetter being used to couple an input / output pad (I / O pad) to a buffer circuit within an input receiver circuit to act as a sub-circuit of the input receiver circuit, the device comprising: A voltage-detection-based gate bias control circuit is used to perform voltage-detection-based gate bias control on a first N-type transistor within an input tolerance input / output level offsetter, wherein a second N-type transistor within the input tolerance input / output level offsetter is coupled to the first N-type transistor, and the gate of the second N-type transistor is coupled to a power supply voltage. The voltage-detection-based gate bias control circuit includes: A voltage detection and control circuit, coupled to the input / output pad, is used to perform at least one voltage detection operation on the received voltage level on the input / output pad to generate at least one voltage detection result, which is used to generate a self-control signal corresponding to the at least one voltage detection result for gate bias control, wherein the at least one voltage detection result indicates whether the received voltage level corresponds to a logic high state or a logic low state; and A level-down device, coupled to the voltage detection and control circuit and the gate of the first N-type transistor, is used to selectively perform a level-down operation based on the at least one voltage detection result to generate a level-down voltage as the self-control signal based on the received voltage level, so as to control the gate bias voltage of the first N-type transistor.

2. The device of claim 1, wherein the voltage detection and control circuit comprises: A first voltage detection and path control sub-circuit, coupled to the input / output pad, is used to selectively open the signal path between the input / output pad and the level reduction device based on the at least one voltage detection result, so as to allow the level reduction device to perform the level reduction operation to generate the level reduction voltage as the self-control signal; and The second voltage detection and path control sub-circuit, coupled to the input / output pad, is used to selectively shut off the power path between the power supply voltage and the output terminal of the level reduction device based on the at least one voltage detection result, so as to allow the level reduction device to correctly output the level reduction voltage as the self-control signal without being affected by the power supply voltage.

3. The device of claim 2, wherein the at least one voltage detection result includes a first voltage detection result at a first time point, and the first voltage detection result indicates that the received voltage level corresponds to the logic high state, wherein: The first voltage detection and path control sub-circuit is used to open the signal path at the first time point according to the first voltage detection result, so as to allow the level reduction device to perform the level reduction operation to generate the level reduction voltage as the self-control signal. as well as The second voltage detection and path control sub-circuit is used to shut down the power path at the first time point based on the first voltage detection result, so as to allow the level reduction device to correctly output the level reduction voltage as the self-control signal, without being affected by the power supply voltage.

4. The device of claim 3, wherein the at least one voltage detection result further includes a second voltage detection result at a second time point, and the second voltage detection result indicates that the received voltage level corresponds to the logic low state, wherein: The first voltage detection and path control sub-circuit is used to close the signal path at the second time point based on the second voltage detection result, so as to prevent the level reduction device from performing the level reduction operation. as well as The second voltage detection and path control sub-circuit is used to activate the power path at the second time point based on the second voltage detection result, so as to generate the self-control signal based on the power supply voltage.

5. The device as claimed in claim 2, wherein: The first voltage detection and path control sub-circuit includes: A first switch, coupled to the input / output pad, is used to selectively open the signal path based on the at least one voltage detection result, so as to allow the level reduction device to perform the level reduction operation to generate the level reduction voltage as the self-control signal; as well as The second voltage detection and path control sub-circuit includes: A second switch, coupled to the input / output pad, is used to selectively shut off the power path based on the at least one voltage detection result, so as to allow the level-down device to correctly output the level-down voltage as the self-control signal, without being affected by the power supply voltage.

6. The device of claim 5, wherein the first switch and the second switch are respectively implemented as a first P-type transistor and a second P-type transistor, wherein the gate of the first P-type transistor and the gate of the second P-type transistor are respectively coupled to the power supply voltage and the input / output pad, the source of the first P-type transistor and the source of the second P-type transistor are respectively coupled to the input / output pad and the power supply voltage, and the drain of the first P-type transistor and the drain of the second P-type transistor are respectively coupled to the input terminal and the output terminal of the level reduction device.

7. The device of claim 1, wherein the at least one voltage detection result includes a first voltage detection result at a first time point, and the first voltage detection result indicates that the received voltage level corresponds to the logic high state; and at the first time point, the power supply voltage is less than the received voltage level.

8. The device of claim 1, wherein the level reduction device comprises: A diode-connected transistor, coupled to the voltage detection and control circuit and the gate of the first N-type transistor, is used to perform the level reduction operation to generate the level reduction voltage as the self-control signal.

9. The device as claimed in claim 8, wherein: The diode-connected transistor is implemented as a third N-type transistor, wherein the drain and gate of the third N-type transistor are electrically connected to each other and coupled to the signal path between the input / output pad and the level reduction device, and the source of the third N-type transistor is coupled to the power path between the power supply voltage and the level reduction device; or The diode-connected transistor is implemented as a P-type transistor, wherein the drain and gate of the P-type transistor are electrically connected to each other and coupled to the power supply path, and the source of the P-type transistor is coupled to the signal path.

10. The device of claim 1, wherein the self-control signal is received as the gate bias voltage of the first N-type transistor, and the device further comprises: The input tolerance input / output level offset is coupled to the voltage-sensing gate bias control circuit to receive the self-control signal and operate according to the self-control signal.

11. A method for controlling a level offsetter as an input-tolerance input / output level offsetter, the input-tolerance input / output level offsetter being used to couple input / output pads to a buffer circuit within an input receiver circuit to act as a sub-circuit of the input receiver circuit, the method comprising: The voltage-sensing-based gate bias control is performed on the first N-type transistor within the input tolerance input / output level offsetter, wherein a second N-type transistor within the input tolerance input / output level offsetter is coupled to the first N-type transistor, and the gate of the second N-type transistor is coupled to the power supply voltage. The voltage-sensing-based gate bias control of the first N-type transistor within the input tolerance input / output level offsetter further includes: At least one voltage detection operation is performed on the received voltage level on the input / output pad to generate at least one voltage detection result, which is used to generate a self-control signal corresponding to the at least one voltage detection result for gate bias control, wherein the at least one voltage detection result indicates whether the received voltage level corresponds to a logic high state or a logic low state; and Based on the at least one voltage detection result, a level reduction operation is selectively performed to generate a level reduction voltage as the self-control signal based on the received voltage level, so as to control the gate bias voltage of the first N-type transistor.

12. The method of claim 11, wherein the level-down device is used to perform the level-down operation; and the at least one voltage detection operation is performed on the received voltage level on the input / output pad to generate the at least one voltage detection result, for generating the self-control signal corresponding to the at least one voltage detection result for gate bias control, further comprising: Based on the at least one voltage detection result, the signal path between the input / output pad and the level reduction device is selectively opened to allow the level reduction device to perform the level reduction operation to generate the level reduction voltage as the self-control signal; and Based on the at least one voltage detection result, the power path between the power supply voltage and the output terminal of the level reduction device is selectively shut off, so as to allow the level reduction device to correctly output the level reduction voltage as the self-control signal without being affected by the power supply voltage.

13. The method of claim 12, wherein the at least one voltage detection result includes a first voltage detection result at a first time point, and the first voltage detection result indicates that the received voltage level corresponds to the logic high state, wherein: Selectively opening the signal path between the input / output pad and the level-down device based on the at least one voltage detection result, to allow the level-down device to perform the level-down operation to generate the level-down voltage, the self-control signal further includes: At the first time point, the signal path is opened according to the first voltage detection result, so as to allow the level reduction device to perform the level reduction operation to generate the level reduction voltage as the self-control signal; as well as Selectively shutting off the power path between the power supply voltage and the level-down device based on the at least one voltage detection result, so as to allow the level-down device to correctly output the level-down voltage as the self-control signal, without being affected by the power supply voltage, further includes: At the first time point, the power path is shut off based on the first voltage detection result, so that the level reduction device can correctly output the level reduction voltage as the self-control signal without being affected by the power supply voltage.

14. The method of claim 13, wherein the at least one voltage detection result further includes a second voltage detection result at a second time point, and the second voltage detection result indicates that the received voltage level corresponds to the logic low state, wherein: Selectively opening the signal path between the input / output pad and the level-down device based on the at least one voltage detection result, to allow the level-down device to perform the level-down operation to generate the level-down voltage, the self-control signal further includes: At the second time point, the signal path is shut off based on the second voltage detection result to prevent the level reduction device from performing the level reduction operation. as well as Selectively shutting off the power path between the power supply voltage and the level-down device based on the at least one voltage detection result, so as to allow the level-down device to correctly output the level-down voltage as the self-control signal, without being affected by the power supply voltage, further includes: At the second time point, the power path is activated based on the second voltage detection result to generate the self-control signal according to the power supply voltage.

15. The method of claim 12, wherein: Selectively opening the signal path between the input / output pad and the level-down device based on the at least one voltage detection result, to allow the level-down device to perform the level-down operation to generate the level-down voltage, the self-control signal further includes: Using a first switch, the signal path is selectively opened based on the at least one voltage detection result, so as to allow the level reduction device to perform the level reduction operation to generate the level reduction voltage as the self-control signal; as well as Selectively shutting off the power path between the power supply voltage and the level-down device based on the at least one voltage detection result, so as to allow the level-down device to correctly output the level-down voltage as the self-control signal, without being affected by the power supply voltage, further includes: Using a second switch, the power path is selectively shut off based on the at least one voltage detection result, so that the level reduction device can correctly output the level reduction voltage as the self-control signal without being affected by the power supply voltage.

16. The method of claim 15, wherein the first switch and the second switch are respectively implemented as a first P-type transistor and a second P-type transistor, wherein the gate of the first P-type transistor and the gate of the second P-type transistor are respectively coupled to the power supply voltage and the input / output pad, the source of the first P-type transistor and the source of the second P-type transistor are respectively coupled to the input / output pad and the power supply voltage, and the drain of the first P-type transistor and the drain of the second P-type transistor are respectively coupled to the input terminal and the output terminal of the level reduction device.

17. The method of claim 11, wherein the at least one voltage detection result includes a first voltage detection result at a first time point, and the first voltage detection result indicates that the received voltage level corresponds to the logic high state; and at the first time point, the power supply voltage is less than the received voltage level.

18. The method of claim 11, wherein the level-lowering device is used to perform the level-lowering operation; and the level-lowering device comprises: A diode-connected transistor, coupled to the voltage detection and control circuit and the gate of the first N-type transistor, is used to perform the level reduction operation to generate the level reduction voltage as the self-control signal.

19. The method of claim 18, wherein: The diode-connected transistor is implemented as a third N-type transistor, wherein the drain and gate of the third N-type transistor are electrically connected to each other and coupled to the signal path between the input / output pad and the level reduction device, and the source of the third N-type transistor is coupled to the power path between the power supply voltage and the level reduction device; or The diode-connected transistor is implemented as a P-type transistor, wherein the drain and gate of the P-type transistor are electrically connected to each other and coupled to the power supply path, and the source of the P-type transistor is coupled to the signal path.

20. The method of claim 11, wherein the self-control signal is received as the gate bias voltage of the first N-type transistor, and the method further comprises: The input tolerance input / output level offset is used to receive the automatic control signal and operate according to the automatic control signal.

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