circuitry

Abstract

A circuit includes a clock buffer, a first circuit module, and a second circuit module. The clock buffer is configured to generate a first clock signal and a second clock signal. The first circuit module includes a first frequency divider configured to divide the first clock signal to generate a plurality of first divided clock signals. The second circuit module includes a second frequency divider configured to divide the first clock signal to generate a plurality of second divided clock signals. The first circuit module and the second circuit module use the second clock signal to perform a phase alignment operation during the dividing operation, such that the plurality of first divided clock signals and the plurality of second divided clock signals are phase-aligned.

Description

Technical Field

[0001] This invention relates to frequency dividers, and more particularly to a method for aligning the phases of multiple frequency dividers. Background Technology

[0002] In chips with multiple analog-to-digital converters (ADCs) and multiple digital-to-analog converters (DACs), because multiple ADCs and multiple DACs may require multiple clock signals with different frequencies, these ADCs or DACs typically incorporate frequency dividers to divide a high-frequency clock signal from a phase-locked loop (PLL) to generate multiple clock signals with the desired frequencies for internal operation. For example, refer to... Figure 1 Frequency dividers 110 and 120 can be located in the first ADC and the second ADC, respectively. Frequency divider 110 divides a clock signal CK by 2 to generate a divided clock signal CK1, and frequency divider 110 divides the clock signal CK by 2 to generate a divided clock signal CK2.

[0003] However, Figure 1 The architecture shown may cause phase misalignment of the divided clock signals CK1 and CK2 used by the first and second ADCs. Specifically, refer to... Figure 2 Assuming that frequency divider 110 has been enabled by an enable signal EN1 and is generating a divided clock signal CK1, and if frequency divider 120 is then enabled by an enable signal EN2, the upper edge of the first clock signal CK it sees is... Figure 2 The position marked "x" indicates that the phase of the divided clock signal CK2 generated by frequency divider 120 will have a 180-degree phase difference with the phase of the divided clock signal CK1 generated by frequency divider 110, meaning they are misaligned. Conversely, if the upper edge of the first clock signal CK1 seen when frequency divider 120 is enabled by the enable signal EN2 is... Figure 2 The position marked "o" indicates that the phase of the divided clock signal CK2 generated by frequency divider 120 will be aligned with the phase of the divided clock signal CK1 generated by frequency divider 110. As mentioned above, when frequency dividers 110 and 120 are frequency dividers with a divisor of "2", the divided clock signals CK1 and CK2 they generate will have two possible phases.

[0004] Similarly, if frequency dividers 110 and 120 are frequency dividers with divisors of "4", "8", "16", ..., the resulting divided clock signals CK1 and CK2 will have "4", "8", "16", ... phase possibilities, making phase alignment more difficult.

[0005] To ensure phase alignment of the clock signals used by each ADC and DAC, another method is to simultaneously send the required clock frequency to each ADC and DAC via a clock buffer. However, this method results in significant power consumption from the clock buffer, interference between multiple clock signals of different frequencies during transmission, the need for numerous traces to transmit these signals to multiple ADCs and DACs, and the requirement for robust power supply traces and voltage regulators to prevent the interference of different clock frequencies on the power supply traces. Therefore, due to its high power consumption and large chip area, this method is not very suitable in practice. Summary of the Invention

[0006] Therefore, one of the objectives of this invention is to provide a phase alignment method for multiple frequency dividers to solve the problems described in the prior art.

[0007] In one embodiment of the present invention, a circuit is disclosed, comprising a clock buffer, a first circuit module, and a second circuit module. The clock buffer is used to generate a first clock signal and a second clock signal. The first circuit module includes a first frequency divider, wherein the first frequency divider is used to receive the first clock signal and the second clock signal, and to perform a frequency division operation on the first clock signal to generate a plurality of first frequency-divided clock signals. The second circuit module includes a second frequency divider, wherein the second frequency divider is used to receive the first clock signal and the second clock signal, and to perform the frequency division operation on the first clock signal to generate a plurality of second frequency-divided clock signals. During the frequency division operation, the first circuit module and the second circuit module use the second clock signal to perform a phase alignment operation, so that the plurality of first frequency-divided clock signals and the plurality of second frequency-divided clock signals are phase-aligned. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of two frequency dividers dividing a clock signal in the prior art.

[0009] Figure 2 for Figure 1 The diagram shown illustrates the potential for phase misalignment between the two divided clock signals generated by the two frequency dividers.

[0010] Figure 3This is a schematic diagram of a circuit according to an embodiment of the present invention.

[0011] Figure 4 This is a schematic diagram of a clock buffer and a portion of a receiving circuit according to an embodiment of the present invention.

[0012] Figure 5 This is a schematic diagram of a buffer according to an embodiment of the present invention.

[0013] Figure 6 This is a timing diagram showing the relationship between an enable signal and a delayed enable signal.

[0014] Figure 7 According to an embodiment of the present invention Figure 4 The timing diagram of some of the signals is shown.

[0015] Figure 8 According to an embodiment of the present invention Figure 3 The diagram shows how the clock signals generated by different ADCs can be phase-aligned after frequency division. Detailed Implementation

[0016] Figure 3 This is a schematic diagram of a circuit 300 according to an embodiment of the present invention. Figure 3 As shown, circuit 300 includes a phase-locked loop 310, a clock buffer 320, and multiple circuit modules, exemplified by multiple ADCs 330_1, 330_2 and multiple DACs 340_1, 340_2. In this embodiment, ADCs 330_1, 330_2 and DACs 340_1, 340_2 require multiple clock signals with different frequencies, and each of ADCs 330_1, 330_2 and DACs 340_1, 340_2 has a frequency divider to divide the clock signal from the phase-locked loop 310 to generate multiple divided clock signals for internal operation.

[0017] In the operation of circuit 300, phase-locked loop 310 generates four clock signals CK_HP, CK_HN, CK_LP, and CK_LN. Clock signals CK_HP and CK_HN are high-frequency differential signals, meaning they have the same frequency but opposite phases. Clock signals CK_LP and CK_LN are low-frequency differential signals (i.e., their frequencies are lower than those of CK_HP and CK_HN), meaning they have the same frequency but opposite phases. In this embodiment, ADCs 330_1 and 330_2 are used to receive clock signals CK_HP and CK_LP, while DACs 340_1 and 340_2 are used to receive clock signals CK_HN and CK_LN; however, this invention is not limited to these methods. Upon receiving the clock signal, ADCs 330_1, 330_2 and DACs 340_1, 340_2 divide the clock signal CK_HP / CK_HN to generate multiple divided clock signals for internal use. During the division operation, ADCs 330_1, 330_2 and DACs 340_1, 340_2 use clock signals CK_LP / CK_LN for phase alignment to ensure that the multiple divided clock signals generated by each of ADCs 330_1, 330_2 and DACs 340_1, 340_2 are phase aligned with each other.

[0018] In this embodiment, to allow ADCs 330_1, 330_2 and DACs 340_1, 340_2 to use clock signals CK_LP / CK_LN for phase alignment during frequency division operations, the frequencies of clock signals CK_LP and CK_LN are the least common multiples of the frequencies of multiple divided clock signals generated by ADCs 330_1, 330_2 and DACs 340_1, 340_2 dividing clock signals CK_HP / CK_HN. For example, assuming the frequencies of clock signals CK_HP and CK_HN are "F", and the frequencies of the divided clock signals required by ADCs 330_1, 330_2 and DACs 340_1, 340_2 are "F / 2", "F / 4", "F / 8", and "F / 16", then the frequency of clock signals CK_LP and CK_LN is "F / 16". In another example, assuming that the frequencies of the divided clock signals required by ADC 330_1, 330_2 and DAC 340_1, 340_2 are “F / 2”, “F / 3”, and “F / 4”, then the frequencies of clock signals CK_LP and CKLN are “F / 12”.

[0019] With the architecture of circuit 300, regardless of the number of frequencies required by ADCs 330_1, 330_2 and DACs 340_1, 340_2, the phase-locked loop 310 only needs to generate four clock signals CK_HP, CK_HN, CK_LP, and CK_LN. Furthermore, each of ADCs 330_1, 330_2 and DACs 340_1, 340_2 only needs to receive two clock signals. Therefore, the phase-locked loop 310 and the clock buffer 320 will have low power consumption, and the clock buffer 320 to ADCs 330_1, 330_2 and DACs 340_1, 340_2 also has a small number of traces, which improves signal quality and reduces chip area.

[0020] It should be noted that, Figure 3 The clock signal generated by the phase-locked loop 310 shown is a differential signal to avoid electromagnetic interference. However, in other embodiments, the phase-locked loop 310 may not need to transmit a differential signal; that is, the phase-locked loop 310 may only transmit two clock signals, CK_HP and CK_LP, to the ADCs 330_1 and 330_2 and the DACs 340_1 and 340_2.

[0021] Figure 4 This is a schematic diagram of a clock buffer 320 and a portion of a receiving circuit 410 according to an embodiment of the present invention, wherein the receiving circuit 410 may be disposed in one of ADCs 330_1, 330_2 and DACs 340_1, 340_2. Figure 4 As shown, the clock buffer 320 includes two buffers 322 and 324, and the receiving circuit 410 includes a frequency divider 412, two inverters 424 and 426, and two sampling circuits (implemented by D-type flip-flops 425 and 427).

[0022] In one embodiment, each of the ADCs 330_1, 330_2 and DACs 340_1, 340_2 includes a receiving circuit 410, and the clock buffer 320 also provides two corresponding buffers 322, 324 for each of the ADCs 330_1, 330_2 and DACs 340_1, 340_2.

[0023] exist Figure 3 In the operation of the clock buffer 320 and the receiving circuit 410 shown, the buffer 322 receives a clock signal CK_H and selectively generates a buffered clock signal CK_H' under the control of a delayed enable signal EN_LATE. The clock signal CK_H can be... Figure 3The clock signals CK_HP and CK_HN shown are either high-frequency clock signals, i.e., clock signal CK_H is a high-frequency clock signal. Furthermore, when the delayed enable signal EN_LATE enables buffer 322, buffer 322 generates a buffered clock signal CK_H' based on the clock signal CK_H; conversely, when the delayed enable signal EN_LATE does not enable buffer 322, buffer 322 will not output the buffered clock signal CK_H' (for example, it will output a logic value "1" corresponding to a high voltage). Buffer 324 receives a clock signal CK_L and selectively generates a buffered clock signal CK_L' under the control of the delayed enable signal EN_LATE, wherein the clock signal CK_L can be... Figure 3 Either the clock signal CK_LP or CK_LN shown, i.e., the clock signal CK_L, is a low-frequency clock signal. Furthermore, when the delayed enable signal EN_LATE enables buffer 324, buffer 324 will generate a buffered clock signal CK_L' based on the clock signal CK_L; however, when the delayed enable signal EN_LATE does not enable buffer 324, buffer 324 will not output the buffered clock signal CK_L' (for example, it will output a logic value "1" corresponding to a high voltage).

[0024] Figure 5 This is a schematic diagram of a buffer 500 according to an embodiment of the present invention, wherein the buffer 500 can be used to implement Figure 4 Either of the buffers 322 and 324 shown. Figure 5 As shown, buffer 500 includes a buffer circuit 510, two sampling circuits (implemented using D-type flip-flops 520 and 530), and a multiplexer 540. In the operation of buffer 500, the clock signal CK_H / CK_L is transmitted through buffer circuit 510 to D-type flip-flops 520 and 530 and multiplexer 540. D-type flip-flops 520 and 530 sequentially use the clock signal CK_H / CK_L to sample the delayed enable signal EN_LATE, thereby controlling multiplexer 540 to select either the clock signal CK_H / CK_L or the corresponding logic value "1" as its output. Specifically, when the output of D-type flip-flop 530 has a high voltage level, multiplexer 540 outputs the clock signal CK_H / CK_L as the buffered clock signal CK_H' / CK_L'; and when the output of D-type flip-flop 530 has a low voltage level, multiplexer 540 outputs the logic value "1".

[0025] It should be noted that, Figure 5The circuit architecture of the buffer 500 shown is merely illustrative and not intended to limit the invention. In other embodiments, the buffer 500 can have different circuit designs, as long as it can selectively generate the buffered clock signal CK_H' / CK_L' based on the clock signal CK_H / CK_L according to the delayed enable signal EN_LATE.

[0026] In the operation of the receiving circuit 410, the D-type flip-flop 425 is controlled by the delayed enable signal EN_LATE to determine whether it operates normally. For example, when the delayed enable signal EN_LATE enables the D-type flip-flop 425, it operates normally, that is, the D-type flip-flop 425 samples the buffered clock signal CK_L' according to the buffered clock signal CK_H' to generate a first sampled signal; and when the delayed enable signal EN_LATE does not enable the D-type flip-flop 425, it resets so that its output corresponds to the logic value "0". Specifically, the inverter 424 inverts the buffered clock signal CK_H' to generate an inverted clock signal, and when the D-type flip-flop 425 operates normally, it uses the inverted clock signal to sample the buffered clock signal CK_L' to generate the first sampled signal.

[0027] Next, the D-type flip-flop 427 is controlled by the delayed enable signal EN_LATE to determine whether it operates normally. For example, when the delayed enable signal EN_LATE enables the D-type flip-flop 427, the D-type flip-flop 427 operates normally, that is, the D-type flip-flop 427 samples an enable signal EN based on the first sampled signal output by the D-type flip-flop 425 to generate a sampled enable signal to the frequency divider 412; and when the delayed enable signal EN_LATE does not enable the D-type flip-flop 427, the D-type flip-flop 427 will reset so that its output corresponds to the logic value "0". Specifically, inverter 426 inverts the first sampled signal output by D-type flip-flop 425 to generate an inverted first sampled signal. When D-type flip-flop 427 is operating normally, it uses the inverted first sampled signal to sample the enable signal EN to generate the sampled enable signal.

[0028] refer to Figure 6 , it is Figure 4 The timing relationship between the enable signal EN and the delayed enable signal EN_LATE is shown in the diagram. Figure 6As shown, assuming that a high voltage level (logic value "1") for both the enable signal EN and the delayed enable signal EN_LATE represents an enabled state, and a low voltage level (logic value "1") represents a disabled state, then the starting enable time (rising edge time) of the delayed enable signal EN_LATE is later than the starting enable time (rising edge time) of the enable signal EN. That is, the rising edge time difference td1 between the delayed enable signal EN_LATE and the enable signal EN, as shown in the diagram, is greater than zero. Furthermore, the falling edge time (falling edge time) of the delayed enable signal EN_LATE is later than the falling edge time (falling edge time) of the enable signal EN, and the falling edge time difference td2 between the delayed enable signal EN_LATE and the enable signal EN is greater than or equal to twice the period of the clock signal CK_L.

[0029] It should be noted that, Figure 4 and Figure 6 The enable signal EN and the delayed enable signal EN_LATE shown can be generated internally by ADC330_1, 330_2 and DAC340_1, 340_2, or generated by clock buffer 320 and sent to ADC330_1, 330_2 and DAC340_1, 340_2.

[0030] Figure 7 According to an embodiment of the present invention Figure 4 The timing diagram shown is for a portion of the signals, where, Figure 7 The signal at terminal NA shown is the inverted, first-sampled signal generated by inverter 426, while the signal at terminal NB is the sampled enable signal generated by D-type flip-flop 427. (See also...) Figure 4 , Figure 7At time t1, the enable signal EN transitions from a low voltage level to a high voltage level, meaning it changes from logic value "0" to logic value "1" and enters the enabled state. At time t2, the delayed enable signal EN_LATE transitions from a low voltage level to a high voltage level, meaning it changes from logic value "0" to logic value "1" and enters the enabled state. At time t3, the buffered clock signal CK_H' will first show a lower edge, while the buffered clock signal CK_L' still has a high voltage level (logic value "1"), thus causing the first sampled signal after inversion at endpoint NA to begin showing a lower edge. At time t4, after the buffered clock signal CK_L' becomes a low voltage level (logic value "0"), when the buffered clock signal CK_H' has its first lower edge, the inverted first sampled signal at terminal NA and the sampled enable signal at terminal NB will both have their upper edges, thus enabling the frequency divider 412.

[0031] When frequency divider 412 is enabled, it can perform multiple frequency division operations on the buffered clock signal CK_H' to generate multiple divided clock signals for internal circuit use. It should be noted that since the circuit implementation of frequency divider 412 is well known to those skilled in the art, it will not be described in detail in this specification.

[0032] On the other hand, if it is necessary to turn off the frequency divider 412, please refer to... Figure 4 as well as Figure 6 The following steps are performed in sequence: (1) The enable signal EN will first switch from a high voltage level to a low voltage level, that is, the enable signal EN will switch from logic value "1" to logic value "0" and begin to enter the disabled state. (2) After sampling the upper edge of the signal after the first inverted sample at the terminal NA, the enable signal at the terminal NB will switch from a high voltage level to a low voltage level and begin to enter the disabled state, and the frequency divider 412 will be turned off. (3) After a delay, the enable signal EN_LATE will switch from a high voltage level to a low voltage level, that is, after a delay, the enable signal EN_LATE will switch from logic value "1" to logic value "0" and begin to enter the disabled state.

[0033] In summary, the corresponding time points for turning the frequency divider 412 on or off are... Figure 7 The time point at which the upper edge of the signal appears after the first sample following the inversion of the midpoint NA.

[0034] exist Figure 4In this embodiment, since the D-type flip-flop 425 samples the low-frequency buffered clock signal CK_L' based on the high-frequency buffered clock signal CK_H', the frequency of the first sampled signal after inversion at terminal NA is equal to the frequency of the buffered clock signal CK_L'. Furthermore, since the upper edge of the first sampled signal after inversion at terminal NA is aligned with the lower edge of the buffered clock signal CK_H', the voltage level switching of the enable signal after sampling at terminal NB must be near the lower edge of the buffered clock signal CK_H'. This ensures maximum timing margin when the frequency divider 412 needs to be enabled. In addition, since the time difference between when the frequency divider 412 is turned on or off is always an integer multiple of the period of the buffered clock signal CK_L', when the frequency divider 412 needs to be turned off, it must be done when both the divided clock signal and the buffered clock signal CK_L' are logic values ​​"0", thus avoiding glitch phenomena.

[0035] pass Figure 3 and Figure 4 In this embodiment, the divided clock signals generated by each of the ADCs 330_1, 330_2 and DACs 340_1, 340_2 can be phase-aligned to avoid Figure 2 The prior art shown here suffers from the problem of potential phase misalignment in the divided clock signals generated by each ADC and DAC. Specifically, refer to... Figure 8 The timing diagram shown indicates that EN_ADC1 represents... Figure 4 The enable signal EN is used as the enable signal for ADC 330_1. EN_LATE_ADC1 indicates... Figure 4 The delayed enable signal EN_LATE is used for the delayed enable signal of ADC 330_1, NB_ADC1 indicates Figure 4 The receiving circuit 410 is used for the sampled enable signal of the ADC 330_1 endpoint NB, EN_ADC2 indicates... Figure 4 The enable signal EN is used as the enable signal for ADC330_2. EN_LATE_ADC2 indicates... Figure 4 The delayed enable signal EN_LATE is used for the delayed enable signal of ADC 330_2, and NB_ADC2 indicates... Figure 4 The receiving circuit 410 is used for the sampled enable signal of the time endpoint NB of ADC 330_2. Furthermore, in this embodiment, it is assumed that the frequency of the clock signal CK_H is four times the frequency of the clock signal CK_L. Figure 8In this context, "T" represents the period of the clock signal CK_H, "D" represents the enable time difference (i.e., the upper edge time difference) between the enable signal EN_ADC1 for ADC 330_1 and the enable signal EN_ADC2 for ADC 330_2, and "N" is any suitable positive integer. (See reference) Figure 8 Regardless of the value of the enable time difference D between the enable signal EN_ADC1 of ADC 330_1 and the enable signal EN_ADC2 of ADC 330_2, the time difference td between the sampled enable signal at the endpoint NB_ADC1 of ADC 330_1 and the sampled enable signal at the endpoint NB_ADC2 of ADC 330_2 will always differ by (4×N)×T. This is because, ignoring trace transmission errors and circuit mismatches, different ADCs 330_1 and 330_2 will have different enable times. Figure 4 The upper edge of the signal after the first sample after the inversion of the endpoint NA will be fully aligned, and the frequency of the signal after the first sample after the inversion of the endpoint NA will be equal to the frequency of the clock signal CK_L.

[0036] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

[0037] [Symbol Explanation]

[0038] 110, 120: Frequency divider

[0039] 300: Circuit

[0040] 310: Phase-locked loop

[0041] 320: Clock buffer

[0042] 330_1, 330_2: ADC

[0043] 340_1, 340_2: DAC

[0044] 322, 324: Buffer

[0045] 410: Receiving circuit

[0046] 412: Frequency divider

[0047] 424, 426: Inverters

[0048] 425, 427, 520, 530: Type D flip-flops

[0049] 510: Buffer circuit

[0050] 540: Multiplexer

[0051] CK_H, CK_L, CK_HP, CK_HN, CK_LP, CK_LN: Clock signals

[0052] CK_H', CK_L': Buffered clock signals

[0053] Clock signals after frequency division by CK1 and CK2

[0054] EN1, EN2, EN, EN_ADC1, EN_ADC2: Enable signals

[0055] EN_LATE, EN_LATE_ADC1, EN_LATE_ADC2: Delayed enable signals

[0056] NA, NB, NB_ADC1, NB_ADC2: Endpoints.

Claims

1. A circuit comprising: A clock buffer for generating a first clock signal and a second clock signal; A first circuit module includes a first frequency divider, wherein, The first frequency divider is used to receive the first clock signal and the second clock signal, and to perform a frequency division operation on the first clock signal to generate multiple first frequency divided clock signals; as well as A second circuit module includes a second frequency divider, wherein the second frequency divider is used to receive the first clock signal and the second clock signal, and to perform the frequency division operation on the first clock signal to generate a plurality of second frequency-divided clock signals; In this process, the first circuit module and the second circuit module use the second clock signal to perform phase alignment operation during the frequency division operation, so that the plurality of first frequency divided clock signals and the plurality of second frequency divided clock signals are aligned in phase.

2. The circuit according to claim 1, wherein, The clock buffer contains: A first buffer for receiving the first clock signal and selectively generating a buffered first clock signal by control of a delayed enable signal; and A second buffer for receiving the second clock signal and selectively generating a buffered second clock signal by controlling the delayed enable signal; and The first circuit module and / or the second circuit module includes a receiving circuit, and the receiving circuit includes: A first sampling circuit is used to sample the buffered second clock signal based on the buffered first clock signal to generate a first sampled signal; and A second sampling circuit is used to sample an enable signal based on the first sampled signal to generate a sampled enable signal to the first frequency divider. Wherein, the initial enable time of the delayed enable signal is later than the initial enable time of the enable signal.

3. The circuit according to claim 2, wherein, Both the first circuit module and the second circuit module include the receiving circuit.

4. The circuit according to claim 2, wherein, The receiving circuit also includes: A first inverter is provided for inverting the buffered first clock signal to generate an inverted clock signal; wherein the first sampling circuit samples the buffered second clock signal based on the inverted clock signal to generate the first sampled signal; and A second inverter is used to invert the first sampled signal to generate an inverted first sampled signal; wherein the second sampling circuit is used to sample the enable signal based on the inverted first sampled signal to generate the sampled enable signal to the first frequency divider.

5. The circuit according to claim 2, wherein, The first sampling circuit and the second sampling circuit are controlled by the delayed enable signal. When the delayed enable signal enables the first sampling circuit and the second sampling circuit, the first sampling circuit samples the buffered second clock signal according to the buffered first clock signal to generate the first sampled signal, and the second sampling circuit samples the enable signal according to the first sampled signal to generate the sampled enable signal to the first frequency divider.

6. The circuit according to claim 2, wherein, The initial disabling time of the delayed enable signal is later than the initial disabling time of the enable signal.

7. The circuit according to claim 6, wherein, The frequency of the second clock signal is lower than the frequency of the first clock signal, and the time difference between the delayed enable signal and the initial disable time of the enable signal is greater than or equal to twice the period of the second clock signal.

8. The circuit according to claim 7, wherein, The plurality of first frequency-divided clock signals have different frequencies, the plurality of second frequency-divided clock signals have different frequencies, and the frequency of the second clock signal is the least common multiple of the plurality of frequencies of the plurality of first frequency-divided clock signals or the plurality of second frequency-divided clock signals.

9. The circuit according to claim 1, wherein, The plurality of first frequency-divided clock signals have different frequencies, the plurality of second frequency-divided clock signals have different frequencies, and the frequency of the second clock signal is the least common multiple of the plurality of frequencies of the plurality of first frequency-divided clock signals or the plurality of second frequency-divided clock signals; And the clock buffer does not transmit other clock signals to the first circuit module and the second circuit module.

10. The circuit according to claim 1, wherein, The first circuit module and the second circuit module are analog-to-digital converters or digital-to-analog converters.

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